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// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: rgmii_out4.v
// Megafunction Name(s):
// altddio_out
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_out4 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_bb.v TRUE
|
// Module: altera_tse_xcvr_resync
//
// Description:
// A general purpose resynchronization module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
//
module altera_tse_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0 // See description above
) (
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
wire [INT_LEN :0] next_r; // One larger real chain
assign q[ig] = r[INT_LEN-1]; // Output signal
assign next_r = {r,d_in};
always @(posedge clk)
r <= next_r[INT_LEN-1:0];
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r;
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : (DDR1/2/3,LPDDR1) address and command decoder
//
// File : alt_mem_ddrx_addr_cmd.v
//
// Abstract : Address and command decoder
///////////////////////////////////////////////////////////////////////////////
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits (For ddr3 >=13 even if row=12)
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_CTL_RATE = "FULL",
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_type,
cfg_output_regd,
cfg_enable_chipsel_for_sideband, // to indicate should we de-assert cs_n for sideband signal (self refresh and deep power down specific)
// AFI interface (Signals from Arbiter block)
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_zq_cal,
bg_do_lmr,
bg_do_burst_terminate, //Currently does not exist in arbiter
bg_do_deep_pdown, //Currently does not exist in arbiter
// address information
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr, //Currently doesn not exist in arbiter
lmr_opcode,
//output to PHY
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n
);
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
input cfg_enable_chipsel_for_sideband;
// Arbiter command inputs
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
input bg_do_auto_precharge;
input bg_do_activate;
input bg_do_precharge;
input [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] bg_do_refresh;
input [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] bg_do_power_down;
input [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal;
input bg_do_lmr;
input bg_do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown;
input [CFG_MEM_IF_CHIP-1:0] bg_to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] bg_to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] bg_to_col;
input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_lmr;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
wire bg_do_read;
wire bg_do_burst_chop;
wire bg_do_auto_precharge;
wire bg_do_activate;
wire bg_do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal;
wire bg_do_lmr;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown;
wire bg_do_burst_terminate;
reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down_r;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown_r;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg int_ras_n;
reg int_cas_n;
reg int_we_n;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] int_ba;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke ;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n ;
reg combi_ras_n;
reg combi_cas_n;
reg combi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr ;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r ;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r ;
reg combi_ras_n_r;
reg combi_cas_n_r;
reg combi_we_n_r ;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba_r ;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r ;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_row;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] temp_col;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col;
wire col12;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col_r;
reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh;
//=================================================================================================//
generate
if (CFG_MEM_IF_ADDR_WIDTH > CFG_MEM_IF_ROW_WIDTH)
begin
assign int_row = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_ROW_WIDTH){1'b0}},bg_to_row};
end
else
begin
assign int_row = bg_to_row;
end
endgenerate
assign temp_col = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_COL_WIDTH){1'b0}},bg_to_col};
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
assign col12 = (cfg_type == `MMR_TYPE_DDR3) ? ~bg_do_burst_chop : temp_col[11]; //DDR3
generate
if (CFG_MEM_IF_ADDR_WIDTH < 13)
begin
assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-1:10],bg_do_auto_precharge,temp_col[9:0]};
end
else if (CFG_MEM_IF_ADDR_WIDTH == 13)
begin
assign int_col = {col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
end
else
begin
assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-3:11],col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
end
endgenerate
generate
if (CFG_DWIDTH_RATIO == 2)
begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_ras_n = int_ras_n;
assign afi_cas_n = int_cas_n;
assign afi_we_n = int_we_n;
assign afi_ba = int_ba;
assign afi_addr = int_addr;
end
else
begin
assign afi_cke = {int_cke,int_cke_r};
assign afi_cs_n = {int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}}; // to provide time for addr bus to settle at high freq, cs sent on 2nd phase
assign afi_ras_n = {int_ras_n,int_ras_n};
assign afi_cas_n = {int_cas_n,int_cas_n};
assign afi_we_n = {int_we_n,int_we_n};
assign afi_ba = {int_ba,int_ba};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n) // aligns cke with cs for slf rfsh & pwrdwn(lpddr1)which is defined only when cs_n goes low
begin
if (!ctl_reset_n)
int_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b0}};
else
int_cke_r <= int_cke;
end
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
begin
if (!ctl_reset_n)
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
else
if ((bg_do_self_refresh) || (bg_do_deep_pdown && cfg_type == `MMR_TYPE_LPDDR1)) //LPDDDR1
chip_in_self_refresh <= bg_to_chip;
else
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
combi_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n_r <= {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n_r <= 1'b1;
combi_cas_n_r <= 1'b1;
combi_we_n_r <= 1'b1;
combi_ba_r <= {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr_r <= {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else
begin
combi_cke_r <= combi_cke;
combi_cs_n_r <= combi_cs_n;
combi_ras_n_r <= combi_ras_n;
combi_cas_n_r <= combi_cas_n;
combi_we_n_r <= combi_we_n;
combi_ba_r <= combi_ba;
combi_addr_r <= combi_addr;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_ras_n = combi_ras_n_r;
int_cas_n = combi_cas_n_r;
int_we_n = combi_we_n_r;
int_ba = combi_ba_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_ras_n = combi_ras_n;
int_cas_n = combi_cas_n;
int_we_n = combi_we_n;
int_ba = combi_ba;
int_addr = combi_addr;
end
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(bg_do_self_refresh | bg_do_power_down | bg_do_deep_pdown);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
//Pulse generator for self refresh, power down and deep power down
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_self_refresh_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_power_down_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_deep_pdown_r <= {(CFG_MEM_IF_CHIP){1'b0}};
end
else
begin
do_self_refresh_r <= ~bg_do_self_refresh;
do_power_down_r <= ~bg_do_power_down;
do_deep_pdown_r <= ~bg_do_deep_pdown;
end
end
always @(*)
begin
do_self_refresh = bg_do_self_refresh & do_self_refresh_r;
do_power_down = bg_do_power_down & do_power_down_r;
do_deep_pdown = bg_do_deep_pdown & do_deep_pdown_r;
end
always @(*) //All Command inputs are mutually exclusive
begin
if (ctl_cal_success)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; //Should we put default condition into if(!bg_do_refresh && !bg_do_activate....)??
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|bg_do_refresh)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_refresh;
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|bg_do_precharge_all)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_precharge_all;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr[10]= 1'b1;
end
if (bg_do_activate)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = bg_to_bank;
combi_addr = int_row;
end
if (bg_do_precharge)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (bg_do_write)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr = int_col;
end
if (bg_do_read)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = bg_to_bank;
combi_addr = int_col;
end
if (|do_power_down)
begin
// combi_cke = ~bg_to_chip;
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|do_deep_pdown) //Put assertion for memory type ddr2 and ddr3 as an error
begin
// combi_cke = ~bg_to_chip;
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~do_deep_pdown; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|do_self_refresh)
begin
// combi_cke = ~bg_to_chip;
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|bg_do_zq_cal) // Only short zqcal supported
begin
if (cfg_type == `MMR_TYPE_DDR3) //DDR3
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_zq_cal;
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else // Should we flag error or issue as NOP
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
if (bg_do_lmr)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; // to support chng rfsh time based on temp
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b0;
combi_ba = bg_to_lmr;
combi_addr = lmr_opcode;
end
if (bg_do_burst_terminate)
begin
if (cfg_type == `MMR_TYPE_LPDDR1) //lpddr1
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
end
else
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
module alt_mem_ddrx_addr_cmd_wrap
# ( parameter
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CKE_WIDTH = 2, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_LPDDR2_ENABLED = 1,
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_LOCAL_ID_WIDTH = 8,
CFG_DATA_ID_WIDTH = 4,
CFG_INT_SIZE_WIDTH = 4,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_CAS_WR_LAT = 5,
CFG_PORT_WIDTH_TCL = 5,
CFG_PORT_WIDTH_ADD_LAT = 5,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 1
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd_for_afi_output,
// burst generator command signals
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_lmr_read,
bg_do_refresh_1bank,
bg_do_zq_cal,
bg_do_lmr,
bg_localid,
bg_dataid,
bg_size,
// burst generator address signals
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_rst_n,
afi_odt
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam CFG_FR_DWIDTH_RATIO = 2;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk ;
input ctl_reset_n ;
input ctl_cal_success ;
//run-time csr chain input
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type ;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl ;
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat ;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat ;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip ;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip ;
input [4:0] cfg_burst_length ;
//output regd signal from rdwr_tmg block
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
//command inputs
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col ;
input bg_do_lmr_read ;
input bg_do_refresh_1bank ;
input [7:0] bg_to_lmr ;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid ;
input [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid ;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size ;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode ;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// port type declaration
// -----------------------------
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
reg [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
reg [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// signal declaration
// -----------------------------
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_correct ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_partial ;
wire [CFG_MEM_IF_CKE_WIDTH- 1:0] int_afi_cke [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_ras_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_cas_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_we_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_ADDR_WIDTH:0] int_afi_addr [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rst_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_correct [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_partial [(CFG_DWIDTH_RATIO/2)-1:0];
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cke ;
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cs_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_ras_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_cas_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_we_n ;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_ba ;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_addr ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rst_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_correct ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_partial ;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_rst_n;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_write ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_read ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_chop ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_terminate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_auto_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_activate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct_r ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_precharge_all [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_self_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_power_down [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_deep_pdown [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_zq_cal [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_lmr ;
reg [CFG_MEM_IF_CHIP -1:0] int_bg_to_chip [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_col [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] int_bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_bg_size;
reg int_bg_do_lmr_read;
reg int_bg_do_refresh_1bank;
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] cfg_enable_chipsel_for_sideband;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh_r;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown_r;
wire one = 1'b1;
wire zero = 1'b0;
// -----------------------------
// module definition
// -----------------------------
genvar afi_j, afi_n;
generate
// map int_afi_* multi-dimensional array signals to afi_* output port signals
for (afi_n = 0; afi_n < (CFG_DWIDTH_RATIO/2); afi_n = afi_n + 1'b1)
begin : gen_afi_signals
always @ (*)
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n [afi_n] ;
//afi_odt [((afi_n+1) * CFG_MEM_IF_ODT_WIDTH) -1 : (afi_n * CFG_MEM_IF_ODT_WIDTH)] = int_afi_odt [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial [afi_n] ;
end
end
// generate int_afi_* signals based on CFG_DWIDTH_RATIO & CFG_AFI_INTF_PHASE_NUM
if (CFG_DWIDTH_RATIO == 2)
begin
// full rate, with any phase
assign int_afi_cke [0] = fr_afi_cke ;
assign int_afi_cs_n [0] = fr_afi_cs_n ;
assign int_afi_ras_n [0] = fr_afi_ras_n ;
assign int_afi_cas_n [0] = fr_afi_cas_n ;
assign int_afi_we_n [0] = fr_afi_we_n ;
assign int_afi_ba [0] = fr_afi_ba ;
assign int_afi_addr [0] = fr_afi_addr ;
assign int_afi_rst_n [0] = fr_afi_rst_n ;
assign int_afi_rmw_correct [0] = fr_afi_rmw_correct ;
assign int_afi_rmw_partial [0] = fr_afi_rmw_partial ;
end
else if ((CFG_DWIDTH_RATIO/2) == CFG_AFI_INTF_PHASE_NUM)
begin
// map phase_afi_* signals to int_afi_* signals
// half rate , with phase=2
// quarter rate, with phase=4
for (afi_j = 0; afi_j < CFG_AFI_INTF_PHASE_NUM; afi_j = afi_j + 1'b1)
begin : gen_afi_signals_0
assign int_afi_cke [afi_j] = phase_afi_cke [afi_j] ;
assign int_afi_cs_n [afi_j] = phase_afi_cs_n [afi_j] ;
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j] ;
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j] ;
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j] ;
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j] ;
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j] ;
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j] ;
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j] ;
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j] ;
end
end
else // only supports case CFG_AFI_INTF_PHASE_NUM < (CFG_DWIDTH_RATIO/2)
begin
// map phase_afi_* signals to selected int_afi_* signals, and drive the rest to default values
// for cs_n signals:
// half rate , with phase=1, drives int_afi_* 1 only
// quarter rate , with phase=2, drives int_afi_* 1 & 3
// for other signals:
// half rate , with phase=1, drives int_afi_* 0 & 1 with the same value
// quarter rate , with phase=2, drives int_afi_* 0 & 1 or 2 & 3 with the same value
// Why? to improve timing margin on PHY side
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_1
// Assign even phase with '1' because we only issue on odd phase (2T timing)
assign int_afi_cs_n [afi_j] = ((afi_j % CFG_AFI_INTF_PHASE_NUM) == 1) ? phase_afi_cs_n [afi_j / CFG_AFI_INTF_PHASE_NUM] : { CFG_MEM_IF_CHIP {1'b1} };
// Assign the last CKE with phase_afi_cs_n[1], the rest with phase_afi_cs_n[0]
assign int_afi_cke [afi_j] = (afi_j == ((CFG_DWIDTH_RATIO/2) - 1)) ? phase_afi_cke [1] : phase_afi_cke [0];
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j / CFG_AFI_INTF_PHASE_NUM];
end
end
endgenerate
// phase_afi_* signal generation
// instantiates an alt_mem_ddrx_addr_cmd for every phase
// maps bg_* signals to the correct instantiation
genvar afi_k;
generate
for (afi_k = 0; afi_k < CFG_AFI_INTF_PHASE_NUM; afi_k = afi_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_write [afi_k] = bg_do_write [afi_k];
int_bg_do_read [afi_k] = bg_do_read [afi_k];
int_bg_do_burst_chop [afi_k] = bg_do_burst_chop [afi_k];
int_bg_do_burst_terminate [afi_k] = bg_do_burst_terminate [afi_k];
int_bg_do_auto_precharge [afi_k] = bg_do_auto_precharge [afi_k];
int_bg_do_rmw_correct [afi_k] = bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial [afi_k] = bg_do_rmw_partial [afi_k];
int_bg_do_activate [afi_k] = bg_do_activate [afi_k];
int_bg_do_precharge [afi_k] = bg_do_precharge [afi_k];
int_bg_to_chip [afi_k] = bg_to_chip [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_to_bank [afi_k] = bg_to_bank [(((afi_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(afi_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [afi_k] = bg_to_row [(((afi_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(afi_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_col [afi_k] = bg_to_col [(((afi_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(afi_k*CFG_MEM_IF_COL_WIDTH)];
end
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_refresh [afi_k] = bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_self_refresh [afi_k] = bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_deep_pdown [afi_k] = bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_zq_cal [afi_k] = bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_lmr [afi_k] = bg_do_lmr [afi_k];
end
always @ (*)
begin
cfg_enable_chipsel_for_sideband [afi_k] = one;
end
end
else // half and quarter rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : 0;
int_bg_do_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : 0;
int_bg_do_zq_cal [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : 0;
int_bg_do_lmr [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_lmr [afi_k ] : 0;
// We need to assign these command to all phase
// because these command might take one or more controller clock cycles
// and we want to prevent CKE from toggling due to prolong commands
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_self_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_self_refresh_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_deep_pdown [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_deep_pdown_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
end
always @ (*)
begin
// We need to disable one phase of chipsel logic for sideband in half/quarter rate
// in order to prevent CS_N from going low for 2 clock cycles (deep power down and self refresh only)
cfg_enable_chipsel_for_sideband [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? one : zero;
end
end
// addresss command block instantiated based on number of phases
alt_mem_ddrx_addr_cmd # (
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO ( CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_addr_cmd_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_cal_success ( ctl_cal_success ),
.cfg_type ( cfg_type ),
.cfg_output_regd ( cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband ( cfg_enable_chipsel_for_sideband [afi_k] ),
.bg_do_write ( int_bg_do_write [afi_k] ),
.bg_do_read ( int_bg_do_read [afi_k] ),
.bg_do_auto_precharge ( int_bg_do_auto_precharge [afi_k] ),
.bg_do_burst_chop ( int_bg_do_burst_chop [afi_k] ),
.bg_do_activate ( int_bg_do_activate [afi_k] ),
.bg_do_precharge ( int_bg_do_precharge [afi_k] ),
.bg_do_refresh ( int_bg_do_refresh [afi_k] ),
.bg_do_power_down ( int_bg_do_power_down [afi_k] ),
.bg_do_self_refresh ( int_bg_do_self_refresh [afi_k] ),
.bg_do_lmr ( int_bg_do_lmr [afi_k] ),
.bg_do_precharge_all ( int_bg_do_precharge_all [afi_k] ),
.bg_do_zq_cal ( int_bg_do_zq_cal [afi_k] ),
.bg_do_deep_pdown ( int_bg_do_deep_pdown [afi_k] ),
.bg_do_burst_terminate ( int_bg_do_burst_terminate [afi_k] ),
.bg_to_chip ( int_bg_to_chip [afi_k] ),
.bg_to_bank ( int_bg_to_bank [afi_k] ),
.bg_to_row ( int_bg_to_row [afi_k] ),
.bg_to_col ( int_bg_to_col [afi_k] ),
.bg_to_lmr ( ),
.lmr_opcode ( lmr_opcode ),
.afi_cke ( int_ddrx_afi_cke [afi_k] ),
.afi_cs_n ( int_ddrx_afi_cs_n [afi_k] ),
.afi_ras_n ( int_ddrx_afi_ras_n [afi_k] ),
.afi_cas_n ( int_ddrx_afi_cas_n [afi_k] ),
.afi_we_n ( int_ddrx_afi_we_n [afi_k] ),
.afi_ba ( int_ddrx_afi_ba [afi_k] ),
.afi_addr ( int_ddrx_afi_addr [afi_k] ),
.afi_rst_n ( int_ddrx_afi_rst_n [afi_k] )
);
if (CFG_LPDDR2_ENABLED)
begin
alt_mem_ddrx_lpddr2_addr_cmd # (
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_lpddr2_addr_cmd_inst (
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.do_write (int_bg_do_write [afi_k] ),
.do_read (int_bg_do_read [afi_k] ),
.do_auto_precharge (int_bg_do_auto_precharge [afi_k] ),
.do_activate (int_bg_do_activate [afi_k] ),
.do_precharge (int_bg_do_precharge [afi_k] ),
.do_refresh (int_bg_do_refresh [afi_k] ),
.do_power_down (int_bg_do_power_down [afi_k] ),
.do_self_refresh (int_bg_do_self_refresh [afi_k] ),
.do_lmr (int_bg_do_lmr [afi_k] ),
.do_precharge_all (int_bg_do_precharge_all [afi_k] ),
.do_deep_pwrdwn (int_bg_do_deep_pdown [afi_k] ),
.do_burst_terminate (int_bg_do_burst_terminate [afi_k] ),
.do_lmr_read (int_bg_do_lmr_read ),
.do_refresh_1bank (int_bg_do_refresh_1bank ),
.to_chip (int_bg_to_chip [afi_k] ),
.to_bank (int_bg_to_bank [afi_k] ),
.to_row (int_bg_to_row [afi_k] ),
.to_col (int_bg_to_col [afi_k] ),
.to_lmr ( ),
.lmr_opcode (lmr_opcode[7:0] ),
.afi_cke (int_lpddr2_afi_cke [afi_k] ),
.afi_cs_n (int_lpddr2_afi_cs_n [afi_k] ),
.afi_addr (int_lpddr2_afi_addr [afi_k] ),
.afi_rst_n (int_lpddr2_afi_rst_n [afi_k] )
);
end
else
begin
assign int_lpddr2_afi_cke [afi_k] = {(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_cs_n [afi_k] = {(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_addr [afi_k] = {(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_rst_n [afi_k] = { (CFG_FR_DWIDTH_RATIO/2) {1'b0}};
end
always @ (*)
begin
// Mux to select ddrx or lpddr2 addrcmd decoder blocks
if (cfg_type == `MMR_TYPE_LPDDR2)
begin
phase_afi_cke [afi_k] = int_lpddr2_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_lpddr2_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_cas_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_we_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_ba [afi_k] = {(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
phase_afi_addr [afi_k] = int_lpddr2_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_lpddr2_afi_rst_n[afi_k] ;
end
else
begin
phase_afi_cke [afi_k] = int_ddrx_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_ddrx_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = int_ddrx_afi_ras_n [afi_k] ;
phase_afi_cas_n [afi_k] = int_ddrx_afi_cas_n [afi_k] ;
phase_afi_we_n [afi_k] = int_ddrx_afi_we_n [afi_k] ;
phase_afi_ba [afi_k] = int_ddrx_afi_ba [afi_k] ;
phase_afi_addr [afi_k] = int_ddrx_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_ddrx_afi_rst_n [afi_k] ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_bg_do_rmw_correct_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
int_bg_do_rmw_partial_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
end
else
begin
int_bg_do_rmw_correct_r[afi_k] <= int_bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial_r[afi_k] <= int_bg_do_rmw_partial [afi_k];
end
end
always @ (*)
begin
if (cfg_output_regd_for_afi_output)
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct_r [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial_r [afi_k];
end
else
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial [afi_k];
end
end
alt_mem_ddrx_odt_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
odt_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.bg_do_read (int_bg_do_read [afi_k]),
.bg_do_write (int_bg_do_write [afi_k]),
.bg_do_burst_chop (int_bg_do_burst_chop [afi_k]),
.bg_to_chip (int_bg_to_chip [afi_k]),
.afi_odt (afi_odt_h_l [afi_k])
);
end
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
int_bg_do_lmr_read = bg_do_lmr_read;
int_bg_do_refresh_1bank = bg_do_refresh_1bank;
end
endgenerate
// ODT output generation
always @ (*)
begin
afi_odt = mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1];
end
// generate ODT output signal from odt_gen
assign mux_afi_odt_h_l [0] = afi_odt_h_l [0];
genvar afi_m;
generate
for (afi_m = 1; afi_m < CFG_AFI_INTF_PHASE_NUM; afi_m = afi_m + 1)
begin : mux_for_odt
assign mux_afi_odt_h_l [afi_m] = mux_afi_odt_h_l [afi_m-1] | afi_odt_h_l [afi_m];
end
endgenerate
// generate fr_* signals from phase_* signals
assign mux_afi_cke [0] = phase_afi_cke [0];
assign mux_afi_cs_n [0] = phase_afi_cs_n [0];
assign mux_afi_ras_n [0] = phase_afi_ras_n [0];
assign mux_afi_cas_n [0] = phase_afi_cas_n [0];
assign mux_afi_we_n [0] = phase_afi_we_n [0];
assign mux_afi_ba [0] = phase_afi_ba [0];
assign mux_afi_addr [0] = phase_afi_addr [0];
assign mux_afi_rst_n [0] = phase_afi_rst_n [0];
assign mux_afi_rmw_correct [0] = phase_afi_rmw_correct [0];
assign mux_afi_rmw_partial [0] = phase_afi_rmw_partial [0];
genvar afi_l;
generate
for (afi_l = 1; afi_l < CFG_AFI_INTF_PHASE_NUM; afi_l = afi_l + 1)
begin : gen_resolve_phase_for_fullrate
assign mux_afi_cke [afi_l] = mux_afi_cke [(afi_l-1)] & phase_afi_cke [afi_l];
assign mux_afi_cs_n [afi_l] = mux_afi_cs_n [(afi_l-1)] & phase_afi_cs_n [afi_l];
assign mux_afi_ras_n [afi_l] = mux_afi_ras_n [(afi_l-1)] & phase_afi_ras_n [afi_l];
assign mux_afi_cas_n [afi_l] = mux_afi_cas_n [(afi_l-1)] & phase_afi_cas_n [afi_l];
assign mux_afi_we_n [afi_l] = mux_afi_we_n [(afi_l-1)] & phase_afi_we_n [afi_l];
assign mux_afi_ba [afi_l] = mux_afi_ba [(afi_l-1)] | phase_afi_ba [afi_l];
assign mux_afi_addr [afi_l] = mux_afi_addr [(afi_l-1)] | phase_afi_addr [afi_l];
assign mux_afi_rst_n [afi_l] = mux_afi_rst_n [(afi_l-1)] | phase_afi_rst_n [afi_l];
assign mux_afi_rmw_correct [afi_l] = mux_afi_rmw_correct [(afi_l-1)] | phase_afi_rmw_correct [afi_l];
assign mux_afi_rmw_partial [afi_l] = mux_afi_rmw_partial [(afi_l-1)] | phase_afi_rmw_partial [afi_l];
end
endgenerate
assign fr_afi_cke = mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cs_n = mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ras_n = mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cas_n = mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_we_n = mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ba = mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_addr = mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rst_n = mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_correct = mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_partial = mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
// Registered version of self refresh and power down
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bg_do_self_refresh_r <= 0;
bg_do_deep_pdown_r <= 0;
end
else
begin
bg_do_self_refresh_r <= bg_do_self_refresh;
bg_do_deep_pdown_r <= bg_do_deep_pdown;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_arbiter #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_REG_REQ = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_DISABLE_PRIORITY = 1
)
(
ctl_clk,
ctl_reset_n,
// Common
stall_row_arbiter,
stall_col_arbiter,
// Sideband Interface
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
// TBP Interface
row_req,
col_req,
act_req,
pch_req,
rd_req,
wr_req,
row_grant,
col_grant,
act_grant,
pch_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_activate,
tbp_precharge,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_rmw_correct,
tbp_rmw_partial,
tbp_age,
tbp_priority,
// Rank Timer Interface
can_activate,
can_precharge,
can_write,
can_read,
// Arbiter Output Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// Common
input stall_row_arbiter;
input stall_col_arbiter;
// Sideband Interface
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
// TBP Interface
input [CFG_CTL_TBP_NUM - 1 : 0] row_req;
input [CFG_CTL_TBP_NUM - 1 : 0] col_req;
input [CFG_CTL_TBP_NUM - 1 : 0] act_req;
input [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
input [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
input [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
output [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
output or_row_grant;
output or_col_grant;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
input [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
input [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
input [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
input [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
// Rank Timer Interface
input [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] can_write;
input [CFG_CTL_TBP_NUM - 1 : 0] can_read;
// Arbiter Output Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
wire one = 1'b1;
wire zero = 1'b0;
// TBP Interface
reg [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
reg or_row_grant;
reg or_col_grant;
// Arbiter Output Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// Common
reg granted_read [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_write [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_c ;
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_COL_WIDTH - 1 : 0] granted_col [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_INT_SIZE_WIDTH - 1 : 0] granted_size [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_DATA_ID_WIDTH - 1 : 0] granted_dataid [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] granted_localid [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_ap [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_burst_chop [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_correct [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_partial [CFG_CTL_TBP_NUM - 1 : 0];
// Arbiter
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_wr_grant;
reg int_or_row_grant;
reg int_or_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_wr_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] all_grant;
//--------------------------------------------------------------------------------------------------------
//
// [END] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Granted logic specific grant signals
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
granted_row_grant = row_grant;
granted_col_grant = col_grant;
granted_act_grant = act_grant;
granted_pch_grant = pch_grant;
granted_rd_grant = rd_grant;
granted_wr_grant = wr_grant;
log2_granted_row_grant = log2_row_grant;
log2_granted_col_grant = log2_col_grant;
log2_granted_act_grant = log2_act_grant;
log2_granted_pch_grant = log2_pch_grant;
log2_granted_rd_grant = log2_rd_grant;
log2_granted_wr_grant = log2_wr_grant;
end
//----------------------------------------------------------------------------------------------------
// Sideband outputs
//----------------------------------------------------------------------------------------------------
// Precharge all
always @ (*)
begin
arb_do_precharge_all = {CFG_AFI_INTF_PHASE_NUM{sb_do_precharge_all}};
end
// Refresh
always @ (*)
begin
arb_do_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_refresh}};
end
// Self refresh
always @ (*)
begin
arb_do_self_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_self_refresh}};
end
// Power down
always @ (*)
begin
arb_do_power_down = {CFG_AFI_INTF_PHASE_NUM{sb_do_power_down}};
end
// Power down
always @ (*)
begin
arb_do_deep_pdown = {CFG_AFI_INTF_PHASE_NUM{sb_do_deep_pdown}};
end
// ZQ calibration
always @ (*)
begin
arb_do_zq_cal = {CFG_AFI_INTF_PHASE_NUM{sb_do_zq_cal}};
end
// LMR
always @ (*)
begin
arb_do_lmr = {CFG_AFI_INTF_PHASE_NUM{zero}};
end
//----------------------------------------------------------------------------------------------------
// Non arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
// Burst chop
always @ (*)
begin
arb_do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{granted_burst_chop [CFG_CTL_TBP_NUM - 1]}};
end
// Burst terminate
always @ (*)
begin
arb_do_burst_terminate = 0;
end
// RMW Correct
always @ (*)
begin
arb_do_rmw_correct = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_correct [CFG_CTL_TBP_NUM - 1]}};
end
// RMW Partial
always @ (*)
begin
arb_do_rmw_partial = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_partial [CFG_CTL_TBP_NUM - 1]}};
end
// LMR
always @ (*)
begin
arb_do_lmr = 0;
end
// Local ID
always @ (*)
begin
arb_localid = granted_localid [CFG_CTL_TBP_NUM - 1];
end
// Data ID
always @ (*)
begin
arb_dataid = granted_dataid [CFG_CTL_TBP_NUM - 1];
end
// Size
always @ (*)
begin
arb_size = granted_size [CFG_CTL_TBP_NUM - 1];
end
// Column address
// column command will only require column address, therefore there will be no conflcting column addresses
always @ (*)
begin
arb_to_col = {CFG_AFI_INTF_PHASE_NUM{granted_col [CFG_CTL_TBP_NUM - 1]}};
end
//----------------------------------------------------------------------------------------------------
// Arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_LOW_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_LOW_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_LOW_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_HIGH_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_HIGH_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_r [CFG_CTL_TBP_NUM - 1], granted_chipsel_c [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_r, granted_to_chip_c};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_r [CFG_CTL_TBP_NUM - 1], granted_bank_c [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_r [CFG_CTL_TBP_NUM - 1], granted_row_c [CFG_CTL_TBP_NUM - 1]};
end
end
else
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_HIGH_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_HIGH_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_HIGH_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_LOW_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_LOW_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_c [CFG_CTL_TBP_NUM - 1], granted_chipsel_r [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_c, granted_to_chip_r};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_c [CFG_CTL_TBP_NUM - 1], granted_bank_r [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_c [CFG_CTL_TBP_NUM - 1], granted_row_r [CFG_CTL_TBP_NUM - 1]};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Granted outputs
//----------------------------------------------------------------------------------------------------
// Chip address
always @ (*)
begin
granted_chipsel_r [0] = {CFG_MEM_IF_CS_WIDTH {granted_row_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
granted_chipsel_c [0] = {CFG_MEM_IF_CS_WIDTH {granted_col_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
end
// Bank address
always @ (*)
begin
granted_bank_r [0] = {CFG_MEM_IF_BA_WIDTH {granted_row_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
granted_bank_c [0] = {CFG_MEM_IF_BA_WIDTH {granted_col_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
end
// Row address
always @ (*)
begin
granted_row_r [0] = {CFG_MEM_IF_ROW_WIDTH{granted_row_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
granted_row_c [0] = {CFG_MEM_IF_ROW_WIDTH{granted_col_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
end
// Column address
always @ (*)
begin
granted_col [0] = {CFG_MEM_IF_COL_WIDTH{granted_col_grant [0]}} & tbp_col [CFG_MEM_IF_COL_WIDTH - 1 : 0];
end
// Size
always @ (*)
begin
granted_size [0] = {CFG_INT_SIZE_WIDTH {granted_col_grant [0]}} & tbp_size [CFG_INT_SIZE_WIDTH - 1 : 0];
end
// Local ID
always @ (*)
begin
granted_localid [0] = {CFG_LOCAL_ID_WIDTH {granted_col_grant [0]}} & tbp_localid [CFG_LOCAL_ID_WIDTH - 1 : 0];
end
// Data ID
always @ (*)
begin
granted_dataid [0] = {CFG_DATA_ID_WIDTH {granted_col_grant [0]}} & tbp_dataid [CFG_DATA_ID_WIDTH - 1 : 0];
end
// Auto precharge
always @ (*)
begin
granted_ap [0] = granted_col_grant [0] & tbp_ap [ 0];
end
// Burst Chop
always @ (*)
begin
granted_burst_chop [0] = granted_col_grant [0] & tbp_burst_chop [ 0];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [0] = granted_col_grant [0] & tbp_rmw_correct [ 0];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [0] = granted_col_grant [0] & tbp_rmw_partial [ 0];
end
generate
begin
genvar j_tbp;
for (j_tbp = 1;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : granted_information_per_tbp
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] chipsel_addr = tbp_chipsel [(j_tbp + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j_tbp * CFG_MEM_IF_CS_WIDTH ];
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] bank_addr = tbp_bank [(j_tbp + 1) * CFG_MEM_IF_BA_WIDTH - 1 : j_tbp * CFG_MEM_IF_BA_WIDTH ];
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] row_addr = tbp_row [(j_tbp + 1) * CFG_MEM_IF_ROW_WIDTH - 1 : j_tbp * CFG_MEM_IF_ROW_WIDTH];
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] col_addr = tbp_col [(j_tbp + 1) * CFG_MEM_IF_COL_WIDTH - 1 : j_tbp * CFG_MEM_IF_COL_WIDTH];
wire [CFG_INT_SIZE_WIDTH - 1 : 0] size = tbp_size [(j_tbp + 1) * CFG_INT_SIZE_WIDTH - 1 : j_tbp * CFG_INT_SIZE_WIDTH ];
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] localid = tbp_localid [(j_tbp + 1) * CFG_LOCAL_ID_WIDTH - 1 : j_tbp * CFG_LOCAL_ID_WIDTH ];
wire [CFG_DATA_ID_WIDTH - 1 : 0] dataid = tbp_dataid [(j_tbp + 1) * CFG_DATA_ID_WIDTH - 1 : j_tbp * CFG_DATA_ID_WIDTH ];
wire ap = tbp_ap [(j_tbp + 1) - 1 : j_tbp ];
wire burst_chop = tbp_burst_chop [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_correct = tbp_rmw_correct [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_partial = tbp_rmw_partial [(j_tbp + 1) - 1 : j_tbp ];
// Chip address
always @ (*)
begin
granted_chipsel_r [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_row_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_r [j_tbp - 1];
granted_chipsel_c [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_col_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_c [j_tbp - 1];
end
// Bank address
always @ (*)
begin
granted_bank_r [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_row_grant [j_tbp]}} & bank_addr ) | granted_bank_r [j_tbp - 1];
granted_bank_c [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_col_grant [j_tbp]}} & bank_addr ) | granted_bank_c [j_tbp - 1];
end
// Row address
always @ (*)
begin
granted_row_r [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_row_grant [j_tbp]}} & row_addr ) | granted_row_r [j_tbp - 1];
granted_row_c [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_col_grant [j_tbp]}} & row_addr ) | granted_row_c [j_tbp - 1];
end
// Column address
always @ (*)
begin
granted_col [j_tbp] = ({CFG_MEM_IF_COL_WIDTH{granted_col_grant [j_tbp]}} & col_addr ) | granted_col [j_tbp - 1];
end
// Size
always @ (*)
begin
granted_size [j_tbp] = ({CFG_INT_SIZE_WIDTH {granted_col_grant [j_tbp]}} & size ) | granted_size [j_tbp - 1];
end
// Local ID
always @ (*)
begin
granted_localid [j_tbp] = ({CFG_LOCAL_ID_WIDTH {granted_col_grant [j_tbp]}} & localid ) | granted_localid [j_tbp - 1];
end
// Data ID
always @ (*)
begin
granted_dataid [j_tbp] = ({CFG_DATA_ID_WIDTH {granted_col_grant [j_tbp]}} & dataid ) | granted_dataid [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_ap [j_tbp] = ( granted_col_grant [j_tbp] & ap ) | granted_ap [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_burst_chop [j_tbp] = ( granted_col_grant [j_tbp] & burst_chop ) | granted_burst_chop [j_tbp - 1];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [j_tbp] = ( granted_col_grant [j_tbp] & rmw_correct ) | granted_rmw_correct [j_tbp - 1];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [j_tbp] = ( granted_col_grant [j_tbp] & rmw_partial ) | granted_rmw_partial [j_tbp - 1];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Arbiter
//
// Arbitration Rules (Priority Command-Aging Arbiter):
//
// - If only one master is requesting, grant that master immediately ELSE
// - If two of more masters are requesting:
// - Grant the request with priority ELSE
// - Grant read request over write request ELSE
// - Grant oldest request
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common logic
//----------------------------------------------------------------------------------------------------
// Indicate OR of both grant signal
assign all_grant = row_grant | col_grant;
//----------------------------------------------------------------------------------------------------
// Priority Command-aging logic
//----------------------------------------------------------------------------------------------------
// ==========Command-Aging==========
//
// The following logic will check for the oldest requesting commands by cross checking between age dependencies & request
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies will have the following value:
// TBP0 age - 0000
// TBP1 age - 0001
// TBP2 age - 0011
// TBP3 age - 0111
// Let say TBP1 and TBP2 are requesting at the same time, we would want the command-aging logic to pick TBP1 instead of TBP2
// TBP2 have age dependencies on TBP1, this will cause oldest_req[2] signal to be set to '0'
// TBP1 have no age dependencies on TBP2, this will cause oldest_req[1] signal to be set to '1'
// So the oldest_req signal will have "0010"
//
// ==========Priority==========
//
// The following logic will have similar logic as command-aging logic, this logic will pick commands with priority bit set
// if there are more than 1 priority command, it will pick the oldest priority command
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies and priority bit will have the following value:
// TBP0 age - 0000 priority - 0
// TBP1 age - 0001 priority - 1
// TBP2 age - 0011 priority - 1
// TBP3 age - 0111 priority - 0
// Let say all TBPs are requesting at the same time, priority_req [1] will be set to '1' because it is the oldest priority command
// and the rest will be set to '0'
// If there is/are priority command/s, we need to select between those priority command
// if there is no priority command, we set int_priority to all '1'
// this will cause arbiter to select between all commands which will provide with similar result as non-priority command-aging arbiter
always @ (*)
begin
int_act_priority = {CFG_CTL_TBP_NUM{one}};
int_pch_priority = {CFG_CTL_TBP_NUM{one}};
if (CFG_DISABLE_PRIORITY == 1)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
if ((tbp_priority & col_req) == 0)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
int_col_priority = tbp_priority;
end
end
end
generate
begin
genvar k_tbp;
for (k_tbp = 0;k_tbp < CFG_CTL_TBP_NUM;k_tbp = k_tbp + 1)
begin : priority_request_per_tbp
wire [CFG_CTL_TBP_NUM - 1 : 0] current_age = tbp_age [(k_tbp + 1) * CFG_CTL_TBP_NUM - 1 : k_tbp * CFG_CTL_TBP_NUM];
reg pre_calculated_act_info;
reg pre_calculated_pch_info;
reg pre_calculated_rd_info;
reg pre_calculated_wr_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_act_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_pch_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_rd_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_wr_age_info;
if (CFG_REG_REQ)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_info <= 1'b0;
pre_calculated_pch_info <= 1'b0;
pre_calculated_rd_info <= 1'b0;
pre_calculated_wr_info <= 1'b0;
end
else
begin
pre_calculated_act_info <= int_act_priority [k_tbp];
pre_calculated_pch_info <= int_pch_priority [k_tbp];
pre_calculated_rd_info <= int_col_priority [k_tbp];
pre_calculated_wr_info <= int_col_priority [k_tbp];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_age_info <= 0;
pre_calculated_pch_age_info <= 0;
pre_calculated_rd_age_info <= 0;
pre_calculated_wr_age_info <= 0;
end
else
begin
pre_calculated_act_age_info <= current_age & int_act_priority;
pre_calculated_pch_age_info <= current_age & int_pch_priority;
pre_calculated_rd_age_info <= current_age & int_col_priority;
pre_calculated_wr_age_info <= current_age & int_col_priority;
end
end
end
else
begin
always @ (*)
begin
pre_calculated_act_info = int_act_priority [k_tbp];
pre_calculated_pch_info = int_pch_priority [k_tbp];
pre_calculated_rd_info = int_col_priority [k_tbp];
pre_calculated_wr_info = int_col_priority [k_tbp];
end
always @ (*)
begin
pre_calculated_act_age_info = current_age & int_act_priority;
pre_calculated_pch_age_info = current_age & int_pch_priority;
pre_calculated_rd_age_info = current_age & int_col_priority;
pre_calculated_wr_age_info = current_age & int_col_priority;
end
end
always @ (*)
begin
oldest_act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp] & ~|(pre_calculated_act_age_info & act_req & can_activate );
oldest_pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp] & ~|(pre_calculated_pch_age_info & pch_req & can_precharge);
oldest_rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp] & ~|(pre_calculated_rd_age_info & rd_req & can_read );
oldest_wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp] & ~|(pre_calculated_wr_age_info & wr_req & can_write );
end
always @ (*)
begin
act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp];
pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp];
rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp];
wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp];
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Arbiter logic
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
// Full rate arbiter
always @ (*)
begin
int_row_grant = 0;
int_col_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_row_grant = 1'b0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
end
else
begin
// Half and quarter rate arbiter
// Row arbiter
always @ (*)
begin
int_row_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_or_row_grant = 1'b0;
if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
// Column arbiter
always @ (*)
begin
int_col_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
end
end
end
endgenerate
generate
begin
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
row_grant <= 0;
col_grant <= 0;
act_grant <= 0;
pch_grant <= 0;
rd_grant <= 0;
wr_grant <= 0;
or_row_grant <= 0;
or_col_grant <= 0;
end
else
begin
row_grant <= int_row_grant;
col_grant <= int_col_grant;
act_grant <= int_act_grant;
pch_grant <= int_pch_grant;
rd_grant <= int_rd_grant;
wr_grant <= int_wr_grant;
or_row_grant <= int_or_row_grant;
or_col_grant <= int_or_col_grant;
end
end
always @ (*)
begin
log2_row_grant = log2(row_grant);
log2_col_grant = log2(col_grant);
log2_act_grant = log2(act_grant);
log2_pch_grant = log2(pch_grant);
log2_rd_grant = log2(rd_grant );
log2_wr_grant = log2(wr_grant );
end
end
else
begin
always @ (*)
begin
row_grant = int_row_grant;
col_grant = int_col_grant;
act_grant = int_act_grant;
pch_grant = int_pch_grant;
rd_grant = int_rd_grant;
wr_grant = int_wr_grant;
log2_row_grant = log2(int_row_grant);
log2_col_grant = log2(int_col_grant);
log2_act_grant = log2(int_act_grant);
log2_pch_grant = log2(int_pch_grant);
log2_rd_grant = log2(int_rd_grant );
log2_wr_grant = log2(int_wr_grant );
or_row_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
or_col_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Arbiter
//
//--------------------------------------------------------------------------------------------------------
function integer log2;
input [31 : 0] value;
integer i;
begin
log2 = 0;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_axi_st_converter #
( parameter
AXI_ID_WIDTH = 4,
AXI_ADDR_WIDTH = 32,
AXI_LEN_WIDTH = 4,
AXI_SIZE_WIDTH = 3,
AXI_BURST_WIDTH = 2,
AXI_LOCK_WIDTH = 2,
AXI_CACHE_WIDTH = 4,
AXI_PROT_WIDTH = 3,
AXI_DATA_WIDTH = 32,
AXI_RESP_WIDTH = 4,
ST_ADDR_WIDTH = 32,
ST_SIZE_WIDTH = 5,
ST_ID_WIDTH = 4,
ST_DATA_WIDTH = 32,
COMMAND_ARB_TYPE = "ROUND_ROBIN",
REGISTERED = 1
)
(
ctl_clk,
ctl_reset_n,
// AXI Interface
// Write address channel
awid,
awaddr,
awlen,
awsize,
awburst,
awlock,
awcache,
awprot,
awvalid,
awready,
// Write data channel
wid,
wdata,
wstrb,
wlast,
wvalid,
wready,
// Write response channel
bid,
bresp,
bvalid,
bready,
// Read address channel
arid,
araddr,
arlen,
arsize,
arburst,
arlock,
arcache,
arprot,
arvalid,
arready,
// Read data channel
rid,
rdata,
rresp,
rlast,
rvalid,
rready,
// Avalon ST Interface
// Command channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autoprecharge,
itf_cmd_multicast,
// Write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// Read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
input ctl_clk;
input ctl_reset_n;
// AXI Interface
// Write address channel
input [AXI_ID_WIDTH - 1 : 0] awid;
input [AXI_ADDR_WIDTH - 1 : 0] awaddr;
input [AXI_LEN_WIDTH - 1 : 0] awlen;
input [AXI_SIZE_WIDTH - 1 : 0] awsize;
input [AXI_BURST_WIDTH - 1 : 0] awburst;
input [AXI_LOCK_WIDTH - 1 : 0] awlock;
input [AXI_CACHE_WIDTH - 1 : 0] awcache;
input [AXI_PROT_WIDTH - 1 : 0] awprot;
input awvalid;
output awready;
// Write data channel
input [AXI_ID_WIDTH - 1 : 0] wid;
input [AXI_DATA_WIDTH - 1 : 0] wdata;
input [AXI_DATA_WIDTH / 8 - 1 : 0] wstrb;
input wlast;
input wvalid;
output wready;
// Write response channel
output [AXI_ID_WIDTH - 1 : 0] bid;
output [AXI_RESP_WIDTH - 1 : 0] bresp;
output bvalid;
input bready;
// Read address channel
input [AXI_ID_WIDTH - 1 : 0] arid;
input [AXI_ADDR_WIDTH - 1 : 0] araddr;
input [AXI_LEN_WIDTH - 1 : 0] arlen;
input [AXI_SIZE_WIDTH - 1 : 0] arsize;
input [AXI_BURST_WIDTH - 1 : 0] arburst;
input [AXI_LOCK_WIDTH - 1 : 0] arlock;
input [AXI_CACHE_WIDTH - 1 : 0] arcache;
input [AXI_PROT_WIDTH - 1 : 0] arprot;
input arvalid;
output arready;
// Read data channel
output [AXI_ID_WIDTH - 1 : 0] rid;
output [AXI_DATA_WIDTH - 1 : 0] rdata;
output [AXI_RESP_WIDTH - 1 : 0] rresp;
output rlast;
output rvalid;
input rready;
// Avalon ST Interface
// Command channel
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [ST_ADDR_WIDTH - 1 : 0] itf_cmd_address;
output [ST_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
output [ST_ID_WIDTH - 1 : 0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autoprecharge;
output itf_cmd_multicast;
// Write data channel
input itf_wr_data_ready;
output itf_wr_data_valid;
output [ST_DATA_WIDTH - 1 : 0] itf_wr_data;
output [ST_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [ST_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
output itf_rd_data_ready;
input itf_rd_data_valid;
input [ST_DATA_WIDTH - 1 : 0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [ST_ID_WIDTH - 1 : 0] itf_rd_data_id;
//--------------------------------------------------------------------------------------------------------
//
// [START] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
// AXI outputs
reg awready;
reg wready;
reg [AXI_ID_WIDTH - 1 : 0] bid;
reg [AXI_RESP_WIDTH - 1 : 0] bresp;
reg bvalid;
reg arready;
reg [AXI_ID_WIDTH - 1 : 0] rid;
reg [AXI_DATA_WIDTH - 1 : 0] rdata;
reg [AXI_RESP_WIDTH - 1 : 0] rresp;
reg rlast;
reg rvalid;
// ST outputs
reg itf_cmd_valid;
reg itf_cmd;
reg [ST_ADDR_WIDTH - 1 : 0] itf_cmd_address;
reg [ST_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
reg [ST_ID_WIDTH - 1 : 0] itf_cmd_id;
reg itf_cmd_priority;
reg itf_cmd_autoprecharge;
reg itf_cmd_multicast;
reg itf_wr_data_valid;
reg [ST_DATA_WIDTH - 1 : 0] itf_wr_data;
reg [ST_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
reg itf_wr_data_begin;
reg itf_wr_data_last;
reg [ST_ID_WIDTH - 1 : 0] itf_wr_data_id;
reg itf_rd_data_ready;
wire one = 1'b1;
wire zero = 1'b0;
// Command channel
localparam WORD_ADDR_OFFSET = log2(AXI_DATA_WIDTH / 8);
localparam NATIVE_AXI_SIZE = log2(AXI_DATA_WIDTH) - 3;
integer i;
wire [AXI_ADDR_WIDTH - 1 : 0] byte_rd_addr;
wire [AXI_ADDR_WIDTH - 1 : 0] byte_wr_addr;
wire rd_req;
wire wr_req;
wire [1 : 0] cmd_req;
wire rd_grant;
wire wr_grant;
wire [ST_ID_WIDTH - 1 : 0] rd_id;
wire [ST_ID_WIDTH - 1 : 0] wr_id;
reg [AXI_ID_WIDTH - 1 : 0] int_awid;
reg [AXI_ADDR_WIDTH - 1 : 0] int_awaddr;
reg [AXI_LEN_WIDTH - 1 : 0] int_awlen;
reg [AXI_SIZE_WIDTH - 1 : 0] int_awsize;
reg [AXI_BURST_WIDTH - 1 : 0] int_awburst;
reg [AXI_LOCK_WIDTH - 1 : 0] int_awlock;
reg [AXI_CACHE_WIDTH - 1 : 0] int_awcache;
reg [AXI_PROT_WIDTH - 1 : 0] int_awprot;
reg int_awvalid;
reg [AXI_ID_WIDTH - 1 : 0] int_arid;
reg [AXI_ADDR_WIDTH - 1 : 0] int_araddr;
reg [AXI_LEN_WIDTH - 1 : 0] int_arlen;
reg [AXI_SIZE_WIDTH - 1 : 0] int_arsize;
reg [AXI_BURST_WIDTH - 1 : 0] int_arburst;
reg [AXI_LOCK_WIDTH - 1 : 0] int_arlock;
reg [AXI_CACHE_WIDTH - 1 : 0] int_arcache;
reg [AXI_PROT_WIDTH - 1 : 0] int_arprot;
reg int_arvalid;
reg int_cmd_valid;
reg int_cmd;
reg [ST_ADDR_WIDTH - 1 : 0] int_cmd_address;
reg [ST_SIZE_WIDTH - 1 : 0] int_cmd_burstlen;
reg [ST_ID_WIDTH - 1 : 0] int_cmd_id;
reg int_cmd_priority;
reg int_cmd_autoprecharge;
reg int_cmd_multicast;
reg int_awready;
reg int_arready;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] rd_size;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] wr_size;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] current_size;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] int_size;
reg [AXI_ADDR_WIDTH - 1 : 0] byte_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] byte_addr_counter;
reg [ST_ADDR_WIDTH - 1 : 0] registered_word_addr;
reg [ST_ADDR_WIDTH - 1 : 0] word_rd_addr;
reg [ST_ADDR_WIDTH - 1 : 0] word_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] int_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] int_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_rd_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_wr_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] int_aligned_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_aligned_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_rd_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_wr_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] lower_wrap_boundary_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] upper_wrap_boundary_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] lower_wrap_boundary_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] upper_wrap_boundary_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] lower_wrap_boundary_byte_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] upper_wrap_boundary_byte_addr;
reg upper_boundary_reached;
reg [AXI_BURST_WIDTH - 1 : 0] burst_type;
reg doing_write;
reg [1 : 0] cmd_grant;
reg [1 : 0] prev_cmd_grant;
reg split_axi_cmd;
reg doing_split;
reg [ST_SIZE_WIDTH - 1 : 0] split_counter;
reg [ST_SIZE_WIDTH - 1 : 0] rd_burstlen;
reg [ST_SIZE_WIDTH - 1 : 0] wr_burstlen;
reg int_grant;
reg int_rd_grant;
reg int_wr_grant;
reg int_doing_split;
reg [ST_ID_WIDTH - 1 : 0] registered_id;
// Write data channel
reg int_wr_data_valid;
reg [ST_DATA_WIDTH - 1 : 0] int_wr_data;
reg [ST_DATA_WIDTH / 8 - 1 : 0] int_wr_data_byte_en;
reg int_wr_data_begin;
reg int_wr_data_last;
reg [ST_ID_WIDTH - 1 : 0] int_wr_data_id;
reg write_data_begin_n;
// Write response channel
localparam WR_CMD_FIFO_DATA_WIDTH = AXI_ID_WIDTH;
localparam WR_CMD_FIFO_ADDR_WIDTH = 5; // expected to be able to hold 32 in-flight command information
localparam WR_CMD_FIFO_DEPTH = 2 ** WR_CMD_FIFO_ADDR_WIDTH;
localparam WR_DATA_FIFO_DATA_WIDTH = AXI_ID_WIDTH;
localparam WR_DATA_FIFO_ADDR_WIDTH = 5; // expected to be able to hold 32 in-flight command information
localparam WR_DATA_FIFO_DEPTH = 2 ** WR_DATA_FIFO_ADDR_WIDTH;
wire wr_cmd_fifo_write;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_cmd_fifo_write_data;
wire wr_cmd_fifo_read;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_cmd_fifo_read_data;
wire wr_cmd_fifo_read_data_valid;
wire wr_cmd_fifo_empty;
wire wr_cmd_fifo_almost_full;
wire wr_data_fifo_write;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_data_fifo_write_data;
wire wr_data_fifo_read;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_data_fifo_read_data;
wire wr_data_fifo_read_data_valid;
wire wr_data_fifo_empty;
wire wr_data_fifo_almost_full;
reg wr_cmd_fifo_ready;
reg wr_data_fifo_ready;
reg id_matched;
reg [AXI_ID_WIDTH - 1 : 0] int_bid;
reg [AXI_RESP_WIDTH - 1 : 0] int_bresp;
reg int_bvalid;
// Read data channel
localparam RD_CMD_FIFO_DATA_WIDTH = AXI_LEN_WIDTH + 1;
localparam RD_CMD_FIFO_ADDR_WIDTH = 5; // expected to be able to hold 32 in-flight command information
localparam RD_CMD_FIFO_DEPTH = 2 ** RD_CMD_FIFO_ADDR_WIDTH;
wire rd_cmd_fifo_write;
wire [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] rd_cmd_fifo_write_data;
wire rd_cmd_fifo_read;
wire [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] rd_cmd_fifo_read_data;
wire rd_cmd_fifo_read_data_valid;
wire rd_cmd_fifo_empty;
wire rd_cmd_fifo_almost_full;
reg rd_cmd_fifo_ready;
reg [AXI_ID_WIDTH - 1 : 0] int_rid;
reg [AXI_DATA_WIDTH - 1 : 0] int_rdata;
reg [AXI_RESP_WIDTH - 1 : 0] int_rresp;
reg int_rlast;
reg int_rvalid;
reg int_rd_data_ready;
reg [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] read_data_counter;
reg read_data_last;
//--------------------------------------------------------------------------------------------------------
//
// [END] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Command Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------
// AXI inputs
//--------------------------------------------------------------------------
always @ (*)
begin
int_awid = awid;
int_awaddr = awaddr;
int_awlen = awlen;
int_awsize = awsize;
int_awburst = awburst;
int_awlock = awlock;
int_awcache = awcache;
int_awprot = awprot;
int_awvalid = awvalid;
int_arid = arid;
int_araddr = araddr;
int_arlen = arlen;
int_arsize = arsize;
int_arburst = arburst;
int_arlock = arlock;
int_arcache = arcache;
int_arprot = arprot;
int_arvalid = arvalid;
end
//--------------------------------------------------------------------------
// Size related logics
//--------------------------------------------------------------------------
always @ (*)
begin
rd_size = (2 ** int_arsize);
wr_size = (2 ** int_awsize);
end
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_size <= 0;
end
else
begin
if (rd_grant)
begin
int_size <= rd_size;
end
else if (wr_grant)
begin
int_size <= wr_size;
end
end
end
end
else
begin
always @ (*)
begin
if (rd_grant)
begin
int_size = rd_size;
end
else if (wr_grant)
begin
int_size = wr_size;
end
else
begin
int_size = 0;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
current_size <= 0;
end
else
begin
if (rd_grant)
begin
current_size <= rd_size;
end
else if (wr_grant)
begin
current_size <= wr_size;
end
end
end
//--------------------------------------------------------------------------
// Address related logics
//--------------------------------------------------------------------------
assign byte_rd_addr = int_araddr;
assign byte_wr_addr = int_awaddr;
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_byte_rd_addr <= 0;
int_byte_wr_addr <= 0;
end
else
begin
if (itf_cmd_ready)
begin
int_byte_rd_addr <= byte_rd_addr;
int_byte_wr_addr <= byte_wr_addr;
end
end
end
end
else
begin
always @ (*)
begin
int_byte_rd_addr = byte_rd_addr;
int_byte_wr_addr = byte_wr_addr;
end
end
end
endgenerate
// Obtain address mask for aligned address
always @ (*)
begin
aligned_byte_rd_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
aligned_byte_wr_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
for (i = 0;i < (2 ** AXI_SIZE_WIDTH);i = i + 1'b1)
begin
if (int_arsize > i)
begin
aligned_byte_rd_addr_mask [i] = 1'b0;
end
if (int_awsize > i)
begin
aligned_byte_wr_addr_mask [i] = 1'b0;
end
end
end
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_aligned_byte_rd_addr_mask <= 0;
int_aligned_byte_wr_addr_mask <= 0;
end
else
begin
if (itf_cmd_ready)
begin
int_aligned_byte_rd_addr_mask <= aligned_byte_rd_addr_mask;
int_aligned_byte_wr_addr_mask <= aligned_byte_wr_addr_mask;
end
end
end
end
else
begin
always @ (*)
begin
int_aligned_byte_rd_addr_mask = aligned_byte_rd_addr_mask;
int_aligned_byte_wr_addr_mask = aligned_byte_wr_addr_mask;
end
end
end
endgenerate
// Obtain aligned address
always @ (*)
begin
aligned_byte_rd_addr = (int_byte_rd_addr & int_aligned_byte_rd_addr_mask);
aligned_byte_wr_addr = (int_byte_wr_addr & int_aligned_byte_wr_addr_mask);
end
always @ (*)
begin
if (int_rd_grant)
begin
aligned_byte_addr = aligned_byte_rd_addr;
end
else if (int_wr_grant)
begin
aligned_byte_addr = aligned_byte_wr_addr;
end
else
begin
aligned_byte_addr = 0;
end
end
// Obtain boundary address mask for wrapping burst
always @ (*)
begin
boundary_byte_rd_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
boundary_byte_wr_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
for (i = 0;i < ((2 ** AXI_SIZE_WIDTH) + 4);i = i + 1'b1) // extend by another 4 because max length for wrapping burst is 16
begin
if ((int_arsize + log2_minus_one(int_arlen[3:0])) > i) // constraint burstlen to 4 bits because max length for wrapping burst is 16
begin
boundary_byte_rd_addr_mask [i] = 1'b0;
end
if ((int_awsize + log2_minus_one(int_awlen[3:0])) > i) // constraint burstlen to 4 bits because max length for wrapping burst is 16
begin
boundary_byte_wr_addr_mask [i] = 1'b0;
end
end
end
// Obtain boundary increment value for wrapping burst
always @ (*)
begin
boundary_byte_rd_addr_increment = aligned_byte_rd_addr_mask & ~boundary_byte_rd_addr_mask;
boundary_byte_wr_addr_increment = aligned_byte_wr_addr_mask & ~boundary_byte_wr_addr_mask;
end
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_boundary_byte_rd_addr_mask <= 0;
int_boundary_byte_wr_addr_mask <= 0;
int_boundary_byte_rd_addr_increment <= 0;
int_boundary_byte_wr_addr_increment <= 0;
end
else
begin
if (itf_cmd_ready)
begin
int_boundary_byte_rd_addr_mask <= boundary_byte_rd_addr_mask;
int_boundary_byte_wr_addr_mask <= boundary_byte_wr_addr_mask;
int_boundary_byte_rd_addr_increment <= boundary_byte_rd_addr_increment;
int_boundary_byte_wr_addr_increment <= boundary_byte_wr_addr_increment;
end
end
end
end
else
begin
always @ (*)
begin
int_boundary_byte_rd_addr_mask = boundary_byte_rd_addr_mask;
int_boundary_byte_wr_addr_mask = boundary_byte_wr_addr_mask;
int_boundary_byte_rd_addr_increment = boundary_byte_rd_addr_increment;
int_boundary_byte_wr_addr_increment = boundary_byte_wr_addr_increment;
end
end
end
endgenerate
// Obtain upper and lower boundary of wrapping burst
always @ (*)
begin
lower_wrap_boundary_byte_rd_addr = (int_byte_rd_addr & int_boundary_byte_rd_addr_mask);
lower_wrap_boundary_byte_wr_addr = (int_byte_wr_addr & int_boundary_byte_wr_addr_mask);
upper_wrap_boundary_byte_rd_addr = (int_byte_rd_addr & int_boundary_byte_rd_addr_mask) + int_boundary_byte_rd_addr_increment;
upper_wrap_boundary_byte_wr_addr = (int_byte_wr_addr & int_boundary_byte_wr_addr_mask) + int_boundary_byte_wr_addr_increment;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
lower_wrap_boundary_byte_addr <= 0;
upper_wrap_boundary_byte_addr <= 0;
end
else
begin
if (int_wr_grant)
begin
lower_wrap_boundary_byte_addr <= lower_wrap_boundary_byte_wr_addr;
upper_wrap_boundary_byte_addr <= upper_wrap_boundary_byte_wr_addr;
end
else if (int_rd_grant)
begin
lower_wrap_boundary_byte_addr <= lower_wrap_boundary_byte_rd_addr;
upper_wrap_boundary_byte_addr <= upper_wrap_boundary_byte_rd_addr;
end
end
end
// Byte address counter, to count up for a AXI command with len larger than 1
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
byte_addr_counter <= 0;
end
else
begin
if (int_grant)
begin
byte_addr_counter <= aligned_byte_addr + int_size;
end
else if (itf_cmd_ready)
begin
byte_addr_counter <= byte_addr + current_size;
end
end
end
// Determine whether current burst reached upper wrap boundary
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
upper_boundary_reached <= 1'b0;
end
else
begin
if (int_rd_grant)
begin
if (aligned_byte_rd_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_rd_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
begin
upper_boundary_reached <= 1'b1;
end
else
begin
upper_boundary_reached <= 1'b0;
end
end
else if (int_wr_grant)
begin
if (aligned_byte_wr_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_wr_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
begin
upper_boundary_reached <= 1'b1;
end
else
begin
upper_boundary_reached <= 1'b0;
end
end
else if (itf_cmd_ready)
begin
if (byte_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
begin
upper_boundary_reached <= 1'b1;
end
else
begin
upper_boundary_reached <= 1'b0;
end
end
end
end
// Byte address for wrapping burst command
always @ (*)
begin
if (burst_type == 2'd2 && upper_boundary_reached)
begin
byte_addr = lower_wrap_boundary_byte_addr;
end
else
begin
byte_addr = byte_addr_counter;
end
end
// Byte to word address conversion logic
always @ (*)
begin
word_rd_addr = 0;
word_wr_addr = 0;
registered_word_addr = 0;
word_rd_addr = int_byte_rd_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
word_wr_addr = int_byte_wr_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
registered_word_addr = byte_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
end
// Command address to Avalon ST interface
always @ (*)
begin
if (int_wr_grant)
begin
int_cmd_address = word_wr_addr;
end
else if (int_rd_grant)
begin
int_cmd_address = word_rd_addr;
end
else if (int_doing_split)
begin
int_cmd_address = registered_word_addr;
end
else
begin
int_cmd_address = 0;
end
end
//--------------------------------------------------------------------------
// Command related logics
//--------------------------------------------------------------------------
assign rd_req = int_arvalid & int_arready;
assign wr_req = int_awvalid & int_awready;
assign cmd_req = {rd_req, wr_req};
assign {rd_grant, wr_grant} = cmd_grant;
// Command arbitration logic
generate
begin
if (COMMAND_ARB_TYPE == "ROUND_ROBIN")
begin
always @ (*)
begin
if (&cmd_req) // both command requesting at the same time
begin
cmd_grant = prev_cmd_grant;
end
else
begin
cmd_grant = cmd_req;
end
end
end
else if (COMMAND_ARB_TYPE == "WRITE_PRIORITY")
begin
always @ (*)
begin
if (&cmd_req) // both command requesting at the same time
begin
cmd_grant = 2'b01; // make sure we always grant write request
end
else
begin
cmd_grant = cmd_req;
end
end
end
else if (COMMAND_ARB_TYPE == "READ_PRIORITY")
begin
always @ (*)
begin
if (&cmd_req) // both command requesting at the same time
begin
cmd_grant = 2'b10; // make sure we always grant read request
end
else
begin
cmd_grant = cmd_req;
end
end
end
end
endgenerate
// Previous command grant
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
prev_cmd_grant <= 2'b01; // default round robin priority
end
else
begin
if (|cmd_grant)
begin
prev_cmd_grant <= ~cmd_grant;
end
end
end
// Grant signal for registered output
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_grant <= 1'b0;
int_wr_grant <= 1'b0;
int_rd_grant <= 1'b0;
int_doing_split <= 1'b0;
end
else
begin
if (itf_cmd_ready)
begin
int_grant <= wr_grant | rd_grant;
int_wr_grant <= wr_grant;
int_rd_grant <= rd_grant;
int_doing_split <= doing_split;
end
end
end
end
else
begin
always @ (*)
begin
int_grant = wr_grant | rd_grant;
int_wr_grant = wr_grant;
int_rd_grant = rd_grant;
int_doing_split = doing_split;
end
end
end
endgenerate
// Doing write logic, indicate what we did last
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write <= 1'b0;
end
else
begin
if (wr_grant)
begin
doing_write <= 1'b1;
end
else if (rd_grant)
begin
doing_write <= 1'b0;
end
end
end
// Command & valid to Avalon ST interface
always @ (*)
begin
if (wr_grant)
begin
int_cmd = 1'b1; // Set command to '1' when there is a write, else '0'
int_cmd_valid = 1'b1;
end
else if (rd_grant)
begin
int_cmd = 1'b0; // Set command to '1' when there is a write, else '0'
int_cmd_valid = 1'b1;
end
else if (doing_split)
begin
int_cmd = doing_write;
int_cmd_valid = 1'b1;
end
else
begin
int_cmd = 1'b0;
int_cmd_valid = 1'b0;
end
end
//--------------------------------------------------------------------------
// Burst related logics
//--------------------------------------------------------------------------
// Splitting logic
// we will split AXI command into multiple smaller Avalon ST commands if size if not equal to data width
// or when burst type is set to WRAP
always @ (*)
begin
if (wr_grant)
begin
split_axi_cmd = ((int_awsize != NATIVE_AXI_SIZE || int_awburst == 2) && int_awlen != 0) ? 1'b1 : 1'b0; // don't need to split when size is '1'
end
else if (rd_grant)
begin
split_axi_cmd = ((int_arsize != NATIVE_AXI_SIZE || int_arburst == 2) && int_arlen != 0) ? 1'b1 : 1'b0; // don't need to split when size is '1'
end
else
begin
split_axi_cmd = 1'b0;
end
end
// Splitting logic
// to keep track of how many commands to split
// also to tell other logic that it's currently doing split now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_counter <= 0;
doing_split <= 1'b0;
end
else
begin
if (wr_grant)
begin
split_counter <= int_awlen;
if (split_axi_cmd)
begin
doing_split <= 1'b1;
end
else
begin
doing_split <= 1'b0;
end
end
else if (rd_grant)
begin
split_counter <= int_arlen;
if (split_axi_cmd)
begin
doing_split <= 1'b1;
end
else
begin
doing_split <= 1'b0;
end
end
else if (itf_cmd_ready)
begin
if (split_counter != {ST_SIZE_WIDTH{1'b0}})
begin
split_counter <= split_counter - 1'b1;
end
if (split_counter == 1'b1)
begin
doing_split <= 1'b0;
end
end
end
end
// Convert AXI len to Avalon ST burst size
always @ (*)
begin
rd_burstlen = int_arlen + 1'b1;
wr_burstlen = int_awlen + 1'b1;
end
// Burst size to Avalon ST interface
always @ (*)
begin
if (wr_grant)
begin
int_cmd_burstlen = (split_axi_cmd) ? 1'b1: wr_burstlen;
end
else if (rd_grant)
begin
int_cmd_burstlen = (split_axi_cmd) ? 1'b1: rd_burstlen;
end
else if (doing_split)
begin
int_cmd_burstlen = 1'b1; // Size will always equal to '1' during spliting process
end
else
begin
int_cmd_burstlen = 0;
end
end
// Burst type
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_type <= 0;
end
else
begin
if (wr_grant)
begin
burst_type <= int_awburst;
end
else if (rd_grant)
begin
burst_type <= int_arburst;
end
end
end
//--------------------------------------------------------------------------
// ID related logics
//--------------------------------------------------------------------------
assign rd_id = int_arid;
assign wr_id = int_awid;
// Registered ID, keep track of previous ID
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
registered_id <= 0;
end
else
begin
if (wr_grant)
begin
registered_id <= wr_id;
end
else if (rd_grant)
begin
registered_id <= rd_id;
end
end
end
// Transfer AXI ID to Avalon ST interface
always @ (*)
begin
if (wr_grant)
begin
int_cmd_id = wr_id;
end
else if (rd_grant)
begin
int_cmd_id = rd_id;
end
else if (doing_split)
begin
int_cmd_id = registered_id;
end
else
begin
int_cmd_id = 0;
end
end
//--------------------------------------------------------------------------
// Others
//--------------------------------------------------------------------------
// Setting inband signals to '0'
always @ (*)
begin
int_cmd_priority = zero;
int_cmd_autoprecharge = zero;
int_cmd_multicast = zero;
end
//--------------------------------------------------------------------------
// Outputs
//--------------------------------------------------------------------------
// AXI command output assignment
always @ (*)
begin
// disable ready signal during split or when FIFO is full
int_awready = itf_cmd_ready & ~doing_split & wr_cmd_fifo_ready;
int_arready = itf_cmd_ready & ~doing_split & rd_cmd_fifo_ready;
end
always @ (*)
begin
// disable ready signal when granting other channel
awready = int_awready & ~rd_grant;
arready = int_arready & ~wr_grant;
end
// Avalon ST command output assignment
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
itf_cmd_valid <= 0;
itf_cmd <= 0;
itf_cmd_burstlen <= 0;
itf_cmd_id <= 0;
itf_cmd_priority <= 0;
itf_cmd_autoprecharge <= 0;
itf_cmd_multicast <= 0;
end
else
begin
if (itf_cmd_ready)
begin
itf_cmd_valid <= int_cmd_valid;
itf_cmd <= int_cmd;
itf_cmd_burstlen <= int_cmd_burstlen;
itf_cmd_id <= int_cmd_id;
itf_cmd_priority <= int_cmd_priority;
itf_cmd_autoprecharge <= int_cmd_autoprecharge;
itf_cmd_multicast <= int_cmd_multicast;
end
end
end
always @ (*)
begin
itf_cmd_address = int_cmd_address;
end
end
else
begin
always @ (*)
begin
itf_cmd_valid = int_cmd_valid;
itf_cmd = int_cmd;
itf_cmd_address = int_cmd_address;
itf_cmd_burstlen = int_cmd_burstlen;
itf_cmd_id = int_cmd_id;
itf_cmd_priority = int_cmd_priority;
itf_cmd_autoprecharge = int_cmd_autoprecharge;
itf_cmd_multicast = int_cmd_multicast;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Command Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Write Data Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Write data begin logic
//--------------------------------------------------------------------------
// Determine write data begin based on write data last information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_data_begin_n <= 1'b0;
end
else
begin
if (wlast & wready)
begin
write_data_begin_n <= 1'b0;
end
else if (wvalid & wready) // received a write data packet
begin
write_data_begin_n <= 1'b1;
end
end
end
// Write data begin logic
always @ (*)
begin
if (wvalid & wready)
begin
int_wr_data_begin = ~write_data_begin_n;
end
else
begin
int_wr_data_begin = 1'b0;
end
end
//--------------------------------------------------------------------------
// Others
//--------------------------------------------------------------------------
always @ (*)
begin
int_wr_data_valid = wvalid & wready;
int_wr_data = wdata;
int_wr_data_byte_en = wstrb;
int_wr_data_last = wlast & wready;
int_wr_data_id = wid;
end
//--------------------------------------------------------------------------
// Outputs
//--------------------------------------------------------------------------
// AXI write data channel output assignment
always @ (*)
begin
wready = itf_wr_data_ready & wr_data_fifo_ready;
end
// Avalon ST data chanel output assignment
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
itf_wr_data_valid <= 0;
itf_wr_data <= 0;
itf_wr_data_byte_en <= 0;
itf_wr_data_begin <= 0;
itf_wr_data_last <= 0;
itf_wr_data_id <= 0;
end
else
begin
if (itf_wr_data_ready)
begin
itf_wr_data_valid <= int_wr_data_valid;
itf_wr_data <= int_wr_data;
itf_wr_data_byte_en <= int_wr_data_byte_en;
itf_wr_data_begin <= int_wr_data_begin;
itf_wr_data_last <= int_wr_data_last;
itf_wr_data_id <= int_wr_data_id;
end
end
end
end
else
begin
always @ (*)
begin
itf_wr_data_valid = int_wr_data_valid;
itf_wr_data = int_wr_data;
itf_wr_data_byte_en = int_wr_data_byte_en;
itf_wr_data_begin = int_wr_data_begin;
itf_wr_data_last = int_wr_data_last;
itf_wr_data_id = int_wr_data_id;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Write Data Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Write Response Channel
//
//--------------------------------------------------------------------------------------------------------
assign wr_cmd_fifo_write = wr_grant; // write into FIFO after receiving write request
assign wr_cmd_fifo_write_data = wr_id;
assign wr_cmd_fifo_read = id_matched; // pop from FIFO when ID from both FIFO is matching
assign wr_cmd_fifo_read_data_valid = ~wr_cmd_fifo_empty;
assign wr_data_fifo_write = int_wr_data_last; // write into FIFO after receiving last data
assign wr_data_fifo_write_data = int_wr_data_id;
assign wr_data_fifo_read = id_matched; // pop from FIFO when ID from both FIFO is matching
assign wr_data_fifo_read_data_valid = ~wr_data_fifo_empty;
// FIFO instantiation to store write command information
scfifo # (
.add_ram_output_register ("ON" ),
.intended_device_family ("Stratix IV" ),
.lpm_numwords (WR_CMD_FIFO_DEPTH ),
.lpm_showahead ("ON" ),
.lpm_type ("scfifo" ),
.lpm_width (WR_CMD_FIFO_DATA_WIDTH ),
.lpm_widthu (WR_CMD_FIFO_ADDR_WIDTH ),
.overflow_checking ("OFF" ),
.underflow_checking ("OFF" ),
.use_eab ("ON" ),
.almost_full_value (WR_CMD_FIFO_DEPTH - 1 )
) wr_cmd_fifo (
.aclr (~ctl_reset_n ),
.clock (ctl_clk ),
.data (wr_cmd_fifo_write_data ),
.rdreq (wr_cmd_fifo_read ),
.wrreq (wr_cmd_fifo_write ),
.empty (wr_cmd_fifo_empty ),
.full ( ),
.q (wr_cmd_fifo_read_data ),
.almost_empty ( ),
.almost_full (wr_cmd_fifo_almost_full ),
.sclr (zero ),
.usedw ( )
);
// FIFO instantiation to store write data information
scfifo # (
.add_ram_output_register ("ON" ),
.intended_device_family ("Stratix IV" ),
.lpm_numwords (WR_DATA_FIFO_DEPTH ),
.lpm_showahead ("ON" ),
.lpm_type ("scfifo" ),
.lpm_width (WR_DATA_FIFO_DATA_WIDTH ),
.lpm_widthu (WR_DATA_FIFO_ADDR_WIDTH ),
.overflow_checking ("OFF" ),
.underflow_checking ("OFF" ),
.use_eab ("ON" ),
.almost_full_value (WR_DATA_FIFO_DEPTH - 1 )
) wr_data_fifo (
.aclr (~ctl_reset_n ),
.clock (ctl_clk ),
.data (wr_data_fifo_write_data ),
.rdreq (wr_data_fifo_read ),
.wrreq (wr_data_fifo_write ),
.empty (wr_data_fifo_empty ),
.full ( ),
.q (wr_data_fifo_read_data ),
.almost_empty ( ),
.almost_full (wr_data_fifo_almost_full ),
.sclr (zero ),
.usedw ( )
);
// FIFO full logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wr_cmd_fifo_ready <= 1'b0;
wr_data_fifo_ready <= 1'b0;
end
else
begin
// Set to '1' when either FIFO almost full, to prevent converter from accepting new commands/data
wr_cmd_fifo_ready <= ~wr_cmd_fifo_almost_full;
wr_data_fifo_ready <= ~wr_data_fifo_almost_full;
end
end
// ID macthing logic
always @ (*)
begin
if (wr_cmd_fifo_read_data == wr_data_fifo_read_data && wr_cmd_fifo_read_data_valid && wr_data_fifo_read_data_valid)
begin
id_matched = 1'b1;
end
else
begin
id_matched = 1'b0;
end
end
// Response logic
// logic will keep valid high till response channel is ready to accept the command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_bid <= 0;
int_bresp <= 0;
int_bvalid <= 1'b0;
end
else
begin
if (id_matched)
begin
int_bid <= wr_cmd_fifo_read_data;
int_bresp <= 0;
int_bvalid <= 1'b1;
end
else if (bready)
begin
int_bid <= 0;
int_bresp <= 0;
int_bvalid <= 0;
end
end
end
// AXI write response channel output assignment
always @ (*)
begin
bid = int_bid;
bresp = int_bresp;
bvalid = int_bvalid;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Write Response Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read Data Channel
//
//--------------------------------------------------------------------------------------------------------
assign rd_cmd_fifo_write = rd_grant; // write into FIFO after receiving read request
assign rd_cmd_fifo_write_data = rd_burstlen;
assign rd_cmd_fifo_read = read_data_last; // pop from FIFO after sending last read data
assign rd_cmd_fifo_read_data_valid = ~rd_cmd_fifo_empty;
// FIFO to store read command information
scfifo # (
.add_ram_output_register ("ON" ),
.intended_device_family ("Stratix IV" ),
.lpm_numwords (RD_CMD_FIFO_DEPTH ),
.lpm_showahead ("ON" ),
.lpm_type ("scfifo" ),
.lpm_width (RD_CMD_FIFO_DATA_WIDTH ),
.lpm_widthu (RD_CMD_FIFO_ADDR_WIDTH ),
.overflow_checking ("OFF" ),
.underflow_checking ("OFF" ),
.use_eab ("ON" ),
.almost_full_value (RD_CMD_FIFO_DEPTH - 1 )
) rd_cmd_fifo (
.aclr (~ctl_reset_n ),
.clock (ctl_clk ),
.data (rd_cmd_fifo_write_data ),
.rdreq (rd_cmd_fifo_read ),
.wrreq (rd_cmd_fifo_write ),
.empty (rd_cmd_fifo_empty ),
.full ( ),
.q (rd_cmd_fifo_read_data ),
.almost_empty ( ),
.almost_full (rd_cmd_fifo_almost_full ),
.sclr (zero ),
.usedw ( )
);
// FIFO full logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_cmd_fifo_ready <= 1'b0;
end
else
begin
// Set to '1' when either FIFO almost full, to prevent converter from accepting new commands/data
rd_cmd_fifo_ready <= ~rd_cmd_fifo_almost_full;
end
end
// Read data counter
// keep tracks of read data count, to be used in read data last logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_data_counter <= 1;
end
else
begin
if (int_rvalid && int_rd_data_ready && read_data_last) // reset counter value after reaching last burst
begin
read_data_counter <= 1;
end
else if (int_rvalid && int_rd_data_ready) // count up when there is a read data begin transfered
begin
read_data_counter <= read_data_counter + 1'b1;
end
end
end
// Read data last logic
// indicate which read data is the last burst
always @ (*)
begin
if (int_rvalid && int_rd_data_ready && read_data_counter == rd_cmd_fifo_read_data) // set last to '1' when counter matches FIFO output
begin
read_data_last = 1'b1;
end
else
begin
read_data_last = 1'b0;
end
end
// Others
always @ (*)
begin
int_rid = itf_rd_data_id;
int_rdata = itf_rd_data;
int_rresp = {itf_rd_data_error, 1'b0}; // If there is an error, it will indicate SLVERR on AXI interface
int_rlast = read_data_last;
int_rvalid = itf_rd_data_valid;
int_rd_data_ready = rready;
end
// AXI read data channel output assignment
always @ (*)
begin
rid = int_rid;
rdata = int_rdata;
rresp = int_rresp;
rlast = int_rlast;
rvalid = int_rvalid;
end
// Avalon ST read data channel output assignment
always @ (*)
begin
itf_rd_data_ready = int_rd_data_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Read Data Channel
//
//--------------------------------------------------------------------------------------------------------
function integer log2;
input [31 : 0] value;
integer i;
begin
log2 = 0;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
function integer log2_minus_one;
input [31 : 0] value;
integer i;
begin
log2_minus_one = 1;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2_minus_one = i + 1;
end
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_gen #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_TCCD = 4,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_BURST_GEN_OUTPUT_REG = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_type,
cfg_burst_length,
cfg_tccd,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// Arbiter Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size,
// AFI Interface
bg_do_write_combi,
bg_do_read_combi,
bg_do_burst_chop_combi,
bg_do_burst_terminate_combi,
bg_do_activate_combi,
bg_do_precharge_combi,
bg_to_chip_combi,
bg_effective_size_combi,
bg_interrupt_ready_combi,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_zq_cal,
bg_do_lmr,
bg_to_chipsel,
bg_to_chip,
bg_to_bank,
bg_to_row,
bg_to_col,
bg_doing_write,
bg_doing_read,
bg_rdwr_data_valid,
bg_interrupt_ready,
bg_localid,
bg_dataid,
bg_size,
bg_effective_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// Arbiter Interface
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
input [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
input [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// AFI Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
output bg_interrupt_ready_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
output bg_doing_write;
output bg_doing_read;
output bg_rdwr_data_valid;
output bg_interrupt_ready;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// AFI Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
reg bg_doing_write;
reg bg_doing_read;
reg bg_rdwr_data_valid;
reg bg_interrupt_ready;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
// Burst generation logic
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
reg [2 : 0] int_col_address;
reg [2 : 0] int_address_left;
reg int_do_row_req;
reg int_do_col_req;
reg int_do_rd_req;
reg int_do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_partial;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
reg [2 : 0] col_address;
reg [2 : 0] address_left;
reg do_row_req;
reg do_col_req;
reg do_rd_req;
reg do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_partial;
reg [3 : 0] max_local_burst_size;
reg [3 : 0] max_local_burst_size_divide_2;
reg [3 : 0] max_local_burst_size_minus_2;
reg [3 : 0] max_local_burst_size_divide_2_and_minus_2;
reg [3 : 0] burst_left;
reg current_valid;
reg delayed_valid;
reg combined_valid;
reg [3 : 0] max_burst_left;
reg delayed_doing;
reg last_is_write;
reg last_is_read;
// Burst interrupt logic
reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
reg int_allow_interrupt;
reg int_interrupt_enable_ready;
reg int_interrupt_disable_ready;
reg int_interrupt_gate;
// Burst terminate logic
reg int_allow_terminate;
reg int_do_burst_terminate;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_do_req;
reg doing_burst_terminate;
reg terminate_doing;
// RMW Info
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
// Data ID
reg [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
// Column address
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
// Common
wire zero = 1'b0;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
reg bg_interrupt_ready_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_terminate;
reg doing_write;
reg doing_read;
reg rdwr_data_valid;
reg interrupt_ready;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
// Do signals
generate
if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (! ctl_reset_n)
begin
bg_do_write <= 0;
bg_do_read <= 0;
bg_do_auto_precharge <= 0;
bg_do_rmw_correct <= 0;
bg_do_rmw_partial <= 0;
bg_do_activate <= 0;
bg_do_precharge <= 0;
bg_do_precharge_all <= 0;
bg_do_refresh <= 0;
bg_do_self_refresh <= 0;
bg_do_power_down <= 0;
bg_do_deep_pdown <= 0;
bg_do_zq_cal <= 0;
bg_do_lmr <= 0;
bg_to_chip <= 0;
bg_to_chipsel <= 0;
bg_to_bank <= 0;
bg_to_row <= 0;
bg_localid <= 0;
bg_size <= 0;
bg_to_col <= 0;
bg_dataid <= 0;
bg_do_burst_chop <= 0;
bg_do_burst_terminate <= 0;
bg_doing_write <= 0;
bg_doing_read <= 0;
bg_rdwr_data_valid <= 0;
bg_interrupt_ready <= 0;
bg_effective_size <= 0;
end
else
begin
bg_do_write <= arb_do_write;
bg_do_read <= arb_do_read;
bg_do_auto_precharge <= arb_do_auto_precharge;
bg_do_rmw_correct <= combined_do_rmw_correct;
bg_do_rmw_partial <= combined_do_rmw_partial;
bg_do_activate <= arb_do_activate;
bg_do_precharge <= arb_do_precharge;
bg_do_precharge_all <= arb_do_precharge_all;
bg_do_refresh <= arb_do_refresh;
bg_do_self_refresh <= arb_do_self_refresh;
bg_do_power_down <= arb_do_power_down;
bg_do_deep_pdown <= arb_do_deep_pdown;
bg_do_zq_cal <= arb_do_zq_cal;
bg_do_lmr <= arb_do_lmr;
bg_to_chip <= arb_to_chip;
bg_to_chipsel <= arb_to_chipsel;
bg_to_bank <= arb_to_bank;
bg_to_row <= arb_to_row;
bg_localid <= arb_localid;
bg_size <= arb_size;
bg_to_col <= modified_to_col;
bg_dataid <= combined_dataid;
bg_do_burst_chop <= do_burst_chop;
bg_do_burst_terminate <= do_burst_terminate;
bg_doing_write <= doing_write;
bg_doing_read <= doing_read;
bg_rdwr_data_valid <= rdwr_data_valid;
bg_interrupt_ready <= interrupt_ready;
bg_effective_size <= effective_size;
end
end
end
else
begin
always @ (*)
begin
bg_do_write = arb_do_write;
bg_do_read = arb_do_read;
bg_do_auto_precharge = arb_do_auto_precharge;
bg_do_activate = arb_do_activate;
bg_do_precharge = arb_do_precharge;
bg_do_precharge_all = arb_do_precharge_all;
bg_do_refresh = arb_do_refresh;
bg_do_self_refresh = arb_do_self_refresh;
bg_do_power_down = arb_do_power_down;
bg_do_deep_pdown = arb_do_deep_pdown;
bg_do_zq_cal = arb_do_zq_cal;
bg_do_lmr = arb_do_lmr;
bg_to_chip = arb_to_chip;
bg_to_chipsel = arb_to_chipsel;
bg_to_bank = arb_to_bank;
bg_to_row = arb_to_row;
bg_localid = arb_localid;
bg_size = arb_size;
bg_do_burst_chop = do_burst_chop;
bg_do_burst_terminate = do_burst_terminate;
bg_doing_write = doing_write;
bg_doing_read = doing_read;
bg_rdwr_data_valid = rdwr_data_valid;
bg_interrupt_ready = interrupt_ready;
bg_effective_size = effective_size;
end
// To column
always @ (*)
begin
bg_to_col = modified_to_col;
end
// RMW info
always @ (*)
begin
bg_do_rmw_correct = combined_do_rmw_correct;
bg_do_rmw_partial = combined_do_rmw_partial;
end
// Data ID
always @ (*)
begin
bg_dataid = combined_dataid;
end
end
endgenerate
// Regardless whether CFG_ENABLE_BURST_GEN_OUTPUT_REG is 1/0
// following signals (inputs to rank_timer) need to be combi
always @ (*)
begin
bg_do_write_combi = arb_do_write;
bg_do_read_combi = arb_do_read;
bg_do_burst_chop_combi = do_burst_chop;
bg_do_burst_terminate_combi = do_burst_terminate;
bg_do_activate_combi = arb_do_activate;
bg_do_precharge_combi = arb_do_precharge;
bg_to_chip_combi = arb_to_chip;
bg_effective_size_combi = effective_size;
bg_interrupt_ready_combi = interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Generation Logic
//
// Doing read/write signal will indicate the "FULL" burst duration of a request
// Data Valid signal will indicate "VALID" burst duration of a request
//
// Example: Without address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Input Size ----X 1 X-----------------X 2 X-----------------X 3 X-----------------X 4 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal ____/ 1 \_________________/ 1 X 2 \___________/ 1 X 2 X 3 \_____/ 1 X 2 X 3 X 4 \_____
//
// Example: With address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 1 X-----------------X 2 X-----------------X 2 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 2 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal __________/ 1 \_______________________/ 1 \_________________/ 1 X 2 \_____
// <-----> <-----------> <----------->
// Offset Offset Offset
//
// Example: Burst chop for DDR3 only (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 1 X-----------------X 2 X-----------------X 3 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 1 X-----------------X 1 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 2 X-----------------X 2 X-----------------------
// Output Burst Chop Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Output Doing Signal ____/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \_________________
// Output Valid Signal ____/ 1 \_______________________/ 1 \___________/ 1 \_______________________/ 1 \_________________
// <-----> <----->
// Offset Offset
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Maximum local burst size
//----------------------------------------------------------------------------------------------------
// Calculate maximum local burst size
// based on burst length and controller rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size_divide_2 <= 0;
max_local_burst_size_minus_2 <= 0;
max_local_burst_size_divide_2_and_minus_2 <= 0;
end
else
begin
max_local_burst_size_divide_2 <= max_local_burst_size / 2;
max_local_burst_size_minus_2 <= max_local_burst_size - 2'd2;
max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
end
end
//----------------------------------------------------------------------------------------------------
// Address shifting
//----------------------------------------------------------------------------------------------------
// Column address
// we only require address [2 - 0] because the maximum supported
// local burst count is 8 which is BL of 16 in full rate
// we only take low phase of arb_to_col address because high and low phase is identical
always @ (*)
begin
int_col_address = 0;
if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop) // DDR3 and burst chop, we don't want address shifting during burst chop
begin
if (max_local_burst_size [2]) // max local burst of 4
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else
// max local burst of 1, 2 - address shifting in burst chop is not possible
// max local burst of 8 - not supported in DDR3, there is no BL 16 support in DDR3
int_col_address = 0;
end
else if (max_local_burst_size [0]) // max local burst of 1
int_col_address = 0;
else if (max_local_burst_size [1]) // max local burst of 2
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [2]) // max local burst of 4
int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [3]) // max local burst of 8
int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
end
always @ (*)
begin
col_address = int_col_address;
end
//----------------------------------------------------------------------------------------------------
// Command Info
//----------------------------------------------------------------------------------------------------
// To col address
always @ (*)
begin
int_to_col = arb_to_col;
end
// Row request
always @ (*)
begin
int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
end
// Column request
always @ (*)
begin
int_do_col_req = (|arb_do_write) | (|arb_do_read);
end
// Read and write request
always @ (*)
begin
int_do_rd_req = |arb_do_read;
int_do_wr_req = |arb_do_write;
end
// Burst chop
always @ (*)
begin
int_do_burst_chop = arb_do_burst_chop;
end
// RMW info
always @ (*)
begin
int_do_rmw_correct = arb_do_rmw_correct;
int_do_rmw_partial = arb_do_rmw_partial;
end
// Other Info: size, dataid
always @ (*)
begin
int_size = arb_size;
int_dataid = arb_dataid;
end
always @ (*)
begin
size = int_size;
dataid = int_dataid;
to_col = int_to_col;
do_row_req = int_do_row_req;
do_col_req = int_do_col_req;
do_rd_req = int_do_rd_req;
do_wr_req = int_do_wr_req;
do_burst_chop = int_do_burst_chop;
do_rmw_correct = int_do_rmw_correct;
do_rmw_partial = int_do_rmw_partial;
end
//----------------------------------------------------------------------------------------------------
// Address Count
//----------------------------------------------------------------------------------------------------
// Address counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
address_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address > 1'b1)
address_left <= col_address - 2'd2;
else
address_left <= 0;
end
else if (address_left != 0)
address_left <= address_left - 1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Valid Signal
//----------------------------------------------------------------------------------------------------
// Burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address == 0) // no shifting required
begin
if (size > 1'b1)
burst_left <= size - 2'd2;
else
burst_left <= 0;
end
else if (col_address == 1'b1) // require shifting
begin
burst_left <= size - 1'b1;
end
else // require shifting
begin
burst_left <= size;
end
end
else if (address_left == 0 && burst_left != 0) // start decreasing only after addres shifting is completed
burst_left <= burst_left - 1'b1;
end
end
// Current valid signal
// when there is a column request and column address is "0"
// valid signal must be asserted along with column request
always @ (*)
begin
if (do_col_req && col_address == 0)
current_valid = 1'b1;
else
current_valid = 1'b0;
end
// Delayed valid signal
// when there is a column request with size larger than "1"
// valid signal will be asserted according to the request size
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_valid <= 0;
end
else
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
delayed_valid <= 1'b1;
else if (address_left == 0 && burst_left > 0)
delayed_valid <= 1'b1;
else
delayed_valid <= 1'b0;
end
end
// Combined valid signal
always @ (*)
begin
combined_valid = current_valid | delayed_valid;
end
// Read write valid signal
always @ (*)
begin
rdwr_data_valid = combined_valid;
end
//----------------------------------------------------------------------------------------------------
// Doing Signal
//----------------------------------------------------------------------------------------------------
// Maximum burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (do_burst_chop)
begin
if (max_local_burst_size_divide_2 <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
end
else
begin
if (max_local_burst_size <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_minus_2;
end
end
else if (max_burst_left != 0)
max_burst_left <= max_burst_left - 1'b1;
end
end
// Delayed doing signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_doing <= 0;
end
else
begin
if (do_col_req)
begin
if (max_local_burst_size <= 1'b1) //do not generate delayed_doing if max burst count is 1
delayed_doing <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
delayed_doing <= 1'b0;
else
delayed_doing <= 1'b1;
end
else if (max_burst_left > 0)
delayed_doing <= 1'b1;
else
delayed_doing <= 1'b0;
end
end
// Keep track of last commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b0;
end
else
begin
if (do_wr_req)
begin
last_is_write <= 1'b1;
last_is_read <= 1'b0;
end
else if (do_rd_req)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b1;
end
end
end
// Doing write signal
always @ (*)
begin
if (do_rd_req)
doing_write = 1'b0;
else if (do_wr_req)
doing_write = ~terminate_doing;
else if (last_is_write)
doing_write = delayed_doing & ~terminate_doing;
else
doing_write = 1'b0;
end
// Doing read signal
always @ (*)
begin
if (do_wr_req)
doing_read = 1'b0;
else if (do_rd_req)
doing_read = ~terminate_doing;
else if (last_is_read)
doing_read = delayed_doing & ~terminate_doing;
else
doing_read = 1'b0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Generation Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
// Registered arb_do_rmw_* signal when there is a coumn request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_do_rmw_correct <= 0;
delayed_do_rmw_partial <= 0;
end
else
begin
if (do_col_req)
begin
delayed_do_rmw_correct <= do_rmw_correct;
delayed_do_rmw_partial <= do_rmw_partial;
end
end
end
// Prolong RMW information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
begin
combined_do_rmw_correct = do_rmw_correct;
combined_do_rmw_partial = do_rmw_partial;
end
else if (delayed_doing)
begin
combined_do_rmw_correct = delayed_do_rmw_correct;
combined_do_rmw_partial = delayed_do_rmw_partial;
end
else
begin
combined_do_rmw_correct = 0;
combined_do_rmw_partial = 0;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Data ID
//
//--------------------------------------------------------------------------------------------------------
// Register data ID when there is a column request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_dataid <= 0;
end
else
begin
if (do_col_req)
delayed_dataid <= dataid;
end
end
// Prolong data ID information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
combined_dataid = dataid;
else if (delayed_doing)
combined_dataid = delayed_dataid;
else
combined_dataid = 0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Data ID
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Column Address
//
//--------------------------------------------------------------------------------------------------------
// Change column address bit [2 : 0]
// see waveform examples in burst generation logic portion
always @ (*)
begin
modified_to_col = to_col;
// During burst chop in DDR3 only, retain original column address
// maximum local burst in DDR3 is 4 which is BL8 in full rate
if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
begin
if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
else
begin
if (max_local_burst_size [0]) // max local burst of 1
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 2 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [3]) // max local burst of 8
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 3 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Column Address
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Interrupt
//
// DDR, DDR2, LPDDR and LPDDR2 specific
//
// This logic re-use most of the existing logic in burst generation section (valid signal)
// This signal will be used in rank timer block to gate can_read and can_write signals
//
// Example: (DDR2 full rate, burst length of 8, this will result in maximum local burst of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Do Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Valid Signal ____/ 1 \_______________________/ 1 \_______________________/ 1 \_______________________/ 1 \_____
//
// Interrupt Ready (tCCD = 1) / HIGH \_____/ HIGH \___________/ HIGH \_________________/
// Interrupt Ready (tCCD = 2) / HIGH \_____/ HIGH \_____/ HIGH \_________________/ \_________________/
//
//--------------------------------------------------------------------------------------------------------
// n-prefetch architecture, related tCCD value (only support 1, 2 and 4)
// if tCCD is set to 1, command can be interrupted / terminated at every 2 memory burst boundary (1 memory clock cycle)
// if tCCD is set to 2, command can be interrupted / terminated at every 4 memory burst boundary (2 memory clock cycle)
// if tCCD is set to 4, command can be interrupted / terminated at every 8 memory burst boundary (4 memory clock cycle)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
n_prefetch <= 0;
end
else
begin
n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
end
end
// For n_prefetch of 0 and 1, we will allow interrupt at any controller clock cycles
// for n_prefetch of n, we will allow interrupt at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_interrupt <= 1'b1;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR3) // DDR3 specific, interrupt masking is handled by setting read-to-read and write-to-write to BL/2
int_allow_interrupt <= 1'b1;
else
begin
if (n_prefetch <= 1) // allow interrupt at any clock cycle
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address != 0))
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 2)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [0] == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 4)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [1 : 0] == 0)
int_allow_interrupt <= 1'b1;
end
end
end
end
// Interrupt info when interrupt feature is enabled
always @ (*)
begin
int_interrupt_enable_ready = int_allow_interrupt;
end
// Interrupt info when interrupt feature is disabled
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_interrupt_disable_ready <= 0;
end
else
begin
if (do_col_req)
begin
if (CFG_REG_GRANT)
begin
if (max_local_burst_size <= 2'd2) //do not generate int_interrupt_ready
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 3'd4)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
else
begin
if (max_local_burst_size <= 1'b1) //do not generate int_interrupt_ready if max burst count is 1
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
end
else if (!CFG_REG_GRANT && max_burst_left > 0)
int_interrupt_disable_ready <= 1'b1;
else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
int_interrupt_disable_ready <= 1'b1;
else
int_interrupt_disable_ready <= 1'b0;
end
end
// Assign to output ports
always @ (*)
begin
if (cfg_enable_burst_interrupt)
begin
interrupt_ready = ~int_interrupt_enable_ready;
end
else
begin
interrupt_ready = ~int_interrupt_disable_ready;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Interrupt
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Terminate
//
// LPDDR1 and LPDDR2 specific only
//
//--------------------------------------------------------------------------------------------------------
// For n_prefetch of 0 and 1, we will allow terminate at any controller clock cycles
// for n_prefetch of n, we will allow terminate at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else
begin
if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) // LPDDR1 and LPDDR2 only
begin
if (n_prefetch <= 1) // allow terminate at any clock cycle
begin
if (do_col_req && col_address != 0)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (do_col_req && col_address == 0 && size == 1'b1)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 2)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 4)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [1 : 0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
end
else
begin
int_allow_terminate <= 1'b0;
end
end
end
// Effective size, actual issued size migh be smaller that maximum local burst size
// we need to inform rank timer about this information for efficient DQ bus turnaround operation
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_effective_size <= 0;
end
else
begin
if (do_col_req)
int_effective_size <= 1'b1;
else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
int_effective_size <= int_effective_size + 1'b1;
end
end
// Terminate doing signal, this signal will be used to mask off doing_read or doing_write signal
// when we issue a burst terminate signal, we should also terminate doing_read and doing_write signal
// to prevent unwanted DQS toggle on the memory interface
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
doing_burst_terminate <= 1'b1;
else
doing_burst_terminate <= 1'b0;
end
end
always @ (*)
begin
if (cfg_enable_burst_terminate)
begin
terminate_doing = (|do_burst_terminate) | doing_burst_terminate;
end
else
begin
terminate_doing = zero;
end
end
// Burst terminate output ports
// set burst terminate signal to '0' when there is a do_col_req (in half and quarter rate)
// or both do_col_req and do_row_req (full rate) because this indicate there is a incoming command
// any command from arbiter is have higher priority compared to burst terminate command
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
int_do_req = do_col_req | do_row_req;
else
int_do_req = do_col_req;
end
generate
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate)
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
else
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
end
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate)
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
else
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
end
end
end
endgenerate
// Effective size output ports
always @ (*)
begin
if (cfg_enable_burst_terminate)
begin
effective_size = int_effective_size;
end
else
begin
effective_size = {CFG_INT_SIZE_WIDTH{zero}};
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Terminate
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Chop
//
// DDR3 specific only
//
//--------------------------------------------------------------------------------------------------------
// yyong generate
// yyong begin
// yyong if (CFG_DWIDTH_RATIO == 2)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size <= 2 && arb_to_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 4)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = 0;
// yyong
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 8)
// yyong begin
// yyong // Burst chop is not available in quarter rate
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{zero}};
// yyong end
// yyong end
// yyong end
// yyong endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Chop
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
module alt_mem_ddrx_burst_tracking
# (
// module parameter port list
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
// port list
ctl_clk,
ctl_reset_n,
// data burst interface
burst_ready,
burst_valid,
// burstcount counter sent to data_id_manager
burst_pending_burstcount,
burst_next_pending_burstcount,
// burstcount consumed by data_id_manager
burst_consumed_valid,
burst_counsumed_burstcount
);
// -----------------------------
// local parameter declarations
// -----------------------------
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// data burst interface
input burst_ready;
input burst_valid;
// burstcount counter sent to data_id_manager
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
// burstcount consumed by data_id_manager
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// data burst interface
wire burst_ready;
wire burst_valid;
// burstcount counter sent to data_id_manager
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
//wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_count_accepted;
// burstcount consumed by data_id_manager
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// signal declaration
// -----------------------------
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
// -----------------------------
// module definition
// -----------------------------
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_cmd_gen
# (parameter
// cmd_gen settings
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 4,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_DWIDTH_RATIO = 2, // 2-FR,4-HR,8-QR
CFG_CTL_QUEUE_DEPTH = 8,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary coded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_ENABLE_QUEUE = 1,
CFG_ENABLE_BURST_MERGE = 1,
CFG_CMD_GEN_OUTPUT_REG = 0,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
ctl_clk,
ctl_reset_n,
// tbp interface
tbp_full,
tbp_load,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_multicast,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// input interface
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_id,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
// datapath interface
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
proc_read,
proc_size,
proc_localid,
wdatap_free_id_valid, // from wdata path
wdatap_free_id_dataid, // from wdata path
rdatap_free_id_valid, // from rdata path
rdatap_free_id_dataid, // from rdata path
tbp_load_index,
data_complete,
data_rmw_complete,
// nodm and ecc signal
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
data_partial_be,
// configuration ports
cfg_enable_cmd_split,
cfg_burst_length,
cfg_addr_order,
cfg_enable_ecc,
cfg_enable_no_dm,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width
);
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + CFG_DATA_ID_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH;
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2(CFG_LOCAL_ADDR_WIDTH);
localparam INT_LOCAL_ADDR_WIDTH = 2**CFG_LOCAL_ADDR_BITSELECT_WIDTH;
input ctl_clk;
input ctl_reset_n;
input tbp_full;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] tbp_read;
input [CFG_CTL_TBP_NUM-1:0] tbp_write;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output cmd_gen_load;
output [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
output cmd_gen_write;
output cmd_gen_read;
output cmd_gen_multicast;
output [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
output [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
output cmd_gen_priority;
output cmd_gen_rmw_correct;
output cmd_gen_rmw_partial;
output cmd_gen_autopch;
output cmd_gen_complete;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output cmd_gen_full;
input cmd_valid;
input [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
input cmd_write;
input cmd_read;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
input cmd_multicast;
input [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
input cmd_priority;
input cmd_autoprecharge;
output proc_busy;
output proc_load;
output proc_load_dataid;
output proc_write;
output proc_read;
output [CFG_INT_SIZE_WIDTH-1:0] proc_size;
output [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
input wdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
input rdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output errcmd_ready; // high means cmd_gen accepts command
input errcmd_valid;
input [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
input [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
input data_partial_be;
input cfg_enable_cmd_split;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length; // this contains immediate BL value, max is 31
input [CFG_PORT_WIDTH_ADDR_ORDER-1:0] cfg_addr_order; // 0 is chiprowbankcol , 1 is chipbankrowcol , 2 is rowchipbankcol
input cfg_enable_ecc;
input cfg_enable_no_dm;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH-1:0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH-1:0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH-1:0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0] cfg_cs_addr_width;
// === address mapping
integer n;
integer j;
integer k;
integer m;
wire [INT_LOCAL_ADDR_WIDTH-1:0] int_cmd_address;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr;
// === command splitting block
reg [CFG_MEM_IF_CS_WIDTH-1:0] split_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] split_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] split_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] split_col_addr;
reg split_read;
reg split_write;
reg [CFG_INT_SIZE_WIDTH-1:0] split_size;
reg split_autopch;
reg split_multicast;
reg split_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] split_localid;
reg buf_read_req;
reg buf_write_req;
reg buf_autopch_req;
reg buf_multicast;
reg buf_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] buf_localid;
reg [CFG_LOCAL_SIZE_WIDTH:0] buf_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] buf_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] buf_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] buf_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] buf_col_addr;
reg [CFG_LOCAL_SIZE_WIDTH-1:0] decrmntd_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] incrmntd_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] incrmntd_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] incrmntd_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] incrmntd_col_addr;
reg [CFG_MEM_IF_CS_WIDTH-1:0] max_chip_from_csr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] max_bank_from_csr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] max_row_from_csr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] max_col_from_csr;
wire copy;
reg [2:0] unaligned_burst; // because planned max native size is 8, unaligned burst can be a max of 7
reg [3:0] native_size; // support native size up to 15, bl16 FR have native size of 8
wire require_gen;
reg deassert_ready;
reg registered;
reg generating;
// === ecc mux
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr_combi;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr_combi;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr_combi;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr_combi;
reg ecc_read_combi;
reg ecc_write_combi;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size_combi;
reg ecc_autopch_combi;
reg ecc_multicast_combi;
reg ecc_priority_combi;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid_combi;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr;
reg ecc_read;
reg ecc_write;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size;
reg ecc_autopch;
reg ecc_multicast;
reg ecc_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid;
reg ecc_int_combi;
reg errcmd_ready_combi;
reg partial_combi;
reg correct_combi;
reg partial_opr_combi;
reg ecc_int;
reg ecc_int_r;
reg errcmd_ready;
reg partial;
reg correct;
reg partial_opr;
wire mux_busy;
wire [CFG_MEM_IF_CS_WIDTH-1:0] muxed_cs_addr;
wire [CFG_MEM_IF_BA_WIDTH-1:0] muxed_bank_addr;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] muxed_row_addr;
wire [CFG_MEM_IF_COL_WIDTH-1:0] muxed_col_addr;
wire muxed_read;
wire muxed_write;
wire [CFG_INT_SIZE_WIDTH-1:0] muxed_size;
wire muxed_autopch;
wire muxed_multicast;
wire muxed_priority;
wire [CFG_LOCAL_ID_WIDTH-1:0] muxed_localid;
wire [CFG_DATA_ID_WIDTH-1:0] muxed_dataid;
wire muxed_complete;
wire muxed_correct;
wire muxed_partial;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_0;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_1;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_2;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_3;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
reg proc_busy_sig;
reg proc_ecc_busy_sig;
reg proc_load_sig;
reg proc_load_dataid_sig;
reg proc_write_sig;
reg proc_read_sig;
reg [CFG_INT_SIZE_WIDTH-1:0] proc_size_sig;
reg [CFG_LOCAL_ID_WIDTH-1:0] proc_localid_sig;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
// === merging signals
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_one;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_two;
wire can_merge;
reg [CFG_INT_SIZE_WIDTH-1:0] last_size;
reg last_read_req;
reg last_write_req;
reg last_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last_col_addr;
reg [CFG_INT_SIZE_WIDTH-1:0] last2_size;
reg last2_read_req;
reg last2_write_req;
reg last2_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last2_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last2_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last2_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last2_col_addr;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_row;
// === queue
reg [BUFFER_WIDTH-1:0] pipe[CFG_CTL_QUEUE_DEPTH-1:0];
reg pipefull[CFG_CTL_QUEUE_DEPTH-1:0];
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire write_to_queue;
wire queue_empty;
wire queue_full;
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_row_addr;
reg read [CFG_CTL_TBP_NUM-1:0];
reg write [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
wire [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire one = 1'b1;
wire zero = 1'b0;
//======================= TBP info ===========================
generate
genvar p;
for (p=0; p<CFG_CTL_TBP_NUM; p=p+1)
begin : info_per_tbp
always @ (*)
begin
if (tbp_load[p])
begin
read [p] = cmd_gen_read;
write [p] = cmd_gen_write;
chipsel[p] = cmd_gen_chipsel;
bank [p] = cmd_gen_bank;
row [p] = cmd_gen_row;
col [p] = cmd_gen_col;
end
else
begin
read [p] = tbp_read [p];
write [p] = tbp_write [p];
chipsel[p] = tbp_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
bank [p] = tbp_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
row [p] = tbp_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
col [p] = tbp_col [(p+1)*CFG_MEM_IF_COL_WIDTH-1:p*CFG_MEM_IF_COL_WIDTH];
end
end
end
for (p=0; p<CFG_CTL_SHADOW_TBP_NUM; p=p+1)
begin : info_per_shadow_tbp
assign shadow_chipsel[p] = tbp_shadow_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
assign shadow_bank [p] = tbp_shadow_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
assign shadow_row [p] = tbp_shadow_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
end
endgenerate
//======================= Address Remapping ===========================
// Pre-calculate int_*_addr chipsel, bank, row, col bit select offsets
always @ (*)
begin
// Row width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_row = cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_row = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_row = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Bank width info
if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_bank = cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_bank = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Chipsel width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
end
assign int_cmd_address = cmd_address;
// Supported addr order
// 0 - chip-row-bank-col
// 1 - chip-bank-row-col
// 2 - row-chip-bank-col
// Derive column address from address
always @(*)
begin : Col_addr_loop
int_col_addr[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0] = int_cmd_address[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0];
for (n = MIN_COL - log2(CFG_DWIDTH_RATIO);n < MAX_COL;n = n + 1'b1)
begin
if (n < (cfg_col_addr_width - log2(CFG_DWIDTH_RATIO))) // Bit of col_addr can be configured in CSR using cfg_col_addr_width
begin
int_col_addr[n] = int_cmd_address[n];
end
else
begin
int_col_addr[n] = 1'b0;
end
end
int_col_addr = int_col_addr << log2(CFG_DWIDTH_RATIO);
end
// Derive row address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_2;
always @(*)
begin : Row_addr_loop
for (j = 0;j < MIN_ROW;j = j + 1'b1) // The purpose of using this for-loop is to get rid of "if (j < cfg_row_addr_width) begin" which causes multiplexers
begin
row_addr_loop_1 = j + cfg_addr_bitsel_row;
int_row_addr[j] = int_cmd_address[row_addr_loop_1];
end
for (j = MIN_ROW;j < MAX_ROW;j = j + 1'b1)
begin
row_addr_loop_2 = j + cfg_addr_bitsel_row;
if(j < cfg_row_addr_width) // Bit of row_addr can be configured in CSR using cfg_row_addr_width
begin
int_row_addr[j] = int_cmd_address[row_addr_loop_2];
end
else
begin
int_row_addr[j] = 1'b0;
end
end
end
// Derive bank address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_2;
always @(*)
begin : Bank_addr_loop
for (k = 0;k < MIN_BANK;k = k + 1'b1) // The purpose of using this for-loop is to get rid of "if (k < cfg_bank_addr_width) begin" which causes multiplexers
begin
bank_addr_loop_1 = k + cfg_addr_bitsel_bank;
int_bank_addr[k] = int_cmd_address[bank_addr_loop_1];
end
for (k = MIN_BANK;k < MAX_BANK;k = k + 1'b1)
begin
bank_addr_loop_2 = k + cfg_addr_bitsel_bank;
if (k < cfg_bank_addr_width) // Bit of bank_addr can be configured in CSR using cfg_bank_addr_width
begin
int_bank_addr[k] = int_cmd_address[bank_addr_loop_2];
end
else
begin
int_bank_addr[k] = 1'b0;
end
end
end
// Derive chipsel address from address
always @(*)
begin
m = 0;
if (cfg_cs_addr_width > 1'b0) // If cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
begin
for (m=0; m<MIN_CS; m=m+1'b1) // The purpose of using this for-loop is to get rid of "if (m < cfg_cs_addr_width) begin" which causes multiplexers
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1)
begin
if (m < cfg_cs_addr_width) // Bit of cs_addr can be configured in CSR using cfg_cs_addr_width
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
else
begin
int_cs_addr[m] = 1'b0;
end
end
end
else // If CFG_MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
begin
int_cs_addr = {CFG_MEM_IF_CS_WIDTH{1'b0}};
end
end
//===================== end of address remapping =========================
//======================= burst splitting logic ===========================
assign cmd_gen_full = mux_busy | deassert_ready;
assign copy = ~cmd_gen_full & cmd_valid; // Copy current input command info into a register
assign require_gen = (cmd_size > native_size | unaligned_burst + cmd_size > native_size) & cfg_enable_cmd_split; // Indicate that current input command require splitting
// CSR address calculation
always @ (*)
begin
max_chip_from_csr = (2**cfg_cs_addr_width) - 1'b1;
max_bank_from_csr = (2**cfg_bank_addr_width) - 1'b1;
max_row_from_csr = (2**cfg_row_addr_width) - 1'b1;
max_col_from_csr = (2**cfg_col_addr_width) - 1'b1;
end
// Calculate native size for selected burstlength and controller rate
always @ (*)
begin
native_size = cfg_burst_length / CFG_DWIDTH_RATIO; // 1 for bl2 FR, 2 for bl8 HR, ...
end
always @(*)
begin
if (native_size == 1)
begin
unaligned_burst = 0;
end
else if (native_size == 2)
begin
unaligned_burst = {2'd0,int_col_addr[log2(CFG_DWIDTH_RATIO)]};
end
else if (native_size == 4)
begin
unaligned_burst = {1'd0,int_col_addr[(log2(CFG_DWIDTH_RATIO)+1):log2(CFG_DWIDTH_RATIO)]};
end
else // native_size == 8
begin
unaligned_burst = int_col_addr[(log2(CFG_DWIDTH_RATIO)+2):log2(CFG_DWIDTH_RATIO)];
end
end
// Deassert local_ready signal because need to split local command into multiple memory commands
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
deassert_ready <= 0;
end
else
begin
if (copy && require_gen)
begin
deassert_ready <= 1;
end
else if ((buf_size > native_size*2) && cfg_enable_cmd_split)
begin
deassert_ready <= 1;
end
else if (generating && ~mux_busy)
begin
deassert_ready <= 0;
end
end
end
// Assert register signal so that we will pass split command into TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
registered <= 0;
end
else
begin
if (copy && require_gen)
begin
registered <= 1;
end
else
begin
registered <= 0;
end
end
end
// Generating signal will notify that current command in under splitting process
// Signal stays high until the last memory burst aligned command is generated
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
generating <= 0;
end
else
begin
if (registered)
begin
generating <= 1;
end
else if ((generating && buf_size > native_size*2) && cfg_enable_cmd_split)
begin
generating <= 1;
end
else if (~mux_busy)
begin
generating <= 0;
end
end
end
// Determine the correct size
always @(*)
begin
if (!generating)
begin
if ((unaligned_burst + cmd_size < native_size) || !cfg_enable_cmd_split) //(local_size > 1 && !unaligned_burst)
begin
split_size = cmd_size;
end
else
begin
split_size = native_size - unaligned_burst;
end
end
else
begin
if (decrmntd_size > native_size - 1)
begin
split_size = native_size;
end
else
begin
split_size = decrmntd_size;
end
end
end
// MUX logic to determine where to take the command info from
always @(*)
begin
if (!generating) // not generating so take direct input from avalon if
begin
split_read = cmd_read & cmd_valid & ~registered;
split_write = cmd_write & cmd_valid & ~registered;
split_autopch = cmd_autoprecharge;
split_multicast = cmd_multicast;
split_priority = cmd_priority;
split_localid = cmd_id;
split_cs_addr = int_cs_addr;
split_bank_addr = int_bank_addr;
split_row_addr = int_row_addr;
split_col_addr = int_col_addr;
end
else // generating cmd so process buffer content
begin
split_read = buf_read_req;
split_write = buf_write_req;
split_autopch = buf_autopch_req;
split_multicast = buf_multicast;
split_priority = buf_priority;
split_localid = buf_localid;
split_cs_addr = incrmntd_cs_addr;
split_bank_addr = incrmntd_bank_addr;
split_row_addr = incrmntd_row_addr;
if (cfg_burst_length == 2)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1],1'b0};
end
else if (cfg_burst_length == 4)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2],2'b00};
end
else if (cfg_burst_length == 8)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3],3'b000};
end
else // if (cfg_burst_length == 16)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4],4'b0000};
end
end
end
// Buffered command info, to be used in split process
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_read_req <= 1'b0;
buf_write_req <= 1'b0;
buf_autopch_req <= 1'b0;
buf_multicast <= 1'b0;
buf_priority <= 1'b0;
buf_localid <= 0;
end
else
begin
if (copy)
begin
buf_read_req <= cmd_read;
buf_write_req <= cmd_write;
buf_autopch_req <= cmd_autoprecharge;
buf_multicast <= cmd_multicast;
buf_priority <= cmd_priority;
buf_localid <= cmd_id;
end
end
end
// Keep track of command size during a split process
// will keep decreasing when a split command was sent to TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_size <= 0;
end
else
begin
if (copy)
begin
buf_size <= cmd_size + unaligned_burst;
end
else if (!registered && buf_size > native_size && ~mux_busy)
begin
buf_size <= buf_size - native_size;
end
end
end
always @(*)
begin
decrmntd_size = buf_size - native_size;
end
// Keep track of command address during a split process
// will keep increasing when a split command was sent to TBP
// also takes into account address order
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_cs_addr <= 0;
buf_bank_addr <= 0;
buf_row_addr <= 0;
buf_col_addr <= 0;
end
else
if (copy)
begin
buf_cs_addr <= int_cs_addr;
buf_bank_addr <= int_bank_addr;
buf_row_addr <= int_row_addr;
buf_col_addr <= int_col_addr;
end
else if (registered || (generating && ~mux_busy))
if ((cfg_burst_length == 16 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
||
(cfg_burst_length == 8 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
||
(cfg_burst_length == 4 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
||
(cfg_burst_length == 2 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
)
begin
if (cfg_burst_length == 16)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] <= 0;
else if (cfg_burst_length == 8)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] <= 0;
else if (cfg_burst_length == 4)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] <= 0;
else // if (cfg_burst_length == 2)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] <= 0;
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL) // 2 is rowchipbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
begin
buf_cs_addr <= 0;
if (buf_row_addr == max_row_from_csr)
buf_row_addr <= 0;
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL) // 1 is chipbankrowcol
begin
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else // 0 is chiprowbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
end
else
buf_col_addr <= buf_col_addr + cfg_burst_length;
end
always @(*)
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr;
end
//======================= end of burst splitting logic ===========================
//====================== ecc mux start ========================
// ECC process info
always @ (*)
begin
ecc_int_combi = ecc_int;
correct_combi = correct;
partial_combi = partial;
errcmd_ready_combi = errcmd_ready;
ecc_dataid_combi = ecc_dataid;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert partial after ECC write was sent to TBP
begin
partial_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (correct)
begin
errcmd_ready_combi = 1'b0;
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert correct after ECC write was sent to TBP
begin
correct_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // if there is a auto correction request
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b1;
partial_combi = 1'b0;
errcmd_ready_combi = 1'b1;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // if there is a write request in no-DM or ECC case
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b0;
partial_combi = 1'b1;
ecc_dataid_combi = wdatap_free_id_dataid;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int <= 0;
correct <= 0;
partial <= 0;
errcmd_ready <= 0;
ecc_dataid <= 0;
end
else
begin
ecc_int <= ecc_int_combi;
correct <= correct_combi;
partial <= partial_combi;
errcmd_ready <= errcmd_ready_combi;
ecc_dataid <= ecc_dataid_combi;
end
end
// Buffer for ECC command information
always @ (*)
begin
if (partial || correct)
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
else if (cfg_enable_ecc && errcmd_valid) // take in error command info
begin
ecc_cs_addr_combi = errcmd_chipsel;
ecc_bank_addr_combi = errcmd_bank;
ecc_row_addr_combi = errcmd_row;
ecc_col_addr_combi = errcmd_column;
ecc_size_combi = errcmd_size;
ecc_autopch_combi = 1'b0;
ecc_multicast_combi = 1'b0;
ecc_localid_combi = errcmd_localid;
ecc_priority_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // take in command info from split logic
begin
ecc_cs_addr_combi = split_cs_addr;
ecc_bank_addr_combi = split_bank_addr;
ecc_row_addr_combi = split_row_addr;
ecc_col_addr_combi = split_col_addr;
ecc_size_combi = split_size;
ecc_autopch_combi = split_autopch;
ecc_multicast_combi = split_multicast;
ecc_localid_combi = split_localid;
ecc_priority_combi = split_priority;
end
else
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_cs_addr <= 0;
ecc_bank_addr <= 0;
ecc_row_addr <= 0;
ecc_col_addr <= 0;
ecc_size <= 0;
ecc_autopch <= 0;
ecc_multicast <= 0;
ecc_localid <= 0;
ecc_priority <= 0;
end
else
begin
ecc_cs_addr <= ecc_cs_addr_combi;
ecc_bank_addr <= ecc_bank_addr_combi;
ecc_row_addr <= ecc_row_addr_combi;
ecc_col_addr <= ecc_col_addr_combi;
ecc_size <= ecc_size_combi;
ecc_autopch <= ecc_autopch_combi;
ecc_multicast <= ecc_multicast_combi;
ecc_localid <= ecc_localid_combi;
ecc_priority <= ecc_priority_combi;
end
end
// Logic to determine when to issue ECC read/write request
// based on partial_be info from wdata path
// if partial_be is high, it issues a read-modify-write command
// else issues normal write command
always @ (*)
begin
ecc_read_combi = ecc_read;
ecc_write_combi = ecc_write;
partial_opr_combi = partial_opr;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
partial_opr_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (data_complete[0]) // wait for data_complete from wdata path
begin
if (!data_partial_be) // if not partial_be, issues normal write
begin
ecc_write_combi = 1'b1;
end
else // else issues a RMW's read
begin
ecc_read_combi = 1'b1;
partial_opr_combi = 1'b1;
end
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
begin
ecc_write_combi = 1'b1;
end
else
begin
ecc_write_combi = 1'b0;
end
end
end
else if (correct)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
ecc_write_combi = 1'b1;
else
ecc_write_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // issues a RMW's read when there is a error correction
begin
ecc_read_combi = 1'b1;
ecc_write_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy)
begin
ecc_read_combi = 1'b0;
ecc_write_combi = 1'b0;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_read <= 1'b0;
ecc_write <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_read <= ecc_read_combi;
ecc_write <= ecc_write_combi;
partial_opr <= partial_opr_combi;
end
end
// We only need to gate split_read/write in non cmd_gen registered output mode
assign mux_busy = (
queue_full |
errcmd_valid |
(
(cfg_enable_no_dm | cfg_enable_ecc) &
(
ecc_int |
(
!(CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE) &
(
(split_read & ~rdatap_free_id_valid) |
(split_write & ~wdatap_free_id_valid)
)
)
)
)
);
assign muxed_cs_addr = ecc_int ? ecc_cs_addr : split_cs_addr;
assign muxed_bank_addr = ecc_int ? ecc_bank_addr : split_bank_addr;
assign muxed_row_addr = ecc_int ? ecc_row_addr : split_row_addr;
assign muxed_col_addr = ecc_int ? ecc_col_addr : split_col_addr;
assign muxed_read = ecc_int ? (CFG_CMD_GEN_OUTPUT_REG ? (ecc_read & rdatap_free_id_valid) : ecc_read) : split_read & ~errcmd_valid; // We only need to check for free ID valid in CMD_GEN_OUTPUT_REG mode
assign muxed_write = (cfg_enable_no_dm || cfg_enable_ecc) ? ecc_write : split_write & ~errcmd_valid;
assign muxed_size = ecc_int ? ecc_size : split_size;
assign muxed_autopch = ecc_int ? ecc_autopch : split_autopch;
assign muxed_multicast = ecc_int ? ecc_multicast : split_multicast;
assign muxed_localid = ecc_int ? ecc_localid : split_localid;
assign muxed_priority = ecc_int ? ecc_priority : split_priority;
assign muxed_dataid = ecc_int ? ecc_dataid : rdatap_free_id_dataid;
assign muxed_complete = ecc_int ? 1'b1 : split_read;
assign muxed_correct = ecc_int ? correct : 1'b0;
assign muxed_partial = ecc_int ? partial_opr : 1'b0;
assign muxed_same_chipsel_addr = ecc_int_r ? ecc_same_chipsel_addr : split_same_chipsel_addr;
assign muxed_same_bank_addr = ecc_int_r ? ecc_same_bank_addr : split_same_bank_addr;
assign muxed_same_row_addr_0 = ecc_int_r ? ecc_same_row_addr_0 : split_same_row_addr_0;
assign muxed_same_row_addr_1 = ecc_int_r ? ecc_same_row_addr_1 : split_same_row_addr_1;
assign muxed_same_row_addr_2 = ecc_int_r ? ecc_same_row_addr_2 : split_same_row_addr_2;
assign muxed_same_row_addr_3 = ecc_int_r ? ecc_same_row_addr_3 : split_same_row_addr_3;
assign muxed_same_col_addr = ecc_int_r ? ecc_same_col_addr : split_same_col_addr;
assign muxed_same_read_cmd = ecc_int_r ? ecc_same_read_cmd : split_same_read_cmd;
assign muxed_same_write_cmd = ecc_int_r ? ecc_same_write_cmd : split_same_write_cmd;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int_r <= 1'b0;
end
else
begin
ecc_int_r <= ecc_int;
end
end
// Address comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (split_cs_addr == chipsel[j])
begin
split_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
split_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (split_bank_addr == bank[j])
begin
split_same_bank_addr_combi[j] = 1'b1;
end
else
begin
split_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (split_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_0_combi[j] = 1'b0;
end
if (split_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_1_combi[j] = 1'b0;
end
if (split_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_2_combi[j] = 1'b0;
end
if (split_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (split_col_addr == col[j])
begin
split_same_col_addr_combi[j] = 1'b1;
end
else
begin
split_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (split_read == read[j])
begin
split_same_read_cmd_combi[j] = 1'b1;
end
else
begin
split_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (split_write == write[j])
begin
split_same_write_cmd_combi[j] = 1'b1;
end
else
begin
split_same_write_cmd_combi[j] = 1'b0;
end
end
end
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (ecc_cs_addr == chipsel[j])
begin
ecc_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (ecc_bank_addr == bank[j])
begin
ecc_same_bank_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (ecc_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_0_combi[j] = 1'b0;
end
if (ecc_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_1_combi[j] = 1'b0;
end
if (ecc_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_2_combi[j] = 1'b0;
end
if (ecc_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (ecc_col_addr == col[j])
begin
ecc_same_col_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (ecc_read == read[j])
begin
ecc_same_read_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (ecc_write == write[j])
begin
ecc_same_write_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_write_cmd_combi[j] = 1'b0;
end
end
end
generate
if (CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE)
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
proc_write_sig <= 0;
proc_read_sig <= 0;
proc_size_sig <= 0;
proc_localid_sig <= 0;
proc_load_dataid_sig <= 0;
proc_ecc_busy_sig <= 0;
end
else
begin
if (proc_busy_sig)
begin
// Do nothing, keep old value
end
else
begin
proc_load_dataid_sig <= ~(ecc_int & (ecc_read | ecc_write));
if (ecc_int)
begin
proc_write_sig <= ecc_write & correct;
proc_read_sig <= ecc_read;
proc_size_sig <= ecc_size;
proc_localid_sig <= ecc_localid;
proc_ecc_busy_sig <= (ecc_read & ~rdatap_free_id_valid) | ((ecc_write & correct) & ~wdatap_free_id_valid);
end
else
begin
proc_write_sig <= split_write & ~errcmd_valid;
proc_read_sig <= split_read & ~errcmd_valid;
proc_size_sig <= split_size;
proc_localid_sig <= split_localid;
proc_ecc_busy_sig <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_same_chipsel_addr <= 0;
split_same_bank_addr <= 0;
split_same_row_addr_0 <= 0;
split_same_row_addr_1 <= 0;
split_same_row_addr_2 <= 0;
split_same_row_addr_3 <= 0;
split_same_col_addr <= 0;
split_same_read_cmd <= 0;
split_same_write_cmd <= 0;
ecc_same_chipsel_addr <= 0;
ecc_same_bank_addr <= 0;
ecc_same_row_addr_0 <= 0;
ecc_same_row_addr_1 <= 0;
ecc_same_row_addr_2 <= 0;
ecc_same_row_addr_3 <= 0;
ecc_same_col_addr <= 0;
ecc_same_read_cmd <= 0;
ecc_same_write_cmd <= 0;
end
else
begin
split_same_chipsel_addr <= split_same_chipsel_addr_combi;
split_same_bank_addr <= split_same_bank_addr_combi;
split_same_row_addr_0 <= split_same_row_addr_0_combi;
split_same_row_addr_1 <= split_same_row_addr_1_combi;
split_same_row_addr_2 <= split_same_row_addr_2_combi;
split_same_row_addr_3 <= split_same_row_addr_3_combi;
split_same_col_addr <= split_same_col_addr_combi;
split_same_read_cmd <= split_same_read_cmd_combi;
split_same_write_cmd <= split_same_write_cmd_combi;
ecc_same_chipsel_addr <= ecc_same_chipsel_addr_combi;
ecc_same_bank_addr <= ecc_same_bank_addr_combi;
ecc_same_row_addr_0 <= ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 <= ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 <= ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 <= ecc_same_row_addr_3_combi;
ecc_same_col_addr <= ecc_same_col_addr_combi;
ecc_same_read_cmd <= ecc_same_read_cmd_combi;
ecc_same_write_cmd <= ecc_same_write_cmd_combi;
end
end
end
else
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_ecc_busy_sig = zero;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
proc_load_dataid_sig = ~(ecc_int & (ecc_read | ecc_write));
proc_write_sig = ecc_int ? ecc_write & correct : split_write & ~errcmd_valid;
proc_read_sig = ecc_int ? ecc_read : split_read & ~errcmd_valid;
proc_size_sig = ecc_int ? ecc_size : split_size;
proc_localid_sig = ecc_int ? ecc_localid : split_localid;
end
always @ (*)
begin
split_same_chipsel_addr = split_same_chipsel_addr_combi;
split_same_bank_addr = split_same_bank_addr_combi;
split_same_row_addr_0 = split_same_row_addr_0_combi;
split_same_row_addr_1 = split_same_row_addr_1_combi;
split_same_row_addr_2 = split_same_row_addr_2_combi;
split_same_row_addr_3 = split_same_row_addr_3_combi;
split_same_col_addr = split_same_col_addr_combi;
split_same_read_cmd = split_same_read_cmd_combi;
split_same_write_cmd = split_same_write_cmd_combi;
ecc_same_chipsel_addr = ecc_same_chipsel_addr_combi;
ecc_same_bank_addr = ecc_same_bank_addr_combi;
ecc_same_row_addr_0 = ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 = ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 = ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 = ecc_same_row_addr_3_combi;
ecc_same_col_addr = ecc_same_col_addr_combi;
ecc_same_read_cmd = ecc_same_read_cmd_combi;
ecc_same_write_cmd = ecc_same_write_cmd_combi;
end
end
endgenerate
//====================== ecc mux end ========================
//====================== sequential address detector ========================
//Last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n)
begin
last_read_req <= 1'b0;
last_write_req <= 1'b0;
last_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last_read_req <= muxed_read;
last_write_req <= muxed_write;
last_multicast <= muxed_multicast;
last_chip_addr <= muxed_cs_addr;
last_bank_addr <= muxed_bank_addr;
last_row_addr <= muxed_row_addr;
last_col_addr <= muxed_col_addr;
last_size <= muxed_size;
end
else if (can_merge)
begin
last_size <= 2;
end
end
//Second last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last2_read_req <= 1'b0;
last2_write_req <= 1'b0;
last2_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last2_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last2_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last2_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last2_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last2_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last2_read_req <= last_read_req;
last2_write_req <= last_write_req;
last2_multicast <= last_multicast;
last2_chip_addr <= last_chip_addr;
last2_bank_addr <= last_bank_addr;
last2_row_addr <= last_row_addr;
last2_col_addr <= last_col_addr;
last2_size <= last_size;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last <= 0;
last_minus_one <= 0;
last_minus_two <= 0;
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
if (write_to_queue)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
else
begin
last <= last - 2;
last_minus_one <= last - 3;
last_minus_two <= last - 4;
end
end
else
begin
if (write_to_queue) begin
// do nothing
end
else if (last != 0)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
// do nothing
end
else if (!queue_empty)
begin
last <= last + 1;
last_minus_one <= last;
last_minus_two <= last - 1;
end
end
else if (can_merge)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
// Merging logic
assign can_merge = (CFG_ENABLE_BURST_MERGE == 1) ?
last != 0
& pipefull[last]
& last2_read_req == last_read_req
& last2_write_req == last_write_req
& last2_multicast == last_multicast
& last2_chip_addr == last_chip_addr
& last2_bank_addr == last_bank_addr
& last2_row_addr == last_row_addr
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2]) : (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3]) )
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[1] == 0 & last_col_addr[1] == 1) : (last2_col_addr[2] == 0 & last_col_addr[2] == 1) )
& last2_size == 1 & last_size == 1
:
1'b0;
//=================== end of sequential address detector ====================
//=============================== queue ===================================
// mapping of buffer_input
assign buffer_input = {muxed_read,muxed_write,muxed_multicast,muxed_autopch,muxed_priority,muxed_complete,muxed_correct,muxed_partial,muxed_dataid,muxed_localid,muxed_size,muxed_cs_addr,muxed_row_addr,muxed_bank_addr,muxed_col_addr};
generate
if (CFG_ENABLE_QUEUE == 1)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
// TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr = muxed_same_row_addr_0 & muxed_same_row_addr_1 & muxed_same_row_addr_2 & muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
// Chipselect address
if (cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
assign queue_empty = !pipefull[0];
assign queue_full = pipefull[CFG_CTL_QUEUE_DEPTH-1] | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
assign cmd_gen_load = pipefull[0] & ((cfg_enable_no_dm | cfg_enable_ecc) | ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid)));
assign cmd_gen_read = pipe[0][BUFFER_WIDTH-1];
assign cmd_gen_write = pipe[0][BUFFER_WIDTH-2];
assign cmd_gen_multicast = pipe[0][BUFFER_WIDTH-3];
assign cmd_gen_autopch = pipe[0][BUFFER_WIDTH-4];
assign cmd_gen_priority = pipe[0][BUFFER_WIDTH-5];
assign cmd_gen_complete = pipe[0][BUFFER_WIDTH-6];
assign cmd_gen_rmw_correct = pipe[0][BUFFER_WIDTH-7];
assign cmd_gen_rmw_partial = pipe[0][BUFFER_WIDTH-8];
assign cmd_gen_dataid = cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid;
assign cmd_gen_localid = pipe[0][CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_size = pipe[0][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_chipsel = pipe[0][CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_row = pipe[0][CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_bank = pipe[0][CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_col = pipe[0][CFG_MEM_IF_COL_WIDTH - 1 : 0];
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
else
begin
wire int_queue_full;
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
reg int_register_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cmd_gen_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_cmd_gen_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_cmd_gen_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_cmd_gen_col;
reg int_cmd_gen_write;
reg int_cmd_gen_read;
reg int_cmd_gen_multicast;
reg [CFG_INT_SIZE_WIDTH-1:0] int_cmd_gen_size;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_cmd_gen_localid;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid;
reg int_cmd_gen_priority;
reg int_cmd_gen_rmw_correct;
reg int_cmd_gen_rmw_partial;
reg int_cmd_gen_autopch;
reg int_cmd_gen_complete;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid_mux;
// TBP address and command comparison logic
always @ (*)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr_0 = muxed_same_row_addr_0;
int_same_row_addr_1 = muxed_same_row_addr_1;
int_same_row_addr_2 = muxed_same_row_addr_2;
int_same_row_addr_3 = muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (int_queue_full)
begin
// Chipselect address
if (int_cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (int_cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (int_cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
else
begin
// Chipselect address
if (muxed_cs_addr == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (muxed_bank_addr == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (muxed_row_addr == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
end
if (CFG_CMD_GEN_OUTPUT_REG)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr_r;
reg int_ecc_int;
reg int_queue_full_r;
assign int_queue_full = (tbp_full & int_register_valid) | ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid));
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_queue_full_r <= 1'b0;
end
else
begin
int_queue_full_r <= int_queue_full;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 0;
int_cmd_gen_write <= 0;
int_cmd_gen_multicast <= 0;
int_cmd_gen_autopch <= 0;
int_cmd_gen_priority <= 0;
int_cmd_gen_complete <= 0;
int_cmd_gen_rmw_correct <= 0;
int_cmd_gen_rmw_partial <= 0;
int_cmd_gen_dataid <= 0;
int_cmd_gen_localid <= 0;
int_cmd_gen_size <= 0;
int_cmd_gen_chipsel <= 0;
int_cmd_gen_row <= 0;
int_cmd_gen_bank <= 0;
int_cmd_gen_col <= 0;
int_ecc_int <= 0;
end
else
begin
if (fetch)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 1'b0;
int_cmd_gen_write <= 1'b0;
end
if (!int_queue_full)
begin
if (muxed_read || muxed_write)
begin
int_register_valid <= 1'b1;
end
int_cmd_gen_read <= muxed_read;
int_cmd_gen_write <= muxed_write;
int_cmd_gen_multicast <= muxed_multicast;
int_cmd_gen_autopch <= muxed_autopch;
int_cmd_gen_priority <= muxed_priority;
int_cmd_gen_complete <= muxed_complete;
int_cmd_gen_rmw_correct <= muxed_correct;
int_cmd_gen_rmw_partial <= muxed_partial;
int_cmd_gen_dataid <= muxed_dataid;
int_cmd_gen_localid <= muxed_localid;
int_cmd_gen_size <= muxed_size;
int_cmd_gen_chipsel <= muxed_cs_addr;
int_cmd_gen_row <= muxed_row_addr;
int_cmd_gen_bank <= muxed_bank_addr;
int_cmd_gen_col <= muxed_col_addr;
int_ecc_int <= ecc_int;
end
end
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_ecc_int ? int_cmd_gen_dataid : rdatap_free_id_dataid;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_same_chipsel_addr_r <= 0;
int_same_bank_addr_r <= 0;
int_same_row_addr_0_r <= 0;
int_same_row_addr_1_r <= 0;
int_same_row_addr_2_r <= 0;
int_same_row_addr_3_r <= 0;
int_same_col_addr_r <= 0;
int_same_read_cmd_r <= 0;
int_same_write_cmd_r <= 0;
int_same_shadow_chipsel_addr_r <= 0;
int_same_shadow_bank_addr_r <= 0;
int_same_shadow_row_addr_r <= 0;
end
else
begin
if (int_queue_full & !int_queue_full_r) // positive edge detector
begin
int_same_chipsel_addr_r <= int_same_chipsel_addr;
int_same_bank_addr_r <= int_same_bank_addr;
int_same_row_addr_0_r <= int_same_row_addr_0;
int_same_row_addr_1_r <= int_same_row_addr_1;
int_same_row_addr_2_r <= int_same_row_addr_2;
int_same_row_addr_3_r <= int_same_row_addr_3;
int_same_col_addr_r <= int_same_col_addr;
int_same_read_cmd_r <= int_same_read_cmd;
int_same_write_cmd_r <= int_same_write_cmd;
end
int_same_shadow_chipsel_addr_r <= int_same_shadow_chipsel_addr;
int_same_shadow_bank_addr_r <= int_same_shadow_bank_addr;
int_same_shadow_row_addr_r <= int_same_shadow_row_addr;
end
end
always @ (*)
begin
if (!int_queue_full_r)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1 & int_same_row_addr_2 & int_same_row_addr_3;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
end
else
begin
same_chipsel_addr = int_same_chipsel_addr_r;
same_bank_addr = int_same_bank_addr_r;
same_row_addr = int_same_row_addr_0_r & int_same_row_addr_1_r & int_same_row_addr_2_r & int_same_row_addr_3_r;
same_col_addr = int_same_col_addr_r;
same_read_cmd = int_same_read_cmd_r;
same_write_cmd = int_same_write_cmd_r;
end
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr_r;
same_shadow_bank_addr = int_same_shadow_bank_addr_r;
same_shadow_row_addr = int_same_shadow_row_addr_r;
end
end
else
begin
assign int_queue_full = tbp_full | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
always @ (*)
begin
int_register_valid = one;
int_cmd_gen_read = muxed_read;
int_cmd_gen_write = muxed_write;
int_cmd_gen_multicast = muxed_multicast;
int_cmd_gen_autopch = muxed_autopch;
int_cmd_gen_priority = muxed_priority;
int_cmd_gen_complete = muxed_complete;
int_cmd_gen_rmw_correct = muxed_correct;
int_cmd_gen_rmw_partial = muxed_partial;
int_cmd_gen_dataid = muxed_dataid;
int_cmd_gen_localid = muxed_localid;
int_cmd_gen_size = muxed_size;
int_cmd_gen_chipsel = muxed_cs_addr;
int_cmd_gen_row = muxed_row_addr;
int_cmd_gen_bank = muxed_bank_addr;
int_cmd_gen_col = muxed_col_addr;
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_cmd_gen_dataid;
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
end
assign queue_empty = 1;
assign queue_full = int_queue_full;
assign cmd_gen_load = (cmd_gen_read | cmd_gen_write) & ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid));
assign cmd_gen_read = int_cmd_gen_read;
assign cmd_gen_write = int_cmd_gen_write;
assign cmd_gen_multicast = int_cmd_gen_multicast;
assign cmd_gen_autopch = int_cmd_gen_autopch;
assign cmd_gen_priority = int_cmd_gen_priority;
assign cmd_gen_complete = int_cmd_gen_complete;
assign cmd_gen_rmw_correct = int_cmd_gen_rmw_correct;
assign cmd_gen_rmw_partial = int_cmd_gen_rmw_partial;
assign cmd_gen_dataid = (cfg_enable_no_dm || cfg_enable_ecc) ? int_cmd_gen_dataid_mux : (cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid);
assign cmd_gen_localid = int_cmd_gen_localid;
assign cmd_gen_size = int_cmd_gen_size;
assign cmd_gen_chipsel = int_cmd_gen_chipsel;
assign cmd_gen_row = int_cmd_gen_row;
assign cmd_gen_bank = int_cmd_gen_bank;
assign cmd_gen_col = int_cmd_gen_col;
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
endgenerate
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign write_to_queue = (muxed_read | muxed_write) & ~queue_full;
assign fetch = cmd_gen_load & ~tbp_full;
// proc signals to datapath
assign proc_busy = (cfg_enable_no_dm || cfg_enable_ecc) ? (proc_busy_sig | proc_ecc_busy_sig) : tbp_full;
assign proc_load = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_sig : cmd_gen_load;
assign proc_load_dataid= (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_dataid_sig : cmd_gen_load;
assign proc_write = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_write_sig : cmd_gen_write;
assign proc_read = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_read_sig : cmd_gen_read;
assign proc_size = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_size_sig : cmd_gen_size;
assign proc_localid = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_localid_sig : cmd_gen_localid;
assign tbp_load_index = (cfg_enable_no_dm || cfg_enable_ecc) ? 1 : tbp_load;
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
pipefull[j] <= 1'b0;
pipe [j] <= 0;
end
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else if (j == last_minus_one)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else if (j == last_minus_two)
begin
pipe[j] <= {pipe[j+1][BUFFER_WIDTH-1:BUFFER_WIDTH-4],2'd2,pipe[j+1][BUFFER_WIDTH-7:0]};
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe[CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
else
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= pipefull[CFG_CTL_QUEUE_DEPTH-1] & write_to_queue;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe [CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
pipe[last] <= buffer_input;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
else
begin
for(j=1; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0)
begin
pipefull[j] <= 1'b1;
pipe [j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0)
begin
pipefull[0] <= 1'b1;
pipe [0] <= buffer_input;
end
end
end
else if (can_merge)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else
begin
pipefull[j] <= pipefull[j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
end
end
//============================ end of queue ===============================
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_controller #
( parameter
// Local interface parameters
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_LOCAL_DATA_WIDTH = 80, // Maximum DQ width of 40
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_IF_TYPE = "AVALON",
// Memory interface parameters
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 15,
CFG_MEM_IF_COL_WIDTH = 12,
CFG_MEM_IF_ADDR_WIDTH = 15,
CFG_MEM_IF_CKE_WIDTH = 2,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_MEM_IF_DM_WIDTH = 5,
// Controller parameters
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1, // NOTICE: required?
CFG_OUTPUT_REGD = 0, // NOTICE: un-used and will be removed
CFG_CTL_TBP_NUM = 4,
CFG_LPDDR2_ENABLED = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_ECC_MULTIPLES_16_24_40_72 = 1,
// Data path buffer & fifo parameters
CFG_WRBUFFER_ADDR_WIDTH = 6,
CFG_RDBUFFER_ADDR_WIDTH = 10,
// MMR port width
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_DEVICE_WIDTH = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
// cfg: address mapping signals
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// cfg: control signals
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_USER_RFSH = 1,
CFG_PORT_WIDTH_SELF_RFSH = 1,
CFG_PORT_WIDTH_REGDIMM_ENABLE = 1,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_CMD_SPLIT = 1'b1, // disable this (set to 0) when using the controller with hard MPFE
// cfg: ecc signals
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
// cfg: odt
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
// cfg: ecc signals
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8,
// PHY parameters
CFG_WLAT_BUS_WIDTH = 4,
// controller read data return mode
CFG_RDATA_RETURN_MODE = "PASSTHROUGH"
)
(
// Clock and reset
ctl_clk,
ctl_reset_n,
// Command channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// Write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// Read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
itf_rd_data_id_early_valid, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
// Sideband signals
local_refresh_req,
local_refresh_chip,
local_deep_powerdn_chip,
local_deep_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
// Controller commands to the AFI interface
afi_rst_n,
afi_ba,
afi_addr,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_odt,
// Controller read and write data to the AFI interface
afi_wlat,
afi_dqs_burst,
afi_dm,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
// Status and control signal to the AFI interface
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_init_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
// cfg: general
cfg_type,
cfg_interface_width, // not sure where this signal is used
cfg_burst_length,
cfg_device_width, // not sure where this signal is used
cfg_output_regd,
// cfg: address mapping signals
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// cfg: timing parameters
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_auto_pd_cycles,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_power_saving_exit_cycles,
cfg_mem_clk_entry_cycles,
cfg_tmrd,
// cfg: extra timing parameters
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// cfg: control signals
cfg_reorder_data, // enable data reordering
cfg_starve_limit, // starvation counter limit
cfg_user_rfsh,
cfg_regdimm_enable,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// cfg: ecc signals
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_ecc_code_overwrites,
cfg_enable_no_dm,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// cfg: odt
cfg_write_odt_chip,
cfg_read_odt_chip,
// sts: ecc signals
ecc_interrupt,
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
//calibration
cfg_cal_req,
sts_cal_fail,
sts_cal_success,
// DQS enable tracking
cfg_enable_dqs_tracking, //enable DQS enable tracking support in controller
afi_ctl_refresh_done, // Controller asserts this after tRFC is done, also acts as stall ack to phy
afi_seq_busy, // Sequencer busy signal to controller, also acts as stall request to ctlr
afi_ctl_long_idle // Controller asserts this after long period of no refresh, protocol is the same as rfsh_done
);
// General parameters
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_INT_SIZE_WIDTH = (CFG_DWIDTH_RATIO == 2) ? 4 : ((CFG_DWIDTH_RATIO == 4) ? 3 : ((CFG_DWIDTH_RATIO == 8) ? 2 : 4));
localparam CFG_CTL_QUEUE_DEPTH = 8;
localparam CFG_ENABLE_QUEUE = 0;
localparam CFG_ENABLE_BURST_MERGE = 0;
localparam CFG_CMD_GEN_OUTPUT_REG = 1; // only in effect when CFG_ENABLE_QUEUE is set to '0'
localparam CFG_CTL_ARBITER_TYPE = "ROWCOL";
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_CODE_WIDTH = 8;
localparam CFG_ECC_MULTIPLES = CFG_DWIDTH_RATIO * CFG_ECC_MULTIPLES_16_24_40_72;
localparam CFG_PARTIAL_BE_PER_WORD_ENABLE = 1;
localparam CFG_ENABLE_BURST_GEN_OUTPUT_REG = 1;
localparam CFG_DISABLE_PRIORITY = 1;
localparam CFG_REG_GRANT = (CFG_DWIDTH_RATIO == 8) ? 0 : 1; // disable grant register for better efficiency in quarter rate
localparam CFG_REG_REQ = 0;
localparam CFG_RANK_TIMER_OUTPUT_REG = 1;
localparam CFG_ECC_DEC_REG = 1;
localparam CFG_ECC_RDATA_REG = 1;
localparam CFG_ECC_ENC_REG = 1; // only one of CFG_ECC_ENC_REG / CFG_WDATA_REG can be set to '1'
localparam CFG_WDATA_REG = 0; // only one of CFG_ECC_ENC_REG / CFG_WDATA_REG can be set to '1'
localparam CFG_DISABLE_READ_REODERING = 0;
localparam CFG_ENABLE_SHADOW_TBP = 0;
localparam CFG_CTL_SHADOW_TBP_NUM = CFG_CTL_TBP_NUM; // similar to TBP number
// Datapath buffer & fifo size calculation
localparam CFG_MAX_PENDING_RD_CMD = 16; // temporary
localparam CFG_MAX_PENDING_WR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_ERR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_RD_CMD_WIDTH = log2(CFG_MAX_PENDING_RD_CMD);
localparam CFG_WRDATA_ID_WIDTH = log2(CFG_MAX_PENDING_WR_CMD);
localparam CFG_ERRCMD_FIFO_ADDR_WIDTH = log2(CFG_MAX_PENDING_ERR_CMD);
localparam CFG_RDDATA_ID_WIDTH = CFG_RDBUFFER_ADDR_WIDTH - CFG_INT_SIZE_WIDTH;
localparam CFG_DATA_ID_WIDTH = (CFG_WRDATA_ID_WIDTH >= CFG_RDDATA_ID_WIDTH) ? CFG_WRDATA_ID_WIDTH : CFG_RDDATA_ID_WIDTH;
localparam integer CFG_DATA_ID_REMAINDER = 2**(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH);
localparam CFG_WRDATA_VEC_ID_WIDTH = CFG_MAX_PENDING_WR_CMD;
// AFI
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH;
localparam CFG_DRAM_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : CFG_MEM_IF_DQS_WIDTH; // Supports single / multiple DQS group of afi_wlat
localparam CFG_LOCAL_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : (((CFG_LOCAL_DATA_WIDTH / CFG_DWIDTH_RATIO) == CFG_MEM_IF_DQ_WIDTH) ? CFG_MEM_IF_DQS_WIDTH : CFG_MEM_IF_DQS_WIDTH - CFG_ECC_MULTIPLES_16_24_40_72); // Determine the wlat group for local data width (without ECC code)
// Derived timing parameters width
localparam T_PARAM_ACT_TO_RDWR_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_ACT_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_RD_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_BC_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_RD_AP_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_WR_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_BC_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_WR_AP_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_PCH_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_PCH_ALL_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 6; // temporary
localparam T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 6; // temporary
localparam T_PARAM_ARF_TO_VALID_WIDTH = 8; // temporary
localparam T_PARAM_PDN_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_SRF_TO_VALID_WIDTH = 10; // temporary
localparam T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10; // temporary
localparam T_PARAM_ARF_PERIOD_WIDTH = 13; // temporary
localparam T_PARAM_PDN_PERIOD_WIDTH = 16; // temporary
localparam T_PARAM_POWER_SAVING_EXIT_WIDTH = 6; // temporary
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam integer CFG_WRDATA_ID_WIDTH_SQRD = 2**CFG_WRDATA_ID_WIDTH;
// Clock and reset
input ctl_clk;
input ctl_reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// Sideband signals
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
// Controller commands to the AFI interface
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
output [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
// Controller read and write data to the AFI interface
input [CFG_WLAT_BUS_WIDTH - 1 : 0] afi_wlat;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
output [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
output [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
input [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Status and control signal to the AFI interface
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output ctl_init_req;
output [CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n ;
output [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// cfg: general
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd;
// cfg: address mapping signals
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// cfg: timing parameters
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
// cfg: extra timing parameters
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// cfg: control signals
input [CFG_PORT_WIDTH_REORDER_DATA - 1 : 0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
input [CFG_PORT_WIDTH_USER_RFSH - 1 : 0] cfg_user_rfsh;
input [CFG_PORT_WIDTH_REGDIMM_ENABLE - 1 : 0] cfg_regdimm_enable;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// cfg: ecc signals
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites;
// cfg: odt
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
// sts: ecc signals
output ecc_interrupt;
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// calibration signals
input cfg_cal_req;
output sts_cal_fail;
output sts_cal_success;
// DQS enable tracking
input cfg_enable_dqs_tracking;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
//==============================================================================
//
// Wires
//
//==============================================================================
// General
wire init_done = ctl_cal_success;
wire sts_cal_success = ctl_cal_success;
wire sts_cal_fail = ctl_cal_fail;
wire ctl_cal_req = cfg_cal_req;
wire ctl_init_req;
wire [CFG_MEM_IF_DQS_WIDTH*CFG_MEM_IF_CHIP-1: 0] ctl_cal_byte_lane_sel_n = 0;
// alt_mem_ddrx_input_if
wire itf_cmd_ready;
wire itf_wr_data_ready;
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
wire cmd_valid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] cmd_address;
wire cmd_write;
wire cmd_read;
wire cmd_multicast;
wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] cmd_size;
wire cmd_priority;
wire cmd_autoprecharge;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_id;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] write_data;
wire [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] byte_en;
wire write_data_valid;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] write_data_id;
wire local_refresh_ack;
wire local_deep_powerdn_ack;
wire local_power_down_ack;
wire local_self_rfsh_ack;
wire local_init_done;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] rfsh_chip;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] deep_powerdn_chip;
wire self_rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] self_rfsh_chip;
// alt_mem_ddrx_cmd_gen
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_row_addr;
wire cmd_gen_full;
// alt_mem_ddrx_tbp
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM - 1 : 0] row_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
wire [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
wire [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
wire [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_bank_active;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_timer_ready;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load_index;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
// alt_mem_ddrx_arbiter
wire [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
wire or_row_grant;
wire or_col_grant;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// alt_mem_ddrx_burst_gen
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
wire bg_interrupt_ready_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
wire bg_do_lmr_read = 0;
wire bg_do_refresh_1bank = 0;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
wire bg_doing_write;
wire bg_doing_read;
wire bg_rdwr_data_valid;
wire bg_interrupt_ready;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] bg_rddataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
wire [ 7 : 0] bg_to_lmr = 0;
// alt_mem_ddrx_addr_cmd_wrap
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
wire [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
wire [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
wire [CFG_AFI_IF_FR_ADDR_WIDTH - 1 : 0] lmr_opcode = 0;
// alt_mem_ddrx_rdwr_data_tmg
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
wire [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_read;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_first;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_first;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_last;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_last;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
// alt_mem_ddrx_wdata_path
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
wire wdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] wdatap_free_id_dataid;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] wdatap_free_id_wrdataid;
wire wr_data_mem_full;
wire [CFG_CTL_TBP_NUM - 1 : 0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [(CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS) - 1 : 0] wdatap_dm;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
wire [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// alt_mem_ddrx_rdata_path
wire rdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] rdatap_free_id_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] rdatap_free_id_rddataid;
wire read_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] read_data;
wire read_data_error;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] read_data_localid;
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
wire rdatap_rcvd_cmd;
wire rdatap_rcvd_corr_dropped;
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
wire ecc_rdata_valid;
wire [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
wire ecc_interrupt;
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// alt_mem_ddrx_sideband
wire rfsh_ack;
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire stall_row_arbiter;
wire stall_col_arbiter;
wire [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
wire [CFG_CTL_TBP_NUM - 1 : 0] sb_tbp_precharge_all;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// alt_mem_ddrx_rank_timer
wire [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_write;
// alt_mem_ddrx_timing_param
wire [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
wire [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
wire [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
wire [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
wire [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
wire [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
wire [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
wire [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
wire [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
wire [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
wire [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
wire [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
wire [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
wire [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
wire [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
wire [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
wire [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
wire [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
wire [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
wire [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
wire [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
wire [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
wire [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
wire [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
wire [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
wire [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
wire [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
wire [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
// Log 2 function
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
// register init_done signal
reg init_done_reg;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
init_done_reg <= 0;
end
else
begin
init_done_reg <= init_done;
end
end
//==============================================================================
// alt_mem_ddrx_input_if
//------------------------------------------------------------------------------
//
// Input interface block
//
// Info: Includes cmd channel, and both read and write channels
// * Optional half-rate bridge logic
//
//==============================================================================
alt_mem_ddrx_input_if #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE )
)
input_if_inst
(
.itf_cmd_ready (itf_cmd_ready ),
.itf_cmd_valid (itf_cmd_valid ),
.itf_cmd (itf_cmd ),
.itf_cmd_address (itf_cmd_address ),
.itf_cmd_burstlen (itf_cmd_burstlen ),
.itf_cmd_id (itf_cmd_id ),
.itf_cmd_priority (itf_cmd_priority ),
.itf_cmd_autopercharge (itf_cmd_autopercharge ),
.itf_cmd_multicast (itf_cmd_multicast ),
.itf_wr_data_ready (itf_wr_data_ready ),
.itf_wr_data_valid (itf_wr_data_valid ),
.itf_wr_data (itf_wr_data ),
.itf_wr_data_byte_en (itf_wr_data_byte_en ),
.itf_wr_data_begin (itf_wr_data_begin ),
.itf_wr_data_last (itf_wr_data_last ),
.itf_wr_data_id (itf_wr_data_id ),
.itf_rd_data_ready (itf_rd_data_ready ),
.itf_rd_data_valid (itf_rd_data_valid ),
.itf_rd_data (itf_rd_data ),
.itf_rd_data_error (itf_rd_data_error ),
.itf_rd_data_begin (itf_rd_data_begin ),
.itf_rd_data_last (itf_rd_data_last ),
.itf_rd_data_id (itf_rd_data_id ),
.itf_rd_data_id_early (itf_rd_data_id_early ),
.itf_rd_data_id_early_valid(itf_rd_data_id_early_valid ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.cmd_id (cmd_id ),
.write_data (write_data ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_id (write_data_id ),
.byte_en (byte_en ),
.write_data_valid (write_data_valid ),
.read_data (read_data ),
.read_data_valid (read_data_valid ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.read_data_begin ( ), // NOTICE: not connected?
.read_data_last ( ), // NOTICE: not connected?
.bg_do_read (bg_do_read ),
.bg_localid (bg_localid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.local_refresh_req (local_refresh_req ),
.local_refresh_chip (local_refresh_chip ),
.local_deep_powerdn_req (local_deep_powerdn_req ),
.local_deep_powerdn_chip (local_deep_powerdn_chip ),
.local_self_rfsh_req (local_self_rfsh_req ),
.local_self_rfsh_chip (local_self_rfsh_chip ),
.local_refresh_ack (local_refresh_ack ),
.local_deep_powerdn_ack (local_deep_powerdn_ack ),
.local_power_down_ack (local_power_down_ack ),
.local_self_rfsh_ack (local_self_rfsh_ack ),
.local_init_done (local_init_done ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.self_rfsh_ack (self_rfsh_ack ),
.init_done (init_done_reg )
);
//==============================================================================
// alt_mem_ddrx_cmd_gen
//------------------------------------------------------------------------------
//
// Command generator block
//
// Info: * generates cmd from local and internal ECC block
// * splitting and merging of all commands
// * optional queue for latency reduction purpose when no merging is required
//
//==============================================================================
alt_mem_ddrx_cmd_gen #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_QUEUE_DEPTH (CFG_CTL_QUEUE_DEPTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_ENABLE_QUEUE (CFG_ENABLE_QUEUE ),
.CFG_ENABLE_BURST_MERGE (CFG_ENABLE_BURST_MERGE ),
.CFG_CMD_GEN_OUTPUT_REG (CFG_CMD_GEN_OUTPUT_REG ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM )
)
cmd_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_load (tbp_load ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_multicast (cmd_gen_multicast ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_id (cmd_id ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_dataid ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_dataid ),
.tbp_load_index (tbp_load_index ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.data_partial_be (data_partial_be ),
.cfg_enable_cmd_split (CFG_ENABLE_CMD_SPLIT ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width )
);
//==============================================================================
// alt_mem_ddrx_tbp
//------------------------------------------------------------------------------
//
// Timing bank pool block
//
// Info: * parallel queue in which a cmd is present
// * tracks timer and bank status information of the command it hold
// * monitor other TBPs content to update status bit in itself such
// as the autoprecharge bit
// * pass timer value to another TBP if need arises
//
//==============================================================================
alt_mem_ddrx_tbp #
(
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM ),
.CFG_ENABLE_SHADOW_TBP (CFG_ENABLE_SHADOW_TBP ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_PORT_WIDTH_STARVE_LIMIT (CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_REORDER_DATA (CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_DATA_REORDERING_TYPE (CFG_DATA_REORDERING_TYPE ),
.CFG_DISABLE_READ_REODERING (CFG_DISABLE_READ_REODERING ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH )
)
tbp_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_empty (tbp_empty ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.row_req (row_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.col_req (col_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_precharge (tbp_precharge ),
.tbp_activate (tbp_activate ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.sb_do_precharge_all (sb_do_precharge_all ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.tbp_bank_active (tbp_bank_active ),
.tbp_timer_ready (tbp_timer_ready ),
.cfg_reorder_data (cfg_reorder_data ),
.tbp_load (tbp_load ),
.data_complete (data_complete ),
.cfg_starve_limit (cfg_starve_limit ),
.cfg_type (cfg_type )
);
//==============================================================================
// alt_mem_ddrx_arbiter
//------------------------------------------------------------------------------
//
// Arbiter block
//
// Info: Priority command-aging arbiter, it will grant command with priority
// first, during tie-break situation, oldest command will be granted.
// Read comment in arbiter code for more information
//
//==============================================================================
alt_mem_ddrx_arbiter #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY )
)
arbiter_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.row_req (row_req ),
.col_req (col_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_activate (tbp_activate ),
.tbp_precharge (tbp_precharge ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_write (can_write ),
.can_read (can_read ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size )
);
//==============================================================================
// alt_mem_ddrx_burst_gen
//------------------------------------------------------------------------------
//
// Burst generation block
//
// Info: Create DQ/DQS burst information for AFI block
//
//==============================================================================
alt_mem_ddrx_burst_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT (CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE (CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_ENABLE_BURST_GEN_OUTPUT_REG (CFG_ENABLE_BURST_GEN_OUTPUT_REG )
)
burst_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_burst_length (cfg_burst_length ),
.cfg_tccd (cfg_tccd ),
.cfg_enable_burst_interrupt (cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate (cfg_enable_burst_terminate ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size ),
.bg_do_write_combi (bg_do_write_combi ),
.bg_do_read_combi (bg_do_read_combi ),
.bg_do_burst_chop_combi (bg_do_burst_chop_combi ),
.bg_do_burst_terminate_combi (bg_do_burst_terminate_combi ),
.bg_do_activate_combi (bg_do_activate_combi ),
.bg_do_precharge_combi (bg_do_precharge_combi ),
.bg_to_chip_combi (bg_to_chip_combi ),
.bg_effective_size_combi (bg_effective_size_combi ),
.bg_interrupt_ready_combi (bg_interrupt_ready_combi ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr (bg_do_lmr ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_doing_write (bg_doing_write ),
.bg_doing_read (bg_doing_read ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.bg_interrupt_ready (bg_interrupt_ready ),
.bg_localid (bg_localid ),
.bg_dataid (bg_dataid ),
.bg_size (bg_size ),
.bg_effective_size (bg_effective_size )
);
//==============================================================================
// alt_mem_ddrx_addr_cmd_wrap
//------------------------------------------------------------------------------
//
// Address and command decoder block
//
// Info: Trasalate controller internal command into AFI command
//
//==============================================================================
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_to_chip = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0] | bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP ];
// wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] temp_to_bank = bg_to_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0] | bg_to_bank [2 * CFG_MEM_IF_BA_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH ];
// wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] temp_to_row = bg_to_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0] | bg_to_row [2 * CFG_MEM_IF_ROW_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH];
// wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] temp_to_col = bg_to_col [CFG_MEM_IF_COL_WIDTH - 1 : 0] | bg_to_col [2 * CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
//
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_refresh = bg_do_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_power_down = bg_do_power_down [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_power_down [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_self_refresh = bg_do_self_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_self_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_precharge_all = bg_do_precharge_all [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_precharge_all [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_deep_pdown = bg_do_deep_pdown [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_deep_pdown [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_zq_cal = bg_do_zq_cal [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_zq_cal [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
alt_mem_ddrx_addr_cmd_wrap #
(
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_AFI_IF_FR_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_LPDDR2_ENABLED (CFG_LPDDR2_ENABLED ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
addr_cmd_wrap_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_lmr (bg_do_lmr ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr_read (bg_do_lmr_read ),
.bg_do_refresh_1bank (bg_do_refresh_1bank ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_to_lmr (bg_to_lmr ),
.bg_dataid (bg_dataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.lmr_opcode (lmr_opcode ),
.afi_cke (afi_cke ),
.afi_cs_n (afi_cs_n ),
.afi_ras_n (afi_ras_n ),
.afi_cas_n (afi_cas_n ),
.afi_we_n (afi_we_n ),
.afi_ba (afi_ba ),
.afi_addr (afi_addr ),
.afi_rst_n (afi_rst_n ),
.afi_odt (afi_odt )
);
//==============================================================================
// alt_mem_ddrx_odt_gen
//------------------------------------------------------------------------------
//
// ODT generation block
//
// Info: Generate ODT information based on user configuration
//
//==============================================================================
// alt_mem_ddrx_odt_gen #
// (
// .CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
// .CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
// .CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
// .CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
// .CFG_OUTPUT_REGD (CFG_OUTPUT_REGD ),
// .CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
// .CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
// .CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
// .CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE )
// )
// odt_gen_inst
// (
// .ctl_clk (ctl_clk ),
// .ctl_reset_n (ctl_reset_n ),
// .cfg_type (cfg_type ),
// .cfg_tcl (cfg_tcl ),
// .cfg_cas_wr_lat (cfg_cas_wr_lat ),
// .cfg_add_lat (cfg_add_lat ),
// .cfg_write_odt_chip (cfg_write_odt_chip ),
// .cfg_read_odt_chip (cfg_read_odt_chip ),
// .cfg_burst_length (cfg_burst_length ),
// .bg_do_read (bg_do_read ),
// .bg_do_write (bg_do_write ),
// .bg_to_chip (bg_to_chip ),
// .afi_odt (afi_odt )
// );
//==============================================================================
// alt_mem_ddrx_rdwr_data_tmg
//------------------------------------------------------------------------------
//
// Read / write data timing block
//
// Info: Adjust read and write data timing based on AFI information
//
//==============================================================================
alt_mem_ddrx_rdwr_data_tmg #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DM_WIDTH (CFG_MEM_IF_DM_WIDTH ),
.CFG_WLAT_BUS_WIDTH (CFG_WLAT_BUS_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
rdwr_data_tmg_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_output_regd (cfg_output_regd ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_doing_read (bg_doing_read ),
.bg_doing_write (bg_doing_write ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.dataid (bg_dataid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_wdata (ecc_wdata ),
.ecc_dm (ecc_dm ),
.afi_wlat (afi_wlat ),
.afi_doing_read (afi_rdata_en ),
.afi_doing_read_full (afi_rdata_en_full ),
.ecc_wdata_fifo_read (ecc_wdata_fifo_read ),
.ecc_wdata_fifo_dataid (ecc_wdata_fifo_dataid ),
.ecc_wdata_fifo_dataid_vector (ecc_wdata_fifo_dataid_vector ),
.ecc_wdata_fifo_rmw_correct (ecc_wdata_fifo_rmw_correct ),
.ecc_wdata_fifo_rmw_partial (ecc_wdata_fifo_rmw_partial ),
.ecc_wdata_fifo_read_first (ecc_wdata_fifo_read_first ),
.ecc_wdata_fifo_dataid_first (ecc_wdata_fifo_dataid_first ),
.ecc_wdata_fifo_dataid_vector_first (ecc_wdata_fifo_dataid_vector_first ),
.ecc_wdata_fifo_rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.ecc_wdata_fifo_rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.ecc_wdata_fifo_first_vector (ecc_wdata_fifo_first_vector ),
.ecc_wdata_fifo_read_last (ecc_wdata_fifo_read_last ),
.ecc_wdata_fifo_dataid_last (ecc_wdata_fifo_dataid_last ),
.ecc_wdata_fifo_dataid_vector_last (ecc_wdata_fifo_dataid_vector_last ),
.ecc_wdata_fifo_rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.ecc_wdata_fifo_rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.afi_dqs_burst (afi_dqs_burst ),
.afi_wdata_valid (afi_wdata_valid ),
.afi_wdata (afi_wdata ),
.afi_dm (afi_dm )
);
//==============================================================================
// alt_mem_ddrx_wdata_path
//------------------------------------------------------------------------------
//
// Write data path block
//
// Info: Handles write data processing
//
//==============================================================================
// match datapath id width, with command path id width
generate
begin : gen_resolve_datap_id
genvar i;
for (i = 0;i < CFG_DRAM_WLAT_GROUP;i = i + 1)
begin : write_dataid_per_dqs_group
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ];
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH];
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ]};
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = {{CFG_DATA_ID_REMAINDER {1'b0}},ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH]};
end
end
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_WRDATA_ID_WIDTH){1'b0}},wdatap_free_id_wrdataid};
assign ecc_wdata_wrdataid_first = ecc_wdata_fifo_dataid_first;
assign ecc_wdata_wrdataid_vector_first = ecc_wdata_fifo_dataid_vector_first;
assign ecc_wdata_wrdataid_last = ecc_wdata_fifo_dataid_last;
assign ecc_wdata_wrdataid_vector_last = ecc_wdata_fifo_dataid_vector_last;
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = wdatap_free_id_wrdataid[CFG_DATA_ID_WIDTH-1:0];
assign ecc_wdata_wrdataid_first = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_first};
assign ecc_wdata_wrdataid_vector_first = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_first};
assign ecc_wdata_wrdataid_last = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_last};
assign ecc_wdata_wrdataid_vector_last = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_last};
end
if (CFG_RDDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_RDDATA_ID_WIDTH){1'b0}},rdatap_free_id_rddataid};
assign bg_rddataid = bg_dataid[CFG_RDDATA_ID_WIDTH-1:0];
end
else // (CFG_RDDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
assign bg_rddataid = {{(CFG_RDDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},bg_dataid};
end
end
endgenerate
alt_mem_ddrx_wdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_WRDATA_ID_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP ),
.CFG_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_BUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_PARTIAL_BE_PER_WORD_ENABLE (CFG_PARTIAL_BE_PER_WORD_ENABLE ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES (CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH )
)
wdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites (cfg_enable_ecc_code_overwrites ),
.cfg_interface_width (cfg_interface_width ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_wrdataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.tbp_load_index (tbp_load_index ),
.proc_size (proc_size ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_en (write_data_valid ),
.write_data (write_data ),
.byte_en (byte_en ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.data_partial_be (data_partial_be ),
.doing_write (ecc_wdata_fifo_read ),
.dataid (ecc_wdata_wrdataid ),
.dataid_vector (ecc_wdata_wrdataid_vector ),
.rdwr_data_valid (ecc_wdata_fifo_read ),
.rmw_correct (ecc_wdata_fifo_rmw_correct ),
.rmw_partial (ecc_wdata_fifo_rmw_partial ),
.doing_write_first (ecc_wdata_fifo_read_first ),
.dataid_first (ecc_wdata_wrdataid_first ),
.dataid_vector_first (ecc_wdata_wrdataid_vector_first ),
.rdwr_data_valid_first (ecc_wdata_fifo_read_first ),
.rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.doing_write_first_vector (ecc_wdata_fifo_first_vector ),
.rdwr_data_valid_first_vector (ecc_wdata_fifo_first_vector ),
.doing_write_last (ecc_wdata_fifo_read_last ),
.dataid_last (ecc_wdata_wrdataid_last ),
.dataid_vector_last (ecc_wdata_wrdataid_vector_last ),
.rdwr_data_valid_last (ecc_wdata_fifo_read_last ),
.rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_dm (wdatap_dm ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_rdata_path
//------------------------------------------------------------------------------
//
// Read data path block
//
// Info: Handles read data processing
//
//==============================================================================
alt_mem_ddrx_rdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_RDDATA_ID_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_BUFFER_ADDR_WIDTH (CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MAX_READ_CMD_NUM_WIDTH (CFG_MAX_PENDING_RD_CMD_WIDTH ),
.CFG_RDATA_RETURN_MODE (CFG_RDATA_RETURN_MODE ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_ERRCMD_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH )
)
rdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_rddataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.read_data_valid (read_data_valid ),
.read_data (read_data ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.bg_do_read (bg_do_read ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_column (bg_to_col ),
.bg_dataid (bg_rddataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_rdata (ecc_rdata ),
.ecc_rdatav (ecc_rdata_valid ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
//------------------------------------------------------------------------------
//
// ECC encoder/decoder block
//
// Info: Encode write data and decode read data, correct single bit error
// and detect double bit errors
//
//==============================================================================
alt_mem_ddrx_ecc_encoder_decoder_wrapper #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR),
.CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR ),
.STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR ),
.STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR ),
.STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT ),
.STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT ),
.STS_PORT_WIDTH_CORR_DROP_ERROR (STS_PORT_WIDTH_CORR_DROP_ERROR ),
.STS_PORT_WIDTH_CORR_DROP_COUNT (STS_PORT_WIDTH_CORR_DROP_COUNT )
)
ecc_encoder_decoder_wrapper_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_interface_width (cfg_interface_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_gen_sbe (cfg_gen_sbe ),
.cfg_gen_dbe (cfg_gen_dbe ),
.cfg_enable_intr (cfg_enable_intr ),
.cfg_mask_sbe_intr (cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr (cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr (cfg_mask_corr_dropped_intr ),
.cfg_clr_intr (cfg_clr_intr ),
.wdatap_dm (wdatap_dm ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.afi_rdata (afi_rdata ),
.afi_rdata_valid (afi_rdata_valid ),
.ecc_rdata (ecc_rdata ),
.ecc_rdata_valid (ecc_rdata_valid ),
.ecc_dm (ecc_dm ),
.ecc_wdata (ecc_wdata ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.ecc_interrupt (ecc_interrupt ),
.sts_sbe_error (sts_sbe_error ),
.sts_dbe_error (sts_dbe_error ),
.sts_sbe_count (sts_sbe_count ),
.sts_dbe_count (sts_dbe_count ),
.sts_err_addr (sts_err_addr ),
.sts_corr_dropped (sts_corr_dropped ),
.sts_corr_dropped_count (sts_corr_dropped_count ),
.sts_corr_dropped_addr (sts_corr_dropped_addr )
);
//==============================================================================
// alt_mem_ddrx_sideband
//------------------------------------------------------------------------------
//
// Sideband block
//
// Info: Monitor and issue sideband specific commands such as user/auto
// refresh, self refresh, power down, deep power down,
// precharge all and zq calibration commands
//
//==============================================================================
alt_mem_ddrx_sideband #
(
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_MEM_IF_CLK_PAIR_COUNT (CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH )
)
sideband_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.self_rfsh_ack (self_rfsh_ack ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.stall_chip (stall_chip ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.ctl_mem_clk_disable (ctl_mem_clk_disable ),
.ctl_init_req (ctl_init_req ),
.ctl_cal_success (ctl_cal_success ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit ),
.tbp_empty (tbp_empty ),
.tbp_bank_active (tbp_bank_active ),
.tbp_timer_ready (tbp_timer_ready ),
.row_grant (or_row_grant ),
.col_grant (or_col_grant ),
.afi_ctl_refresh_done (afi_ctl_refresh_done ),
.afi_seq_busy (afi_seq_busy ),
.afi_ctl_long_idle (afi_ctl_long_idle ),
.cfg_enable_dqs_tracking (cfg_enable_dqs_tracking ),
.cfg_user_rfsh (cfg_user_rfsh ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_regdimm_enable (cfg_regdimm_enable )
);
//==============================================================================
// alt_mem_ddrx_rank_timer
//------------------------------------------------------------------------------
//
// Rank timer block
//
// Info: Monitor rank specific timing parameter for activate, precharge,
// read and write commands
//
//==============================================================================
alt_mem_ddrx_rank_timer #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH )
)
rank_timer_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.bg_do_write (bg_do_write_combi ),
.bg_do_read (bg_do_read_combi ),
.bg_do_burst_chop (bg_do_burst_chop_combi ),
.bg_do_burst_terminate (bg_do_burst_terminate_combi ),
.bg_do_activate (bg_do_activate_combi ),
.bg_do_precharge (bg_do_precharge_combi ),
.bg_to_chip (bg_to_chip_combi ),
.bg_effective_size (bg_effective_size_combi ),
.bg_interrupt_ready (bg_interrupt_ready_combi ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.stall_chip (stall_chip ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_read (can_read ),
.can_write (can_write )
);
//==============================================================================
// alt_mem_ddrx_timing_param
//------------------------------------------------------------------------------
//
// Timing parameter block
//
// Info: Pre-calculate required timing parameters for each memory commands
// based on memory type
//
//==============================================================================
alt_mem_ddrx_timing_param #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD (CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW (CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC (CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI (CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD (CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP (CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR (CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR (CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP (CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS (CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC (CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD (CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES (CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES (CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES (CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES (CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH )
)
timing_param_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_type (cfg_type ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_tcl (cfg_tcl ),
.cfg_trrd (cfg_trrd ),
.cfg_tfaw (cfg_tfaw ),
.cfg_trfc (cfg_trfc ),
.cfg_trefi (cfg_trefi ),
.cfg_trcd (cfg_trcd ),
.cfg_trp (cfg_trp ),
.cfg_twr (cfg_twr ),
.cfg_twtr (cfg_twtr ),
.cfg_trtp (cfg_trtp ),
.cfg_tras (cfg_tras ),
.cfg_trc (cfg_trc ),
.cfg_tccd (cfg_tccd ),
.cfg_tmrd (cfg_tmrd ),
.cfg_self_rfsh_exit_cycles (cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles (cfg_pdn_exit_cycles ),
.cfg_auto_pd_cycles (cfg_auto_pd_cycles ),
.cfg_power_saving_exit_cycles (cfg_power_saving_exit_cycles ),
.cfg_extra_ctl_clk_act_to_rdwr (cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch (cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act (cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd (cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip (cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr (cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc (cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip (cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch (cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid (cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr (cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip (cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd (cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc (cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip (cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch (cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid (cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid (cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid (cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank (cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act (cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid (cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid (cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid (cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal (cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period (cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period (cfg_extra_ctl_clk_pdn_period ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit )
);
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//////////////////////////////////////////////////////////////////////////////
// This module is a ST wrapper for the soft IP NextGen controller and the MMR
//////////////////////////////////////////////////////////////////////////////
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
module alt_mem_ddrx_controller_st_top(
clk,
half_clk,
reset_n,
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_init_req,
afi_mem_clk_disable,
afi_cal_byte_lane_sel_n,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_init_done,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_deep_powerdn_ack,
local_refresh_req,
local_refresh_chip,
local_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_multicast,
local_priority,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_burst_count,
csr_beginbursttransfer,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest
);
//////////////////////////////////////////////////////////////////////////////
parameter LOCAL_SIZE_WIDTH = "";
parameter LOCAL_ADDR_WIDTH = "";
parameter LOCAL_DATA_WIDTH = "";
parameter LOCAL_BE_WIDTH = "";
parameter LOCAL_ID_WIDTH = "";
parameter LOCAL_CS_WIDTH = "";
parameter MEM_IF_ADDR_WIDTH = "";
parameter MEM_IF_CLK_PAIR_COUNT = "";
parameter LOCAL_IF_TYPE = "";
parameter DWIDTH_RATIO = "";
parameter CTL_ODT_ENABLED = "";
parameter CTL_OUTPUT_REGD = "";
parameter CTL_TBP_NUM = "";
parameter WRBUFFER_ADDR_WIDTH = "";
parameter RDBUFFER_ADDR_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_IF_CHIP = "";
parameter MEM_IF_BANKADDR_WIDTH = "";
parameter MEM_IF_ROW_WIDTH = "";
parameter MEM_IF_COL_WIDTH = "";
parameter MEM_IF_ODT_WIDTH = "";
parameter MEM_IF_DQS_WIDTH = "";
parameter MEM_IF_DWIDTH = "";
parameter MEM_IF_DM_WIDTH = "";
parameter MAX_MEM_IF_CS_WIDTH = "";
parameter MAX_MEM_IF_CHIP = "";
parameter MAX_MEM_IF_BANKADDR_WIDTH = "";
parameter MAX_MEM_IF_ROWADDR_WIDTH = "";
parameter MAX_MEM_IF_COLADDR_WIDTH = "";
parameter MAX_MEM_IF_ODT_WIDTH = "";
parameter MAX_MEM_IF_DQS_WIDTH = "";
parameter MAX_MEM_IF_DQ_WIDTH = "";
parameter MAX_MEM_IF_MASK_WIDTH = "";
parameter MAX_LOCAL_DATA_WIDTH = "";
parameter CFG_TYPE = "";
parameter CFG_INTERFACE_WIDTH = "";
parameter CFG_BURST_LENGTH = "";
parameter CFG_DEVICE_WIDTH = "";
parameter CFG_REORDER_DATA = "";
parameter CFG_DATA_REORDERING_TYPE = "";
parameter CFG_STARVE_LIMIT = "";
parameter CFG_ADDR_ORDER = "";
parameter MEM_CAS_WR_LAT = "";
parameter MEM_ADD_LAT = "";
parameter MEM_TCL = "";
parameter MEM_TRRD = "";
parameter MEM_TFAW = "";
parameter MEM_TRFC = "";
parameter MEM_TREFI = "";
parameter MEM_TRCD = "";
parameter MEM_TRP = "";
parameter MEM_TWR = "";
parameter MEM_TWTR = "";
parameter MEM_TRTP = "";
parameter MEM_TRAS = "";
parameter MEM_TRC = "";
parameter CFG_TCCD = "";
parameter MEM_AUTO_PD_CYCLES = "";
parameter CFG_SELF_RFSH_EXIT_CYCLES = "";
parameter CFG_PDN_EXIT_CYCLES = "";
parameter CFG_POWER_SAVING_EXIT_CYCLES = "";
parameter CFG_MEM_CLK_ENTRY_CYCLES = "";
parameter MEM_TMRD_CK = "";
parameter CTL_ECC_ENABLED = "";
parameter CTL_ECC_RMW_ENABLED = "";
parameter CTL_ECC_MULTIPLES_16_24_40_72 = "";
parameter CFG_GEN_SBE = "";
parameter CFG_GEN_DBE = "";
parameter CFG_ENABLE_INTR = "";
parameter CFG_MASK_SBE_INTR = "";
parameter CFG_MASK_DBE_INTR = "";
parameter CFG_MASK_CORRDROP_INTR = 0;
parameter CFG_CLR_INTR = "";
parameter CTL_USR_REFRESH = "";
parameter CTL_REGDIMM_ENABLED = "";
parameter CTL_ENABLE_BURST_INTERRUPT = "";
parameter CTL_ENABLE_BURST_TERMINATE = "";
parameter CFG_WRITE_ODT_CHIP = "";
parameter CFG_READ_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_WRITE_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_READ_ODT_CHIP = "";
parameter MEM_IF_CKE_WIDTH = "";//check
parameter CTL_CSR_ENABLED = "";
parameter CFG_ENABLE_NO_DM = "";
parameter CSR_ADDR_WIDTH = "";
parameter CSR_DATA_WIDTH = "";
parameter CSR_BE_WIDTH = "";
parameter CFG_ENABLE_DQS_TRACKING = 0;
parameter CFG_WLAT_BUS_WIDTH = 6;
parameter CFG_RLAT_BUS_WIDTH = 6;
parameter MEM_IF_RD_TO_WR_TURNAROUND_OCT = "";
parameter MEM_IF_WR_TO_RD_TURNAROUND_OCT = "";
parameter CTL_RD_TO_PCH_EXTRA_CLK = 0;
//////////////////////////////////////////////////////////////////////////////
localparam CFG_LOCAL_SIZE_WIDTH = LOCAL_SIZE_WIDTH;
localparam CFG_LOCAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH;
localparam CFG_LOCAL_DATA_WIDTH = LOCAL_DATA_WIDTH;
localparam CFG_LOCAL_BE_WIDTH = LOCAL_BE_WIDTH;
localparam CFG_LOCAL_ID_WIDTH = LOCAL_ID_WIDTH;
localparam CFG_LOCAL_IF_TYPE = LOCAL_IF_TYPE;
localparam CFG_MEM_IF_ADDR_WIDTH = MEM_IF_ADDR_WIDTH;
localparam CFG_MEM_IF_CLK_PAIR_COUNT = MEM_IF_CLK_PAIR_COUNT;
localparam CFG_DWIDTH_RATIO = DWIDTH_RATIO;
localparam CFG_ODT_ENABLED = CTL_ODT_ENABLED;
localparam CFG_CTL_TBP_NUM = CTL_TBP_NUM;
localparam CFG_WRBUFFER_ADDR_WIDTH = WRBUFFER_ADDR_WIDTH;
localparam CFG_RDBUFFER_ADDR_WIDTH = RDBUFFER_ADDR_WIDTH;
localparam CFG_MEM_IF_CS_WIDTH = MEM_IF_CS_WIDTH;
localparam CFG_MEM_IF_CHIP = MEM_IF_CHIP;
localparam CFG_MEM_IF_BA_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_MEM_IF_ROW_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_MEM_IF_COL_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_MEM_IF_CKE_WIDTH = MEM_IF_CKE_WIDTH;
localparam CFG_MEM_IF_ODT_WIDTH = MEM_IF_ODT_WIDTH;
localparam CFG_MEM_IF_DQS_WIDTH = MEM_IF_DQS_WIDTH;
localparam CFG_MEM_IF_DQ_WIDTH = MEM_IF_DWIDTH;
localparam CFG_MEM_IF_DM_WIDTH = MEM_IF_DM_WIDTH;
localparam CFG_COL_ADDR_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_ROW_ADDR_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_BANK_ADDR_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_CS_ADDR_WIDTH = LOCAL_CS_WIDTH;
localparam CFG_CAS_WR_LAT = MEM_CAS_WR_LAT;
localparam CFG_ADD_LAT = MEM_ADD_LAT;
localparam CFG_TCL = MEM_TCL;
localparam CFG_TRRD = MEM_TRRD;
localparam CFG_TFAW = MEM_TFAW;
localparam CFG_TRFC = MEM_TRFC;
localparam CFG_TREFI = MEM_TREFI;
localparam CFG_TRCD = MEM_TRCD;
localparam CFG_TRP = MEM_TRP;
localparam CFG_TWR = MEM_TWR;
localparam CFG_TWTR = MEM_TWTR;
localparam CFG_TRTP = MEM_TRTP;
localparam CFG_TRAS = MEM_TRAS;
localparam CFG_TRC = MEM_TRC;
localparam CFG_AUTO_PD_CYCLES = MEM_AUTO_PD_CYCLES;
localparam CFG_TMRD = MEM_TMRD_CK;
localparam CFG_ENABLE_ECC = CTL_ECC_ENABLED;
localparam CFG_ENABLE_AUTO_CORR = CTL_ECC_RMW_ENABLED;
localparam CFG_ECC_MULTIPLES_16_24_40_72 = CTL_ECC_MULTIPLES_16_24_40_72;
localparam CFG_ENABLE_ECC_CODE_OVERWRITES = 1'b1;
localparam CFG_CAL_REQ = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH = 0 + CTL_RD_TO_PCH_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0;
localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD = 0;
localparam CFG_OUTPUT_REGD = CTL_OUTPUT_REGD;
localparam CFG_MASK_CORR_DROPPED_INTR = 0;
localparam CFG_USER_RFSH = CTL_USR_REFRESH;
localparam CFG_REGDIMM_ENABLE = CTL_REGDIMM_ENABLED;
localparam CFG_ENABLE_BURST_INTERRUPT = CTL_ENABLE_BURST_INTERRUPT;
localparam CFG_ENABLE_BURST_TERMINATE = CTL_ENABLE_BURST_TERMINATE;
localparam CFG_PORT_WIDTH_TYPE = 3;
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
localparam CFG_PORT_WIDTH_BURST_LENGTH = 5;
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 4;
localparam CFG_PORT_WIDTH_REORDER_DATA = 1;
localparam CFG_PORT_WIDTH_STARVE_LIMIT = 6;
localparam CFG_PORT_WIDTH_OUTPUT_REGD = 1;
localparam CFG_PORT_WIDTH_ADDR_ORDER = 2;
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 4;
localparam CFG_PORT_WIDTH_ADD_LAT = 3;
localparam CFG_PORT_WIDTH_TCL = 4;
localparam CFG_PORT_WIDTH_TRRD = 4;
localparam CFG_PORT_WIDTH_TFAW = 6;
localparam CFG_PORT_WIDTH_TRFC = 8;
localparam CFG_PORT_WIDTH_TREFI = 13;
localparam CFG_PORT_WIDTH_TRCD = 4;
localparam CFG_PORT_WIDTH_TRP = 4;
localparam CFG_PORT_WIDTH_TWR = 4;
localparam CFG_PORT_WIDTH_TWTR = 4;
localparam CFG_PORT_WIDTH_TRTP = 4;
localparam CFG_PORT_WIDTH_TRAS = 5;
localparam CFG_PORT_WIDTH_TRC = 6;
localparam CFG_PORT_WIDTH_TCCD = 4;
localparam CFG_PORT_WIDTH_TMRD = 3;
localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10;
localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4;
localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4;
localparam CFG_PORT_WIDTH_ENABLE_ECC = 1;
localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1;
localparam CFG_PORT_WIDTH_GEN_SBE = 1;
localparam CFG_PORT_WIDTH_GEN_DBE = 1;
localparam CFG_PORT_WIDTH_ENABLE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1;
localparam CFG_PORT_WIDTH_CLR_INTR = 1;
localparam CFG_PORT_WIDTH_USER_RFSH = 1;
localparam CFG_PORT_WIDTH_SELF_RFSH = 1;
localparam CFG_PORT_WIDTH_REGDIMM_ENABLE = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1;
localparam CFG_RDATA_RETURN_MODE = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
localparam CFG_LPDDR2_ENABLED = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
localparam STS_PORT_WIDTH_SBE_ERROR = 1;
localparam STS_PORT_WIDTH_DBE_ERROR = 1;
localparam STS_PORT_WIDTH_CORR_DROP_ERROR = 1;
localparam STS_PORT_WIDTH_SBE_COUNT = 8;
localparam STS_PORT_WIDTH_DBE_COUNT = 8;
localparam STS_PORT_WIDTH_CORR_DROP_COUNT = 8;
// We are supposed to use these parameters when the CSR is enabled
// but the MAX_ parameters are not defined
//localparam AFI_CS_WIDTH = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CKE_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ODT_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ADDR_WIDTH = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_BA_WIDTH = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
localparam AFI_CS_WIDTH = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CKE_WIDTH = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ODT_WIDTH = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ADDR_WIDTH = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_BA_WIDTH = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
localparam AFI_CMD_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_DQS_BURST_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_VALID_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_DM_WIDTH = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_WLAT_WIDTH = CFG_WLAT_BUS_WIDTH;
localparam AFI_RDATA_EN_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_RDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_RDATA_VALID_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_RLAT_WIDTH = CFG_RLAT_BUS_WIDTH;
localparam AFI_OTF_BITNUM = 12;
localparam AFI_AUTO_PRECHARGE_BITNUM = 10;
localparam AFI_MEM_CLK_DISABLE_WIDTH = CFG_MEM_IF_CLK_PAIR_COUNT;
//////////////////////////////////////////////////////////////////////////////
// BEGIN PORT SECTION
// Clk and reset signals
input clk;
input half_clk;
input reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
// AFI signals
output [AFI_CMD_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CKE_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BA_WIDTH - 1 : 0] afi_ba;
output [AFI_CMD_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_we_n;
output [AFI_DQS_BURST_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WDATA_VALID_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_WDATA_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en_full;
input [AFI_RDATA_WIDTH - 1 : 0] afi_rdata;
input [AFI_RDATA_VALID_WIDTH - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output afi_init_req;
output [AFI_MEM_CLK_DISABLE_WIDTH - 1 : 0] afi_mem_clk_disable;
output [AFI_CAL_BYTE_LANE_SEL_N_WIDTH - 1 : 0] afi_cal_byte_lane_sel_n;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// Sideband signals
output local_init_done;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
output local_deep_powerdn_ack;
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_powerdn_req;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_deep_powerdn_chip;
input local_multicast;
input local_priority;
// Csr & ecc signals
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [1 - 1 : 0] csr_burst_count;
input csr_beginbursttransfer;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
// END PORT SECTION
//////////////////////////////////////////////////////////////////////////////
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_reorder_data;
wire cfg_user_rfsh;
wire cfg_regdimm_enable;
wire cfg_enable_burst_interrupt;
wire cfg_enable_burst_terminate;
wire cfg_enable_dqs_tracking;
wire cfg_output_regd;
wire cfg_enable_no_dm;
wire cfg_enable_ecc_code_overwrites;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
wire [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
wire [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
wire [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
wire [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_clr_intr;
wire cfg_cal_req;
wire [4 - 1 : 0] cfg_clock_off;
wire cfg_self_rfsh;
wire cfg_ganged_arf;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
wire [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
wire [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
wire [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
wire cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] cfg_mem_bl;
wire cfg_user_ecc_en;
//ECC related outputs from controller to csr
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//
// Reconfiguration Support
//
// cfg_* signals may be reconfigured to different values using the Configuration Status Registers
// - some cfg_* signals are not reconfigurable, and are always assigned to parameters
// - When CSR is not enabled
// - cfg_* signals are assigned to parameters
// - when CSR is enabled
// - cfg_* signals are assigned to csr_* signals
// - csr_* signal generation based on Configuration Registers
// - default value for csr_* signals are based on parameters
// cfg_* signals that are not reconfigurable
assign cfg_type = CFG_TYPE;
assign cfg_interface_width = CFG_INTERFACE_WIDTH;
assign cfg_device_width = CFG_DEVICE_WIDTH;
assign cfg_enable_ecc_code_overwrites = CFG_ENABLE_ECC_CODE_OVERWRITES;
assign cfg_enable_no_dm = CFG_ENABLE_NO_DM;
assign cfg_output_regd = CFG_OUTPUT_REGD;
assign cfg_pdn_exit_cycles = CFG_PDN_EXIT_CYCLES;
assign cfg_power_saving_exit_cycles = CFG_POWER_SAVING_EXIT_CYCLES;
assign cfg_mem_clk_entry_cycles = CFG_MEM_CLK_ENTRY_CYCLES;
assign cfg_self_rfsh_exit_cycles = CFG_SELF_RFSH_EXIT_CYCLES;
assign cfg_tccd = CFG_TCCD;
assign cfg_tmrd = CFG_TMRD;
assign cfg_user_rfsh = CFG_USER_RFSH;
assign cfg_write_odt_chip = CFG_WRITE_ODT_CHIP;
assign cfg_read_odt_chip = CFG_READ_ODT_CHIP;
assign cfg_enable_dqs_tracking = CFG_ENABLE_DQS_TRACKING;
assign cfg_enable_burst_interrupt = CFG_ENABLE_BURST_INTERRUPT;
assign cfg_enable_burst_terminate = CFG_ENABLE_BURST_TERMINATE;
assign cfg_extra_ctl_clk_act_to_rdwr = CFG_EXTRA_CTL_CLK_ACT_TO_RDWR;
assign cfg_extra_ctl_clk_act_to_pch = CFG_EXTRA_CTL_CLK_ACT_TO_PCH;
assign cfg_extra_ctl_clk_act_to_act = CFG_EXTRA_CTL_CLK_ACT_TO_ACT;
assign cfg_extra_ctl_clk_rd_to_rd = CFG_EXTRA_CTL_CLK_RD_TO_RD;
assign cfg_extra_ctl_clk_rd_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_wr = CFG_EXTRA_CTL_CLK_RD_TO_WR;
assign cfg_extra_ctl_clk_rd_to_wr_bc = CFG_EXTRA_CTL_CLK_RD_TO_WR_BC;
assign cfg_extra_ctl_clk_rd_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_pch = CFG_EXTRA_CTL_CLK_RD_TO_PCH;
assign cfg_extra_ctl_clk_rd_ap_to_valid = CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID;
assign cfg_extra_ctl_clk_wr_to_wr = CFG_EXTRA_CTL_CLK_WR_TO_WR;
assign cfg_extra_ctl_clk_wr_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_rd = CFG_EXTRA_CTL_CLK_WR_TO_RD;
assign cfg_extra_ctl_clk_wr_to_rd_bc = CFG_EXTRA_CTL_CLK_WR_TO_RD_BC;
assign cfg_extra_ctl_clk_wr_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_pch = CFG_EXTRA_CTL_CLK_WR_TO_PCH;
assign cfg_extra_ctl_clk_wr_ap_to_valid = CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID;
assign cfg_extra_ctl_clk_pch_to_valid = CFG_EXTRA_CTL_CLK_PCH_TO_VALID;
assign cfg_extra_ctl_clk_pch_all_to_valid = CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID;
assign cfg_extra_ctl_clk_act_to_act_diff_bank = CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK;
assign cfg_extra_ctl_clk_four_act_to_act = CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT;
assign cfg_extra_ctl_clk_arf_to_valid = CFG_EXTRA_CTL_CLK_ARF_TO_VALID;
assign cfg_extra_ctl_clk_pdn_to_valid = CFG_EXTRA_CTL_CLK_PDN_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_valid = CFG_EXTRA_CTL_CLK_SRF_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_zq_cal = CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL;
assign cfg_extra_ctl_clk_arf_period = CFG_EXTRA_CTL_CLK_ARF_PERIOD;
assign cfg_extra_ctl_clk_pdn_period = CFG_EXTRA_CTL_CLK_PDN_PERIOD;
// cfg_* signals that are reconfigurable
generate
if (CTL_CSR_ENABLED == 1) begin
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] csr_cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] csr_cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] csr_cfg_addr_order;
wire csr_cfg_enable_ecc;
wire csr_cfg_enable_auto_corr;
wire csr_cfg_gen_sbe;
wire csr_cfg_gen_dbe;
wire csr_cfg_reorder_data;
wire csr_cfg_regdimm_enable;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] csr_cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] csr_cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] csr_cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] csr_cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] csr_cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] csr_cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] csr_cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] csr_cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] csr_cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] csr_cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] csr_cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] csr_cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] csr_cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] csr_cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] csr_cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] csr_cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] csr_cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] csr_cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] csr_cfg_cs_addr_width;
wire csr_cfg_enable_intr;
wire csr_cfg_mask_sbe_intr;
wire csr_cfg_mask_dbe_intr;
wire csr_cfg_clr_intr;
wire csr_cfg_cal_req;
wire [4 - 1 : 0] csr_cfg_clock_off;
wire csr_cfg_self_rfsh;
wire csr_cfg_ganged_arf;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] csr_cfg_starve_limit;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] csr_cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] csr_cfg_device_width;
wire csr_cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] csr_cfg_mem_bl;
wire csr_cfg_user_ecc_en;
assign cfg_burst_length = csr_cfg_burst_length;
assign cfg_reorder_data = csr_cfg_reorder_data;
assign cfg_starve_limit = csr_cfg_starve_limit;
assign cfg_addr_order = csr_cfg_addr_order;
assign cfg_col_addr_width = csr_cfg_col_addr_width;
assign cfg_row_addr_width = csr_cfg_row_addr_width;
assign cfg_bank_addr_width = csr_cfg_bank_addr_width;
assign cfg_cs_addr_width = csr_cfg_cs_addr_width;
assign cfg_cas_wr_lat = csr_cfg_cas_wr_lat;
assign cfg_add_lat = csr_cfg_add_lat;
assign cfg_tcl = csr_cfg_tcl;
assign cfg_trrd = csr_cfg_trrd;
assign cfg_tfaw = csr_cfg_tfaw;
assign cfg_trfc = csr_cfg_trfc;
assign cfg_trefi = csr_cfg_trefi;
assign cfg_trcd = csr_cfg_trcd;
assign cfg_trp = csr_cfg_trp;
assign cfg_twr = csr_cfg_twr;
assign cfg_twtr = csr_cfg_twtr;
assign cfg_trtp = csr_cfg_trtp;
assign cfg_tras = csr_cfg_tras;
assign cfg_trc = csr_cfg_trc;
assign cfg_enable_ecc = csr_cfg_enable_ecc;
assign cfg_enable_auto_corr = csr_cfg_enable_auto_corr;
assign cfg_gen_sbe = csr_cfg_gen_sbe;
assign cfg_gen_dbe = csr_cfg_gen_dbe;
assign cfg_enable_intr = csr_cfg_enable_intr;
assign cfg_mask_sbe_intr = csr_cfg_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_cfg_mask_dbe_intr;
assign cfg_mask_corr_dropped_intr = csr_cfg_mask_corr_dropped_intr;
assign cfg_clr_intr = csr_cfg_clr_intr;
assign cfg_regdimm_enable = csr_cfg_regdimm_enable;
assign cfg_cal_req = csr_cfg_cal_req;
assign cfg_auto_pd_cycles = csr_cfg_auto_pd_cycles;
alt_mem_ddrx_csr # (
.CFG_AVALON_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CFG_AVALON_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CFG_BURST_LENGTH ( CFG_BURST_LENGTH ),
.CFG_REORDER_DATA ( CFG_REORDER_DATA ),
.CFG_STARVE_LIMIT ( CFG_STARVE_LIMIT ),
.CFG_ADDR_ORDER ( CFG_ADDR_ORDER ),
.CFG_COL_ADDR_WIDTH ( CFG_COL_ADDR_WIDTH ),
.CFG_ROW_ADDR_WIDTH ( CFG_ROW_ADDR_WIDTH ),
.CFG_BANK_ADDR_WIDTH ( CFG_BANK_ADDR_WIDTH ),
.CFG_CS_ADDR_WIDTH ( CFG_CS_ADDR_WIDTH ),
.CFG_CAS_WR_LAT ( CFG_CAS_WR_LAT ),
.CFG_ADD_LAT ( CFG_ADD_LAT ),
.CFG_TCL ( CFG_TCL ),
.CFG_TRRD ( CFG_TRRD ),
.CFG_TFAW ( CFG_TFAW ),
.CFG_TRFC ( CFG_TRFC ),
.CFG_TREFI ( CFG_TREFI ),
.CFG_TRCD ( CFG_TRCD ),
.CFG_TRP ( CFG_TRP ),
.CFG_TWR ( CFG_TWR ),
.CFG_TWTR ( CFG_TWTR ),
.CFG_TRTP ( CFG_TRTP ),
.CFG_TRAS ( CFG_TRAS ),
.CFG_TRC ( CFG_TRC ),
.CFG_AUTO_PD_CYCLES ( CFG_AUTO_PD_CYCLES ),
.CFG_ENABLE_ECC ( CFG_ENABLE_ECC ),
.CFG_ENABLE_AUTO_CORR ( CFG_ENABLE_AUTO_CORR ),
.CFG_REGDIMM_ENABLE ( CFG_REGDIMM_ENABLE ),
.MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH )
) register_control_inst (
.avalon_mm_read ( csr_read_req ),
.avalon_mm_write ( csr_write_req ),
.avalon_mm_addr ( csr_addr ),
.avalon_mm_wdata ( csr_wdata ),
.avalon_mm_rdata ( csr_rdata ),
.avalon_mm_be ( csr_be ),
.avalon_mm_waitrequest ( csr_waitrequest ),
.avalon_mm_rdata_valid ( csr_rdata_valid ),
.cfg_burst_length ( csr_cfg_burst_length ),
.cfg_addr_order ( csr_cfg_addr_order ),
.cfg_enable_ecc ( csr_cfg_enable_ecc ),
.cfg_enable_auto_corr ( csr_cfg_enable_auto_corr ),
.cfg_gen_sbe ( csr_cfg_gen_sbe ),
.cfg_gen_dbe ( csr_cfg_gen_dbe ),
.cfg_reorder_data ( csr_cfg_reorder_data ),
.cfg_regdimm_enable ( csr_cfg_regdimm_enable ),
.cfg_cas_wr_lat ( csr_cfg_cas_wr_lat ),
.cfg_add_lat ( csr_cfg_add_lat ),
.cfg_tcl ( csr_cfg_tcl ),
.cfg_trrd ( csr_cfg_trrd ),
.cfg_tfaw ( csr_cfg_tfaw ),
.cfg_trfc ( csr_cfg_trfc ),
.cfg_trefi ( csr_cfg_trefi ),
.cfg_trcd ( csr_cfg_trcd ),
.cfg_trp ( csr_cfg_trp ),
.cfg_twr ( csr_cfg_twr ),
.cfg_twtr ( csr_cfg_twtr ),
.cfg_trtp ( csr_cfg_trtp ),
.cfg_tras ( csr_cfg_tras ),
.cfg_trc ( csr_cfg_trc ),
.cfg_auto_pd_cycles ( csr_cfg_auto_pd_cycles ),
.cfg_col_addr_width ( csr_cfg_col_addr_width ),
.cfg_row_addr_width ( csr_cfg_row_addr_width ),
.cfg_bank_addr_width ( csr_cfg_bank_addr_width ),
.cfg_cs_addr_width ( csr_cfg_cs_addr_width ),
.cfg_enable_intr ( csr_cfg_enable_intr ),
.cfg_mask_sbe_intr ( csr_cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( csr_cfg_mask_dbe_intr ),
.cfg_clr_intr ( csr_cfg_clr_intr ),
.cfg_clock_off ( csr_cfg_clock_off ),
.cfg_starve_limit ( csr_cfg_starve_limit ),
.cfg_mask_corr_dropped_intr ( csr_cfg_mask_corr_dropped_intr ),
.cfg_cal_req ( csr_cfg_cal_req ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.sts_cal_success ( afi_cal_success ),
.sts_cal_fail ( afi_cal_fail ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( sts_err_addr ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( sts_corr_dropped_addr ),
.ctl_clk ( clk ),
.ctl_rst_n ( reset_n )
);
end
else begin
assign csr_rdata = 0;
assign csr_rdata_valid = 0;
assign csr_waitrequest = 0;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_cs_addr_width = CFG_CS_ADDR_WIDTH;
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_enable_ecc = CFG_ENABLE_ECC;
assign cfg_enable_auto_corr = CFG_ENABLE_AUTO_CORR;
assign cfg_gen_sbe = CFG_GEN_SBE;
assign cfg_gen_dbe = CFG_GEN_DBE;
assign cfg_enable_intr = CFG_ENABLE_INTR;
assign cfg_mask_sbe_intr = CFG_MASK_SBE_INTR;
assign cfg_mask_dbe_intr = CFG_MASK_DBE_INTR;
assign cfg_mask_corr_dropped_intr = CFG_MASK_CORR_DROPPED_INTR;
assign cfg_clr_intr = CFG_CLR_INTR;
assign cfg_regdimm_enable = CFG_REGDIMM_ENABLE;
assign cfg_cal_req = CFG_CAL_REQ;
end
endgenerate
// Next Gen Controller
alt_mem_ddrx_controller # (
.CFG_LOCAL_SIZE_WIDTH ( CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH ( CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH ( CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH ( CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_IF_TYPE ( CFG_LOCAL_IF_TYPE ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_CLK_PAIR_COUNT ( CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_DWIDTH_RATIO ( CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED ( CFG_ODT_ENABLED ),
.CFG_LPDDR2_ENABLED ( CFG_LPDDR2_ENABLED ),
.CFG_CTL_TBP_NUM ( CFG_CTL_TBP_NUM ),
.CFG_DATA_REORDERING_TYPE ( CFG_DATA_REORDERING_TYPE ),
.CFG_WRBUFFER_ADDR_WIDTH ( CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_RDBUFFER_ADDR_WIDTH ( CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_ECC_MULTIPLES_16_24_40_72 ( CFG_ECC_MULTIPLES_16_24_40_72 ),
.CFG_MEM_IF_CS_WIDTH ( CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ODT_WIDTH ( CFG_MEM_IF_ODT_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH ( CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DM_WIDTH ( CFG_MEM_IF_DM_WIDTH ),
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH ( CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH ( CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_DEVICE_WIDTH ( CFG_PORT_WIDTH_DEVICE_WIDTH ),
.CFG_PORT_WIDTH_REORDER_DATA ( CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_PORT_WIDTH_STARVE_LIMIT ( CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_PORT_WIDTH_ADDR_ORDER ( CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH ( CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH ( CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH ( CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH ( CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT ( CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT ( CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL ( CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD ( CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW ( CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC ( CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI ( CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD ( CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP ( CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR ( CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR ( CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP ( CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS ( CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC ( CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD ( CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD ( CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ( CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES ( CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES ( CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ( CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ( CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.CFG_PORT_WIDTH_ENABLE_ECC ( CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR ( CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_GEN_SBE ( CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE ( CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR ( CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR ( CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR ( CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_CLR_INTR ( CFG_PORT_WIDTH_CLR_INTR ),
.CFG_PORT_WIDTH_USER_RFSH ( CFG_PORT_WIDTH_USER_RFSH ),
.CFG_PORT_WIDTH_SELF_RFSH ( CFG_PORT_WIDTH_SELF_RFSH ),
.CFG_PORT_WIDTH_REGDIMM_ENABLE ( CFG_PORT_WIDTH_REGDIMM_ENABLE ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ( CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ( CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP ( CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP ( CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_WLAT_BUS_WIDTH ( CFG_WLAT_BUS_WIDTH ),
.CFG_RDATA_RETURN_MODE ( CFG_RDATA_RETURN_MODE )
) controller_inst (
.ctl_clk ( clk ),
.ctl_reset_n ( reset_n ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_deep_powerdn_req ( local_deep_powerdn_req ),
.local_deep_powerdn_chip ( local_deep_powerdn_chip ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_deep_powerdn_ack ( local_deep_powerdn_ack ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_init_done ( local_init_done ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_rdata_en ( afi_rdata_en ),
.afi_rdata_en_full ( afi_rdata_en_full ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.ctl_cal_success ( afi_cal_success ),
.ctl_cal_fail ( afi_cal_fail ),
.ctl_cal_req ( afi_cal_req ),
.ctl_init_req ( afi_init_req ),
.ctl_mem_clk_disable ( afi_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( afi_cal_byte_lane_sel_n ),
.cfg_type ( cfg_type ),
.cfg_interface_width ( cfg_interface_width ),
.cfg_burst_length ( cfg_burst_length ),
.cfg_device_width ( cfg_device_width ),
.cfg_reorder_data ( cfg_reorder_data ),
.cfg_starve_limit ( cfg_starve_limit ),
.cfg_output_regd ( cfg_output_regd ),
.cfg_addr_order ( cfg_addr_order ),
.cfg_col_addr_width ( cfg_col_addr_width ),
.cfg_row_addr_width ( cfg_row_addr_width ),
.cfg_bank_addr_width ( cfg_bank_addr_width ),
.cfg_cs_addr_width ( cfg_cs_addr_width ),
.cfg_cas_wr_lat ( cfg_cas_wr_lat ),
.cfg_add_lat ( cfg_add_lat ),
.cfg_tcl ( cfg_tcl ),
.cfg_trrd ( cfg_trrd ),
.cfg_tfaw ( cfg_tfaw ),
.cfg_trfc ( cfg_trfc ),
.cfg_trefi ( cfg_trefi ),
.cfg_trcd ( cfg_trcd ),
.cfg_trp ( cfg_trp ),
.cfg_twr ( cfg_twr ),
.cfg_twtr ( cfg_twtr ),
.cfg_trtp ( cfg_trtp ),
.cfg_tras ( cfg_tras ),
.cfg_trc ( cfg_trc ),
.cfg_tccd ( cfg_tccd ),
.cfg_auto_pd_cycles ( cfg_auto_pd_cycles ),
.cfg_self_rfsh_exit_cycles ( cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles ( cfg_pdn_exit_cycles ),
.cfg_power_saving_exit_cycles ( cfg_power_saving_exit_cycles ),
.cfg_mem_clk_entry_cycles ( cfg_mem_clk_entry_cycles ),
.cfg_tmrd ( cfg_tmrd ),
.cfg_enable_ecc ( cfg_enable_ecc ),
.cfg_enable_auto_corr ( cfg_enable_auto_corr ),
.cfg_enable_no_dm ( cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites ( cfg_enable_ecc_code_overwrites ),
.cfg_cal_req ( cfg_cal_req ),
.cfg_gen_sbe ( cfg_gen_sbe ),
.cfg_gen_dbe ( cfg_gen_dbe ),
.cfg_enable_intr ( cfg_enable_intr ),
.cfg_mask_sbe_intr ( cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr ( cfg_mask_corr_dropped_intr ),
.cfg_clr_intr ( cfg_clr_intr ),
.cfg_user_rfsh ( cfg_user_rfsh ),
.cfg_regdimm_enable ( cfg_regdimm_enable ),
.cfg_enable_burst_interrupt ( cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate ( cfg_enable_burst_terminate ),
.cfg_write_odt_chip ( cfg_write_odt_chip ),
.cfg_read_odt_chip ( cfg_read_odt_chip ),
.cfg_extra_ctl_clk_act_to_rdwr ( cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch ( cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act ( cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd ( cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip ( cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr ( cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc ( cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip ( cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch ( cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid ( cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr ( cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip ( cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd ( cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc ( cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip ( cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch ( cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid ( cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid ( cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid ( cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank ( cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act ( cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid ( cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid ( cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid ( cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal ( cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period ( cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period ( cfg_extra_ctl_clk_pdn_period ),
.cfg_enable_dqs_tracking ( cfg_enable_dqs_tracking ),
.ecc_interrupt ( ecc_interrupt ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( sts_err_addr ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( sts_corr_dropped_addr ),
.afi_ctl_refresh_done ( afi_ctl_refresh_done ),
.afi_seq_busy ( afi_seq_busy ),
.afi_ctl_long_idle ( afi_ctl_long_idle )
);
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
//altera message_off 10230
module alt_mem_ddrx_csr #
( parameter
DWIDTH_RATIO = 2,
CTL_CSR_ENABLED = 1,
CTL_ECC_CSR_ENABLED = 1,
CTL_CSR_READ_ONLY = 0,
CTL_ECC_CSR_READ_ONLY = 0,
CFG_AVALON_ADDR_WIDTH = 8,
CFG_AVALON_DATA_WIDTH = 32,
MEM_IF_CLK_PAIR_COUNT = 1,
MEM_IF_DQS_WIDTH = 72,
CFG_CS_ADDR_WIDTH = 1, // same as MEM_IF_CHIP
CFG_ROW_ADDR_WIDTH = 13, // max supported row bits
CFG_COL_ADDR_WIDTH = 10, // max supported column bits
CFG_BANK_ADDR_WIDTH = 3, // max supported bank bits
CFG_ENABLE_ECC = 1,
CFG_ENABLE_AUTO_CORR = 1,
CFG_REGDIMM_ENABLE = 0,
// timing parameter width
CAS_WR_LAT_BUS_WIDTH = 4, // max will be 8 in DDR3
ADD_LAT_BUS_WIDTH = 3, // max will be 6 in DDR2
TCL_BUS_WIDTH = 4, // max will be 11 in DDR3
BL_BUS_WIDTH = 5, //
TRRD_BUS_WIDTH = 4, // 2 - 8
TFAW_BUS_WIDTH = 6, // 6 - 32
TRFC_BUS_WIDTH = 8, // 12 - 140?
TREFI_BUS_WIDTH = 13, // 780 - 6240
TRCD_BUS_WIDTH = 4, // 2 - 11
TRP_BUS_WIDTH = 4, // 2 - 11
TWR_BUS_WIDTH = 4, // 2 - 12
TWTR_BUS_WIDTH = 4, // 1 - 10
TRTP_BUS_WIDTH = 4, // 2 - 8
TRAS_BUS_WIDTH = 5, // 4 - 29
TRC_BUS_WIDTH = 6, // 8 - 40
AUTO_PD_BUS_WIDTH = 16, // same as CSR interface
STARVE_LIMIT_BUS_WIDTH = 8,
// timing parameter
CFG_CAS_WR_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_ADD_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_TCL = 0, // these timing parameter must be set properly for controller to work
CFG_BURST_LENGTH = 0, // these timing parameter must be set properly for controller to work
CFG_TRRD = 0, // these timing parameter must be set properly for controller to work
CFG_TFAW = 0, // these timing parameter must be set properly for controller to work
CFG_TRFC = 0, // these timing parameter must be set properly for controller to work
CFG_TREFI = 0, // these timing parameter must be set properly for controller to work
CFG_TRCD = 0, // these timing parameter must be set properly for controller to work
CFG_TRP = 0, // these timing parameter must be set properly for controller to work
CFG_TWR = 0, // these timing parameter must be set properly for controller to work
CFG_TWTR = 0, // these timing parameter must be set properly for controller to work
CFG_TRTP = 0, // these timing parameter must be set properly for controller to work
CFG_TRAS = 0, // these timing parameter must be set properly for controller to work
CFG_TRC = 0, // these timing parameter must be set properly for controller to work
CFG_AUTO_PD_CYCLES = 0, // these timing parameter must be set properly for controller to work
// parameters used by input interface
CFG_ADDR_ORDER = 1, // normally we will use '1' for chip, bank, row, column arrangement
CFG_REORDER_DATA = 0,
CFG_STARVE_LIMIT = 0,
MEM_IF_CSR_COL_WIDTH = 5,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 3,
MEM_IF_CSR_CS_WIDTH = 3
)
(
ctl_clk,
ctl_rst_n,
// csr interface (Avalon)
avalon_mm_addr,
avalon_mm_be,
avalon_mm_write,
avalon_mm_wdata,
avalon_mm_read,
avalon_mm_rdata,
avalon_mm_rdata_valid,
avalon_mm_waitrequest,
// input from PHY
sts_cal_success,
sts_cal_fail,
// input from state machine
local_power_down_ack,
local_self_rfsh_ack,
// input from ecc
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
// output to PHY
cfg_cal_req,
cfg_clock_off,
ctl_cal_byte_lane_sel_n,
// output to timer
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_burst_length,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_auto_pd_cycles,
// output to input interface
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// output to ecc
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// output to others
cfg_regdimm_enable,
cfg_reorder_data,
cfg_starve_limit
);
localparam integer CFG_MEM_IF_CS_WIDTH = (2**CFG_CS_ADDR_WIDTH);
input ctl_clk;
input ctl_rst_n;
input avalon_mm_write;
input avalon_mm_read;
input [CFG_AVALON_ADDR_WIDTH - 1 : 0] avalon_mm_addr;
input [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_wdata;
input [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] avalon_mm_be;
output avalon_mm_waitrequest;
output avalon_mm_rdata_valid;
output [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
// input from AFI
input sts_cal_success;
input sts_cal_fail;
// input from state machine
input local_power_down_ack;
input local_self_rfsh_ack;
// input from ecc
input sts_sbe_error;
input sts_dbe_error;
input sts_corr_dropped;
input [7 : 0] sts_sbe_count;
input [7 : 0] sts_dbe_count;
input [7 : 0] sts_corr_dropped_count;
input [31 : 0] sts_err_addr;
input [31 : 0] sts_corr_dropped_addr;
// output to PHY
output cfg_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
output [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
output [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
output [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
output [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
output [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
output [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
output [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
output [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
output [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
output [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
output [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
output [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
output [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
output [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
output [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
output [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
output [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
output [1 : 0] cfg_addr_order;
output cfg_reorder_data;
output [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
output [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
output [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
output [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
output [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
output cfg_enable_ecc;
output cfg_enable_auto_corr;
output cfg_gen_sbe;
output cfg_gen_dbe;
output cfg_enable_intr;
output cfg_mask_sbe_intr;
output cfg_mask_dbe_intr;
output cfg_mask_corr_dropped_intr;
output cfg_clr_intr;
output cfg_regdimm_enable;
wire avalon_mm_waitrequest;
wire avalon_mm_rdata_valid;
wire [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
reg int_write_req;
reg int_read_req;
reg int_rdata_valid;
reg [8 - 1 : 0] int_addr; // hard-coded to only 8 bits
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_wdata;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_rdata;
reg [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] int_be;
reg int_mask_avalon_mm_write;
reg int_mask_avalon_mm_read;
reg int_mask_ecc_avalon_mm_write;
reg int_mask_ecc_avalon_mm_read;
// output to PHY
wire cfg_cal_req;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
wire [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
wire [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
wire [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
wire [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
wire [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
wire [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
wire [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
wire [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
wire [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
wire [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
wire [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
wire [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
wire [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
wire [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
wire [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
wire [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
wire [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
wire [1 : 0] cfg_addr_order;
wire cfg_reorder_data;
wire [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
wire [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
wire [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
wire [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_mask_corr_dropped_intr;
wire cfg_clr_intr;
// output to others
wire cfg_regdimm_enable;
// CSR read registers
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_100;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_110;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_120;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_121;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_122;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_123;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_124;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_125;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_126;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_130;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_131;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_132;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_133;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_134;
/*------------------------------------------------------------------------------
CSR Interface
------------------------------------------------------------------------------*/
// Assign waitrequest signal to '0'
assign avalon_mm_waitrequest = 1'b0;
generate
if (!CTL_CSR_ENABLED && !CTL_ECC_CSR_ENABLED)
begin
// when both csr and ecc csr is disabled
assign avalon_mm_rdata = 0;
assign avalon_mm_rdata_valid = 0;
end
else
begin
// register all inputs
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_write_req <= 0;
int_read_req <= 0;
int_addr <= 0;
int_wdata <= 0;
int_be <= 0;
end
else
begin
int_addr <= avalon_mm_addr [7 : 0]; // we only need the bottom 8 bits
int_wdata <= avalon_mm_wdata;
int_be <= avalon_mm_be;
if (avalon_mm_write)
int_write_req <= 1'b1;
else
int_write_req <= 1'b0;
if (avalon_mm_read)
int_read_req <= 1'b1;
else
int_read_req <= 1'b0;
end
end
// Write and read request mask
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
if (CTL_CSR_READ_ONLY)
begin
int_mask_avalon_mm_write <= 1'b1;
int_mask_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
end
if (CTL_ECC_CSR_READ_ONLY)
begin
int_mask_ecc_avalon_mm_write <= 1'b1;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
Read Interface
------------------------------------------------------------------------------*/
assign avalon_mm_rdata = int_rdata;
assign avalon_mm_rdata_valid = int_rdata_valid;
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_rdata <= 0;
int_rdata_valid <= 0;
end
else
begin
if (int_read_req)
begin
if (int_addr == 8'h00)
int_rdata <= read_csr_register_100;
else if (int_addr == 8'h10)
int_rdata <= read_csr_register_110;
else if (int_addr == 8'h20)
int_rdata <= read_csr_register_120;
else if (int_addr == 8'h21)
int_rdata <= read_csr_register_121;
else if (int_addr == 8'h22)
int_rdata <= read_csr_register_122;
else if (int_addr == 8'h23)
int_rdata <= read_csr_register_123;
else if (int_addr == 8'h24)
int_rdata <= read_csr_register_124;
else if (int_addr == 8'h25)
int_rdata <= read_csr_register_125;
else if (int_addr == 8'h26)
int_rdata <= read_csr_register_126;
else if (int_addr == 8'h30)
int_rdata <= read_csr_register_130;
else if (int_addr == 8'h31)
int_rdata <= read_csr_register_131;
else if (int_addr == 8'h32)
int_rdata <= read_csr_register_132;
else if (int_addr == 8'h33)
int_rdata <= read_csr_register_133;
else if (int_addr == 8'h34)
int_rdata <= read_csr_register_134;
end
if (int_read_req)
int_rdata_valid <= 1'b1;
else
int_rdata_valid <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
CSR Registers
------------------------------------------------------------------------------*/
generate
genvar i;
if (!CTL_CSR_ENABLED) // when csr is disabled
begin
// assigning values to the top
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_cs_addr_width = CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_cal_req = 0;
assign cfg_clock_off = 0;
assign ctl_cal_byte_lane_sel_n = 0;
assign cfg_regdimm_enable = 1'b1; // udimm or rdimm determined by parameter CFG_REGDIMM_ENABLE
end
else
begin
/*------------------------------------------------------------------------------
0x100 ALTMEPHY Status and Control Register
------------------------------------------------------------------------------*/
reg csr_cal_success;
reg csr_cal_fail;
reg csr_cal_req;
reg [5 : 0] csr_clock_off;
// assign value back to top
assign cfg_cal_req = csr_cal_req;
assign cfg_clock_off = csr_clock_off [MEM_IF_CLK_PAIR_COUNT - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_req <= 0;
csr_clock_off <= 0;
end
else
begin
// write request
if (int_write_req && int_addr == 8'h00)
begin
if (int_be [0])
begin
csr_cal_req <= int_wdata [2] ;
end
if (int_be [1])
begin
csr_clock_off <= int_wdata [13 : 8];
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_success <= 0;
csr_cal_fail <= 0;
end
else
begin
csr_cal_success <= sts_cal_success;
csr_cal_fail <= sts_cal_fail;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_100 = 0;
// then we set individual bits
read_csr_register_100 [0] = csr_cal_success;
read_csr_register_100 [1] = csr_cal_fail;
read_csr_register_100 [2] = csr_cal_req;
read_csr_register_100 [13 : 8] = csr_clock_off;
end
/*------------------------------------------------------------------------------
0x110 Controller Status and Control Register
------------------------------------------------------------------------------*/
reg [15 : 0] csr_auto_pd_cycles;
reg csr_auto_pd_ack;
reg csr_self_rfsh; // yyong: remember to handle this
reg csr_self_rfsh_ack;
reg csr_ganged_arf; // yyong: remember to handle this
reg [1 : 0] csr_addr_order;
reg csr_reg_dimm; // yyong: remember to handle this
reg [1 : 0] csr_drate;
// assign value back to top
assign cfg_auto_pd_cycles = csr_auto_pd_cycles;
assign cfg_addr_order = csr_addr_order;
assign cfg_regdimm_enable = csr_reg_dimm;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_cycles <= CFG_AUTO_PD_CYCLES; // reset to default value
csr_self_rfsh <= 0;
csr_ganged_arf <= 0;
csr_addr_order <= CFG_ADDR_ORDER; // reset to default value
csr_reg_dimm <= CFG_REGDIMM_ENABLE; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h10)
begin
if (int_be [0])
begin
csr_auto_pd_cycles [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_auto_pd_cycles [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_self_rfsh <= int_wdata [17] ;
csr_ganged_arf <= int_wdata [19] ;
csr_addr_order <= int_wdata [21 : 20];
csr_reg_dimm <= int_wdata [22] ;
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_ack <= 0;
csr_self_rfsh_ack <= 0;
csr_drate <= 0;
end
else
begin
csr_auto_pd_ack <= local_power_down_ack;
csr_self_rfsh_ack <= local_self_rfsh_ack;
csr_drate <= (DWIDTH_RATIO == 2) ? 2'b00 : 2'b01; // Fullrate - 00, Halfrate - 01
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_110 = 0;
// then we set individual bits
read_csr_register_110 [15 : 0 ] = csr_auto_pd_cycles;
read_csr_register_110 [16] = csr_auto_pd_ack;
read_csr_register_110 [17] = csr_self_rfsh;
read_csr_register_110 [18] = csr_self_rfsh_ack;
read_csr_register_110 [19] = csr_ganged_arf;
read_csr_register_110 [21 : 20] = csr_addr_order;
read_csr_register_110 [22] = csr_reg_dimm;
read_csr_register_110 [24 : 23] = csr_drate;
end
/*------------------------------------------------------------------------------
0x120 Memory Address Sizes 0
------------------------------------------------------------------------------*/
reg [7 : 0] csr_col_width;
reg [7 : 0] csr_row_width;
reg [3 : 0] csr_bank_width;
reg [3 : 0] csr_chip_width;
// assign value back to top
assign cfg_cs_addr_width = csr_chip_width [MEM_IF_CSR_CS_WIDTH - 1 : 0];
assign cfg_bank_addr_width = csr_bank_width [MEM_IF_CSR_BANK_WIDTH - 1 : 0];
assign cfg_row_addr_width = csr_row_width [MEM_IF_CSR_ROW_WIDTH - 1 : 0];
assign cfg_col_addr_width = csr_col_width [MEM_IF_CSR_COL_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_col_width <= CFG_COL_ADDR_WIDTH; // reset to default value
csr_row_width <= CFG_ROW_ADDR_WIDTH; // reset to default value
csr_bank_width <= CFG_BANK_ADDR_WIDTH; // reset to default value
csr_chip_width <= CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h20)
begin
if (int_be [0])
begin
if (int_wdata [7 : 0] <= CFG_COL_ADDR_WIDTH)
begin
csr_col_width <= int_wdata [7 : 0 ];
end
end
if (int_be [1])
begin
if (int_wdata [15 : 8] <= CFG_ROW_ADDR_WIDTH)
begin
csr_row_width <= int_wdata [15 : 8 ];
end
end
if (int_be [2])
begin
if (int_wdata [19 : 16] <= CFG_BANK_ADDR_WIDTH)
begin
csr_bank_width <= int_wdata [19 : 16];
end
if (int_wdata [23 : 20] <= (CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0))
begin
csr_chip_width <= int_wdata [23 : 20];
end
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_120 = 0;
// then we set individual bits
read_csr_register_120 [7 : 0 ] = csr_col_width;
read_csr_register_120 [15 : 8 ] = csr_row_width;
read_csr_register_120 [19 : 16] = csr_bank_width;
read_csr_register_120 [23 : 20] = csr_chip_width;
end
/*------------------------------------------------------------------------------
0x121 Memory Address Sizes 1
------------------------------------------------------------------------------*/
reg [31 : 0] csr_data_binary_representation;
reg [7 : 0] csr_chip_binary_representation;
reg [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] cal_byte_lane;
// assign value back to top
assign ctl_cal_byte_lane_sel_n = ~cal_byte_lane;
// determine cal_byte_lane base on csr data
for (i = 0;i < CFG_MEM_IF_CS_WIDTH;i = i + 1)
begin : ctl_cal_byte_lane_per_chip
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= {MEM_IF_DQS_WIDTH{1'b1}}; // setting to all ones
else
begin
if (csr_chip_binary_representation[i])
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= csr_data_binary_representation [MEM_IF_DQS_WIDTH - 1 : 0];
else
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= 0;
end
end
end
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_data_binary_representation <= {MEM_IF_DQS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h21)
begin
if (int_be [0])
begin
csr_data_binary_representation [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_data_binary_representation [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_data_binary_representation [23 : 16] <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_data_binary_representation [31 : 24] <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_121 = 0;
// then we set individual bits
read_csr_register_121 [31 : 0 ] = csr_data_binary_representation;
end
/*------------------------------------------------------------------------------
0x122 Memory Address Sizes 2
------------------------------------------------------------------------------*/
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_chip_binary_representation <= {CFG_MEM_IF_CS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h22)
begin
if (int_be [0])
begin
csr_chip_binary_representation [ 7 : 0] <= int_wdata [7 : 0 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_122 = 0;
// then we set individual bits
read_csr_register_122 [7 : 0 ] = csr_chip_binary_representation;
end
/*------------------------------------------------------------------------------
0x123 Memory Timing Parameters Registers 0
------------------------------------------------------------------------------*/
reg [3 : 0] csr_trcd;
reg [3 : 0] csr_trrd;
reg [3 : 0] csr_trp;
reg [3 : 0] csr_tmrd; // yyong: might remove this
reg [7 : 0] csr_tras;
reg [7 : 0] csr_trc;
// assign value back to top
assign cfg_trcd = csr_trcd [TRCD_BUS_WIDTH - 1 : 0];
assign cfg_trrd = csr_trrd [TRRD_BUS_WIDTH - 1 : 0];
assign cfg_trp = csr_trp [TRP_BUS_WIDTH - 1 : 0];
assign cfg_tras = csr_tras [TRAS_BUS_WIDTH - 1 : 0];
assign cfg_trc = csr_trc [TRC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trcd <= CFG_TRCD; // reset to default value
csr_trrd <= CFG_TRRD; // reset to default value
csr_trp <= CFG_TRP; // reset to default value
csr_tmrd <= 0; // yyong: might remove this
csr_tras <= CFG_TRAS; // reset to default value
csr_trc <= CFG_TRC; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h23)
begin
if (int_be [0])
begin
csr_trcd <= int_wdata [3 : 0 ];
csr_trrd <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_trp <= int_wdata [11 : 8 ];
csr_tmrd <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_tras <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_trc <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_123 = 0;
// then we set individual bits
read_csr_register_123 [3 : 0 ] = csr_trcd;
read_csr_register_123 [7 : 4 ] = csr_trrd;
read_csr_register_123 [11 : 8 ] = csr_trp;
read_csr_register_123 [15 : 12] = csr_tmrd;
read_csr_register_123 [23 : 16] = csr_tras;
read_csr_register_123 [31 : 24] = csr_trc;
end
/*------------------------------------------------------------------------------
0x124 Memory Timing Parameters Registers 1
------------------------------------------------------------------------------*/
reg [3 : 0] csr_twtr;
reg [3 : 0] csr_trtp;
reg [5 : 0] csr_tfaw;
// assign value back to top
assign cfg_twtr = csr_twtr [TWTR_BUS_WIDTH - 1 : 0];
assign cfg_trtp = csr_trtp [TRTP_BUS_WIDTH - 1 : 0];
assign cfg_tfaw = csr_tfaw [TFAW_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_twtr <= CFG_TWTR;
csr_trtp <= CFG_TRTP;
csr_tfaw <= CFG_TFAW;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h24)
begin
if (int_be [0])
begin
csr_twtr <= int_wdata [3 : 0 ];
csr_trtp <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_tfaw <= int_wdata [13 : 8 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_124 = 0;
// then we set individual bits
read_csr_register_124 [3 : 0 ] = csr_twtr;
read_csr_register_124 [7 : 4 ] = csr_trtp;
read_csr_register_124 [15 : 8 ] = csr_tfaw;
end
/*------------------------------------------------------------------------------
0x125 Memory Timing Parameters Registers 2
------------------------------------------------------------------------------*/
reg [15 : 0] csr_trefi;
reg [7 : 0] csr_trfc;
// assign value back to top
assign cfg_trefi = csr_trefi [TREFI_BUS_WIDTH - 1 : 0];
assign cfg_trfc = csr_trfc [TRFC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trefi <= CFG_TREFI;
csr_trfc <= CFG_TRFC;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h25)
begin
if (int_be [0])
begin
csr_trefi [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_trefi [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_trfc <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_125 = 0;
// then we set individual bits
read_csr_register_125 [15 : 0 ] = csr_trefi;
read_csr_register_125 [23 : 16] = csr_trfc;
end
/*------------------------------------------------------------------------------
0x126 Memory Timing Parameters Registers 3
------------------------------------------------------------------------------*/
reg [3 : 0] csr_tcl;
reg [3 : 0] csr_al;
reg [3 : 0] csr_cwl;
reg [3 : 0] csr_twr;
reg [7 : 0] csr_bl;
// assign value back to top
assign cfg_tcl = csr_tcl [TCL_BUS_WIDTH - 1 : 0];
assign cfg_add_lat = csr_al [ADD_LAT_BUS_WIDTH - 1 : 0];
assign cfg_cas_wr_lat = csr_cwl [CAS_WR_LAT_BUS_WIDTH - 1 : 0];
assign cfg_twr = csr_twr [TWR_BUS_WIDTH - 1 : 0];
assign cfg_burst_length = csr_bl [BL_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_tcl <= CFG_TCL;
csr_al <= CFG_ADD_LAT;
csr_cwl <= CFG_CAS_WR_LAT;
csr_twr <= CFG_TWR;
csr_bl <= CFG_BURST_LENGTH;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h26)
begin
if (int_be [0])
begin
csr_tcl <= int_wdata [3 : 0 ];
csr_al <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_cwl <= int_wdata [11 : 8 ];
csr_twr <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_bl <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_126 = 0;
// then we set individual bits
read_csr_register_126 [3 : 0 ] = csr_tcl;
read_csr_register_126 [7 : 4 ] = csr_al;
read_csr_register_126 [11 : 8 ] = csr_cwl;
read_csr_register_126 [15 : 12] = csr_twr;
read_csr_register_126 [23 : 16] = csr_bl;
end
end
if (!CTL_ECC_CSR_ENABLED)
begin
assign cfg_enable_ecc = 1'b1; // default value
assign cfg_enable_auto_corr = 1'b1; // default value
assign cfg_gen_sbe = 0;
assign cfg_gen_dbe = 0;
assign cfg_enable_intr = 1'b1; // default value
assign cfg_mask_sbe_intr = 0;
assign cfg_mask_dbe_intr = 0;
assign cfg_clr_intr = 0;
assign cfg_mask_corr_dropped_intr=0;
end
else
begin
/*------------------------------------------------------------------------------
0x130 ECC Control Register
------------------------------------------------------------------------------*/
reg csr_enable_ecc;
reg csr_enable_auto_corr;
reg csr_gen_sbe;
reg csr_gen_dbe;
reg csr_enable_intr;
reg csr_mask_sbe_intr;
reg csr_mask_dbe_intr;
reg csr_ecc_clear;
reg csr_mask_corr_dropped_intr;
// assign value back to top
assign cfg_enable_ecc = csr_enable_ecc;
assign cfg_enable_auto_corr = csr_enable_auto_corr;
assign cfg_gen_sbe = csr_gen_sbe;
assign cfg_gen_dbe = csr_gen_dbe;
assign cfg_enable_intr = csr_enable_intr;
assign cfg_mask_sbe_intr = csr_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_mask_dbe_intr;
assign cfg_clr_intr = csr_ecc_clear;
assign cfg_mask_corr_dropped_intr = csr_mask_corr_dropped_intr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_enable_ecc <= CFG_ENABLE_ECC;
csr_enable_auto_corr <= CFG_ENABLE_AUTO_CORR;
csr_gen_sbe <= 0;
csr_gen_dbe <= 0;
csr_enable_intr <= 1'b1;
csr_mask_sbe_intr <= 0;
csr_mask_dbe_intr <= 0;
csr_ecc_clear <= 0;
csr_mask_corr_dropped_intr <= 0;
end
else
begin
// write request
if (!int_mask_ecc_avalon_mm_write && int_write_req && int_addr == 8'h30)
begin
if (int_be [0])
begin
csr_enable_ecc <= int_wdata [0];
csr_enable_auto_corr <= int_wdata [1];
csr_gen_sbe <= int_wdata [2];
csr_gen_dbe <= int_wdata [3];
csr_enable_intr <= int_wdata [4];
csr_mask_sbe_intr <= int_wdata [5];
csr_mask_dbe_intr <= int_wdata [6];
csr_ecc_clear <= int_wdata [7];
end
if (int_be [1])
begin
csr_mask_corr_dropped_intr <= int_wdata [8];
end
end
// set csr_clear to zero after one clock cycle
if (csr_ecc_clear)
csr_ecc_clear <= 1'b0;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_130 = 0;
// then we set individual bits
read_csr_register_130 [0] = csr_enable_ecc;
read_csr_register_130 [1] = csr_enable_auto_corr;
read_csr_register_130 [2] = csr_gen_sbe;
read_csr_register_130 [3] = csr_gen_dbe;
read_csr_register_130 [4] = csr_enable_intr;
read_csr_register_130 [5] = csr_mask_sbe_intr;
read_csr_register_130 [6] = csr_mask_dbe_intr;
read_csr_register_130 [7] = csr_ecc_clear;
read_csr_register_130 [8] = csr_mask_corr_dropped_intr;
end
/*------------------------------------------------------------------------------
0x131 ECC Status Register (Read Only)
------------------------------------------------------------------------------*/
reg csr_sbe_error;
reg csr_dbe_error;
reg csr_corr_dropped;
reg [7 : 0] csr_sbe_count;
reg [7 : 0] csr_dbe_count;
reg [7 : 0] csr_corr_dropped_count;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
csr_sbe_error <= sts_sbe_error;
csr_dbe_error <= sts_dbe_error;
csr_sbe_count <= sts_sbe_count;
csr_dbe_count <= sts_dbe_count;
csr_corr_dropped <= sts_corr_dropped;
csr_corr_dropped_count <= sts_corr_dropped_count;
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_131 = 0;
// then we set individual bits
read_csr_register_131 [0 ] = csr_sbe_error;
read_csr_register_131 [1 ] = csr_dbe_error;
read_csr_register_131 [2 ] = csr_corr_dropped;
read_csr_register_131 [15 : 8 ] = csr_sbe_count;
read_csr_register_131 [23 : 16] = csr_dbe_count;
read_csr_register_131 [31 : 24] = csr_corr_dropped_count;
end
/*------------------------------------------------------------------------------
0x132 ECC Error Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_error_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_error_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_error_addr <= 0;
else
csr_error_addr <= sts_err_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_132 = csr_error_addr;
end
/*------------------------------------------------------------------------------
0x133 ECC Correction Dropped Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_corr_dropped_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_corr_dropped_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_corr_dropped_addr <= 0;
else
csr_corr_dropped_addr <= sts_corr_dropped_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_133 = csr_corr_dropped_addr;
end
/*------------------------------------------------------------------------------
0x134 Controller Status and Control Register - Advanced Features
------------------------------------------------------------------------------*/
reg csr_reorder_data;
reg [7 : 0] csr_starve_limit;
// assign value back to top
assign cfg_reorder_data = csr_reorder_data;
assign cfg_starve_limit = csr_starve_limit;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_reorder_data <= CFG_REORDER_DATA;
csr_starve_limit <= CFG_STARVE_LIMIT; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h34)
begin
if (int_be [0])
begin
csr_reorder_data <= int_wdata [ 0];
end
if (int_be [2])
begin
csr_starve_limit <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_134 = 0;
// then we set individual bits
read_csr_register_134 [ 0 ] = csr_reorder_data;
read_csr_register_134 [ 23 : 16 ] = csr_starve_limit;
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
module alt_mem_ddrx_dataid_manager
# (
parameter
CFG_DATA_ID_WIDTH = 8,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 1,
CFG_TBP_NUM = 4,
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_DWIDTH_RATIO = 2
)
(
// clock & reset
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
// update cmd interface
update_cmd_if_ready,
update_cmd_if_valid,
update_cmd_if_data_id,
update_cmd_if_burstcount,
update_cmd_if_tbp_id,
// update data interface
update_data_if_valid,
update_data_if_data_id,
update_data_if_data_id_vector,
update_data_if_burstcount,
update_data_if_next_burstcount,
// notify burstcount consumed interface
notify_data_if_valid,
notify_data_if_burstcount,
// notify data ready interface (TBP)
notify_tbp_data_ready,
notify_tbp_data_partial_be,
// buffer write address generate interface
write_data_if_ready,
write_data_if_valid,
write_data_if_accepted,
write_data_if_address,
write_data_if_partial_dm,
// buffer read addresss generate interface
read_data_if_valid,
read_data_if_data_id,
read_data_if_data_id_vector,
read_data_if_valid_first,
read_data_if_data_id_first,
read_data_if_data_id_vector_first,
read_data_if_valid_first_vector,
read_data_if_valid_last,
read_data_if_data_id_last,
read_data_if_data_id_vector_last,
read_data_if_address,
read_data_if_datavalid,
read_data_if_done
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
// clock & reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input cfg_enable_ecc;
input cfg_enable_auto_corr;
input cfg_enable_no_dm;
// update cmd interface
output update_cmd_if_ready;
input update_cmd_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
input [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
input [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
// update data interface
input update_data_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
input [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
output notify_data_if_valid;
output [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
// notify tbp interface
output [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
output notify_tbp_data_partial_be;
// buffer write address generate interface
output write_data_if_ready;
input write_data_if_valid;
output write_data_if_accepted;
output [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
input write_data_if_partial_dm;
// read data interface
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
input read_data_if_valid_first;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_first;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid_first_vector;
input read_data_if_valid_last;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_last;
output [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
output [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
output read_data_if_done;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_enable_no_dm;
// update cmd interface
reg update_cmd_if_ready;
wire update_cmd_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
wire [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
wire [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address;
// update data interface
wire update_data_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
wire notify_data_if_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_notify_data_if_valid;
reg [CFG_INT_SIZE_WIDTH-1:0] mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
// dataid array
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0]; // mano - this should be CFG_INT_SIZE_WIDTH?
reg [CFG_TBP_NUM-1:0] dataid_array_tbp_id [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_dataid_array_done;
// notify tbp interface
wire [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
reg notify_tbp_data_partial_be;
reg [CFG_TBP_NUM-1:0] mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] tbp_data_ready_r;
// buffer write address generate interface
reg write_data_if_ready;
wire write_data_if_valid;
wire write_data_if_accepted;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_nextaddress;
wire write_data_if_partial_dm;
// read data interface
wire [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
reg [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
wire [CFG_INT_SIZE_WIDTH-1:0] read_data_if_burstcount; // used in assertion check
reg [CFG_BUFFER_ADDR_WIDTH-1:0] mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
wire read_data_if_done;
reg write_data_if_address_blocked;
// -----------------------------
// signal declaration
// -----------------------------
reg cfg_enable_partial_be_notification;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount_2x;
wire update_cmd_if_accepted;
wire update_cmd_if_address_blocked;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextmaxaddress;
reg update_cmd_if_nextmaxaddress_wrapped; // nextmaxaddress has wrapped around buffer max address
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_unnotified_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_next_unnotified_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_write_data_if_address_blocked;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_update_cmd_if_address_blocked;
// error debug signals - used in assertions
reg err_dataid_array_overwritten;
reg err_dataid_array_invalidread;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter; // increments on data write, decrements on data read
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_cmd_unallocated_counter; // increments by cmd burstcount on update cmd, decrements on data read
reg buffer_valid_counter_full;
reg err_buffer_valid_counter_overflow;
reg err_buffer_cmd_unallocated_counter_overflow;
reg partial_be_detected;
reg partial_be_when_no_cmd_tracked;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_greatereq;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_same;
wire update_data_bc_gt_update_cmd_unnotified_bc;
wire burstcount_list_read;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_read_data;
wire burstcount_list_read_data_valid;
wire burstcount_list_write;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_write_data;
reg update_data_if_burstcount_greatereq_burstcount_list;
reg update_data_if_burstcount_same_burstcount_list;
integer k;
// -----------------------------
// module definition
// -----------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_enable_partial_be_notification <= 1'b0;
end
else
begin
cfg_enable_partial_be_notification <= cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_max_cmd_burstcount <= 0;
cfg_max_cmd_burstcount_2x <= 0;
end
else
begin
cfg_max_cmd_burstcount <= cfg_burst_length / CFG_DWIDTH_RATIO;
cfg_max_cmd_burstcount_2x <= 2 * cfg_max_cmd_burstcount;
end
end
assign burstcount_list_write = update_cmd_if_accepted;
assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
assign burstcount_list_read = notify_data_if_valid;
// Burst count list to keep track of burst count value,
// to be used for comparison with burst count value from burst tracking logic
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_INT_SIZE_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
burstcount_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (burstcount_list_read_data_valid),
.list_get_entry_ready (burstcount_list_read),
.list_get_entry_id (burstcount_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (burstcount_list_write),
.list_put_entry_ready (),
.list_put_entry_id (burstcount_list_write_data)
);
always @ (*)
begin
if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
end
if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
begin
update_data_if_burstcount_same_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_same_burstcount_list = 1'b0;
end
end
// dataid_array management
genvar i;
generate
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array_management
assign update_data_if_burstcount_greatereq [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
assign update_data_if_burstcount_same [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_address [i] <= 0;
dataid_array_burstcount [i] <= 0;
dataid_array_tbp_id [i] <= 0;
dataid_array_data_ready [i] <= 1'b0;
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b0;
err_dataid_array_overwritten <= 0;
err_dataid_array_invalidread <= 0;
end
else
begin
// update cmd, update data & read data will not happen on same cycle
// update cmd interface
if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
begin
dataid_array_address [i] <= update_cmd_if_address;
dataid_array_burstcount [i] <= update_cmd_if_burstcount;
dataid_array_tbp_id [i] <= update_cmd_if_tbp_id;
dataid_array_valid [i] <= 1'b1;
mux_dataid_array_done [i] <= 1'b0;
if (dataid_array_valid[i])
begin
err_dataid_array_overwritten <= 1;
end
end
// update data interface
if (update_data_if_burstcount_greatereq[i])
begin
dataid_array_data_ready [i] <= 1'b1;
end
// read data interface
if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
begin
dataid_array_address [i] <= dataid_array_address [i] + 1;
dataid_array_burstcount [i] <= dataid_array_burstcount [i] - 1;
dataid_array_data_ready [i] <= 0;
if (dataid_array_burstcount [i] == 1'b1)
begin
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b1;
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
if (~dataid_array_valid[i])
begin
err_dataid_array_invalidread <= 1;
end
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
end
end
always @ (*)
begin
if (update_data_if_burstcount_greatereq[i])
begin
mux_notify_data_if_valid [i] = 1'b1;
end
else
begin
mux_notify_data_if_valid [i] = 1'b0;
end
end
end
endgenerate
// mux to generate signals from output of dataid_array
// 1. notify TBP that data is ready to be read
// 2. notify other blocks burstcount consumed by dataid_array entry
// 3. generate read data address
assign notify_data_if_valid = update_data_if_burstcount_greatereq_burstcount_list;
assign notify_data_if_burstcount= burstcount_list_read_data;
assign read_data_if_burstcount = mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
assign read_data_if_done = |mux_dataid_array_done;
assign update_cmd_if_address_blocked= |mux_update_cmd_if_address_blocked;
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one afi_wlat group
begin
always @ (*)
begin
read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
end
end
else
begin
wire rdata_address_list_read;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
wire rdata_address_list_read_data_valid;
wire rdata_address_list_write;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
assign rdata_address_list_read = read_data_if_valid_last;
assign rdata_address_list_write = read_data_if_valid_first;
assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
// Read data address list, to keep track of read address to different write data buffer group
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CTL_LIST_DEPTH (CFG_DRAM_WLAT_GROUP),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
rdata_address_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (rdata_address_list_read_data_valid),
.list_get_entry_ready (rdata_address_list_read),
.list_get_entry_id (rdata_address_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (rdata_address_list_write),
.list_put_entry_ready (),
.list_put_entry_id (rdata_address_list_write_data)
);
for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
begin : rdata_if_address_per_dqs_group
always @ (*)
begin
if (read_data_if_valid_first_vector [i])
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
end
else
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address_blocked <= 0;
end
else
begin
write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
end
end
always @ (*)
begin
mux_tbp_data_ready [0] = (mux_notify_data_if_valid [0]) ? dataid_array_tbp_id [0] : {CFG_TBP_NUM{1'b0}};
mux_notify_data_if_burstcount [0] = (mux_notify_data_if_valid [0]) ? dataid_array_burstcount [0] : 0;
mux_read_data_if_address [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address [0] : 0;
mux_read_data_if_burstcount [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
mux_write_data_if_address_blocked [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ~( (dataid_array_address[0] < update_cmd_if_address) & (dataid_array_address[0] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
end
end
genvar j;
generate
for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
begin : gen_mux_dataid_array_output
always @ (*)
begin
mux_tbp_data_ready [j] = mux_tbp_data_ready [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_tbp_id [j] : {CFG_TBP_NUM{1'b0}} );
mux_notify_data_if_burstcount [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_burstcount [j] : 0 );
mux_read_data_if_address [j] = mux_read_data_if_address [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address [j] : 0 );
mux_read_data_if_burstcount [j] = mux_read_data_if_burstcount [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
mux_write_data_if_address_blocked [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ~( (dataid_array_address[j] < update_cmd_if_address) & (dataid_array_address[j] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
end
end
end
endgenerate
assign notify_tbp_data_ready = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
// address generation for data location in buffer
assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_address <= 0;
update_cmd_if_nextmaxaddress <= 0;
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
write_data_if_address <= 0;
write_data_if_nextaddress <= 0;
end
else
begin
if (update_cmd_if_accepted)
begin
// dataid allocation/deallocation makes sure doesn't overflow
update_cmd_if_address <= update_cmd_if_nextaddress;
update_cmd_if_nextmaxaddress <= update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x;
if (update_cmd_if_nextaddress > (update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x))
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b1;
end
else
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
end
end
if (write_data_if_accepted)
begin
write_data_if_address <= write_data_if_address + 1;
write_data_if_nextaddress <= write_data_if_address + 2;
end
else
begin
write_data_if_nextaddress <= write_data_if_address + 1;
end
end
end
// un-notified burstcount counter
always @ (*)
begin
// notify_data_if_valid isn't evaluated, as notify_data_if_burstcount is 0 when ~notify_data_if_burstcount
if (update_cmd_if_accepted)
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount + update_cmd_if_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
else
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_unnotified_burstcount <= 0;
end
else
begin
update_cmd_if_unnotified_burstcount <= update_cmd_if_next_unnotified_burstcount;
end
end
// currently buffer_cmd_unallocated_counter only used for debug purposes
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
err_buffer_cmd_unallocated_counter_overflow <= 0;
end
else
begin
if (update_cmd_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
end
else if (update_cmd_if_accepted)
begin
// write only
{err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
end
else if (read_data_if_valid_last)
begin
// read only
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
end
else
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_ready <= 0;
end
else
begin
update_cmd_if_ready <= ~update_cmd_if_address_blocked;
end
end
assign write_data_if_accepted = write_data_if_ready & write_data_if_valid;
always @ (*)
begin
if (write_data_if_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
write_data_if_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
// if cfg_enable_partial_be_notification, de-assert write read if partial be detected, and we have no commands being tracked currently
write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
read_data_if_datavalid <= 0;
end
else
begin
read_data_if_datavalid <= read_data_if_valid;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
buffer_valid_counter_full <= 1'b0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (write_data_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
else if (write_data_if_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0}) // when valid counter is counting up to all_ones
begin
buffer_valid_counter_full <= 1'b1;
end
else
begin
buffer_valid_counter_full <= 1'b0;
end
end
else if (read_data_if_valid_last)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
buffer_valid_counter_full <= 1'b0;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
end
end
// partial be generation logic
always @ (*)
begin
if (partial_be_when_no_cmd_tracked)
begin
notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
end
else
begin
notify_tbp_data_partial_be = partial_be_detected;
end
end
assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else if (partial_be_detected & ~notify_data_if_valid)
begin
partial_be_detected <= partial_be_detected;
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_dm & update_data_bc_gt_update_cmd_unnotified_bc;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
//For tCL = 3 and tCWL = 2 rdwr_data_tmg block output must be registered in order to support ODT
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr2_odt_gen
# ( parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_add_lat,
cfg_burst_length,
cfg_output_regd,
bg_do_write,
bg_do_read,
int_odt_l,
int_odt_h
);
//=================================================================================================//
// Local parameter definition //
//=================================================================================================//
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL; // okay to size this to 4 since max latency in DDR2 is 7+6=13
localparam CFG_TAOND = 2;
localparam CFG_TAOFD = 2.5;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_ADD_LAT-1:0] cfg_add_lat;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
output int_odt_l;
output int_odt_h;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
wire bg_do_read;
reg [1:0] regd_output;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl_unreg;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl;
reg int_tcwl_even;
reg int_tcwl_odd;
reg [CFG_PORT_WIDTH_TCL-1:0] write_latency;
reg [CFG_PORT_WIDTH_TCL-1:0] read_latency;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_read_pipe;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
regd_output <= 0;
end
else
begin
if (cfg_output_regd)
regd_output <= (CFG_DWIDTH_RATIO / 2);
else
regd_output <= 2'd0;
end
end
always @ (*)
begin
int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b0;
end
else
begin
if (int_tcwl % 2 == 0)
begin
int_tcwl_even <= 1'b1;
int_tcwl_odd <= 1'b0;
end
else
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_latency <= 0;
read_latency <= 0;
end
else
begin
write_latency <= (int_tcwl - 4) / (CFG_DWIDTH_RATIO / 2);
read_latency <= (int_tcwl - 3) / (CFG_DWIDTH_RATIO / 2);
end
end
//=================================================================================================//
// Delay ODT signal to match READ DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (bg_do_read)
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
else
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 3)
start_odt_read = bg_do_read;
else
start_odt_read = do_read_pipe[read_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_read_count <= 1;
else
doing_read_count <= 0;
end
else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
//=================================================================================================//
// Delay ODT signal to match WRITE DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (bg_do_write)
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_write};
else
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 4)
start_odt_write = bg_do_write;
else
start_odt_write = do_write_pipe[write_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_write_count <= 1;
else
doing_write_count <= 0;
end
else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else // half and quarter rate
begin
if (int_tcwl_even)
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
else
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
else // half and quarter rate
begin
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_write_count > 0)
begin
if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_read_count > 0)
begin
if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_h | reg_odt_h;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_l | reg_odt_l;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr3_odt_gen
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CAS_WR_LAT = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_cas_wr_lat,
cfg_output_regd,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
int_odt_l,
int_odt_h,
int_odt_i_1,
int_odt_i_2
);
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
//=================================================================================================//
// DDR3 ODT timing parameters //
//=================================================================================================//
localparam integer CFG_ODTH8 = 6; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTH4 = 4; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO / 2;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT-1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
output int_odt_l;
output int_odt_h;
output int_odt_i_1;
output int_odt_i_2;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
reg int_do_read;
reg int_do_write_burst_chop;
reg int_do_read_burst_chop;
reg int_do_read_burst_chop_c;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
wire [3:0] diff_modulo_unreg;
reg [3:0] diff_modulo;
wire [3:0] sel_do_read_pipe_unreg;
reg [3:0] sel_do_read_pipe;
reg diff_modulo_not_zero;
reg diff_modulo_one;
reg diff_modulo_two;
reg diff_modulo_three;
reg int_odt_l_int;
reg int_odt_l_int_r;
reg premux_odt_h;
reg premux_odt_h_r;
reg int_odt_h_int;
reg int_odt_h_int_r;
reg int_odt_i_1_int;
reg int_odt_i_2_int;
reg int_odt_i_1_int_r;
reg int_odt_i_2_int_r;
wire int_odt_l;
wire int_odt_h;
wire int_odt_i_1;
wire int_odt_i_2;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
wire doing_read_count_not_zero;
reg doing_read_count_not_zero_r;
wire [3:0] doing_write_count_limit;
wire [3:0] doing_read_count_limit;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_read_pipe;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_burst_chop_pipe;
//=================================================================================================//
// Define ODT pulse width during READ operation //
//=================================================================================================//
//ODTLon/ODTLoff are calculated based on CWL, Below logic is to compensate for that timing during read, Needs to delay ODT signal by cfg_tcl - cfg_cas_wr_lat
assign diff_unreg = cfg_tcl - cfg_cas_wr_lat;
assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD);
assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo_not_zero;
//assign diff_modulo_not_zero = (|diff_modulo);
//assign sel_do_read_pipe = diff - CFG_ODTPIPE_THRESHOLD;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff <= 0;
diff_modulo <= 0;
sel_do_read_pipe <= 0;
end
else
begin
diff <= diff_unreg;
diff_modulo <= diff_modulo_unreg;
sel_do_read_pipe <= (sel_do_read_pipe_unreg > 0) ? (sel_do_read_pipe_unreg - 1'b1) : 0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff_modulo_not_zero <= 1'b0;
diff_modulo_one <= 1'b0;
diff_modulo_two <= 1'b0;
diff_modulo_three <= 1'b0;
end
else
begin
diff_modulo_not_zero <= |diff_modulo;
diff_modulo_one <= (diff_modulo == 1) ? 1'b1 : 1'b0;
diff_modulo_two <= (diff_modulo == 2) ? 1'b1 : 1'b0;
diff_modulo_three <= (diff_modulo == 3) ? 1'b1 : 1'b0;
end
end
always @ (*)
begin
int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;
int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_read_burst_chop <= 1'b0;
end
else
begin
if (int_do_read)
begin
int_do_read_burst_chop <= int_do_read_burst_chop_c;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_read_pipe <= 0;
end
else
begin
do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_read};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_burst_chop_pipe <= 0;
end
else
begin
do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_burst_chop};
end
end
assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
assign doing_read_count_not_zero = (|doing_read_count);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_count <= 0;
end
else
begin
if (int_do_read)
begin
doing_read_count <= 1;
end
else if (doing_read_count >= doing_read_count_limit)
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
doing_read_count_not_zero_r <= 1'b0;
end
else
begin
doing_read_count_not_zero_r <= doing_read_count_not_zero;
end
end
//=================================================================================================//
// Define ODT pulse width during WRITE operation //
//=================================================================================================//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_write_burst_chop <= 1'b0;
end
else
begin
if (bg_do_write)
begin
int_do_write_burst_chop <= bg_do_burst_chop;
end
end
end
assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_count <= 0;
end
else
begin
if (bg_do_write)
begin
doing_write_count <= 1;
end
else if (doing_write_count >= doing_write_count_limit)
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (bg_do_write || int_do_read)
begin
premux_odt_h = 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
premux_odt_h = 1'b1;
end
else
begin
premux_odt_h = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
premux_odt_h_r <= 1'b0;
end
else
begin
if (int_do_read)
begin
premux_odt_h_r <= 1'b1;
end
else if ((doing_read_count > 1 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 4) || diff_modulo_two)) || (doing_read_count > 0 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 2) || diff_modulo_three)))
begin
premux_odt_h_r <= 1'b1;
end
else
begin
premux_odt_h_r <= 1'b0;
end
end
end
always @ (*)
begin
if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r))
begin
int_odt_h_int = premux_odt_h_r;
end
else // write, read with normal odt
begin
int_odt_h_int = premux_odt_h;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_l_int <= 1'b0;
end
else
begin
if (bg_do_write || (int_do_read && !diff_modulo_two && !diff_modulo_three))
begin
int_odt_l_int <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
int_odt_l_int <= 1'b1;
end
else
begin
int_odt_l_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_1_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_1_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && !diff_modulo_not_zero) || (doing_read_count > 0 && diff_modulo_not_zero))
begin
int_odt_i_1_int <= 1'b1;
end
else
begin
int_odt_i_1_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_2_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_2_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && (!diff_modulo_not_zero || diff_modulo_one)) || (doing_read_count > 0 && (diff_modulo_two || diff_modulo_three)))
begin
int_odt_i_2_int <= 1'b1;
end
else
begin
int_odt_i_2_int <= 1'b0;
end
end
end
//Generate registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_h_int_r <= 1'b0;
int_odt_l_int_r <= 1'b0;
int_odt_i_1_int_r <= 1'b0;
int_odt_i_2_int_r <= 1'b0;
end
else
begin
int_odt_h_int_r <= int_odt_h_int;
int_odt_l_int_r <= int_odt_l_int;
int_odt_i_1_int_r <= int_odt_i_1_int;
int_odt_i_2_int_r <= int_odt_i_2_int;
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i_1 = (cfg_output_regd) ? int_odt_i_1_int_r : int_odt_i_1_int;
assign int_odt_i_2 = (cfg_output_regd) ? int_odt_i_2_int_r : int_odt_i_2_int;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal,
err_sbe
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
reg err_sbe;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
wire int_err_sbe;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg int_err_sbe_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_err_sbe_r <= 1'b0;
int_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_err_sbe_r <= int_err_sbe;
int_output_ecc_code_r <= int_output_ecc_code;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
err_sbe = int_err_sbe_r;
output_ecc_code = int_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
err_sbe = int_err_sbe;
output_ecc_code = int_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64 decoder_inst
(
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_32.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:07:26:21:21:15:PN cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=64 LPM_WIDTH=6 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN VERSION_END
//synthesis_resources = lut 72
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [5:0] data;
output [63:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [5:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire [63:0] eq_node;
wire [63:0] eq_wire;
wire [3:0] w_anode1000w;
wire [3:0] w_anode1010w;
wire [3:0] w_anode1020w;
wire [3:0] w_anode1030w;
wire [3:0] w_anode1041w;
wire [3:0] w_anode1053w;
wire [3:0] w_anode1064w;
wire [3:0] w_anode1074w;
wire [3:0] w_anode1084w;
wire [3:0] w_anode1094w;
wire [3:0] w_anode1104w;
wire [3:0] w_anode1114w;
wire [3:0] w_anode1124w;
wire [3:0] w_anode1135w;
wire [3:0] w_anode1147w;
wire [3:0] w_anode1158w;
wire [3:0] w_anode1168w;
wire [3:0] w_anode1178w;
wire [3:0] w_anode1188w;
wire [3:0] w_anode1198w;
wire [3:0] w_anode1208w;
wire [3:0] w_anode1218w;
wire [3:0] w_anode464w;
wire [3:0] w_anode482w;
wire [3:0] w_anode499w;
wire [3:0] w_anode509w;
wire [3:0] w_anode519w;
wire [3:0] w_anode529w;
wire [3:0] w_anode539w;
wire [3:0] w_anode549w;
wire [3:0] w_anode559w;
wire [3:0] w_anode571w;
wire [3:0] w_anode583w;
wire [3:0] w_anode594w;
wire [3:0] w_anode604w;
wire [3:0] w_anode614w;
wire [3:0] w_anode624w;
wire [3:0] w_anode634w;
wire [3:0] w_anode644w;
wire [3:0] w_anode654w;
wire [3:0] w_anode665w;
wire [3:0] w_anode677w;
wire [3:0] w_anode688w;
wire [3:0] w_anode698w;
wire [3:0] w_anode708w;
wire [3:0] w_anode718w;
wire [3:0] w_anode728w;
wire [3:0] w_anode738w;
wire [3:0] w_anode748w;
wire [3:0] w_anode759w;
wire [3:0] w_anode771w;
wire [3:0] w_anode782w;
wire [3:0] w_anode792w;
wire [3:0] w_anode802w;
wire [3:0] w_anode812w;
wire [3:0] w_anode822w;
wire [3:0] w_anode832w;
wire [3:0] w_anode842w;
wire [3:0] w_anode853w;
wire [3:0] w_anode865w;
wire [3:0] w_anode876w;
wire [3:0] w_anode886w;
wire [3:0] w_anode896w;
wire [3:0] w_anode906w;
wire [3:0] w_anode916w;
wire [3:0] w_anode926w;
wire [3:0] w_anode936w;
wire [3:0] w_anode947w;
wire [3:0] w_anode959w;
wire [3:0] w_anode970w;
wire [3:0] w_anode980w;
wire [3:0] w_anode990w;
wire [2:0] w_data462w;
assign
data_wire = data,
eq = eq_node,
eq_node = eq_wire[63:0],
eq_wire = {{w_anode1218w[3], w_anode1208w[3], w_anode1198w[3], w_anode1188w[3], w_anode1178w[3], w_anode1168w[3], w_anode1158w[3], w_anode1147w[3]}, {w_anode1124w[3], w_anode1114w[3], w_anode1104w[3], w_anode1094w[3], w_anode1084w[3], w_anode1074w[3], w_anode1064w[3], w_anode1053w[3]}, {w_anode1030w[3], w_anode1020w[3], w_anode1010w[3], w_anode1000w[3], w_anode990w[3], w_anode980w[3], w_anode970w[3], w_anode959w[3]}, {w_anode936w[3], w_anode926w[3], w_anode916w[3], w_anode906w[3], w_anode896w[3], w_anode886w[3], w_anode876w[3], w_anode865w[3]}, {w_anode842w[3], w_anode832w[3], w_anode822w[3], w_anode812w[3], w_anode802w[3], w_anode792w[3], w_anode782w[3], w_anode771w[3]}, {w_anode748w[3], w_anode738w[3], w_anode728w[3], w_anode718w[3], w_anode708w[3], w_anode698w[3], w_anode688w[3], w_anode677w[3]}, {w_anode654w[3], w_anode644w[3], w_anode634w[3], w_anode624w[3], w_anode614w[3], w_anode604w[3], w_anode594w[3], w_anode583w[3]}, {w_anode559w[3], w_anode549w[3], w_anode539w[3], w_anode529w[3], w_anode519w[3], w_anode509w[3], w_anode499w[3], w_anode482w[3]}},
w_anode1000w = {(w_anode1000w[2] & w_data462w[2]), (w_anode1000w[1] & (~ w_data462w[1])), (w_anode1000w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode1010w = {(w_anode1010w[2] & w_data462w[2]), (w_anode1010w[1] & (~ w_data462w[1])), (w_anode1010w[0] & w_data462w[0]), w_anode947w[3]},
w_anode1020w = {(w_anode1020w[2] & w_data462w[2]), (w_anode1020w[1] & w_data462w[1]), (w_anode1020w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode1030w = {(w_anode1030w[2] & w_data462w[2]), (w_anode1030w[1] & w_data462w[1]), (w_anode1030w[0] & w_data462w[0]), w_anode947w[3]},
w_anode1041w = {(w_anode1041w[2] & data_wire[5]), (w_anode1041w[1] & data_wire[4]), (w_anode1041w[0] & (~ data_wire[3])), 1'b1},
w_anode1053w = {(w_anode1053w[2] & (~ w_data462w[2])), (w_anode1053w[1] & (~ w_data462w[1])), (w_anode1053w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1064w = {(w_anode1064w[2] & (~ w_data462w[2])), (w_anode1064w[1] & (~ w_data462w[1])), (w_anode1064w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1074w = {(w_anode1074w[2] & (~ w_data462w[2])), (w_anode1074w[1] & w_data462w[1]), (w_anode1074w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1084w = {(w_anode1084w[2] & (~ w_data462w[2])), (w_anode1084w[1] & w_data462w[1]), (w_anode1084w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1094w = {(w_anode1094w[2] & w_data462w[2]), (w_anode1094w[1] & (~ w_data462w[1])), (w_anode1094w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1104w = {(w_anode1104w[2] & w_data462w[2]), (w_anode1104w[1] & (~ w_data462w[1])), (w_anode1104w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1114w = {(w_anode1114w[2] & w_data462w[2]), (w_anode1114w[1] & w_data462w[1]), (w_anode1114w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1124w = {(w_anode1124w[2] & w_data462w[2]), (w_anode1124w[1] & w_data462w[1]), (w_anode1124w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1135w = {(w_anode1135w[2] & data_wire[5]), (w_anode1135w[1] & data_wire[4]), (w_anode1135w[0] & data_wire[3]), 1'b1},
w_anode1147w = {(w_anode1147w[2] & (~ w_data462w[2])), (w_anode1147w[1] & (~ w_data462w[1])), (w_anode1147w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1158w = {(w_anode1158w[2] & (~ w_data462w[2])), (w_anode1158w[1] & (~ w_data462w[1])), (w_anode1158w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1168w = {(w_anode1168w[2] & (~ w_data462w[2])), (w_anode1168w[1] & w_data462w[1]), (w_anode1168w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1178w = {(w_anode1178w[2] & (~ w_data462w[2])), (w_anode1178w[1] & w_data462w[1]), (w_anode1178w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1188w = {(w_anode1188w[2] & w_data462w[2]), (w_anode1188w[1] & (~ w_data462w[1])), (w_anode1188w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1198w = {(w_anode1198w[2] & w_data462w[2]), (w_anode1198w[1] & (~ w_data462w[1])), (w_anode1198w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1208w = {(w_anode1208w[2] & w_data462w[2]), (w_anode1208w[1] & w_data462w[1]), (w_anode1208w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1218w = {(w_anode1218w[2] & w_data462w[2]), (w_anode1218w[1] & w_data462w[1]), (w_anode1218w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode464w = {(w_anode464w[2] & (~ data_wire[5])), (w_anode464w[1] & (~ data_wire[4])), (w_anode464w[0] & (~ data_wire[3])), 1'b1},
w_anode482w = {(w_anode482w[2] & (~ w_data462w[2])), (w_anode482w[1] & (~ w_data462w[1])), (w_anode482w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode499w = {(w_anode499w[2] & (~ w_data462w[2])), (w_anode499w[1] & (~ w_data462w[1])), (w_anode499w[0] & w_data462w[0]), w_anode464w[3]},
w_anode509w = {(w_anode509w[2] & (~ w_data462w[2])), (w_anode509w[1] & w_data462w[1]), (w_anode509w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode519w = {(w_anode519w[2] & (~ w_data462w[2])), (w_anode519w[1] & w_data462w[1]), (w_anode519w[0] & w_data462w[0]), w_anode464w[3]},
w_anode529w = {(w_anode529w[2] & w_data462w[2]), (w_anode529w[1] & (~ w_data462w[1])), (w_anode529w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode539w = {(w_anode539w[2] & w_data462w[2]), (w_anode539w[1] & (~ w_data462w[1])), (w_anode539w[0] & w_data462w[0]), w_anode464w[3]},
w_anode549w = {(w_anode549w[2] & w_data462w[2]), (w_anode549w[1] & w_data462w[1]), (w_anode549w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode559w = {(w_anode559w[2] & w_data462w[2]), (w_anode559w[1] & w_data462w[1]), (w_anode559w[0] & w_data462w[0]), w_anode464w[3]},
w_anode571w = {(w_anode571w[2] & (~ data_wire[5])), (w_anode571w[1] & (~ data_wire[4])), (w_anode571w[0] & data_wire[3]), 1'b1},
w_anode583w = {(w_anode583w[2] & (~ w_data462w[2])), (w_anode583w[1] & (~ w_data462w[1])), (w_anode583w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode594w = {(w_anode594w[2] & (~ w_data462w[2])), (w_anode594w[1] & (~ w_data462w[1])), (w_anode594w[0] & w_data462w[0]), w_anode571w[3]},
w_anode604w = {(w_anode604w[2] & (~ w_data462w[2])), (w_anode604w[1] & w_data462w[1]), (w_anode604w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode614w = {(w_anode614w[2] & (~ w_data462w[2])), (w_anode614w[1] & w_data462w[1]), (w_anode614w[0] & w_data462w[0]), w_anode571w[3]},
w_anode624w = {(w_anode624w[2] & w_data462w[2]), (w_anode624w[1] & (~ w_data462w[1])), (w_anode624w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode634w = {(w_anode634w[2] & w_data462w[2]), (w_anode634w[1] & (~ w_data462w[1])), (w_anode634w[0] & w_data462w[0]), w_anode571w[3]},
w_anode644w = {(w_anode644w[2] & w_data462w[2]), (w_anode644w[1] & w_data462w[1]), (w_anode644w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode654w = {(w_anode654w[2] & w_data462w[2]), (w_anode654w[1] & w_data462w[1]), (w_anode654w[0] & w_data462w[0]), w_anode571w[3]},
w_anode665w = {(w_anode665w[2] & (~ data_wire[5])), (w_anode665w[1] & data_wire[4]), (w_anode665w[0] & (~ data_wire[3])), 1'b1},
w_anode677w = {(w_anode677w[2] & (~ w_data462w[2])), (w_anode677w[1] & (~ w_data462w[1])), (w_anode677w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode688w = {(w_anode688w[2] & (~ w_data462w[2])), (w_anode688w[1] & (~ w_data462w[1])), (w_anode688w[0] & w_data462w[0]), w_anode665w[3]},
w_anode698w = {(w_anode698w[2] & (~ w_data462w[2])), (w_anode698w[1] & w_data462w[1]), (w_anode698w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode708w = {(w_anode708w[2] & (~ w_data462w[2])), (w_anode708w[1] & w_data462w[1]), (w_anode708w[0] & w_data462w[0]), w_anode665w[3]},
w_anode718w = {(w_anode718w[2] & w_data462w[2]), (w_anode718w[1] & (~ w_data462w[1])), (w_anode718w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode728w = {(w_anode728w[2] & w_data462w[2]), (w_anode728w[1] & (~ w_data462w[1])), (w_anode728w[0] & w_data462w[0]), w_anode665w[3]},
w_anode738w = {(w_anode738w[2] & w_data462w[2]), (w_anode738w[1] & w_data462w[1]), (w_anode738w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode748w = {(w_anode748w[2] & w_data462w[2]), (w_anode748w[1] & w_data462w[1]), (w_anode748w[0] & w_data462w[0]), w_anode665w[3]},
w_anode759w = {(w_anode759w[2] & (~ data_wire[5])), (w_anode759w[1] & data_wire[4]), (w_anode759w[0] & data_wire[3]), 1'b1},
w_anode771w = {(w_anode771w[2] & (~ w_data462w[2])), (w_anode771w[1] & (~ w_data462w[1])), (w_anode771w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode782w = {(w_anode782w[2] & (~ w_data462w[2])), (w_anode782w[1] & (~ w_data462w[1])), (w_anode782w[0] & w_data462w[0]), w_anode759w[3]},
w_anode792w = {(w_anode792w[2] & (~ w_data462w[2])), (w_anode792w[1] & w_data462w[1]), (w_anode792w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode802w = {(w_anode802w[2] & (~ w_data462w[2])), (w_anode802w[1] & w_data462w[1]), (w_anode802w[0] & w_data462w[0]), w_anode759w[3]},
w_anode812w = {(w_anode812w[2] & w_data462w[2]), (w_anode812w[1] & (~ w_data462w[1])), (w_anode812w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode822w = {(w_anode822w[2] & w_data462w[2]), (w_anode822w[1] & (~ w_data462w[1])), (w_anode822w[0] & w_data462w[0]), w_anode759w[3]},
w_anode832w = {(w_anode832w[2] & w_data462w[2]), (w_anode832w[1] & w_data462w[1]), (w_anode832w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode842w = {(w_anode842w[2] & w_data462w[2]), (w_anode842w[1] & w_data462w[1]), (w_anode842w[0] & w_data462w[0]), w_anode759w[3]},
w_anode853w = {(w_anode853w[2] & data_wire[5]), (w_anode853w[1] & (~ data_wire[4])), (w_anode853w[0] & (~ data_wire[3])), 1'b1},
w_anode865w = {(w_anode865w[2] & (~ w_data462w[2])), (w_anode865w[1] & (~ w_data462w[1])), (w_anode865w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode876w = {(w_anode876w[2] & (~ w_data462w[2])), (w_anode876w[1] & (~ w_data462w[1])), (w_anode876w[0] & w_data462w[0]), w_anode853w[3]},
w_anode886w = {(w_anode886w[2] & (~ w_data462w[2])), (w_anode886w[1] & w_data462w[1]), (w_anode886w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode896w = {(w_anode896w[2] & (~ w_data462w[2])), (w_anode896w[1] & w_data462w[1]), (w_anode896w[0] & w_data462w[0]), w_anode853w[3]},
w_anode906w = {(w_anode906w[2] & w_data462w[2]), (w_anode906w[1] & (~ w_data462w[1])), (w_anode906w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode916w = {(w_anode916w[2] & w_data462w[2]), (w_anode916w[1] & (~ w_data462w[1])), (w_anode916w[0] & w_data462w[0]), w_anode853w[3]},
w_anode926w = {(w_anode926w[2] & w_data462w[2]), (w_anode926w[1] & w_data462w[1]), (w_anode926w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode936w = {(w_anode936w[2] & w_data462w[2]), (w_anode936w[1] & w_data462w[1]), (w_anode936w[0] & w_data462w[0]), w_anode853w[3]},
w_anode947w = {(w_anode947w[2] & data_wire[5]), (w_anode947w[1] & (~ data_wire[4])), (w_anode947w[0] & data_wire[3]), 1'b1},
w_anode959w = {(w_anode959w[2] & (~ w_data462w[2])), (w_anode959w[1] & (~ w_data462w[1])), (w_anode959w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode970w = {(w_anode970w[2] & (~ w_data462w[2])), (w_anode970w[1] & (~ w_data462w[1])), (w_anode970w[0] & w_data462w[0]), w_anode947w[3]},
w_anode980w = {(w_anode980w[2] & (~ w_data462w[2])), (w_anode980w[1] & w_data462w[1]), (w_anode980w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode990w = {(w_anode990w[2] & (~ w_data462w[2])), (w_anode990w[1] & w_data462w[1]), (w_anode990w[0] & w_data462w[0]), w_anode947w[3]},
w_data462w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_32_decode
//synthesis_resources = lut 72 mux21 32
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32_altecc_decoder
(
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input [38:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [31:0] q;
wire [63:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [31:0] data_t;
wire [38:0] data_wire;
wire [63:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [18:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire parity_bit;
wire [37:0] parity_final_wire;
wire [5:0] parity_t;
wire [31:0] q_wire;
wire syn_bit;
wire syn_e;
wire [4:0] syn_t;
wire [6:0] syndrome;
alt_mem_ddrx_ecc_decoder_32_decode error_bit_decoder
(
.data(syndrome[5:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[6] == 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0];
assign wire_mux21_1_dataout = (syndrome[6] == 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1];
assign wire_mux21_10_dataout = (syndrome[6] == 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10];
assign wire_mux21_11_dataout = (syndrome[6] == 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11];
assign wire_mux21_12_dataout = (syndrome[6] == 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12];
assign wire_mux21_13_dataout = (syndrome[6] == 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13];
assign wire_mux21_14_dataout = (syndrome[6] == 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14];
assign wire_mux21_15_dataout = (syndrome[6] == 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15];
assign wire_mux21_16_dataout = (syndrome[6] == 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16];
assign wire_mux21_17_dataout = (syndrome[6] == 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17];
assign wire_mux21_18_dataout = (syndrome[6] == 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18];
assign wire_mux21_19_dataout = (syndrome[6] == 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19];
assign wire_mux21_2_dataout = (syndrome[6] == 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2];
assign wire_mux21_20_dataout = (syndrome[6] == 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20];
assign wire_mux21_21_dataout = (syndrome[6] == 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21];
assign wire_mux21_22_dataout = (syndrome[6] == 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22];
assign wire_mux21_23_dataout = (syndrome[6] == 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23];
assign wire_mux21_24_dataout = (syndrome[6] == 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24];
assign wire_mux21_25_dataout = (syndrome[6] == 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25];
assign wire_mux21_26_dataout = (syndrome[6] == 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26];
assign wire_mux21_27_dataout = (syndrome[6] == 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27];
assign wire_mux21_28_dataout = (syndrome[6] == 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28];
assign wire_mux21_29_dataout = (syndrome[6] == 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29];
assign wire_mux21_3_dataout = (syndrome[6] == 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3];
assign wire_mux21_30_dataout = (syndrome[6] == 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30];
assign wire_mux21_31_dataout = (syndrome[6] == 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31];
assign wire_mux21_4_dataout = (syndrome[6] == 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4];
assign wire_mux21_5_dataout = (syndrome[6] == 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5];
assign wire_mux21_6_dataout = (syndrome[6] == 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6];
assign wire_mux21_7_dataout = (syndrome[6] == 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7];
assign wire_mux21_8_dataout = (syndrome[6] == 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8];
assign wire_mux21_9_dataout = (syndrome[6] == 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9];
assign
data_bit = data_t[31],
data_t = {(data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2] | decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[32]},
parity_02_wire = {(data_wire[31] ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[33] ^ data_wire[0])},
parity_03_wire = {(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[34] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[35] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {(((((((((((((((data_wire[36] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[37] ^ data_wire[26])},
parity_bit = parity_t[5],
parity_final_wire = {(data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^ parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[38] ^ data_wire[0])},
parity_t = {(parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[4],
syn_e = syndrome[6],
syn_t = {(syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome = {parity_final_wire[37], parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[18]};
endmodule //alt_mem_ddrx_ecc_decoder_32_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32 (
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input [38:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [31:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [31:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [31:0] q = sub_wire3[31:0];
alt_mem_ddrx_ecc_decoder_32_altecc_decoder alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component (
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: data 0 0 39 0 INPUT NODEFVAL "data[38..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @data 0 0 39 0 data 0 0 39 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_64.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:08:18:21:16:35:SJ cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=128 LPM_WIDTH=7 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
//synthesis_resources = lut 144
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [6:0] data;
output [127:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire enable_wire1;
wire enable_wire2;
wire [127:0] eq_node;
wire [63:0] eq_wire1;
wire [63:0] eq_wire2;
wire [3:0] w_anode1006w;
wire [3:0] w_anode1018w;
wire [3:0] w_anode1029w;
wire [3:0] w_anode1040w;
wire [3:0] w_anode1050w;
wire [3:0] w_anode1060w;
wire [3:0] w_anode1070w;
wire [3:0] w_anode1080w;
wire [3:0] w_anode1090w;
wire [3:0] w_anode1100w;
wire [3:0] w_anode1111w;
wire [3:0] w_anode1122w;
wire [3:0] w_anode1133w;
wire [3:0] w_anode1143w;
wire [3:0] w_anode1153w;
wire [3:0] w_anode1163w;
wire [3:0] w_anode1173w;
wire [3:0] w_anode1183w;
wire [3:0] w_anode1193w;
wire [3:0] w_anode1204w;
wire [3:0] w_anode1215w;
wire [3:0] w_anode1226w;
wire [3:0] w_anode1236w;
wire [3:0] w_anode1246w;
wire [3:0] w_anode1256w;
wire [3:0] w_anode1266w;
wire [3:0] w_anode1276w;
wire [3:0] w_anode1286w;
wire [3:0] w_anode1297w;
wire [3:0] w_anode1308w;
wire [3:0] w_anode1319w;
wire [3:0] w_anode1329w;
wire [3:0] w_anode1339w;
wire [3:0] w_anode1349w;
wire [3:0] w_anode1359w;
wire [3:0] w_anode1369w;
wire [3:0] w_anode1379w;
wire [3:0] w_anode1390w;
wire [3:0] w_anode1401w;
wire [3:0] w_anode1412w;
wire [3:0] w_anode1422w;
wire [3:0] w_anode1432w;
wire [3:0] w_anode1442w;
wire [3:0] w_anode1452w;
wire [3:0] w_anode1462w;
wire [3:0] w_anode1472w;
wire [3:0] w_anode1483w;
wire [3:0] w_anode1494w;
wire [3:0] w_anode1505w;
wire [3:0] w_anode1515w;
wire [3:0] w_anode1525w;
wire [3:0] w_anode1535w;
wire [3:0] w_anode1545w;
wire [3:0] w_anode1555w;
wire [3:0] w_anode1565w;
wire [3:0] w_anode1576w;
wire [3:0] w_anode1587w;
wire [3:0] w_anode1598w;
wire [3:0] w_anode1608w;
wire [3:0] w_anode1618w;
wire [3:0] w_anode1628w;
wire [3:0] w_anode1638w;
wire [3:0] w_anode1648w;
wire [3:0] w_anode1658w;
wire [3:0] w_anode1670w;
wire [3:0] w_anode1681w;
wire [3:0] w_anode1698w;
wire [3:0] w_anode1708w;
wire [3:0] w_anode1718w;
wire [3:0] w_anode1728w;
wire [3:0] w_anode1738w;
wire [3:0] w_anode1748w;
wire [3:0] w_anode1758w;
wire [3:0] w_anode1770w;
wire [3:0] w_anode1781w;
wire [3:0] w_anode1792w;
wire [3:0] w_anode1802w;
wire [3:0] w_anode1812w;
wire [3:0] w_anode1822w;
wire [3:0] w_anode1832w;
wire [3:0] w_anode1842w;
wire [3:0] w_anode1852w;
wire [3:0] w_anode1863w;
wire [3:0] w_anode1874w;
wire [3:0] w_anode1885w;
wire [3:0] w_anode1895w;
wire [3:0] w_anode1905w;
wire [3:0] w_anode1915w;
wire [3:0] w_anode1925w;
wire [3:0] w_anode1935w;
wire [3:0] w_anode1945w;
wire [3:0] w_anode1956w;
wire [3:0] w_anode1967w;
wire [3:0] w_anode1978w;
wire [3:0] w_anode1988w;
wire [3:0] w_anode1998w;
wire [3:0] w_anode2008w;
wire [3:0] w_anode2018w;
wire [3:0] w_anode2028w;
wire [3:0] w_anode2038w;
wire [3:0] w_anode2049w;
wire [3:0] w_anode2060w;
wire [3:0] w_anode2071w;
wire [3:0] w_anode2081w;
wire [3:0] w_anode2091w;
wire [3:0] w_anode2101w;
wire [3:0] w_anode2111w;
wire [3:0] w_anode2121w;
wire [3:0] w_anode2131w;
wire [3:0] w_anode2142w;
wire [3:0] w_anode2153w;
wire [3:0] w_anode2164w;
wire [3:0] w_anode2174w;
wire [3:0] w_anode2184w;
wire [3:0] w_anode2194w;
wire [3:0] w_anode2204w;
wire [3:0] w_anode2214w;
wire [3:0] w_anode2224w;
wire [3:0] w_anode2235w;
wire [3:0] w_anode2246w;
wire [3:0] w_anode2257w;
wire [3:0] w_anode2267w;
wire [3:0] w_anode2277w;
wire [3:0] w_anode2287w;
wire [3:0] w_anode2297w;
wire [3:0] w_anode2307w;
wire [3:0] w_anode2317w;
wire [3:0] w_anode2328w;
wire [3:0] w_anode2339w;
wire [3:0] w_anode2350w;
wire [3:0] w_anode2360w;
wire [3:0] w_anode2370w;
wire [3:0] w_anode2380w;
wire [3:0] w_anode2390w;
wire [3:0] w_anode2400w;
wire [3:0] w_anode2410w;
wire [3:0] w_anode912w;
wire [3:0] w_anode929w;
wire [3:0] w_anode946w;
wire [3:0] w_anode956w;
wire [3:0] w_anode966w;
wire [3:0] w_anode976w;
wire [3:0] w_anode986w;
wire [3:0] w_anode996w;
wire [2:0] w_data1669w;
wire [2:0] w_data910w;
assign
data_wire = data[5:0],
enable_wire1 = (~ data[6]),
enable_wire2 = data[6],
eq = eq_node,
eq_node = {eq_wire2[63:0], eq_wire1},
eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_data1669w = data_wire[2:0],
w_data910w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_64_decode
//synthesis_resources = lut 144 mux21 64
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_altecc_decoder
(
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome;
alt_mem_ddrx_ecc_decoder_64_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0];
assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1];
assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10];
assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11];
assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12];
assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13];
assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14];
assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15];
assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16];
assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17];
assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18];
assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19];
assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2];
assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20];
assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21];
assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22];
assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23];
assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24];
assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25];
assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26];
assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27];
assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28];
assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29];
assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3];
assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30];
assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31];
assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_wire[32]) : data_wire[32];
assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_wire[33]) : data_wire[33];
assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_wire[34]) : data_wire[34];
assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_wire[35]) : data_wire[35];
assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_wire[36]) : data_wire[36];
assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_wire[37]) : data_wire[37];
assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_wire[38]) : data_wire[38];
assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_wire[39]) : data_wire[39];
assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4];
assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_wire[40]) : data_wire[40];
assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_wire[41]) : data_wire[41];
assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_wire[42]) : data_wire[42];
assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_wire[43]) : data_wire[43];
assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_wire[44]) : data_wire[44];
assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_wire[45]) : data_wire[45];
assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_wire[46]) : data_wire[46];
assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_wire[47]) : data_wire[47];
assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_wire[48]) : data_wire[48];
assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_wire[49]) : data_wire[49];
assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5];
assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_wire[50]) : data_wire[50];
assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_wire[51]) : data_wire[51];
assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_wire[52]) : data_wire[52];
assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_wire[53]) : data_wire[53];
assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_wire[54]) : data_wire[54];
assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_wire[55]) : data_wire[55];
assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_wire[56]) : data_wire[56];
assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_wire[57]) : data_wire[57];
assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_wire[58]) : data_wire[58];
assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_wire[59]) : data_wire[59];
assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6];
assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_wire[60]) : data_wire[60];
assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_wire[61]) : data_wire[61];
assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_wire[62]) : data_wire[62];
assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_wire[63]) : data_wire[63];
assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7];
assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8];
assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9];
assign
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule //alt_mem_ddrx_ecc_decoder_64_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64 (
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [63:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [63:0] q = sub_wire3[63:0];
alt_mem_ddrx_ecc_decoder_64_altecc_decoder alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_syn.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_encoder_32.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data q
//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final;
wire [37:0] parity_final_wire;
reg [37:0] parity_final_reg;
wire [37:0] q_wire;
reg [37:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
(data_wire[31] ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_final_wire = {
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[37] ^ parity_final[36]),
(q_reg[36] ^ parity_final[35]),
(q_reg[35] ^ parity_final[34]),
(q_reg[34] ^ parity_final[33]),
(q_reg[33] ^ parity_final[32]),
(q_reg[32] ^ parity_final[31]),
parity_final_reg[31 : 0]
},
q = {parity_final[37], q_reg},
q_wire = {parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
generate
if (CFG_ECC_ENC_REG)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_32_altecc_encoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32 #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v TRUE
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_encoder_64.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data q
//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [63:0] data;
output [71:0] q;
wire [63:0] data_wire;
wire [34:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire [70:0] parity_final;
wire [70:0] parity_final_wire;
reg [70:0] parity_final_reg;
wire [70:0] q_wire;
reg [70:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[63] ^ parity_01_wire[33]),
(data_wire[61] ^ parity_01_wire[32]),
(data_wire[59] ^ parity_01_wire[31]),
(data_wire[57] ^ parity_01_wire[30]),
(data_wire[56] ^ parity_01_wire[29]),
(data_wire[54] ^ parity_01_wire[28]),
(data_wire[52] ^ parity_01_wire[27]),
(data_wire[50] ^ parity_01_wire[26]),
(data_wire[48] ^ parity_01_wire[25]),
(data_wire[46] ^ parity_01_wire[24]),
(data_wire[44] ^ parity_01_wire[23]),
(data_wire[42] ^ parity_01_wire[22]),
(data_wire[40] ^ parity_01_wire[21]),
(data_wire[38] ^ parity_01_wire[20]),
(data_wire[36] ^ parity_01_wire[19]),
(data_wire[34] ^ parity_01_wire[18]),
(data_wire[32] ^ parity_01_wire[17]),
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]),
((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]),
((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]),
((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]),
((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]),
((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]),
((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]),
((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]),
((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]),
((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]),
((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]),
((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]),
((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]),
((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]),
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]),
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[56] ^ parity_06_wire[29]),
(data_wire[55] ^ parity_06_wire[28]),
(data_wire[54] ^ parity_06_wire[27]),
(data_wire[53] ^ parity_06_wire[26]),
(data_wire[52] ^ parity_06_wire[25]),
(data_wire[51] ^ parity_06_wire[24]),
(data_wire[50] ^ parity_06_wire[23]),
(data_wire[49] ^ parity_06_wire[22]),
(data_wire[48] ^ parity_06_wire[21]),
(data_wire[47] ^ parity_06_wire[20]),
(data_wire[46] ^ parity_06_wire[19]),
(data_wire[45] ^ parity_06_wire[18]),
(data_wire[44] ^ parity_06_wire[17]),
(data_wire[43] ^ parity_06_wire[16]),
(data_wire[42] ^ parity_06_wire[15]),
(data_wire[41] ^ parity_06_wire[14]),
(data_wire[40] ^ parity_06_wire[13]),
(data_wire[39] ^ parity_06_wire[12]),
(data_wire[38] ^ parity_06_wire[11]),
(data_wire[37] ^ parity_06_wire[10]),
(data_wire[36] ^ parity_06_wire[9]),
(data_wire[35] ^ parity_06_wire[8]),
(data_wire[34] ^ parity_06_wire[7]),
(data_wire[33] ^ parity_06_wire[6]),
(data_wire[32] ^ parity_06_wire[5]),
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_07_wire = {
(data_wire[63] ^ parity_07_wire[5]),
(data_wire[62] ^ parity_07_wire[4]),
(data_wire[61] ^ parity_07_wire[3]),
(data_wire[60] ^ parity_07_wire[2]),
(data_wire[59] ^ parity_07_wire[1]),
(data_wire[58] ^ parity_07_wire[0]),
data_wire[57]
},
parity_final_wire = {
(q_wire[70] ^ parity_final_wire[69]),
(q_wire[69] ^ parity_final_wire[68]),
(q_wire[68] ^ parity_final_wire[67]),
(q_wire[67] ^ parity_final_wire[66]),
(q_wire[66] ^ parity_final_wire[65]),
(q_wire[65] ^ parity_final_wire[64]),
(q_wire[64] ^ parity_final_wire[63]),
(q_wire[63] ^ parity_final_wire[62]),
(q_wire[62] ^ parity_final_wire[61]),
(q_wire[61] ^ parity_final_wire[60]),
(q_wire[60] ^ parity_final_wire[59]),
(q_wire[59] ^ parity_final_wire[58]),
(q_wire[58] ^ parity_final_wire[57]),
(q_wire[57] ^ parity_final_wire[56]),
(q_wire[56] ^ parity_final_wire[55]),
(q_wire[55] ^ parity_final_wire[54]),
(q_wire[54] ^ parity_final_wire[53]),
(q_wire[53] ^ parity_final_wire[52]),
(q_wire[52] ^ parity_final_wire[51]),
(q_wire[51] ^ parity_final_wire[50]),
(q_wire[50] ^ parity_final_wire[49]),
(q_wire[49] ^ parity_final_wire[48]),
(q_wire[48] ^ parity_final_wire[47]),
(q_wire[47] ^ parity_final_wire[46]),
(q_wire[46] ^ parity_final_wire[45]),
(q_wire[45] ^ parity_final_wire[44]),
(q_wire[44] ^ parity_final_wire[43]),
(q_wire[43] ^ parity_final_wire[42]),
(q_wire[42] ^ parity_final_wire[41]),
(q_wire[41] ^ parity_final_wire[40]),
(q_wire[40] ^ parity_final_wire[39]),
(q_wire[39] ^ parity_final_wire[38]),
(q_wire[38] ^ parity_final_wire[37]),
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[70] ^ parity_final[69]),
(q_reg[69] ^ parity_final[68]),
(q_reg[68] ^ parity_final[67]),
(q_reg[67] ^ parity_final[66]),
(q_reg[66] ^ parity_final[65]),
(q_reg[65] ^ parity_final[64]),
parity_final_reg [64 : 0]
},
q = {parity_final[70], q_reg},
q_wire = {parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[34], data_wire};
generate
if (CFG_ECC_ENC_REG)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_64_altecc_encoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_64 #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [63:0] data;
output [71:0] q;
wire [71:0] sub_wire0;
wire [71:0] q = sub_wire0[71:0];
alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
alt_mem_ddrx_ecc_encoder_64_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_syn.v TRUE
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
CFG_LOCAL_DATA_WIDTH = 80,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_ENC_REG = 0,
CFG_ECC_DEC_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_interface_width,
cfg_enable_ecc,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// Wdata & Rdata Interface Inputs
wdatap_dm,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// AFI Interface Inputs
afi_rdata,
afi_rdata_valid,
// Wdata & Rdata Interface Outputs
ecc_rdata,
ecc_rdata_valid,
// AFI Inteface Outputs
ecc_dm,
ecc_wdata,
// ECC Error Information
ecc_sbe,
ecc_dbe,
ecc_code,
ecc_interrupt,
// MMR ECC Information
sts_sbe_error,
sts_dbe_error,
sts_sbe_count,
sts_dbe_count,
sts_err_addr,
sts_corr_dropped,
sts_corr_dropped_count,
sts_corr_dropped_addr
);
//--------------------------------------------------------------------------------------------------------
//
// Important Note:
//
// This block is coded with the following consideration in mind
// - Parameter
// - maximum LOCAL_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - maximum ECC_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - MMR configuration
// - ECC option disabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (40 * DWIDTH_RATIO)
// - WDATAP_DATA and ECC_DATA size will match (no ECC code)
// - ECC option enabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (32 * DWIDTH_RATIO)
// - WDATAP_DATA width will be (8 * DWIDTH_RATIO) lesser than ECC_DATA (ECC code)
//
// Block level diagram
// -----------------------------------
// Write Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// Local Write Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 32 bits ---->| Encoder |---- 40 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//
// -----------------------------------
// Read Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// AFI Read Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 40 bits ---->| Decoder |---- 32 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//--------------------------------------------------------------------------------------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_LOCAL_DM_PER_WORD_WIDTH = CFG_LOCAL_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DATA_PER_WORD_WIDTH = CFG_ECC_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DM_PER_WORD_WIDTH = CFG_ECC_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_LOCAL_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam CFG_MMR_LOCAL_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
// The following 2 parameters should match!
localparam CFG_ENCODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
localparam CFG_DECODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
// Wdata & Rdata Interface Inputs
input [CFG_LOCAL_DM_WIDTH - 1 : 0] wdatap_dm;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
input wdatap_rmw_partial;
input wdatap_rmw_correct;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
input [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
input rdatap_rcvd_cmd;
input rdatap_rcvd_corr_dropped;
// AFI Interface Inputs
input [CFG_ECC_DATA_WIDTH - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Wdata & Rdata Interface Outputs
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
output ecc_rdata_valid;
// AFI Inteface Outputs
output [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
output [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
// ECC Error Information
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
output ecc_interrupt;
// MMR ECC Information
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output registers
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
reg ecc_rdata_valid;
reg [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
reg ecc_interrupt;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// Common
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
reg [CFG_MMR_LOCAL_DM_WIDTH - 1 : 0] cfg_local_dm_width;
// Input Logic
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_correct_data;
reg int_encoder_input_rmw_partial;
reg int_encoder_input_rmw_correct;
reg wdatap_rmw_partial_r;
reg wdatap_rmw_correct_r;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg int_decoder_input_data_valid;
// Output Logic
reg [CFG_ECC_MULTIPLES - 1 : 0] int_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_dbe;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm_r;
wire [CFG_ECC_MULTIPLES - 1 : 0] int_decoder_output_data_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data_r;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_decoder_output_data;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] int_ecc_code;
// ECC specific logic
reg [1 : 0] inject_data_error;
reg int_sbe_detected;
reg int_dbe_detected;
wire int_be_detected;
reg int_sbe_store;
reg int_dbe_store;
reg int_sbe_valid;
reg int_dbe_valid;
reg int_sbe_valid_r;
reg int_dbe_valid_r;
reg int_ecc_interrupt;
wire int_interruptable_error_detected;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] int_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] int_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] int_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] int_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_err_addr ;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] int_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] int_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_corr_dropped_addr ;
reg int_corr_dropped_detected;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// DRAM and local data width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_data_width <= 0;
end
else
begin
// Important note, if we set memory interface width (DQ width) to 8 and enable_ecc to 1,
// this will result in local data width of 0, this case is not supported
// this must be checked with assertion so that this case will not happen in regression
if (cfg_enable_ecc)
begin
cfg_local_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;
end
else
begin
cfg_local_data_width <= cfg_interface_width;
end
end
end
//----------------------------------------------------------------------------------------------------
// DRAM and local be width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_dm_width <= 0;
end
else
begin
cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_rmw_partial_r <= 1'b0;
wdatap_rmw_correct_r <= 1'b0;
end
else
begin
wdatap_rmw_partial_r <= wdatap_rmw_partial;
wdatap_rmw_correct_r <= wdatap_rmw_correct;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_encoder_output_data_r <= 0;
int_encoder_output_dm_r <= 0;
end
else
begin
int_encoder_output_data_r <= int_encoder_output_data;
int_encoder_output_dm_r <= int_encoder_output_dm;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [ENC] Common
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable from wdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_encoder_input_data = wdatap_data;
int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
if (CFG_ECC_ENC_REG)
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
end
else
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial;
int_encoder_input_rmw_correct = wdatap_rmw_correct;
end
end
generate
genvar i_drate;
for (i_drate = 0;i_drate < CFG_ECC_MULTIPLES;i_drate = i_drate + 1)
begin : encoder_input_dm_mux_per_dm_drate
wire [CFG_LOCAL_DM_PER_WORD_WIDTH-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * CFG_LOCAL_DM_PER_WORD_WIDTH - 1 : i_drate * CFG_LOCAL_DM_PER_WORD_WIDTH];
wire int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
always @ (*)
begin
if (cfg_enable_ecc)
begin
if (int_encoder_input_dm_all_zeros)
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b1}},int_encoder_input_dm};
end
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Read data & read data valid from AFI
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_decoder_input_data = afi_rdata;
end
always @ (*)
begin
int_decoder_input_data_valid = afi_rdata_valid [0];
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable to AFI interface
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_wdata = int_encoder_output_data;
end
always @ (*)
begin
if (CFG_ECC_ENC_REG)
begin
ecc_dm = int_encoder_output_dm_r;
end
else
begin
ecc_dm = int_encoder_output_dm;
end
end
//----------------------------------------------------------------------------------------------------
// Read data to rdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_rdata = int_decoder_output_data;
end
always @ (*)
begin
ecc_rdata_valid = |int_decoder_output_data_valid;
end
//----------------------------------------------------------------------------------------------------
// ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_sbe = int_sbe;
else
ecc_sbe = 0;
end
// Double bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_dbe = int_dbe;
else
ecc_dbe = 0;
end
// ECC code
always @ (*)
begin
if (cfg_enable_ecc)
ecc_code = int_ecc_code;
else
ecc_code = 0;
end
// Interrupt signal
always @ (*)
begin
ecc_interrupt = int_ecc_interrupt;
end
//----------------------------------------------------------------------------------------------------
// MMR ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
sts_sbe_error = int_sbe_error;
end
// Double bit error
always @ (*)
begin
sts_dbe_error = int_dbe_error;
end
// Single bit error count
always @ (*)
begin
sts_sbe_count = int_sbe_count;
end
// Double bit error count
always @ (*)
begin
sts_dbe_count = int_dbe_count;
end
// Error address
always @ (*)
begin
sts_err_addr = int_err_addr;
end
// Correctable Error dropped
always @ (*)
begin
sts_corr_dropped = int_corr_dropped;
end
// Single bit error count
always @ (*)
begin
sts_corr_dropped_count = int_corr_dropped_count;
end
// Correctable Error dropped address
always @ (*)
begin
sts_corr_dropped_addr = int_corr_dropped_addr;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Encoder
//----------------------------------------------------------------------------------------------------
generate
genvar m_drate;
for (m_drate = 0;m_drate < CFG_ECC_MULTIPLES;m_drate = m_drate + 1)
begin : encoder_inst_per_drate
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_partial_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_correct_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code = wdatap_ecc_code [(m_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : m_drate * CFG_ECC_CODE_WIDTH];
wire input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_partial_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_correct_data;
always @ (*)
begin
if (int_encoder_input_rmw_partial)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_partial_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else if (int_encoder_input_rmw_correct)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_correct_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_data [1 : 0] ^ inject_data_error [1 : 0])};
end
end
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_partial_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_partial_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_rmw_partial_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_correct_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_correct_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (input_ecc_code_overwrite ),
.output_data (output_rmw_correct_data )
);
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Decoder
//----------------------------------------------------------------------------------------------------
generate
genvar n_drate;
for (n_drate = 0;n_drate < CFG_ECC_MULTIPLES;n_drate = n_drate + 1)
begin : decoder_inst_per_drate
wire err_corrected;
wire err_detected;
wire err_fatal;
wire err_sbe;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_DECODER_DATA_WIDTH - CFG_ECC_DATA_PER_WORD_WIDTH{1'b0}}, int_decoder_input_data [(n_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_ECC_DATA_PER_WORD_WIDTH]};
wire input_data_valid = int_decoder_input_data_valid;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] output_data;
wire output_data_valid;
wire [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
assign int_decoder_output_data [(n_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH] = output_data [CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0];
assign int_ecc_code [(n_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : n_drate * CFG_ECC_CODE_WIDTH ] = output_ecc_code;
assign int_decoder_output_data_valid [n_drate] = output_data_valid;
alt_mem_ddrx_ecc_decoder #
(
.CFG_DATA_WIDTH (CFG_DECODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
decoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_data_valid (input_data_valid ),
.output_data (output_data ),
.output_data_valid (output_data_valid ),
.output_ecc_code (output_ecc_code ),
.err_corrected (err_corrected ),
.err_detected (err_detected ),
.err_fatal (err_fatal ),
.err_sbe (err_sbe )
);
// Error detection
always @ (*)
begin
if (err_detected || err_sbe)
begin
if (err_corrected || err_sbe)
begin
int_sbe [n_drate] = 1'b1;
int_dbe [n_drate] = 1'b0;
end
else if (err_fatal)
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b1;
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common Logic
//----------------------------------------------------------------------------------------------------
// Below information valid on same clock, when rdatap_rcvd_cmd is asserted (at end of every dram command)
// - int_sbe_detected
// - int_dbe_detected
// - int_be_detected
// - int_corr_dropped_detected
// - rdatap_rcvd_addr
//
// see SPR:362993
always @ (*)
begin
int_sbe_valid = |int_sbe & ecc_rdata_valid;
int_dbe_valid = |int_dbe & ecc_rdata_valid;
int_sbe_detected = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
int_dbe_detected = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
int_corr_dropped_detected = rdatap_rcvd_corr_dropped;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_sbe_valid_r <= 0;
int_dbe_valid_r <= 0;
int_sbe_store <= 0;
int_dbe_store <= 0;
end
else
begin
int_sbe_valid_r <= int_sbe_valid;
int_dbe_valid_r <= int_dbe_valid;
int_sbe_store <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
int_dbe_store <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
end
end
//----------------------------------------------------------------------------------------------------
// Error Innjection Logic
//----------------------------------------------------------------------------------------------------
// Data error injection, this will cause output data to be injected with single/double bit error
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
inject_data_error <= 0;
end
else
begin
// Put DBE 1st so that when user sets both gen_sbe and gen_dbe, DBE will have higher priority
if (cfg_gen_dbe)
inject_data_error <= 2'b11;
else if (cfg_gen_sbe)
inject_data_error <= 2'b01;
else
inject_data_error <= 2'b00;
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_sbe_detected)
int_sbe_error <= 1'b1;
else if (cfg_clr_intr)
int_sbe_error <= 1'b0;
end
else
begin
int_sbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_sbe_detected)
int_sbe_count <= 1;
else
int_sbe_count <= 0;
else if (int_sbe_detected)
int_sbe_count <= int_sbe_count + 1'b1;
end
else
begin
int_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_dbe_detected)
int_dbe_error <= 1'b1;
else if (cfg_clr_intr)
int_dbe_error <= 1'b0;
end
else
begin
int_dbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_dbe_detected)
int_dbe_count <= 1;
else
int_dbe_count <= 0;
else if (int_dbe_detected)
int_dbe_count <= int_dbe_count + 1'b1;
end
else
begin
int_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_err_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_be_detected)
int_err_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_err_addr <= 0;
end
else
begin
int_err_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped <= 1'b1;
else if (cfg_clr_intr)
int_corr_dropped <= 1'b0;
end
else
begin
int_corr_dropped <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_corr_dropped_detected)
int_corr_dropped_count <= 1;
else
int_corr_dropped_count <= 0;
else if (int_corr_dropped_detected)
int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
end
else
begin
int_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROP_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_corr_dropped_addr <= 0;
end
else
begin
int_corr_dropped_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Interrupt logic
//----------------------------------------------------------------------------------------------------
assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
assign int_be_detected = int_sbe_detected | int_dbe_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_interrupt <= 1'b0;
end
else
begin
if (cfg_enable_ecc && cfg_enable_intr)
begin
if (int_interruptable_error_detected)
int_ecc_interrupt <= 1'b1;
else if (cfg_clr_intr)
int_ecc_interrupt <= 1'b0;
end
else
begin
int_ecc_interrupt <= 1'b0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_fifo
# (
parameter
CTL_FIFO_DATA_WIDTH = 8,
CTL_FIFO_ADDR_WIDTH = 3
)
(
// general
ctl_clk,
ctl_reset_n,
// pop free fifo entry
get_valid,
get_ready,
get_data,
// push free fifo entry
put_valid,
put_ready,
put_data
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_FIFO_DEPTH = (2 ** CTL_FIFO_ADDR_WIDTH);
localparam CTL_FIFO_TYPE = "SCFIFO"; // SCFIFO, CUSTOM
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free fifo entry
input get_ready;
output get_valid;
output [CTL_FIFO_DATA_WIDTH-1:0] get_data;
// push free fifo entry
output put_ready;
input put_valid;
input [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// port type declaration
// -----------------------------
wire get_valid;
wire get_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] get_data;
wire put_valid;
wire put_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_FIFO_DATA_WIDTH-1:0] fifo [CTL_FIFO_DEPTH-1:0];
reg [CTL_FIFO_DEPTH-1:0] fifo_v;
wire fifo_get;
wire fifo_put;
wire fifo_empty;
wire fifo_full;
wire zero;
// -----------------------------
// module definition
// -----------------------------
assign fifo_get = get_valid & get_ready;
assign fifo_put = put_valid & put_ready;
assign zero = 1'b0;
generate
begin : gen_fifo_instance
if (CTL_FIFO_TYPE == "SCFIFO")
begin
assign get_valid = ~fifo_empty;
assign put_ready = ~fifo_full;
scfifo #(
.add_ram_output_register ( "ON" ),
.intended_device_family ( "Stratix IV" ),
.lpm_numwords ( CTL_FIFO_DEPTH ),
.lpm_showahead ( "ON" ),
.lpm_type ( "scfifo" ),
.lpm_width ( CTL_FIFO_DATA_WIDTH ),
.lpm_widthu ( CTL_FIFO_ADDR_WIDTH ),
.overflow_checking ( "OFF" ),
.underflow_checking ( "OFF" ),
.use_eab ( "ON" )
) scfifo_component (
.aclr (~ctl_reset_n),
.clock (ctl_clk),
.data (put_data),
.rdreq (fifo_get),
.wrreq (fifo_put),
.empty (fifo_empty),
.full (fifo_full),
.q (get_data),
.almost_empty (),
.almost_full (),
.sclr (zero),
.usedw ()
);
end
else // CTL_FIFO_TYPE == "CUSTOM"
begin
assign get_valid = fifo_v[0];
assign put_ready = ~fifo_v[CTL_FIFO_DEPTH-1];
assign get_data = fifo[0];
// put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
// initialize every entry
fifo [i] <= 0;
fifo_v [i] <= 1'b0;
end
end
else
begin
// get request code must be above put request code
if (fifo_get)
begin
// on a get request, fifo entry is shifted to move next entry to head
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
fifo_v [i-1] <= fifo_v [i];
fifo [i-1] <= fifo [i];
end
fifo_v [CTL_FIFO_DEPTH-1] <= 0;
end
if (fifo_put)
begin
// on a put request, next empty fifo entry is written
if (~fifo_get)
begin
// put request only
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i] <= 1'b1;
fifo [i] <= put_data;
end
end
if (~fifo_v[0])
begin
fifo_v [0] <= 1'b1;
fifo [0] <= put_data;
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i-1] <= 1'b1;
fifo [i-1] <= put_data;
end
end
if (~fifo_v[0])
begin
$display("error - fifo underflow");
end
end
end
end
end
end
end
endgenerate
endmodule
//
// ASSERT
//
// fifo underflow
//
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_input_if
#(parameter
CFG_LOCAL_DATA_WIDTH = 64,
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_MEM_IF_CHIP = 1,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL"
)
(
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early,
itf_rd_data_id_early_valid,
// command generator
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
cmd_id,
// write data path
wr_data_mem_full,
write_data_id,
write_data,
byte_en,
write_data_valid,
// read data path
read_data,
read_data_valid,
read_data_error,
read_data_localid,
read_data_begin,
read_data_last,
//side band
local_refresh_req,
local_refresh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
bg_do_read,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_localid,
rfsh_req,
rfsh_chip,
deep_powerdn_req,
deep_powerdn_chip,
self_rfsh_req,
self_rfsh_chip,
rfsh_ack,
deep_powerdn_ack,
power_down_ack,
self_rfsh_ack,
init_done
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
// command channel
output itf_cmd_ready;
input [CFG_LOCAL_ADDR_WIDTH-1:0] itf_cmd_address;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
// read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// command generator
input cmd_gen_full;
output cmd_valid;
output [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
output cmd_write;
output cmd_read;
output cmd_multicast;
output [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
output cmd_priority;
output cmd_autoprecharge;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
// write data path
output [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
output [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
output write_data_valid;
input wr_data_mem_full;
output [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
// read data path
input [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
input read_data_valid;
input read_data_error;
input [CFG_LOCAL_ID_WIDTH-1:0]read_data_localid;
input read_data_begin;
input read_data_last;
//side band
input local_refresh_req;
input [CFG_MEM_IF_CHIP-1:0] local_refresh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
//side band
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output deep_powerdn_req;
output [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output self_rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
input rfsh_ack;
input deep_powerdn_ack;
input power_down_ack;
input self_rfsh_ack;
input init_done;
// command generator
wire cmd_priority;
wire [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
wire cmd_read;
wire cmd_write;
wire cmd_multicast;
wire cmd_gen_full;
wire cmd_valid;
wire itf_cmd_ready;
wire cmd_autoprecharge;
wire [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
//side band
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
wire self_rfsh_req;
//wire rfsh_ack;
//wire deep_powerdn_ack;
wire power_down_ack;
//wire self_rfsh_ack;
// wire init_done;
//write data path
wire itf_wr_data_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire write_data_valid;
wire [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
wire [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
//read data path
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
// commmand generator
assign cmd_priority = itf_cmd_priority;
assign cmd_address = itf_cmd_address;
assign cmd_multicast = itf_cmd_multicast;
assign cmd_size = itf_cmd_burstlen;
assign cmd_autoprecharge = itf_cmd_autopercharge;
assign cmd_id = itf_cmd_id;
// side band
assign rfsh_req = local_refresh_req;
assign rfsh_chip = local_refresh_chip;
assign deep_powerdn_req = local_deep_powerdn_req;
assign deep_powerdn_chip = local_deep_powerdn_chip;
assign self_rfsh_req = local_self_rfsh_req;
assign self_rfsh_chip = local_self_rfsh_chip;
assign local_refresh_ack = rfsh_ack;
assign local_deep_powerdn_ack = deep_powerdn_ack;
assign local_power_down_ack = power_down_ack;
assign local_self_rfsh_ack = self_rfsh_ack;
assign local_init_done = init_done;
//write data path
assign write_data = itf_wr_data;
assign byte_en = itf_wr_data_byte_en;
assign write_data_valid = itf_wr_data_valid;
assign write_data_id = itf_wr_data_id;
// read data path
assign itf_rd_data_id = read_data_localid;
assign itf_rd_data_error = read_data_error;
assign itf_rd_data_valid = read_data_valid;
assign itf_rd_data_begin = read_data_begin;
assign itf_rd_data_last = read_data_last;
assign itf_rd_data = read_data;
assign itf_rd_data_id_early = (itf_rd_data_id_early_valid) ? bg_localid : {CFG_LOCAL_ID_WIDTH{1'b0}};
//==============================================================================
// Logic below is to tie low itf_cmd_ready, itf_cmd_valid and itf_wr_data_ready when local_init_done is low
assign itf_cmd_ready = ~cmd_gen_full & local_init_done;
assign itf_wr_data_ready = ~wr_data_mem_full & local_init_done;
assign cmd_read = ~itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_write = itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_valid = itf_cmd_valid & local_init_done;
generate
begin : gen_rd_data_id_early_valid
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_LOW_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_LOW_PHASE]|bg_do_rmw_partial[AFI_INTF_LOW_PHASE]);
end
else
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_HIGH_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_HIGH_PHASE]|bg_do_rmw_partial[AFI_INTF_HIGH_PHASE]);
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
CTL_LIST_WIDTH = 3, // number of dram commands that can be tracked at a time
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR", // INCR, ZERO
CTL_LIST_INIT_VALID = "VALID" // VALID, INVALID
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
// initialize every entry
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : LPDDR2 controller address and command decoder
//
// File : alt_mem_ddrx_lpddr2_addr_cmd.v
//
// Abstract : LPDDR2 Address and command decoder
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_lpddr2_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 20,
CFG_MEM_IF_ROW_WIDTH = 15, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_output_regd,
// AFI interface (Signals from Arbiter block)
do_write,
do_read,
do_auto_precharge,
do_activate,
do_precharge,
do_precharge_all,
do_refresh,
do_self_refresh,
do_power_down,
do_lmr,
do_lmr_read, //Currently does not exist in arbiter
do_refresh_1bank, //Currently does not exist in arbiter
do_burst_terminate, //Currently does not exist in arbiter
do_deep_pwrdwn, //Currently does not exist in arbiter
// address information
to_chip, // active high input (one hot)
to_bank,
to_row,
to_col,
to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_addr,
afi_rst_n
);
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
// Arbiter command inputs
input do_write;
input do_read;
input do_auto_precharge;
input do_activate;
input do_precharge;
input [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] do_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_power_down;
input [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
input do_lmr;
input do_lmr_read;
input do_refresh_1bank;
input do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] to_col;
input [7:0] to_lmr;
input [7:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
wire do_write;
wire do_read;
wire do_auto_precharge;
wire do_activate;
wire do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
wire do_lmr;
wire do_lmr_read;
wire do_refresh_1bank;
wire do_burst_terminate;
reg [2:0] temp_bank_addr;
reg [14:0] temp_row_addr;
reg [11:0] temp_col_addr;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r;
reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh;
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
generate
if (CFG_DWIDTH_RATIO == 2) begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_addr = int_addr;
end
else begin
assign afi_cke = {int_cke,int_cke};
assign afi_cs_n = (do_burst_terminate)? {int_cs_n,int_cs_n} :{int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
// need half rate code to adjust for half rate cke or cs
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode or DPD
begin
if (!ctl_reset_n)
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
else
if ((do_self_refresh) || (do_deep_pwrdwn))
chip_in_self_refresh <= do_self_refresh | do_deep_pwrdwn;
else
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
combi_cke_r <= {CFG_MEM_IF_CKE_WIDTH{1'b1}} ;
combi_cs_n_r <= {CFG_MEM_IF_CHIP{1'b1}} ;
combi_addr_r <= {CFG_MEM_IF_ADDR_WIDTH{1'b0}};
end
else
begin
combi_cke_r <= combi_cke ;
combi_cs_n_r <= combi_cs_n ;
combi_addr_r <= combi_addr ;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_addr = combi_addr;
end
end
always @ (*)
begin
temp_row_addr = {CFG_MEM_IF_ROW_WIDTH{1'b0}} ;
temp_col_addr = {CFG_MEM_IF_COL_WIDTH{1'b0}} ;
temp_bank_addr = {CFG_MEM_IF_BA_WIDTH {1'b0}} ;
temp_row_addr = to_row ;
temp_col_addr = to_col ;
temp_bank_addr = to_bank;
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(do_self_refresh | do_power_down | do_deep_pwrdwn);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
always @(*)
begin
if (ctl_cal_success)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|do_refresh)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~do_refresh;
combi_addr[3:0] = 4'b1100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_refresh_1bank)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if ((|do_precharge_all) || do_precharge)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~ (do_precharge_all|do_precharge);
combi_addr[3:0] = 4'b1011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,2'b00,(|do_precharge_all)};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_activate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = {temp_row_addr[9:8],2'b10};
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_row_addr[12:10]};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_row_addr[14:13],temp_row_addr[7:0]};
end
if (do_write)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0001;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (do_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0101;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (|do_power_down)
begin
//combi_cke = ~do_power_down;
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_deep_pwrdwn)
begin
//combi_cke = ~do_deep_pwrdwn;
combi_cs_n = ~do_deep_pwrdwn; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_self_refresh)
begin
//combi_cke = ~do_self_refresh;
combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_lmr)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],lmr_opcode};
end
if (do_lmr_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b1000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],{8{1'b0}}};
end
if (do_burst_terminate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
end
else
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_DATA_WIDTH/8-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr ;
assign itf_cmd_burstlen = avl_size ;
assign itf_cmd_autopercharge = local_autopch_req ;
assign itf_cmd_priority = local_priority ;
assign itf_cmd_multicast = local_multicast ;
assign itf_cmd = avl_write_req;
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req : itf_cmd_ready & avl_write_req;
assign itf_wr_data = avl_wdata ;
assign itf_wr_data_byte_en = avl_be ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid;
assign avl_rdata = itf_rd_data;
assign local_rdata_error = itf_rd_data_error;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
burst_counter <= avl_size - 1;
else if (avl_write_req && itf_wr_data_ready)
burst_counter <= burst_counter - 1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
data_pass <= 1;
else if (burst_counter == 1 && avl_write_req && itf_wr_data_ready)
data_pass <= 0;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_odt_gen
#( parameter
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_CHIP = 2, //one_hot
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_CAS_WR_LAT = 4,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4
)
(
ctl_clk,
ctl_reset_n,
//Configuration Interface
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd,
//Arbiter Interface
bg_do_read,
bg_do_write,
bg_do_burst_chop,
bg_to_chip, //one_hot
//AFI Interface
afi_odt
);
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
//Input from Configuration Interface
input [CFG_PORT_WIDTH_TYPE -1:0] cfg_type;
input [CFG_PORT_WIDTH_TCL -1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT -1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT -1:0] cfg_add_lat;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP -1:0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP -1:0] cfg_read_odt_chip;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
//Inputs from Arbiter Interface
input bg_do_read;
input bg_do_write;
input bg_do_burst_chop;
input [CFG_MEM_IF_CHIP -1:0] bg_to_chip;
//Output to AFI Interface
output [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2))-1:0] afi_odt;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire [CFG_MEM_IF_ODT_WIDTH-1:0] write_odt_chip [CFG_MEM_IF_CHIP-1:0];
wire [CFG_MEM_IF_ODT_WIDTH-1:0] read_odt_chip [CFG_MEM_IF_CHIP-1:0];
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr2_odt_l;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr2_odt_h;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_l;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_h;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_i_1;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_i_2;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_l;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_h;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_i_1;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_i_2;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_write_odt_chip;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_read_odt_chip;
integer i;
//=================================================================================================//
// cfg_write_odt_chip & cfg_read_odt_chip definition //
//=================================================================================================//
/*
DDR3
four chip selects odt scheme, for two ranks per dimm configuration
.---------------------------------------++---------------------------------------.
| write to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || 1 | | 1 | | //cfg_write_odt_chip[0] = 4'b0101; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | 1 | | 1 | //cfg_write_odt_chip[1] = 4'b1010; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | 1 | | //cfg_write_odt_chip[2] = 4'b0101; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | 1 | //cfg_write_odt_chip[3] = 4'b1010; //chip[3] -> chip[0]
'---------+---------+---------+---------++---------+---------+---------+---------'
.---------------------------------------++---------------------------------------.
| read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | | //cfg_read_odt_chip[0] = 4'b0100; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 | //cfg_read_odt_chip[1] = 4'b1000; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | | //cfg_read_odt_chip[2] = 4'b0001; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | | //cfg_read_odt_chip[3] = 4'b0010; //chip[3] -> chip[0]
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
/*
DDR2
four or more chip selects odt scheme, assumes two ranks per dimm
.---------------------------------------++---------------------------------------.
| write/read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 || chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | |
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
//Unpack read/write_odt_chip array into per chip array
generate
genvar a;
begin : unpack_odt_config
for (a=0; a<CFG_MEM_IF_CHIP; a=a+1)
begin : unpack_odt_config_per_chip
assign write_odt_chip[a] = cfg_write_odt_chip [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
assign read_odt_chip[a] = cfg_read_odt_chip [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
end
end
endgenerate
always @(*)
begin
int_write_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_read_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
if (bg_to_chip[i])
begin
int_write_odt_chip = write_odt_chip[i];
int_read_odt_chip = read_odt_chip[i];
end
end
end
//=================================================================================================//
// Instantiate DDR2 ODT generation Block //
//=================================================================================================//
generate
genvar b;
for (b=0; b<CFG_MEM_IF_ODT_WIDTH; b=b+1)
begin : ddr2_odt_gen
alt_mem_ddrx_ddr2_odt_gen
# (
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL)
)
alt_mem_ddrx_ddr2_odt_gen_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.cfg_tcl (cfg_tcl),
.cfg_add_lat (cfg_add_lat),
.cfg_burst_length (cfg_burst_length),
.cfg_output_regd (cfg_output_regd),
.bg_do_write (bg_do_write & int_write_odt_chip[b]),
.bg_do_read (bg_do_read & int_read_odt_chip[b]),
.int_odt_l (ddr2_odt_l[b]),
.int_odt_h (ddr2_odt_h[b])
);
end
endgenerate
//=================================================================================================//
// Instantiate DDR3 ODT generation Block //
//=================================================================================================//
generate
genvar c;
for (c=0; c<CFG_MEM_IF_ODT_WIDTH; c=c+1)
begin : ddr3_odt_gen
alt_mem_ddrx_ddr3_odt_gen
# (
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT)
)
alt_mem_ddrx_ddr3_odt_gen_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.cfg_tcl (cfg_tcl),
.cfg_cas_wr_lat (cfg_cas_wr_lat),
.cfg_output_regd (cfg_output_regd),
.bg_do_write (bg_do_write & int_write_odt_chip[c]),
.bg_do_read (bg_do_read & int_read_odt_chip[c]),
.bg_do_burst_chop (bg_do_burst_chop),
.int_odt_l (ddr3_odt_l[c]),
.int_odt_h (ddr3_odt_h[c]),
.int_odt_i_1 (ddr3_odt_i_1[c]),
.int_odt_i_2 (ddr3_odt_i_2[c])
);
end
endgenerate
//=================================================================================================//
// ODT Output generation based on memory type and ODT feature turned ON or not //
//=================================================================================================//
always @(*)
begin
if (cfg_type == `MMR_TYPE_DDR2)
begin
int_odt_l = ddr2_odt_l;
int_odt_h = ddr2_odt_h;
int_odt_i_1 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_i_2 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
end
else if (cfg_type == `MMR_TYPE_DDR3)
begin
int_odt_l = ddr3_odt_l;
int_odt_h = ddr3_odt_h;
int_odt_i_1 = ddr3_odt_i_1;
int_odt_i_2 = ddr3_odt_i_2;
end
else
begin
int_odt_l = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_h = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_i_1 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_i_2 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
end
end
generate
if (CFG_ODT_ENABLED == 1)
begin
if (CFG_DWIDTH_RATIO == 2) // quarter rate
assign afi_odt = int_odt_l;
else if (CFG_DWIDTH_RATIO == 4) // half rate
assign afi_odt = {int_odt_h,int_odt_l};
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
assign afi_odt = {int_odt_h,int_odt_i_2, int_odt_i_1, int_odt_l};
end
else
assign afi_odt = {(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)){1'b0}};
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
module alt_mem_ddrx_rank_timer #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_REG_GRANT = 0,
CFG_RANK_TIMER_OUTPUT_REG = 0,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 0,
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 0,
T_PARAM_WR_TO_WR_WIDTH = 0,
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 0,
T_PARAM_WR_TO_RD_WIDTH = 0,
T_PARAM_WR_TO_RD_BC_WIDTH = 0,
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_RD_WIDTH = 0,
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_WR_WIDTH = 0,
T_PARAM_RD_TO_WR_BC_WIDTH = 0,
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Configurations
cfg_burst_length,
// Timing parameters
t_param_four_act_to_act,
t_param_act_to_act_diff_bank,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
// Arbiter Interface
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_activate,
bg_do_precharge,
bg_to_chip,
bg_effective_size,
bg_interrupt_ready,
// Command Generator Interface
cmd_gen_chipsel,
// TBP Interface
tbp_chipsel,
tbp_load,
// Sideband Interface
stall_chip,
can_activate,
can_precharge,
can_read,
can_write
);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
input [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
input [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
input [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
input [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
input [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
input [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
input [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
input [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
input [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
input [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
input [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
input bg_interrupt_ready;
input [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
input [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
output [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
output [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
output [CFG_CTL_TBP_NUM - 1 : 0] can_read;
output [CFG_CTL_TBP_NUM - 1 : 0] can_write;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
localparam RANK_TIMER_TFAW_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
localparam ENABLE_BETTER_TRRD_EFFICIENCY = 1; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
wire one = 1'b1;
wire zero = 1'b0;
// Timing Parameter Comparison Logic
reg less_than_1_act_to_act_diff_bank;
reg less_than_2_act_to_act_diff_bank;
reg less_than_3_act_to_act_diff_bank;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
reg less_than_1_rd_to_rd;
reg less_than_1_rd_to_wr;
reg less_than_1_wr_to_wr;
reg less_than_1_wr_to_rd;
reg less_than_1_rd_to_wr_bc;
reg less_than_1_wr_to_rd_bc;
reg less_than_1_rd_to_rd_diff_chip;
reg less_than_1_rd_to_wr_diff_chip;
reg less_than_1_wr_to_wr_diff_chip;
reg less_than_1_wr_to_rd_diff_chip;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_wr_to_rd_bc;
reg less_than_2_rd_to_rd_diff_chip;
reg less_than_2_rd_to_wr_diff_chip;
reg less_than_2_wr_to_wr_diff_chip;
reg less_than_2_wr_to_rd_diff_chip;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_wr_to_rd_bc;
reg less_than_3_rd_to_rd_diff_chip;
reg less_than_3_rd_to_wr_diff_chip;
reg less_than_3_wr_to_wr_diff_chip;
reg less_than_3_wr_to_rd_diff_chip;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_wr_to_rd_bc;
reg less_than_4_rd_to_rd_diff_chip;
reg less_than_4_rd_to_wr_diff_chip;
reg less_than_4_wr_to_wr_diff_chip;
reg less_than_4_wr_to_rd_diff_chip;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_wr_to_rd_bc;
reg more_than_3_rd_to_rd_diff_chip;
reg more_than_3_rd_to_wr_diff_chip;
reg more_than_3_wr_to_wr_diff_chip;
reg more_than_3_wr_to_rd_diff_chip;
reg less_than_xn1_act_to_act_diff_bank;
reg less_than_xn1_rd_to_rd;
reg less_than_xn1_rd_to_wr;
reg less_than_xn1_wr_to_wr;
reg less_than_xn1_wr_to_rd;
reg less_than_xn1_rd_to_wr_bc;
reg less_than_xn1_wr_to_rd_bc;
reg less_than_xn1_rd_to_rd_diff_chip;
reg less_than_xn1_rd_to_wr_diff_chip;
reg less_than_xn1_wr_to_wr_diff_chip;
reg less_than_xn1_wr_to_rd_diff_chip;
reg less_than_x0_act_to_act_diff_bank;
reg less_than_x0_rd_to_rd;
reg less_than_x0_rd_to_wr;
reg less_than_x0_wr_to_wr;
reg less_than_x0_wr_to_rd;
reg less_than_x0_rd_to_wr_bc;
reg less_than_x0_wr_to_rd_bc;
reg less_than_x0_rd_to_rd_diff_chip;
reg less_than_x0_rd_to_wr_diff_chip;
reg less_than_x0_wr_to_wr_diff_chip;
reg less_than_x0_wr_to_rd_diff_chip;
reg less_than_x1_act_to_act_diff_bank;
reg less_than_x1_rd_to_rd;
reg less_than_x1_rd_to_wr;
reg less_than_x1_wr_to_wr;
reg less_than_x1_wr_to_rd;
reg less_than_x1_rd_to_wr_bc;
reg less_than_x1_wr_to_rd_bc;
reg less_than_x1_rd_to_rd_diff_chip;
reg less_than_x1_rd_to_wr_diff_chip;
reg less_than_x1_wr_to_wr_diff_chip;
reg less_than_x1_wr_to_rd_diff_chip;
// Input
reg int_do_activate;
reg int_do_precharge;
reg int_do_burst_chop;
reg int_do_burst_terminate;
reg int_do_write;
reg int_do_read;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_r;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_c;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_interrupt_ready;
// Activate Monitor
localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
localparam ACTIVATE_COMMAND_WIDTH = 3;
localparam NUM_OF_TFAW_SHIFT_REG = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_ready;
wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
// Read/Write Monitor
localparam IDLE = 32'h49444C45;
localparam WR = 32'h20205752;
localparam RD = 32'h20205244;
localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] max_local_burst_size;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr_combi;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd_combi;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
reg [CFG_MEM_IF_CHIP - 1 : 0] read_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] write_ready;
// Precharge Monitor
reg [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
// Output
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_write;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] sel_act_tfaw_shift_out_point;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input
//
//--------------------------------------------------------------------------------------------------------
// Do activate
always @ (*)
begin
int_do_activate = |bg_do_activate;
end
// Do precharge
always @ (*)
begin
int_do_precharge = |bg_do_precharge;
end
//Do burst chop
always @ (*)
begin
int_do_burst_chop = |bg_do_burst_chop;
end
//Do burst terminate
always @ (*)
begin
int_do_burst_terminate = |bg_do_burst_terminate;
end
// Do write
always @ (*)
begin
int_do_write = |bg_do_write;
end
// Do read
always @ (*)
begin
int_do_read = |bg_do_read;
end
// To chip
always @ (*)
begin
// _r for row command and _c for column command
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
end
// Effective size
always @ (*)
begin
int_effective_size = bg_effective_size;
end
// Interrupt ready
always @ (*)
begin
int_interrupt_ready = bg_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output
//
//--------------------------------------------------------------------------------------------------------
generate
genvar x_cs;
for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
begin : can_logic_per_chip
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
begin
chip_addr = cmd_gen_chipsel;
end
else
begin
chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
end
end
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
always @ (*)
begin
can_activate [x_cs] = int_can_activate [x_cs] ;
can_precharge [x_cs] = int_can_precharge [x_cs] ;
can_read [x_cs] = int_can_read [x_cs] & int_interrupt_ready;
can_write [x_cs] = int_can_write [x_cs] & int_interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_activate [x_cs] <= 1'b0;
end
else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
int_can_activate [x_cs] <= act_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
int_can_precharge [x_cs] <= pch_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_read [x_cs] <= 1'b0;
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_wr_to_rd_bc)
begin
int_can_read [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_wr_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_rd_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else
begin
int_can_read [x_cs] <= read_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_write [x_cs] <= 1'b0;
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_rd_to_wr_bc)
begin
int_can_write [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_rd_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_wr_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else
begin
int_can_write [x_cs] <= write_ready [chip_addr];
end
end
end
end
else
begin
// Can activate
always @ (*)
begin
can_activate [x_cs] = act_ready [chip_addr];
end
// Can precharge
always @ (*)
begin
can_precharge [x_cs] = pch_ready [chip_addr];
end
// Can read
always @ (*)
begin
can_read [x_cs] = read_ready [chip_addr];
end
// Can write
always @ (*)
begin
can_write [x_cs] = write_ready [chip_addr];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Output
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 1)
less_than_1_act_to_act_diff_bank <= 1'b1;
else
less_than_1_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
if (t_param_four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 1)
less_than_1_rd_to_rd <= 1'b1;
else
less_than_1_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 1)
less_than_1_rd_to_wr <= 1'b1;
else
less_than_1_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 1)
less_than_1_wr_to_wr <= 1'b1;
else
less_than_1_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 1)
less_than_1_wr_to_rd <= 1'b1;
else
less_than_1_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 1)
less_than_1_rd_to_wr_bc <= 1'b1;
else
less_than_1_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 1)
less_than_1_wr_to_rd_bc <= 1'b1;
else
less_than_1_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 1)
less_than_1_rd_to_rd_diff_chip <= 1'b1;
else
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 1)
less_than_1_rd_to_wr_diff_chip <= 1'b1;
else
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 1)
less_than_1_wr_to_wr_diff_chip <= 1'b1;
else
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 1)
less_than_1_wr_to_rd_diff_chip <= 1'b1;
else
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 2)
less_than_2_wr_to_rd_bc <= 1'b1;
else
less_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 2)
less_than_2_rd_to_rd_diff_chip <= 1'b1;
else
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 2)
less_than_2_rd_to_wr_diff_chip <= 1'b1;
else
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 2)
less_than_2_wr_to_wr_diff_chip <= 1'b1;
else
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 2)
less_than_2_wr_to_rd_diff_chip <= 1'b1;
else
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 3)
less_than_3_wr_to_rd_bc <= 1'b1;
else
less_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 3)
less_than_3_rd_to_rd_diff_chip <= 1'b1;
else
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 3)
less_than_3_rd_to_wr_diff_chip <= 1'b1;
else
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 3)
less_than_3_wr_to_wr_diff_chip <= 1'b1;
else
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 3)
less_than_3_wr_to_rd_diff_chip <= 1'b1;
else
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 4)
less_than_4_wr_to_rd_bc <= 1'b1;
else
less_than_4_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 4)
less_than_4_rd_to_rd_diff_chip <= 1'b1;
else
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 4)
less_than_4_rd_to_wr_diff_chip <= 1'b1;
else
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 4)
less_than_4_wr_to_wr_diff_chip <= 1'b1;
else
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 4)
less_than_4_wr_to_rd_diff_chip <= 1'b1;
else
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 3)
more_than_3_wr_to_rd_bc <= 1'b1;
else
more_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 3)
more_than_3_rd_to_rd_diff_chip <= 1'b1;
else
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 3)
more_than_3_rd_to_wr_diff_chip <= 1'b1;
else
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 3)
more_than_3_wr_to_wr_diff_chip <= 1'b1;
else
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 3)
more_than_3_wr_to_rd_diff_chip <= 1'b1;
else
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
generate
begin
if (CFG_REG_GRANT)
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_3_rd_to_rd;
less_than_x0_rd_to_wr = less_than_3_rd_to_wr;
less_than_x0_wr_to_wr = less_than_3_wr_to_wr;
less_than_x0_wr_to_rd = less_than_3_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_4_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_4_rd_to_rd;
less_than_x1_rd_to_wr = less_than_4_rd_to_wr;
less_than_x1_wr_to_wr = less_than_4_wr_to_wr;
less_than_x1_wr_to_rd = less_than_4_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_4_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_4_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_4_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_4_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_4_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_4_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
end
end
else
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_1_rd_to_rd;
less_than_x0_rd_to_wr = less_than_1_rd_to_wr;
less_than_x0_wr_to_wr = less_than_1_wr_to_wr;
less_than_x0_wr_to_rd = less_than_1_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_2_rd_to_rd;
less_than_x1_rd_to_wr = less_than_2_rd_to_wr;
less_than_x1_wr_to_wr = less_than_2_wr_to_wr;
less_than_x1_wr_to_rd = less_than_2_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Activate Monitor
//
// Monitors the following rank timing parameters:
//
// - tFAW, four activate window, only four activate is allowed in a specific timing window
// - tRRD, activate to activate different bank
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sel_act_tfaw_shift_out_point <= 0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
end
else
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
end
end
end
generate
genvar t_cs;
genvar t_tfaw;
for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
begin : act_monitor_per_chip
//----------------------------------------------------------------------------------------------------
// tFAW Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
reg [NUM_OF_TFAW_SHIFT_REG - 1 : 0] act_tfaw_shift_reg;
assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
// Shift register to keep track of tFAW
// Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
// Shift in '1' when there is an activate else shift in '0'
// Shift out every clock cycles
// Shift register [3]
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [3] <= 1'b0;
end
else
begin
// Shift in '1' if there is an activate
// else shift in '0'
if (int_do_activate && int_to_chip_r [t_cs])
act_tfaw_shift_reg [3] <= 1'b1;
else
act_tfaw_shift_reg [3] <= 1'b0;
end
end
// Shift register [n : 3]
for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
begin : tfaw_shift_register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [t_tfaw] <= 1'b0;
end
else
begin
act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
end
end
end
// Activate command counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_cmd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
else
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
end
else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
end
end
// tFAW ready signal
always @ (*)
begin
// If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
if (less_than_4_four_act_to_act)
begin
act_tfaw_ready_combi [t_cs] = 1'b1;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
act_tfaw_ready_combi [t_cs] = 1'b0;
else if (act_tfaw_cmd_cnt < 3'd4)
act_tfaw_ready_combi [t_cs] = 1'b1;
else
act_tfaw_ready_combi [t_cs] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_ready [t_cs] <= 1'b0;
end
else
begin
act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// tRRD Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
// tRRD counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
end
else
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
end
end
else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
begin
act_trrd_cnt <= act_trrd_cnt + 1'b1;
end
end
end
// tRRD monitor
always @ (*)
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_ready [t_cs] <= 1'b0;
end
else
begin
act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// Overall activate ready
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
begin
act_ready [t_cs] = 1'b0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
end
else
begin
act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Activate Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read/Write Monitor
//
// Monitors the following rank timing parameters:
//
// - Write to read timing parameter (tWTR)
// - Read to write timing parameter
//
// Missing Features:
//
// - Burst interrupt
// - Burst terminate
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Effective Timing Parameters
// Only when burst interrupt option is enabled
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
effective_rd_to_wr <= 0;
effective_rd_to_wr_diff_chip <= 0;
effective_wr_to_rd <= 0;
effective_wr_to_rd_diff_chip <= 0;
end
else
begin
if (int_do_burst_chop)
begin
effective_rd_to_wr <= t_param_rd_to_wr_bc;
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip;
effective_wr_to_rd <= t_param_wr_to_rd_bc;
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip;
end
else if (int_do_burst_terminate)
begin
if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
effective_rd_to_wr <= t_param_rd_to_wr - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr <= 1'b1;
if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_diff_chip <= 1'b1;
if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
effective_wr_to_rd <= t_param_wr_to_rd - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd <= 1'b1;
if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_diff_chip <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Read / Write State Machine
//----------------------------------------------------------------------------------------------------
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : rdwr_monitor_per_chip
reg [31 : 0] rdwr_state;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
reg int_do_read_this_chip;
reg int_do_write_this_chip;
reg int_do_read_diff_chip;
reg int_do_write_diff_chip;
reg doing_burst_chop;
reg doing_burst_terminate;
reg int_read_ready;
reg int_write_ready;
// Do read/write to this/different chip
always @ (*)
begin
if (int_do_read)
begin
if (int_to_chip_c [s_cs])
begin
int_do_read_this_chip = 1'b1;
int_do_read_diff_chip = 1'b0;
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b1;
end
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b0;
end
end
always @ (*)
begin
if (int_do_write)
begin
if (int_to_chip_c [s_cs])
begin
int_do_write_this_chip = 1'b1;
int_do_write_diff_chip = 1'b0;
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b1;
end
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b0;
end
end
// Read write counter to this chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_this_chip <= 0;
write_cnt_this_chip <= 0;
end
else
begin
if (int_do_read_this_chip)
read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
if (int_do_write_this_chip)
write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
end
end
// Read write counter to different chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_diff_chip <= 0;
write_cnt_diff_chip <= 0;
end
else
begin
if (int_do_read_diff_chip)
read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
if (int_do_write_diff_chip)
write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
end
end
// Doing burst chop signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
begin
if (int_do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
// Doing burst terminate signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
doing_burst_terminate <= 1'b0;
else if (int_do_burst_terminate)
doing_burst_terminate <= 1'b1;
end
end
// Register comparison logic for better fMAX
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (less_than_x1_rd_to_rd)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (less_than_x1_rd_to_wr)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (less_than_x1_rd_to_rd_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (less_than_x1_rd_to_wr_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (less_than_x1_wr_to_wr)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (less_than_x1_wr_to_rd)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (less_than_x1_wr_to_wr_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (less_than_x1_wr_to_rd_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (effective_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (effective_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
// Read write monitor state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b0;
int_write_ready <= 1'b0;
end
else
begin
case (rdwr_state)
IDLE :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b1;
int_write_ready <= 1'b1;
end
end
WR :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
RD :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
default :
rdwr_state <= IDLE;
endcase
end
end
// Assign read/write ready signal to top
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
begin
read_ready [s_cs] = 1'b0;
write_ready [s_cs] = 1'b0;
end
else
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
read_ready [s_cs] = int_read_ready;
write_ready [s_cs] = int_write_ready;
end
else
begin
read_ready [s_cs] = int_read_ready & int_interrupt_ready;
write_ready [s_cs] = int_write_ready & int_interrupt_ready;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Read/Write Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : pch_monitor_per_chip
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
pch_ready [u_cs] = 1'b0;
else
pch_ready [u_cs] = one;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
module alt_mem_ddrx_rdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 2,
CFG_DATA_ID_WIDTH = 3, // number of buckets
CFG_LOCAL_ID_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_BUFFER_ADDR_WIDTH = 5,
CFG_MEM_IF_CS_WIDTH = 2,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_MAX_READ_CMD_NUM_WIDTH = 4, // expected in-flight read commands at a time
CFG_RDATA_RETURN_MODE = "PASSTHROUGH", // INORDER, PASSTHROUGH
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ERRCMD_FIFO_ADDR_WIDTH = 3,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 9,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 12,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration
cfg_type,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_burst_length,
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// command generator & TBP command load interface / cmd update interface
rdatap_free_id_valid,
rdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_read,
proc_size,
proc_localid,
// input interface data channel / buffer read interface
read_data_valid, // data sent to either dataid_manager, or input interface
read_data,
read_data_error,
read_data_localid,
// Arbiter issued reads interface
bg_do_read,
bg_to_chipsel,
bg_to_bank,
bg_to_row,
bg_to_column,
bg_dataid,
bg_localid,
bg_size,
bg_do_rmw_correct,
bg_do_rmw_partial,
// read data from memory interface
ecc_rdata,
ecc_rdatav,
ecc_sbe,
ecc_dbe,
ecc_code,
// ECC Error commands interface, to command generator
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
// ECC Error address interface, to ECC block
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// RMW fifo interface, to wdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_ECC_RDATA_COUNTER_REG = 0; // set to 1 to improve timing
localparam CFG_RMW_BIT_WIDTH = 1;
localparam CFG_RMW_PARTIAL_BIT_WIDTH = 1;
localparam CFG_PENDING_RD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_DATA_ID_WIDTH + CFG_RMW_BIT_WIDTH + CFG_RMW_PARTIAL_BIT_WIDTH;
localparam CFG_ERRCMD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_INT_SIZE_WIDTH + CFG_LOCAL_ID_WIDTH;
localparam CFG_INORDER_INFO_FIFO_WIDTH = CFG_INT_SIZE_WIDTH+CFG_LOCAL_ID_WIDTH;
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam CFG_RDATA_ERROR_WIDTH = 1;
localparam CFG_IN_ORDER_BUFFER_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RDATA_ERROR_WIDTH;
localparam CFG_MAX_READ_CMD_NUM = 2**CFG_MAX_READ_CMD_NUM_WIDTH;
localparam MIN_COL = 8;
localparam MIN_ROW = 12;
localparam MIN_BANK = 2;
localparam MIN_CS = 1;
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam CFG_IGNORE_NUM_BITS_COL = log2 (CFG_DWIDTH_RATIO);
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2 (CFG_LOCAL_ADDR_WIDTH);
integer j,k,m,n;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM-1:0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
output rdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_read;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
input [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
output read_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
output read_data_error;
output [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
input [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
input [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
input [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
// read data from memory interface
input [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
input ecc_rdatav;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
input errcmd_ready;
output errcmd_valid;
output [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
output [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
output [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// ECC Error address interface, to ECC block
output [CFG_LOCAL_ADDR_WIDTH-1:0] rdatap_rcvd_addr;
output rdatap_rcvd_cmd;
output rdatap_rcvd_corr_dropped;
// RMW fifo interface, to wdatap
output rmwfifo_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
output [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// configuration
wire [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
wire [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
reg rdatap_free_id_valid;
reg [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
reg read_data_valid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
reg read_data_error;
reg [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
wire [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
wire [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
wire [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH -1:0] int_bg_to_chipsel[CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_column [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_DATA_ID_WIDTH -1:0] int_bg_dataid;
reg [CFG_LOCAL_ID_WIDTH -1:0] int_bg_localid;
reg [CFG_INT_SIZE_WIDTH -1:0] int_bg_size;
// read data from memory interface
wire [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
wire ecc_rdatav;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// RMW fifo interface, to wdatap
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
reg rdatap_rcvd_cmd;
reg rdatap_rcvd_corr_dropped;
// -----------------------------
// signal declaration
// -----------------------------
wire[CFG_INT_SIZE_WIDTH-1:0] cfg_max_cmd_burstcount;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_row;
wire cmdload_valid;
reg [CFG_MAX_READ_CMD_NUM_WIDTH-1:0] cmd_counter;
reg cmd_counter_full;
wire cmd_counter_load;
wire free_id_get_ready;
wire free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0]free_id_dataid_vector;
wire allocated_put_ready;
wire allocated_put_valid;
wire int_free_id_valid;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_input;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_output;
wire pfifo_output_valid;
wire pfifo_input_ready;
wire rdata_burst_complete;
reg rdata_burst_complete_r;
reg rout_data_valid; // rout_data sent to dataid_manager
reg rout_cmd_valid; // rout_cmd sent to dataid_manager
reg rout_data_rmwfifo_valid; // rout_data sent to rmwfifo
reg rout_cmd_rmwfifo_valid; // rout_cmd sent to rmwfifo
wire rout_rmw_rmwpartial;
reg rout_data_error;
reg rout_sbecmd_valid;
reg rout_errnotify_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rout_data;
wire [CFG_DATA_ID_WIDTH-1:0] rout_data_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] rout_data_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] rout_data_burstcount;
wire [CFG_ECC_MULTIPLES- 1 : 0] rout_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rout_ecc_code;
reg pfifo_input_do_read;
reg pfifo_input_rmw;
reg pfifo_input_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_input_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_input_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_input_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_input_column;
reg [CFG_DATA_ID_WIDTH-1:0] pfifo_input_dataid;
reg [CFG_LOCAL_ID_WIDTH-1:0] pfifo_input_localid;
reg [CFG_INT_SIZE_WIDTH-1:0] pfifo_input_size;
reg mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM -1 : 0];
wire pfifo_rmw;
wire pfifo_rmw_partial;
wire [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel_r;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank_r;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned_r;
wire [CFG_DATA_ID_WIDTH-1:0] pfifo_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] pfifo_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] pfifo_size;
reg [CFG_LOCAL_ADDR_WIDTH-1:0] pfifo_addr;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_current_count;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdatavalid_count;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_burst_complete_count;
reg ecc_sbe_cmd_detected;
reg ecc_dbe_cmd_detected;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_LOCAL_ID_WIDTH-1:0] dataid_array_localid [CFG_DATAID_ARRAY_DEPTH-1:0];
wire inordr_id_data_complete;
reg inordr_id_data_complete_r;
wire inordr_id_valid;
wire inordr_id_list_valid;
wire inordr_read_data_valid;
reg inordr_read_data_valid_r;
wire [CFG_LOCAL_DATA_WIDTH-1:0] inordr_read_data;
wire inordr_read_data_error;
wire [CFG_DATA_ID_WIDTH-1:0] inordr_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] inordr_id_dataid_vector;
wire [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid;
reg [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid_r;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter_plus_1;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_next_data_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_id_expected_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_inordr_data_ready;
wire inordr_info_input_ready;
wire inordr_info_output_valid;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_input;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_output;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffwrite_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffwrite_data;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffread_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffread_data;
wire int_ecc_sbe;
wire int_ecc_dbe;
wire errcmd_fifo_in_cmddropped;
reg errcmd_fifo_in_cmddropped_r;
wire errcmd_fifo_in_ready;
wire errcmd_fifo_in_valid;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_in;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_out;
// -----------------------------
// module definition
// -----------------------------
//
// READ DATA MAIN OUTPUT MUX
//
generate
begin : gen_rdata_output_mux
if (CFG_RDATA_RETURN_MODE == "PASSTHROUGH")
begin
always @ (*)
begin
read_data_valid = rout_data_valid;
read_data = rout_data;
read_data_error = rout_data_error;
read_data_localid = rout_data_localid;
rdatap_free_id_valid = ~cmd_counter_full;
rdatap_free_id_dataid = 0;
end
end
else
begin
always @ (*)
begin
read_data_valid = inordr_read_data_valid_r;
read_data = inordr_read_data;
read_data_error = inordr_read_data_error;
read_data_localid = inordr_id_localid_r;
rdatap_free_id_valid = ~cmd_counter_full & free_id_valid;
rdatap_free_id_dataid = free_id_dataid;
end
end
end
endgenerate
//
// RDATA_ROUTER
//
// mux to select correct burst gen output phase for read command
// assumes bg_do_read only asserted for 1 of the CFG_AFI_INTF_PHASE_NUM
genvar rdp_k;
generate
for (rdp_k = 0; rdp_k < CFG_AFI_INTF_PHASE_NUM; rdp_k = rdp_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_read [rdp_k] = bg_do_read [rdp_k];
int_bg_do_rmw_correct [rdp_k] = bg_do_rmw_correct [rdp_k];
int_bg_do_rmw_partial [rdp_k] = bg_do_rmw_partial [rdp_k];
int_bg_to_chipsel [rdp_k] = bg_to_chipsel [(((rdp_k+1)*CFG_MEM_IF_CS_WIDTH )-1):(rdp_k*CFG_MEM_IF_CS_WIDTH )];
int_bg_to_bank [rdp_k] = bg_to_bank [(((rdp_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(rdp_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [rdp_k] = bg_to_row [(((rdp_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(rdp_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_column [rdp_k] = bg_to_column [(((rdp_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(rdp_k*CFG_MEM_IF_COL_WIDTH)];
end
end
endgenerate
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
end
always @ (*)
begin
mux_pfifo_input_rmw [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_correct [0] : 0;
mux_pfifo_input_rmw_partial [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_partial [0] : 0;
mux_pfifo_input_chipsel [0] = (int_bg_do_read [0]) ? int_bg_to_chipsel [0] : 0;
mux_pfifo_input_bank [0] = (int_bg_do_read [0]) ? int_bg_to_bank [0] : 0;
mux_pfifo_input_row [0] = (int_bg_do_read [0]) ? int_bg_to_row [0] : 0;
mux_pfifo_input_column [0] = (int_bg_do_read [0]) ? int_bg_to_column [0] : 0;
end
genvar rdp_j;
generate
for (rdp_j = 1; rdp_j < CFG_AFI_INTF_PHASE_NUM; rdp_j = rdp_j + 1)
begin : gen_bg_afi_phase_mux
always @ (*)
begin
mux_pfifo_input_rmw [rdp_j] = mux_pfifo_input_rmw [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_correct [rdp_j] : 0);
mux_pfifo_input_rmw_partial [rdp_j] = mux_pfifo_input_rmw_partial [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_partial [rdp_j] : 0);
mux_pfifo_input_chipsel [rdp_j] = mux_pfifo_input_chipsel [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_chipsel [rdp_j] : 0);
mux_pfifo_input_bank [rdp_j] = mux_pfifo_input_bank [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_bank [rdp_j] : 0);
mux_pfifo_input_row [rdp_j] = mux_pfifo_input_row [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_row [rdp_j] : 0);
mux_pfifo_input_column [rdp_j] = mux_pfifo_input_column [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_column [rdp_j] : 0);
end
end
endgenerate
always @ (*)
begin
pfifo_input_do_read = |int_bg_do_read;
pfifo_input_rmw = mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_rmw_partial = mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_chipsel = mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_bank = mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_row = mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_column = mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_dataid = int_bg_dataid ;
pfifo_input_localid = int_bg_localid ;
pfifo_input_size = int_bg_size ;
end
// format for pfifo_input & pfifo_output must be same
assign pfifo_input = {pfifo_input_chipsel, pfifo_input_bank, pfifo_input_row, pfifo_input_column, pfifo_input_localid, pfifo_input_size, pfifo_input_rmw, pfifo_input_rmw_partial, pfifo_input_dataid};
assign {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column, pfifo_localid, pfifo_size, pfifo_rmw, pfifo_rmw_partial, pfifo_dataid} = pfifo_output;
// read data for this command has been fully received from memory
assign rdata_burst_complete = (pfifo_output_valid & (pfifo_size == ecc_rdata_current_count)) ? 1 : 0;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_PENDING_RD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_MAX_READ_CMD_NUM_WIDTH)
)
pending_rd_fifo
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rdata_burst_complete),
.get_valid (pfifo_output_valid),
.get_data (pfifo_output),
.put_ready (pfifo_input_ready), // no back-pressure allowed
.put_valid (pfifo_input_do_read),
.put_data (pfifo_input)
);
assign cmd_counter_load = ~proc_busy & proc_load & proc_read;
assign cmdload_valid = cmd_counter_load & proc_load_dataid;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cmd_counter <= 0;
cmd_counter_full <= 1'b0;
end
else
begin
if (cmd_counter_load & rdata_burst_complete)
begin
cmd_counter <= cmd_counter;
cmd_counter_full <= cmd_counter_full;
end
else if (cmd_counter_load)
begin
cmd_counter <= cmd_counter + 1;
if (cmd_counter == {{(CFG_MAX_READ_CMD_NUM_WIDTH - 1){1'b1}}, 1'b0}) // when cmd counter is counting up to all_ones
begin
cmd_counter_full <= 1'b1;
end
else
begin
cmd_counter_full <= 1'b0;
end
end
else if (rdata_burst_complete)
begin
cmd_counter <= cmd_counter - 1;
cmd_counter_full <= 1'b0;
end
end
end
assign rout_data = ecc_rdata;
assign rout_data_dataid = pfifo_dataid;
assign rout_data_localid = pfifo_localid;
assign rout_data_burstcount = ecc_rdata_current_count;
assign rout_rmw_rmwpartial = (pfifo_rmw | pfifo_rmw_partial);
assign rout_ecc_dbe = ecc_dbe;
assign rout_ecc_code = ecc_code;
always @ (*)
begin
//rout_data_valid = 0;
//rout_cmd_valid = 0;
rout_data_rmwfifo_valid = 0;
rout_cmd_rmwfifo_valid = 0;
rout_sbecmd_valid = 0;
rout_data_error = 0;
rout_errnotify_valid = 0;
if (~cfg_enable_ecc & ~cfg_enable_no_dm)
begin
rout_data_valid = ecc_rdatav;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
end
else
begin
rout_data_rmwfifo_valid = ecc_rdatav & rout_rmw_rmwpartial;
rout_data_valid = ecc_rdatav & ~rout_rmw_rmwpartial;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
rout_cmd_rmwfifo_valid = rout_data_rmwfifo_valid & rdata_burst_complete;
rout_data_error = int_ecc_dbe;
rout_errnotify_valid = ecc_rdatav & ( int_ecc_sbe | int_ecc_dbe );
if (cfg_enable_auto_corr)
begin
rout_sbecmd_valid = rout_cmd_valid & (ecc_sbe_cmd_detected | int_ecc_sbe);
end
end
end
// rmwfifo interface
assign rmwfifo_data_valid = rout_data_rmwfifo_valid;
assign rmwfifo_data = rout_data;
assign rmwfifo_ecc_dbe = rout_ecc_dbe;
assign rmwfifo_ecc_code = rout_ecc_code;
// ecc_sbe_cmd_detected
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else if (int_ecc_sbe)
begin
ecc_sbe_cmd_detected <= 1;
end
else if (int_ecc_dbe)
begin
ecc_dbe_cmd_detected <= 1;
end
end
end
assign int_ecc_sbe = ecc_rdatav & (|ecc_sbe);
assign int_ecc_dbe = ecc_rdatav & (|ecc_dbe);
//
// ECC_RDATA counter
//
assign ecc_rdata_current_count = (CFG_ECC_RDATA_COUNTER_REG) ? ecc_rdata_counter : ecc_rdatavalid_count;
assign ecc_rdatavalid_count = (ecc_rdatav) ? ecc_rdata_counter + 1 : ecc_rdata_counter;
assign ecc_rdata_burst_complete_count = pfifo_size;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_rdata_counter <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_rdata_counter <= ecc_rdatavalid_count - ecc_rdata_burst_complete_count;
end
else
begin
ecc_rdata_counter <= ecc_rdatavalid_count;
end
end
end
assign errcmd_fifo_in_valid = rout_sbecmd_valid;
assign errcmd_fifo_in = {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column_burst_aligned, cfg_max_cmd_burstcount, pfifo_localid};
assign {errcmd_chipsel, errcmd_bank, errcmd_row, errcmd_column, errcmd_size, errcmd_localid} = errcmd_fifo_out;
assign errcmd_fifo_in_cmddropped = ~errcmd_fifo_in_ready & errcmd_fifo_in_valid;
assign cfg_max_cmd_burstcount = (cfg_burst_length / CFG_DWIDTH_RATIO);
// DDR3, pfifo_column_burst_aligned is burst length 8 aligned
// DDR2, pfifo_column is already burst aligned
assign pfifo_column_burst_aligned = (cfg_type == `MMR_TYPE_DDR3) ? {pfifo_column[(CFG_MEM_IF_COL_WIDTH-1):3],{3{1'b0}} } : pfifo_column;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pfifo_chipsel_r <= 0;
pfifo_bank_r <= 0;
pfifo_row_r <= 0;
pfifo_column_r <= 0;
pfifo_column_burst_aligned_r <= 0;
end
else
begin
pfifo_chipsel_r <= pfifo_chipsel ;
pfifo_bank_r <= pfifo_bank ;
pfifo_row_r <= pfifo_row ;
pfifo_column_r <= pfifo_column ;
pfifo_column_burst_aligned_r <= pfifo_column_burst_aligned;
end
end
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_ERRCMD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH)
)
errcmd_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (errcmd_ready),
.get_valid (errcmd_valid),
.get_data (errcmd_fifo_out),
.put_ready (errcmd_fifo_in_ready),
.put_valid (errcmd_fifo_in_valid),
.put_data (errcmd_fifo_in)
);
//
// error address information for MMR's
//
// - rdatap_rcvd_addr, rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped
// - rdatap_rcvd_addr generation takes 1 cycle after an error, so need to register
// rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped to keep in sync, see SPR:362993
//
assign rdatap_rcvd_addr = pfifo_addr;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rdata_burst_complete_r <= 0;
errcmd_fifo_in_cmddropped_r <= 0;
rdatap_rcvd_cmd <= 0;
rdatap_rcvd_corr_dropped <= 0;
end
else
begin
rdata_burst_complete_r <= rdata_burst_complete;
errcmd_fifo_in_cmddropped_r <= errcmd_fifo_in_cmddropped;
rdatap_rcvd_cmd <= rdata_burst_complete;
rdatap_rcvd_corr_dropped <= errcmd_fifo_in_cmddropped;
end
end
// generate local address from chip, bank, row, column addresses
always @(*)
begin : addr_loop
pfifo_addr = 0;
// column
pfifo_addr[MIN_COL - CFG_IGNORE_NUM_BITS_COL - 1 : 0] = pfifo_column_burst_aligned_r[MIN_COL - 1 : CFG_IGNORE_NUM_BITS_COL];
for (n=MIN_COL; n<MAX_COL; n=n+1'b1) begin
if(n < cfg_col_addr_width) begin // bit of col_addr can be configured in CSR using cfg_col_addr_width
pfifo_addr[n - CFG_IGNORE_NUM_BITS_COL] = pfifo_column_burst_aligned_r[n];
end
end
// row
for (j=0; j<MIN_ROW; j=j+1'b1) begin //The purpose of using this for-loop is to get rid of "if(j < cfg_row_addr_width) begin" which causes multiplexers
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
for (j=MIN_ROW; j<MAX_ROW; j=j+1'b1) begin
if(j < cfg_row_addr_width) begin // bit of row_addr can be configured in CSR using cfg_row_addr_width
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
end
// bank
for (k=0; k<MIN_BANK; k=k+1'b1) begin //The purpose of using this for-loop is to get rid of "if(k < cfg_bank_addr_width) begin" which causes multiplexers
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
for (k=MIN_BANK; k<MAX_BANK; k=k+1'b1) begin
if(k < cfg_bank_addr_width) begin // bit of bank_addr can be configured in CSR using cfg_bank_addr_width
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
end
// cs
m = 0;
if (cfg_cs_addr_width > 1'b0) begin //if cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
for (m=0; m<MIN_CS; m=m+1'b1) begin //The purpose of using this for-loop is to get rid of "if(m < cfg_cs_addr_width) begin" which causes multiplexers
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1) begin
if(m < cfg_cs_addr_width) begin // bit of cs_addr can be configured in CSR using cfg_cs_addr_width
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
end
end
end
// pre-calculate pfifo_addr chipsel, bank, row, col bit select offsets
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cfg_addr_bitsel_chipsel <= 0;
cfg_addr_bitsel_bank <= 0;
cfg_addr_bitsel_row <= 0;
end
else
begin
//row
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_row <= cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_row <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_row <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
// bank
if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_bank <= cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_bank <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
//chipsel
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
end
end
//
// Everything below is for
// CFG_RDATA_RETURN_MODE == INORDER support
//
generate
begin : gen_rdata_return_inorder
if (CFG_RDATA_RETURN_MODE == "INORDER")
begin
//
// DATAID MANAGEMENT
//
genvar i;
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array
assign dataid_array_valid[i] = |(dataid_array_burstcount[i]);
// dataid_array
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
dataid_array_localid [i] <= 0;
end
else
begin
// update command
if (cmdload_valid & free_id_dataid_vector[i])
begin
dataid_array_burstcount[i] <= proc_size;
end
// writing data to buffer
if (rout_data_valid & (rout_data_dataid == i))
begin
dataid_array_data_ready[i] <= 1'b1;
dataid_array_localid[i] <= rout_data_localid;
end
// completed reading data from buffer
if (inordr_id_data_complete & inordr_id_dataid_vector[i])
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
end
end
end
// dataid_array output decode mux
always @ (*)
begin
if (inordr_id_valid & inordr_id_dataid_vector[i])
begin
mux_inordr_data_ready[i] = dataid_array_data_ready[i];
end
else
begin
mux_inordr_data_ready[i] = 1'b0;
end
end
end
assign inordr_read_data_valid = |mux_inordr_data_ready;
//
// FREE & ALLOCATED DATAID LIST
//
assign free_id_get_ready = cmdload_valid;
assign allocated_put_valid = free_id_get_ready & free_id_valid;
// list & fifo ready & valid assertion/de-assertion behavior may differ based on implementation, SPR:358527
assign free_id_valid = int_free_id_valid & inordr_info_input_ready;
assign inordr_id_valid = inordr_id_list_valid & inordr_info_output_valid;
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (free_id_get_ready),
.list_get_entry_valid (int_free_id_valid),
.list_get_entry_id (free_id_dataid),
.list_get_entry_id_vector (free_id_dataid_vector),
// ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (),
.list_put_entry_valid (inordr_id_data_complete),
.list_put_entry_id (inordr_id_dataid)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (inordr_id_data_complete),
.list_get_entry_valid (inordr_id_list_valid),
.list_get_entry_id (inordr_id_dataid),
.list_get_entry_id_vector (inordr_id_dataid_vector),
// allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (allocated_put_ready),
.list_put_entry_valid (allocated_put_valid),
.list_put_entry_id (free_id_dataid)
);
// format for inordr_info_input & inordr_info_output must be same
assign inordr_info_input = {proc_localid,proc_size};
assign {inordr_id_localid,inordr_id_expected_burstcount} = inordr_info_output;
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_INORDER_INFO_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_DATA_ID_WIDTH)
)
inordr_info_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (inordr_id_data_complete),
.get_valid (inordr_info_output_valid),
.get_data (inordr_info_output),
.put_ready (inordr_info_input_ready),
.put_valid (allocated_put_valid),
.put_data (inordr_info_input)
);
//
// IN-ORDER READ MANAGER
//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 0;
inordr_read_data_valid_r <= 0;
inordr_id_data_complete_r <= 0;
inordr_id_localid_r <= 0;
end
else
begin
if (inordr_id_data_complete)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 1;
end
else
begin
inordr_data_counter <= inordr_next_data_counter;
inordr_data_counter_plus_1 <= inordr_next_data_counter + 1;
end
inordr_id_localid_r <= inordr_id_localid;
// original signal used to read from buffer
// _r version used to pop the fifos
inordr_read_data_valid_r <= inordr_read_data_valid;
inordr_id_data_complete_r <= inordr_id_data_complete;
end
end
assign inordr_next_data_counter = (inordr_read_data_valid) ? (inordr_data_counter_plus_1) : inordr_data_counter;
assign inordr_id_data_complete = inordr_read_data_valid & (inordr_data_counter_plus_1 == inordr_id_expected_burstcount);
//
// BUFFER
//
assign buffwrite_offset = ecc_rdata_counter;
assign buffwrite_address = {rout_data_dataid,buffwrite_offset};
assign buffwrite_data = {rout_data_error,rout_data};
assign buffread_offset = inordr_data_counter;
assign buffread_address = {inordr_id_dataid,buffread_offset};
assign {inordr_read_data_error,inordr_read_data} = buffread_data;
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_IN_ORDER_BUFFER_DATA_WIDTH)
)
in_order_buffer_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (rout_data_valid),
.write_address (buffwrite_address),
.write_data (buffwrite_data),
// read interface
.read_valid (inordr_read_data_valid),
.read_address (buffread_address),
.read_data (buffread_data)
);
end
end
endgenerate
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
//
// assert
//
// - rdatap_free_id_valid XOR rdatap_allocated_put_ready must always be 1
// - CFG_BUFFER_ADDR_WIDTH must be >= CFG_INT_SIZE_WIDTH. must have enough location to store 1 dram command worth of data
// - put_ready goes low
// - ecc_rdatav is high, but pfifo_output_valid is low
// - buffer size must be dataid x max size per command
// - is rdata_burst_complete allowed to be high every cycle?
// - CFG_BUFFER_ADDR_WIDTH > CFG_DATA_ID_WIDTH
// - if cfg_enable_ecc is low, sbe, dbe, rdata error must all be low
// - if cfg_enable_auto_corr is low, rmw & rmw_partial must be low, errcmd_valid must never be high
// - cmd_counter_full & cmdload_valid
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller AFi interfacing block
//
// File : afi_block.v
//
// Abstract : AFi block
///////////////////////////////////////////////////////////////////////////////
//Things to check
//1. Does afi_wlat need to be registered?
//2. Does ecc_wdata_fifo_read generation changes with ECC
//3. Why in ddrx controller int_dqs_burst and int_wdata_valid signals are registered when CFG_OUTPUT_REGD is 1. Why complex logic instead of simple registering??
//4. We need rdwr_data_valid signal from arbiter to determine how many datas are valid within one dram burst
//5. Do we need to end rdwr_data_valid with doing_write to generate ecc_wdata_fifo_read? Yes
//6. Look at all comments and SPRs for old ddrx afi block
//7. Currently additive_latency, ECC, HR features are not supported
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rdwr_data_tmg
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_MEM_IF_DM_WIDTH = 1,
CFG_WLAT_BUS_WIDTH = 6,
CFG_DRAM_WLAT_GROUP = 1,
CFG_DATA_ID_WIDTH = 10,
CFG_WDATA_REG = 0,
CFG_ECC_ENC_REG = 0,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_OUTPUT_REGD = 1
)
(
ctl_clk,
ctl_reset_n,
// configuration
cfg_enable_ecc,
cfg_output_regd,
cfg_output_regd_for_afi_output,
//Arbiter command input
bg_doing_read,
bg_doing_write,
bg_rdwr_data_valid, //Required for user burst length lesser than dram burst length
dataid,
bg_do_rmw_correct,
bg_do_rmw_partial,
//Inputs from ECC/WFIFO blocks
ecc_wdata,
ecc_dm,
//Input from AFI Block
afi_wlat,
//Output from AFI Block
afi_doing_read, //Use to generate rdata_valid signals in PHY
afi_doing_read_full, //AFI 2.0 signal, used by UniPHY for dqs enable control
ecc_wdata_fifo_read,
ecc_wdata_fifo_dataid,
ecc_wdata_fifo_dataid_vector,
ecc_wdata_fifo_rmw_correct,
ecc_wdata_fifo_rmw_partial,
ecc_wdata_fifo_read_first,
ecc_wdata_fifo_dataid_first,
ecc_wdata_fifo_dataid_vector_first,
ecc_wdata_fifo_rmw_correct_first,
ecc_wdata_fifo_rmw_partial_first,
ecc_wdata_fifo_first_vector,
ecc_wdata_fifo_read_last,
ecc_wdata_fifo_dataid_last,
ecc_wdata_fifo_dataid_vector_last,
ecc_wdata_fifo_rmw_correct_last,
ecc_wdata_fifo_rmw_partial_last,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm
);
localparam integer CFG_WLAT_PIPE_LENGTH = 2**(CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP);
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
integer i;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
output [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
//Arbiter command input
input bg_doing_read;
input bg_doing_write;
input bg_rdwr_data_valid;
input [CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
//Inputs from ECC/WFIFO blocks
input [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] ecc_wdata;
input [(CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO)/(CFG_MEM_IF_DQ_WIDTH/CFG_MEM_IF_DQS_WIDTH)-1:0] ecc_dm;
//Input from AFI Block
input [CFG_WLAT_BUS_WIDTH-1:0] afi_wlat;
//output to AFI block
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
output [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
output [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
output ecc_wdata_fifo_read_first;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
output ecc_wdata_fifo_rmw_correct_first;
output ecc_wdata_fifo_rmw_partial_first;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
output ecc_wdata_fifo_read_last;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
output ecc_wdata_fifo_rmw_correct_last;
output ecc_wdata_fifo_rmw_partial_last;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
output [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
output [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_doing_read;
wire bg_doing_write;
wire bg_rdwr_data_valid;
wire [CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read_r;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//Internal signals
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path;
reg doing_read_combi;
reg doing_read_full_combi;
reg doing_read_r;
reg doing_read_full_r;
reg [CFG_WLAT_PIPE_LENGTH-1:0] doing_write_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rdwr_data_valid_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_correct_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_partial_pipe;
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
reg int_dqs_burst;
reg int_dqs_burst_r;
reg int_wdata_valid;
reg int_wdata_valid_r;
reg int_real_wdata_valid;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial_r;
wire int_do_rmw_correct;
wire int_do_rmw_partial;
// DQS burst logic for half rate design
reg int_dqs_burst_half_rate;
reg int_dqs_burst_half_rate_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] first_afi_wlat;
reg [CFG_DRAM_WLAT_GROUP-1:0] last_afi_wlat;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg smallest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_3;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_0;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_1;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_2;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_x;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg largest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_3;
reg largest_doing_write_pipe_eq_afi_wlat_minus_0;
reg largest_doing_write_pipe_eq_afi_wlat_minus_1;
reg largest_doing_write_pipe_eq_afi_wlat_minus_2;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg largest_doing_write_pipe_eq_afi_wlat_minus_x;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg afi_wlat_eq_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
//=================================================================================================//
// Internal cfg_output_regd //
//=================================================================================================//
generate
genvar N;
for (N = 0;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_logic_per_dqs_group
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] <= 1)
begin
// We enable output_regd for signals going to PHY
// because we need to fetch data 2 clock cycles earlier
cfg_output_regd_for_afi_output_combi [N] = 1'b1;
// We disable output_regd for signals going to wdata_path
// because we need to fecth data 2 clock cycles earlier
cfg_output_regd_for_wdata_path_combi [N] = 1'b0;
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
end
for (N = 1;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_mux_logic
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [N] = cfg_output_regd_for_afi_output_combi [N] | cfg_output_regd_for_afi_output_mux [N-1];
cfg_output_regd_for_wdata_path_mux [N] = cfg_output_regd_for_wdata_path_combi [N] | cfg_output_regd_for_wdata_path_mux [N-1];
end
end
endgenerate
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [0] = cfg_output_regd_for_afi_output_combi [0];
cfg_output_regd_for_wdata_path_mux [0] = cfg_output_regd_for_wdata_path_combi [0];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_output_regd_for_afi_output <= 1'b0;
cfg_output_regd_for_wdata_path <= 1'b0;
end
else
begin
cfg_output_regd_for_afi_output <= cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1];
cfg_output_regd_for_wdata_path <= cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1];
end
end
//=================================================================================================//
// Read timing logic //
//=================================================================================================//
//*************************************************************************************************//
// afi_doing_read generation logic //
//*************************************************************************************************//
always @(*)
begin
if (bg_doing_read && bg_rdwr_data_valid)
begin
doing_read_combi = 1'b1;
end
else
begin
doing_read_combi = 1'b0;
end
doing_read_full_combi = bg_doing_read;
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_r <= 1'b0;
doing_read_full_r <= 1'b0;
end
else
begin
doing_read_r <= doing_read_combi;
doing_read_full_r <= doing_read_full_combi;
end
end
generate
genvar I;
for (I = 0; I < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); I = I + 1)
begin : B
assign afi_doing_read [I] = (cfg_output_regd_for_afi_output) ? doing_read_r : doing_read_combi;
assign afi_doing_read_full [I] = (cfg_output_regd_for_afi_output) ? doing_read_full_r : doing_read_full_combi;
end
endgenerate
//=================================================================================================//
// Write timing logic //
//=================================================================================================//
// Content of pipe shows how long dqs should toggle, used to generate dqs_burst
// content of pipe is also used to generate wdata_valid signal
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe <= 0;
end
else
begin
doing_write_pipe <= {doing_write_pipe[CFG_WLAT_PIPE_LENGTH -2 :0],bg_doing_write};
end
end
// content of pipe shows how much data should be read out of the write data FIFO
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe <= 0;
end
else
begin
rdwr_data_valid_pipe <= {rdwr_data_valid_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],bg_rdwr_data_valid};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= 0;
end
end
else
begin
dataid_pipe [0] <= dataid;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= dataid_pipe[i-1];
end
end
end
//pre-calculated dataid comparison logic
always @ (*)
begin
for (i=0; i<(CFG_DATAID_ARRAY_DEPTH); i=i+1)
begin
if (dataid == i)
begin
dataid_vector [i] = 1'b1;
end
else
begin
dataid_vector [i] = 1'b0;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_vector_pipe [0] <= 0;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= 0;
end
end
else
begin
dataid_vector_pipe [0] <= dataid_vector;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= dataid_vector_pipe[i-1];
end
end
end
assign int_do_rmw_correct = |bg_do_rmw_correct;
assign int_do_rmw_partial = |bg_do_rmw_partial;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe <= 0;
end
else
begin
rmw_correct_pipe <= {rmw_correct_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_correct};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_partial_pipe <= 0;
end
else
begin
rmw_partial_pipe <= {rmw_partial_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_partial};
end
end
// Pre-calculated logic for each DQS group
generate
genvar P;
for (P = 0;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : pre_calculate_logic_per_dqs_group
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_wlat_eq_0 [P] <= 1'b0;
afi_wlat_minus_1 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_2 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_3 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (current_afi_wlat == 0)
begin
afi_wlat_eq_0 [P] <= 1'b1;
end
else
begin
afi_wlat_eq_0 [P] <= 1'b0;
end
afi_wlat_minus_1 [P] <= current_afi_wlat - 1;
afi_wlat_minus_2 [P] <= current_afi_wlat - 2;
afi_wlat_minus_3 [P] <= current_afi_wlat - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (doing_write_pipe[1])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (doing_write_pipe[afi_wlat_minus_1 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_2 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_3 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[afi_wlat_minus_2 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rdwr_data_valid_pipe[afi_wlat_minus_3 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
end
else
begin
if (current_afi_wlat == 0)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
end
else if (current_afi_wlat == 1)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (current_afi_wlat == 2)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [0];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[0];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector;
end
else
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [afi_wlat_minus_2 [P]];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid_pipe [afi_wlat_minus_3 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[afi_wlat_minus_2 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector_pipe[afi_wlat_minus_3 [P]];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rmw_correct_pipe[0])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[afi_wlat_minus_2 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_2 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_correct_pipe[afi_wlat_minus_3 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_3 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_2 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_2 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_2 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_2 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_2 [P];
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_1 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_1 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_1 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_1 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_1 [P];
end
end
// First vector
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == smallest_afi_wlat [CFG_DRAM_WLAT_GROUP - 1])
begin
ecc_wdata_fifo_first_vector [P] <= 1'b1;
end
else
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
end
end
end
for (P = 1;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : afi_wlat_info_logic
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [P] <= 0;
largest_afi_wlat [P] <= 0;
end
else
begin
if (current_afi_wlat < smallest_afi_wlat [P-1])
begin
smallest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
smallest_afi_wlat [P] <= smallest_afi_wlat [P-1];
end
if (current_afi_wlat > largest_afi_wlat [P-1])
begin
largest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
largest_afi_wlat [P] <= largest_afi_wlat [P-1];
end
end
end
end
endgenerate
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [0] <= 0;
largest_afi_wlat [0] <= 0;
end
else
begin
smallest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
largest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
end
end
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
always @ (*)
begin
smallest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
smallest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
smallest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
smallest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
largest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
largest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
largest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
largest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
end
end
else
begin
// Pre-calculated logic for smallest/largest afi_wlat (for afi addr/cmd logic)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat_eq_0 <= 1'b0;
smallest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
smallest_afi_wlat_eq_0 <= 1'b0;
end
smallest_afi_wlat_minus_1 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
smallest_afi_wlat_minus_2 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
smallest_afi_wlat_minus_3 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[smallest_afi_wlat_minus_1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_2])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_3])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
end
else
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [smallest_afi_wlat_minus_2];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [smallest_afi_wlat_minus_3];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[smallest_afi_wlat_minus_2];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[smallest_afi_wlat_minus_3];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_2 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_2 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_1 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_1 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_afi_wlat_eq_0 <= 1'b0;
largest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
largest_afi_wlat_eq_0 <= 1'b0;
end
largest_afi_wlat_minus_1 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
largest_afi_wlat_minus_2 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
largest_afi_wlat_minus_3 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[largest_afi_wlat_minus_1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_2])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_3])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_2])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_3])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
end
else
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [largest_afi_wlat_minus_2];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [largest_afi_wlat_minus_3];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[largest_afi_wlat_minus_2];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[largest_afi_wlat_minus_3];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_2 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_2 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_1 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_1 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
end
endgenerate
//*************************************************************************************************//
// afi_dqs_burst generation logic //
//*************************************************************************************************//
// high earlier than wdata_valid but ends the same
// for writes only, where dqs should toggle, use doing_write_pipe
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_doing_write || doing_write_pipe[0])
begin
int_dqs_burst = 1'b1;
end
else
begin
int_dqs_burst = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_1 || smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_dqs_burst = 1'b1;
end
else
begin
int_dqs_burst = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_r <= 1'b0;
end
else
begin
int_dqs_burst_r <= int_dqs_burst;
end
end
always @ (*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (doing_write_pipe[0])
begin
int_dqs_burst_half_rate = 1'b1;
end
else
begin
int_dqs_burst_half_rate = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_dqs_burst_half_rate = 1'b1;
end
else
begin
int_dqs_burst_half_rate = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_half_rate_r <= 1'b0;
end
else
begin
int_dqs_burst_half_rate_r <= int_dqs_burst_half_rate;
end
end
generate
genvar K;
if (CFG_DWIDTH_RATIO == 2) // fullrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst;
end
end
else if (CFG_DWIDTH_RATIO == 4) // halfrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst ;
assign afi_dqs_burst[K ] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
end
end
else if (CFG_DWIDTH_RATIO == 8) // quarterrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 3] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst ;
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 2] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 1] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
assign afi_dqs_burst[K ] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
end
end
endgenerate
//*************************************************************************************************//
// afi_wdata_valid generation logic //
//*************************************************************************************************//
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (doing_write_pipe[0])
begin
int_wdata_valid = 1'b1;
end
else
begin
int_wdata_valid = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_wdata_valid = 1'b1;
end
else
begin
int_wdata_valid = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_wdata_valid_r <= 1'b0;
end
else
begin
int_wdata_valid_r <= int_wdata_valid;
end
end
generate
genvar L;
for (L = 0; L < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); L = L + 1)
begin : D
assign afi_wdata_valid[L] = (cfg_output_regd_for_afi_output) ? int_wdata_valid_r : int_wdata_valid;
end
endgenerate
//*************************************************************************************************//
// afi_wdata generation logic //
//*************************************************************************************************//
generate
genvar M;
for (M = 0;M < CFG_DRAM_WLAT_GROUP;M = M + 1) // generate wlat logic for each DQS group
begin : wlat_logic_per_dqs_group
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_r [M] <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_r [M] <= int_ecc_wdata_fifo_read [M];
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_r [M] : int_ecc_wdata_fifo_read [M];
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_r [M] <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_r [M] <= ecc_wdata_fifo_read [M];
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid [M] = dataid;
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_dataid [M] = dataid_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_r [M] <= 0;
int_ecc_wdata_fifo_dataid_vector_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_r [M] <= int_ecc_wdata_fifo_dataid [M];
int_ecc_wdata_fifo_dataid_vector_r [M] <= int_ecc_wdata_fifo_dataid_vector [M];
end
end
assign ecc_wdata_fifo_dataid [(M + 1) * CFG_DATA_ID_WIDTH - 1 : M * CFG_DATA_ID_WIDTH ] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_r [M] : int_ecc_wdata_fifo_dataid [M];
assign ecc_wdata_fifo_dataid_vector [(M + 1) * CFG_DATAID_ARRAY_DEPTH - 1 : M * CFG_DATAID_ARRAY_DEPTH] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_r [M] : int_ecc_wdata_fifo_dataid_vector [M];
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct [M] = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial [M] = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_rmw_correct [M] = rmw_correct_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_rmw_partial [M] = rmw_partial_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= 0;
int_ecc_wdata_fifo_rmw_partial_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= int_ecc_wdata_fifo_rmw_correct [M];
int_ecc_wdata_fifo_rmw_partial_r [M] <= int_ecc_wdata_fifo_rmw_partial [M];
end
end
assign ecc_wdata_fifo_rmw_correct [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_r [M] : int_ecc_wdata_fifo_rmw_correct [M];
assign ecc_wdata_fifo_rmw_partial [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_r [M] : int_ecc_wdata_fifo_rmw_partial [M];
end
endgenerate
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
assign ecc_wdata_fifo_read_first = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_first = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_first = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_first = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_first = ecc_wdata_fifo_rmw_partial;
assign ecc_wdata_fifo_read_last = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_last = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_last = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_last = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_last = ecc_wdata_fifo_rmw_partial;
end
else
begin
reg ecc_wdata_fifo_read_first_r;
reg int_ecc_wdata_fifo_read_first;
reg int_ecc_wdata_fifo_read_first_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first_r;
reg int_ecc_wdata_fifo_rmw_correct_first;
reg int_ecc_wdata_fifo_rmw_correct_first_r;
reg int_ecc_wdata_fifo_rmw_partial_first;
reg int_ecc_wdata_fifo_rmw_partial_first_r;
reg ecc_wdata_fifo_read_last_r;
reg int_ecc_wdata_fifo_read_last;
reg int_ecc_wdata_fifo_read_last_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last_r;
reg int_ecc_wdata_fifo_rmw_correct_last;
reg int_ecc_wdata_fifo_rmw_correct_last_r;
reg int_ecc_wdata_fifo_rmw_partial_last;
reg int_ecc_wdata_fifo_rmw_partial_last_r;
// Determine first ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_first_r <= int_ecc_wdata_fifo_read_first;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_first_r : int_ecc_wdata_fifo_read_first;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_first_r <= ecc_wdata_fifo_read_first;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_first = dataid;
int_ecc_wdata_fifo_dataid_vector_first = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_first = smallest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_first = smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_first_r <= 0;
int_ecc_wdata_fifo_dataid_vector_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_first_r <= int_ecc_wdata_fifo_dataid_first ;
int_ecc_wdata_fifo_dataid_vector_first_r <= int_ecc_wdata_fifo_dataid_vector_first;
end
end
assign ecc_wdata_fifo_dataid_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_first_r : int_ecc_wdata_fifo_dataid_first ;
assign ecc_wdata_fifo_dataid_vector_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_first_r : int_ecc_wdata_fifo_dataid_vector_first;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_first = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_first = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_first = smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_first = smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= 0;
int_ecc_wdata_fifo_rmw_partial_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= int_ecc_wdata_fifo_rmw_correct_first;
int_ecc_wdata_fifo_rmw_partial_first_r <= int_ecc_wdata_fifo_rmw_partial_first;
end
end
assign ecc_wdata_fifo_rmw_correct_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_first_r : int_ecc_wdata_fifo_rmw_correct_first;
assign ecc_wdata_fifo_rmw_partial_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_first_r : int_ecc_wdata_fifo_rmw_partial_first;
// Determine last ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_last_r <= int_ecc_wdata_fifo_read_last;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_last_r : int_ecc_wdata_fifo_read_last;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_last_r <= ecc_wdata_fifo_read_last;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_last = dataid;
int_ecc_wdata_fifo_dataid_vector_last = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_last = largest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_last = largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_last_r <= 0;
int_ecc_wdata_fifo_dataid_vector_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_last_r <= int_ecc_wdata_fifo_dataid_last ;
int_ecc_wdata_fifo_dataid_vector_last_r <= int_ecc_wdata_fifo_dataid_vector_last;
end
end
assign ecc_wdata_fifo_dataid_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_last_r : int_ecc_wdata_fifo_dataid_last ;
assign ecc_wdata_fifo_dataid_vector_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_last_r : int_ecc_wdata_fifo_dataid_vector_last;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_last = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_last = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_last = largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_last = largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= 0;
int_ecc_wdata_fifo_rmw_partial_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= int_ecc_wdata_fifo_rmw_correct_last;
int_ecc_wdata_fifo_rmw_partial_last_r <= int_ecc_wdata_fifo_rmw_partial_last;
end
end
assign ecc_wdata_fifo_rmw_correct_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_last_r : int_ecc_wdata_fifo_rmw_correct_last;
assign ecc_wdata_fifo_rmw_partial_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_last_r : int_ecc_wdata_fifo_rmw_partial_last;
end
endgenerate
// No data manipulation on wdata
assign afi_wdata = ecc_wdata;
//*************************************************************************************************//
// afi_dm generation logic //
//*************************************************************************************************//
//Why do we need ecc_dm and rdwr_data_valid to determine DM
// ecc_dm will not get updated till we read another data from wrfifo, so we need to drive DMs based on rdwr_data_valid
//Output registered information already backed in ecc_wdata_fifo_read
// data valid one clock cycle after read
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_real_wdata_valid <= 1'b0;
end
else
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
int_real_wdata_valid <= ecc_wdata_fifo_read_r;
end
else
begin
int_real_wdata_valid <= ecc_wdata_fifo_read;
end
end
end
generate
genvar J;
for (J = 0; J < CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO; J = J + 1)
begin : F
assign afi_dm[J] = ~ecc_dm[J] | ~int_real_wdata_valid;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_sideband
# (parameter
// parameters
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2, //2-FR,4-HR,8-QR
CFG_REG_GRANT = 1,
CFG_CTL_TBP_NUM = 4,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_BA_WIDTH = 3,
CFG_PORT_WIDTH_TCL = 4,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_RANK_TIMER_OUTPUT_REG = 0,
T_PARAM_ARF_TO_VALID_WIDTH = 10,
T_PARAM_ARF_PERIOD_WIDTH = 13,
T_PARAM_PCH_ALL_TO_VALID_WIDTH = 10,
T_PARAM_SRF_TO_VALID_WIDTH = 10,
T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10,
T_PARAM_PDN_TO_VALID_WIDTH = 6,
BANK_TIMER_COUNTER_OFFSET = 2, //used to be 4
T_PARAM_PDN_PERIOD_WIDTH = 16,// temporary
T_PARAM_POWER_SAVING_EXIT_WIDTH = 6
)
(
ctl_clk,
ctl_reset_n,
// local interface
rfsh_req,
rfsh_chip,
rfsh_ack,
self_rfsh_req,
self_rfsh_chip,
self_rfsh_ack,
deep_powerdn_req,
deep_powerdn_chip,
deep_powerdn_ack,
power_down_ack,
// sideband output
stall_row_arbiter,
stall_col_arbiter,
stall_chip,
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
sb_tbp_precharge_all,
// PHY interface
ctl_mem_clk_disable,
ctl_init_req,
ctl_cal_success,
// tbp & cmd gen
cmd_gen_chipsel,
tbp_chipsel,
tbp_load,
// timing
t_param_arf_to_valid,
t_param_arf_period,
t_param_pch_all_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_pdn_to_valid,
t_param_pdn_period,
t_param_power_saving_exit,
// block status
tbp_empty,
tbp_bank_active,
tbp_timer_ready,
row_grant,
col_grant,
// dqs tracking
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
// config ports
cfg_enable_dqs_tracking,
cfg_user_rfsh,
cfg_type,
cfg_tcl,
cfg_regdimm_enable
);
// states for our DQS bus monitor state machine
localparam IDLE = 32'h49444C45;
localparam ARF = 32'h20415246;
localparam PDN = 32'h2050444E;
localparam SRF = 32'h20535246;
localparam INIT = 32'h696e6974;
localparam PCHALL = 32'h70636861;
localparam REFRESH = 32'h72667368;
localparam PDOWN = 32'h7064776e;
localparam SELFRFSH = 32'h736c7266;
localparam DEEPPDN = 32'h64656570;
localparam ZQCAL = 32'h7a63616c;
localparam DQSTRK = 32'h6471746b;
localparam DQSLONG = 32'h64716c6e;
localparam POWER_SAVING_COUNTER_WIDTH = T_PARAM_SRF_TO_VALID_WIDTH;
localparam POWER_SAVING_EXIT_COUNTER_WIDTH = T_PARAM_POWER_SAVING_EXIT_WIDTH;
localparam ARF_COUNTER_WIDTH = T_PARAM_ARF_PERIOD_WIDTH;
localparam PDN_COUNTER_WIDTH = T_PARAM_PDN_PERIOD_WIDTH;
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam integer CFG_PORT_WIDTH_TCL_SQRD = 2**CFG_PORT_WIDTH_TCL;
input ctl_clk;
input ctl_reset_n;
input rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output rfsh_ack;
input self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
output self_rfsh_ack;
input deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output deep_powerdn_ack;
output power_down_ack;
output stall_row_arbiter;
output stall_col_arbiter;
output [CFG_MEM_IF_CHIP-1:0] stall_chip;
output [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
output [CFG_MEM_IF_CHIP-1:0] sb_do_refresh;
output [CFG_MEM_IF_CHIP-1:0] sb_do_self_refresh;
output [CFG_MEM_IF_CHIP-1:0] sb_do_power_down;
output [CFG_MEM_IF_CHIP-1:0] sb_do_deep_pdown;
output [CFG_MEM_IF_CHIP-1:0] sb_do_zq_cal;
output [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
output [CFG_MEM_IF_CLK_PAIR_COUNT-1:0] ctl_mem_clk_disable;
output ctl_init_req;
input ctl_cal_success;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
input [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
input [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
input [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
input [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
input [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
input [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
input [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
input tbp_empty;
input [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
input [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
input row_grant;
input col_grant;
output [CFG_MEM_IF_CHIP-1:0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP-1:0] afi_seq_busy;
output [CFG_MEM_IF_CHIP-1:0] afi_ctl_long_idle;
input cfg_enable_dqs_tracking;
input cfg_user_rfsh;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input cfg_regdimm_enable;
// end of port declaration
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire [CFG_MEM_IF_CLK_PAIR_COUNT-1:0] ctl_mem_clk_disable;
wire ctl_init_req;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_refresh;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_self_refresh;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_zq_cal;
reg [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] do_refresh;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] do_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] stall_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_stall_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_stall_chip_combi;
reg [CFG_MEM_IF_CHIP-1:0] stall_arbiter;
reg [CFG_MEM_IF_CHIP-1:0] afi_ctl_refresh_done;
reg [CFG_MEM_IF_CHIP-1:0] afi_ctl_long_idle;
reg [CFG_MEM_IF_CHIP-1:0] dqstrk_exit;
reg [CFG_MEM_IF_CHIP-1:0] dqslong_exit;
reg [CFG_MEM_IF_CHIP-1:0] doing_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] refresh_chip_req;
reg [CFG_MEM_IF_CHIP-1:0] self_refresh_chip_req;
reg self_rfsh_req_r;
reg [CFG_MEM_IF_CHIP-1:0] deep_pdown_chip_req;
reg [CFG_MEM_IF_CHIP-1:0] power_down_chip_req;
wire [CFG_MEM_IF_CHIP-1:0] power_down_chip_req_combi;
wire [CFG_MEM_IF_CHIP-1:0] all_banks_closed;
wire [CFG_MEM_IF_CHIP-1:0] tcom_not_running;
reg [CFG_PORT_WIDTH_TCL_SQRD-1:0] tcom_not_running_pipe [CFG_MEM_IF_CHIP-1:0];
reg [CFG_MEM_IF_CHIP-1:0] can_refresh;
reg [CFG_MEM_IF_CHIP-1:0] can_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] can_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] can_power_down;
reg [CFG_MEM_IF_CHIP-1:0] can_exit_power_saving_mode;
reg [CFG_MEM_IF_CHIP-1:0] cs_refresh_req;
wire grant;
wire [CFG_MEM_IF_CHIP-1:0] cs_zq_cal_req;
wire [CFG_MEM_IF_CHIP-1:0] power_saving_enter_ready;
wire [CFG_MEM_IF_CHIP-1:0] power_saving_exit_ready;
reg [PDN_COUNTER_WIDTH - 1 : 0] power_down_cnt;
reg no_command_r1;
reg [CFG_MEM_IF_CHIP-1:0] afi_seq_busy_r; // synchronizer
reg [CFG_MEM_IF_CHIP-1:0] afi_seq_busy_r2; // synchronizer
//new! to avoid contention
reg [CFG_MEM_IF_CHIP-1:0] do_refresh_req;
reg refresh_req_ack;
reg dummy_do_refresh;
reg dummy_do_refresh_r;
reg do_refresh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_req;
reg self_rfsh_req_ack;
reg dummy_do_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] do_zqcal_req;
reg zqcal_req_ack;
reg dummy_do_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] do_pch_all_req;
reg pch_all_req_ack;
reg dummy_do_pch_all;
integer i;
assign ctl_mem_clk_disable = {CFG_MEM_IF_CLK_PAIR_COUNT{1'b0}};
//generate *_chip_ok signals by checking can_*[chip], only when for_chip[chip] is 1
generate
genvar chip;
for (chip = 0; chip < CFG_MEM_IF_CHIP; chip = chip + 1)
begin : gen_chip_ok
// check can_* only for chips that we'd like to precharge_all to, ^~ is XNOR
assign tcom_not_running[chip] = tbp_timer_ready[chip];
assign all_banks_closed[chip] = ~tbp_bank_active[chip];
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
tcom_not_running_pipe[chip] <= 0;
end
else
begin
if (!tcom_not_running[chip])
tcom_not_running_pipe[chip] <= 0;
else
tcom_not_running_pipe[chip] <= {tcom_not_running_pipe[chip][CFG_PORT_WIDTH_TCL_SQRD -2 :0],tcom_not_running[chip]};
end
end
end
endgenerate
assign rfsh_ack = (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) ? |do_refresh : ((|do_refresh | do_refresh_r) & refresh_req_ack);
assign self_rfsh_ack = |do_self_rfsh;
assign deep_powerdn_ack = |do_deep_pdown;
assign power_down_ack = |do_power_down;
// Register sideband signals when CFG_REG_GRANT is '1'
// to prevent sideband request going out on the same cycle as tbp request
generate
begin
genvar j;
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_do_precharge_all <= 0;
sb_do_refresh <= 0;
sb_do_self_refresh <= 0;
sb_do_power_down <= 0;
sb_do_deep_pdown <= 0;
sb_do_zq_cal <= 0;
end
else
begin
sb_do_precharge_all <= do_precharge_all;
sb_do_refresh <= do_refresh;
sb_do_self_refresh <= do_self_rfsh;
sb_do_power_down <= do_power_down;
sb_do_deep_pdown <= do_deep_pdown;
sb_do_zq_cal <= do_zqcal;
end
end
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin : tbp_loop_1
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_tbp_precharge_all [j] <= 1'b0;
end
else
begin
if (tbp_load[j])
begin
sb_tbp_precharge_all [j] <= do_precharge_all [cmd_gen_chipsel];
end
else
begin
sb_tbp_precharge_all [j] <= do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
end
end
end
end
end
else
begin
always @ (*)
begin
sb_do_precharge_all = do_precharge_all;
sb_do_refresh = do_refresh;
sb_do_self_refresh = do_self_rfsh;
sb_do_power_down = do_power_down;
sb_do_deep_pdown = do_deep_pdown;
sb_do_zq_cal = do_zqcal;
end
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin : tbp_loop_2
always @ (*)
begin
sb_tbp_precharge_all [j] = do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
end
end
end
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_req_ack <= 0;
zqcal_req_ack <= 0;
pch_all_req_ack <= 0;
self_rfsh_req_ack <= 0;
dummy_do_refresh_r <= dummy_do_refresh;
do_refresh_r <= 0;
end
else
begin
refresh_req_ack <= dummy_do_refresh;
zqcal_req_ack <= dummy_do_zqcal;
pch_all_req_ack <= dummy_do_pch_all;
self_rfsh_req_ack <= dummy_do_self_rfsh;
dummy_do_refresh_r <= dummy_do_refresh;
if (dummy_do_refresh && !dummy_do_refresh_r)
do_refresh_r <= |do_refresh;
else
do_refresh_r <= 0;
end
end
always @(*)
begin
i = 0;
dummy_do_refresh = 0;
dummy_do_pch_all = 0;
dummy_do_zqcal = 0;
if (|do_refresh_req)
begin
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) // if not (regdimm and DDR3), normal refresh
do_refresh = do_refresh_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_refresh[i] = do_refresh_req[i];
dummy_do_refresh= |do_refresh_req;
end
else if (i%2 == 1 && refresh_req_ack)
do_refresh[i] = do_refresh_req[i];
else
do_refresh[i] = 0;
end
end
do_precharge_all = 0;
do_zqcal = 0;
end
else if (|do_pch_all_req)
begin
do_refresh = 0;
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
do_precharge_all = do_pch_all_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_precharge_all[i] = do_pch_all_req[i];
dummy_do_pch_all = |do_pch_all_req;
end
else if (i%2 == 1 && pch_all_req_ack)
do_precharge_all[i] = do_pch_all_req[i];
else
do_precharge_all[i] = 0;
end
end
do_zqcal = 0;
end
else if (|do_zqcal_req)
begin
do_refresh = 0;
do_precharge_all = 0;
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
do_zqcal = do_zqcal_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_zqcal[i] = do_zqcal_req[i];
dummy_do_zqcal= |do_zqcal_req;
end
else if (i%2 == 1 && zqcal_req_ack)
do_zqcal[i] = do_zqcal_req[i];
else
do_zqcal[i] = 0;
end
end
end
else
begin
do_refresh = 0;
dummy_do_refresh = 0;
do_precharge_all = 0;
dummy_do_pch_all = 0;
do_zqcal = 0;
dummy_do_zqcal = 0;
end
end
always @(*)
begin
i = 0;
dummy_do_self_rfsh = 1'b0;
if (|do_refresh || |do_precharge_all || |do_zqcal)
begin
if (|do_self_rfsh_r)
begin
do_self_rfsh = do_self_rfsh_req;
dummy_do_self_rfsh = 1'b1;
end
else
do_self_rfsh = 0;
end
else
begin
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
do_self_rfsh = do_self_rfsh_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_self_rfsh[i] = do_self_rfsh_req[i];
dummy_do_self_rfsh= |do_self_rfsh_req;
end
else if (i%2 == 1 && self_rfsh_req_ack)
do_self_rfsh[i] = do_self_rfsh_req[i];
else
do_self_rfsh[i] = 0;
end
end
end
end
assign stall_row_arbiter = |stall_arbiter;
assign stall_col_arbiter = |stall_arbiter;
assign grant = (CFG_REG_GRANT == 1) ? (row_grant | col_grant) : 1'b0;
//register self_rfsh_req and deep_powerdn_req
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
self_refresh_chip_req <= 0;
deep_pdown_chip_req <= 0;
self_rfsh_req_r <= 0;
do_self_rfsh_r <= 0;
end
else
begin
if (self_rfsh_req)
self_refresh_chip_req <= self_rfsh_chip;
else
self_refresh_chip_req <= 0;
self_rfsh_req_r <= self_rfsh_req & |self_rfsh_chip;
do_self_rfsh_r <= do_self_rfsh;
if (deep_powerdn_req)
deep_pdown_chip_req <= deep_powerdn_chip;
else
deep_pdown_chip_req <= 0;
end
end
//combi user refresh
always @(*)
begin
if (cfg_user_rfsh)
begin
if (rfsh_req)
refresh_chip_req = rfsh_chip;
else
refresh_chip_req = 0;
end
else
refresh_chip_req = cs_refresh_req;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_seq_busy_r <= 0;
afi_seq_busy_r2 <= 0;
end
else
begin
afi_seq_busy_r <= afi_seq_busy;
afi_seq_busy_r2 <= afi_seq_busy_r;
end
end
// cans
generate
genvar w_cs;
for (w_cs = 0;w_cs < CFG_MEM_IF_CHIP;w_cs = w_cs + 1)
begin : can_signal_per_chip
// Can refresh signal for each rank
always @ (*)
begin
can_refresh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & ~grant;
end
// Can self refresh signal for each rank
always @ (*)
begin
can_self_rfsh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & tcom_not_running_pipe[w_cs][cfg_tcl] & ~grant;
end
always @ (*)
begin
can_deep_pdown [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & ~grant;
end
// Can power down signal for each rank
always @ (*)
begin
can_power_down [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & tcom_not_running_pipe[w_cs][cfg_tcl] & ~grant;
end
// Can exit power saving mode signal for each rank
always @ (*)
begin
can_exit_power_saving_mode [w_cs] = power_saving_exit_ready [w_cs];
end
end
endgenerate
/*------------------------------------------------------------------------------
[START] Power Saving Rank Monitor
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Power Saving State Machine
------------------------------------------------------------------------------*/
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : power_saving_logic_per_chip
reg [POWER_SAVING_COUNTER_WIDTH - 1 : 0] power_saving_cnt;
reg [POWER_SAVING_EXIT_COUNTER_WIDTH - 1 : 0] power_saving_exit_cnt;
reg [31 : 0] state;
reg [31 : 0] sideband_state;
reg int_enter_power_saving_ready;
reg int_exit_power_saving_ready;
reg registered_reset;
reg int_zq_cal_req;
reg int_do_power_down;
reg int_do_power_down_r1;
reg int_do_power_down_r2;
reg int_do_self_refresh;
reg int_do_self_refresh_r1;
reg int_do_self_refresh_r2;
reg int_do_self_refresh_r3;
// assignment
assign power_saving_enter_ready [u_cs] = int_enter_power_saving_ready;
assign power_saving_exit_ready [u_cs] = int_exit_power_saving_ready & ~((int_do_power_down & ~int_do_power_down_r1) | (int_do_self_refresh & ~int_do_self_refresh_r1));
assign cs_zq_cal_req [u_cs] = int_zq_cal_req;
// counter for power saving state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
power_saving_cnt <= 0;
else
begin
if (do_precharge_all[u_cs] || do_refresh[u_cs] || do_self_rfsh[u_cs] || do_power_down[u_cs])
power_saving_cnt <= BANK_TIMER_COUNTER_OFFSET;
else if (power_saving_cnt != {POWER_SAVING_COUNTER_WIDTH{1'b1}})
power_saving_cnt <= power_saving_cnt + 1'b1;
end
end
// Do power down and self refresh register
always @ (*)
begin
int_do_power_down = do_power_down[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_power_down_r1 <= 1'b0;
int_do_power_down_r2 <= 1'b0;
end
else
begin
int_do_power_down_r1 <= int_do_power_down;
int_do_power_down_r2 <= int_do_power_down_r1;
end
end
always @ (*)
begin
int_do_self_refresh = do_self_rfsh[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_self_refresh_r1 <= 1'b0;
int_do_self_refresh_r2 <= 1'b0;
int_do_self_refresh_r3 <= 1'b0;
end
else
begin
int_do_self_refresh_r1 <= int_do_self_refresh;
int_do_self_refresh_r2 <= int_do_self_refresh_r1;
int_do_self_refresh_r3 <= int_do_self_refresh_r2;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_saving_exit_cnt <= 0;
end
else
begin
if ((int_do_power_down & !int_do_power_down_r1) || (int_do_self_refresh & !int_do_self_refresh_r1))
begin
power_saving_exit_cnt <= BANK_TIMER_COUNTER_OFFSET;
end
else if (power_saving_exit_cnt != {POWER_SAVING_EXIT_COUNTER_WIDTH{1'b1}})
begin
power_saving_exit_cnt = power_saving_exit_cnt + 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_exit_power_saving_ready <= 1'b0;
end
else
begin
if (( int_do_power_down) && (!int_do_power_down_r1)) // positive edge detector but late by one clock cycle
begin
int_exit_power_saving_ready <= 1'b0;
end
else if (( int_do_self_refresh ) && (!int_do_self_refresh_r1 )) // positive edge detector
begin
int_exit_power_saving_ready <= 1'b0;
end
else if (power_saving_exit_cnt >= t_param_power_saving_exit)
begin
int_exit_power_saving_ready <= 1'b1;
end
else
begin
int_exit_power_saving_ready <= 1'b0;
end
end
end
// stall_chip output signal
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
stall_chip[u_cs] = int_stall_chip[u_cs] | int_stall_chip_combi[u_cs];
end
else
begin
stall_chip[u_cs] = int_stall_chip[u_cs];
end
end
// int_stall_chip_combi signal, we need to issue stall chip one clock cycle earlier to rank timer
// because rank timer is using a register output
always @ (*)
begin
if (state == IDLE)
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
// command issuing state machine
always @(posedge ctl_clk, negedge ctl_reset_n)
begin : FSM
if (!ctl_reset_n)
begin
state <= INIT;
int_stall_chip[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
do_power_down[u_cs] <= 1'b0;
do_deep_pdown[u_cs] <= 1'b0;
do_self_rfsh_req[u_cs] <= 1'b0;
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
do_pch_all_req[u_cs] <= 1'b0;
do_refresh_req[u_cs] <= 1'b0;
afi_ctl_refresh_done[u_cs] <= 1'b0;
afi_ctl_long_idle[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
dqslong_exit[u_cs] <= 1'b0;
end
else
case(state)
INIT :
if (ctl_cal_success == 1'b1)
begin
state <= IDLE;
int_stall_chip[u_cs] <= 1'b0;
end
else
begin
state <= INIT;
int_stall_chip[u_cs] <= 1'b1;
end
IDLE :
begin
do_pch_all_req[u_cs] <= 1'b0;
if (do_zqcal_req[u_cs])
begin
if (do_zqcal[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
else if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= REFRESH;
else
state <= PCHALL;
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= SELFRFSH;
else
state <= PCHALL;
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= DEEPPDN;
else
state <= PCHALL;
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= PDOWN;
else
state <= PCHALL;
end
else if (int_stall_chip[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
int_stall_chip[u_cs] <= 1'b0;
end
PCHALL :
begin
if (refresh_chip_req[u_cs] | self_refresh_chip_req[u_cs] | power_down_chip_req_combi[u_cs])
begin
if (do_precharge_all[u_cs] || all_banks_closed[u_cs])
begin
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (refresh_chip_req[u_cs])
state <= REFRESH;
else if (self_refresh_chip_req[u_cs])
state <= SELFRFSH;
else state <= PDOWN;
end
else if (refresh_chip_req[u_cs])
begin
if ((~all_banks_closed&refresh_chip_req)==(~all_banks_closed&tcom_not_running&refresh_chip_req) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (self_refresh_chip_req[u_cs])
begin
if ((~all_banks_closed&self_refresh_chip_req)==(~all_banks_closed&tcom_not_running&self_refresh_chip_req) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (&tcom_not_running && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
state <= IDLE;
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
REFRESH :
begin
if (do_refresh[u_cs])
begin
do_refresh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_enable_dqs_tracking && &do_refresh)
state <= DQSTRK;
else if (!refresh_chip_req[u_cs] && power_down_chip_req_combi[u_cs])
state <= PDOWN;
else
state <= IDLE;
end
else if (refresh_chip_req[u_cs])
begin
if (!all_banks_closed[u_cs])
state <= PCHALL;
else if (refresh_chip_req==(can_refresh&refresh_chip_req))
begin
do_refresh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
state <= IDLE;
stall_arbiter[u_cs] <= 1'b0;
end
end
DQSTRK :
begin
if (!dqstrk_exit[u_cs] && !afi_ctl_refresh_done[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
afi_ctl_refresh_done[u_cs] <= 1'b1;
else if (!dqstrk_exit[u_cs] && afi_seq_busy_r2[u_cs] && afi_ctl_refresh_done[u_cs]) // stall until seq_busy is deasserted
dqstrk_exit[u_cs] <= 1;
else if (dqstrk_exit[u_cs] && !afi_seq_busy_r2[u_cs])
begin
afi_ctl_refresh_done[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
if (!refresh_chip_req[u_cs] && power_down_chip_req_combi[u_cs])
state <= PDOWN;
else
state <= IDLE;
end
end
DQSLONG :
begin
if (do_zqcal[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
if (!dqslong_exit[u_cs] && !afi_ctl_long_idle[u_cs] && power_saving_enter_ready[u_cs])
afi_ctl_long_idle[u_cs] <= 1'b1;
else if (!dqslong_exit[u_cs] && afi_seq_busy_r2[u_cs] && afi_ctl_long_idle[u_cs])
dqslong_exit[u_cs] <= 1;
else if (dqslong_exit[u_cs] && !afi_seq_busy_r2[u_cs])
begin
afi_ctl_long_idle[u_cs] <= 1'b0;
dqslong_exit[u_cs] <= 1'b0;
state <= IDLE;
end
end
PDOWN :
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs] && can_exit_power_saving_mode[u_cs])
begin
state <= REFRESH;
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
else if (!power_down_chip_req_combi[u_cs] && can_exit_power_saving_mode[u_cs])
begin
if (self_refresh_chip_req[u_cs])
state <= SELFRFSH;
else
state <= IDLE;
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
else if (&can_power_down && !(|refresh_chip_req))
begin
do_power_down[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
else
state <= PDOWN;
end
DEEPPDN :
begin
if (!deep_pdown_chip_req[u_cs] && can_exit_power_saving_mode[u_cs])
begin
do_deep_pdown[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_enable_dqs_tracking)
state <= DQSLONG;
else
state <= IDLE;
end
else if (can_deep_pdown[u_cs] && !do_precharge_all[u_cs])
begin
do_deep_pdown[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
SELFRFSH :
begin
if (!all_banks_closed[u_cs])
state <= PCHALL;
else if (!self_refresh_chip_req[u_cs] && can_exit_power_saving_mode[u_cs])
begin
do_self_rfsh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_type == `MMR_TYPE_DDR3) // DDR3
begin
state <= ZQCAL;
doing_zqcal[u_cs] <= 1'b1;
end
else if (cfg_enable_dqs_tracking && &do_self_rfsh)
state <= DQSLONG;
else
state <= IDLE;
end
else if (self_refresh_chip_req==(can_self_rfsh&self_refresh_chip_req) && !(|do_precharge_all))
begin
do_self_rfsh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
ZQCAL :
begin
if (cs_zq_cal_req[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
if (cfg_enable_dqs_tracking && &cs_zq_cal_req)
state <= DQSLONG;
else
state <= IDLE;
end
end
default : state <= IDLE;
endcase
end
// sideband state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b0;
int_zq_cal_req <= 1'b0;
end
else
begin
case (sideband_state)
IDLE :
begin
int_zq_cal_req <= 1'b0;
if (power_saving_cnt >= t_param_pch_all_to_valid)
int_enter_power_saving_ready <= 1'b1;
else
int_enter_power_saving_ready <= 1'b0;
if (do_precharge_all[u_cs])
begin
int_enter_power_saving_ready <= 1'b0;
end
if (do_refresh[u_cs])
begin
sideband_state <= ARF;
int_enter_power_saving_ready <= 1'b0;
end
if (do_self_rfsh[u_cs])
begin
sideband_state <= SRF;
int_enter_power_saving_ready <= 1'b0;
end
if (do_power_down[u_cs])
begin
sideband_state <= PDN;
int_enter_power_saving_ready <= 1'b0;
end
end
ARF :
begin
int_zq_cal_req <= 1'b0;
if (power_saving_cnt >= t_param_arf_to_valid)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= ARF;
int_enter_power_saving_ready <= 1'b0;
end
end
SRF :
begin
// ZQ request to state machine
if (power_saving_cnt == t_param_srf_to_zq_cal) // only one cycle
int_zq_cal_req <= 1'b1;
else
int_zq_cal_req <= 1'b0;
if (!do_self_rfsh[u_cs] && power_saving_cnt >= t_param_srf_to_valid)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= SRF;
int_enter_power_saving_ready <= 1'b0;
end
end
PDN :
begin
int_zq_cal_req <= 1'b0;
if (!do_power_down[u_cs] && power_saving_cnt >= t_param_pdn_to_valid)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= PDN;
int_enter_power_saving_ready <= 1'b0;
end
end
default :
begin
sideband_state <= IDLE;
end
endcase
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Refresh Request
------------------------------------------------------------------------------*/
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : auto_refresh_logic_per_chip
reg [ARF_COUNTER_WIDTH - 1 : 0] refresh_cnt;
// refresh counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_cnt <= 0;
end
else
begin
if (self_rfsh_req && |self_rfsh_chip && !self_rfsh_req_r)
refresh_cnt <= {ARF_COUNTER_WIDTH{1'b1}};
else if (do_refresh[s_cs])
refresh_cnt <= 3;
else if (refresh_cnt != {ARF_COUNTER_WIDTH{1'b1}})
refresh_cnt <= refresh_cnt + 1'b1;
end
end
// refresh request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cs_refresh_req [s_cs] <= 1'b0;
end
else
begin
if (self_rfsh_req && |self_rfsh_chip && !self_rfsh_req_r)
cs_refresh_req [s_cs] <= 1'b1;
else if (do_refresh[s_cs] || do_self_rfsh[s_cs])
cs_refresh_req [s_cs] <= 1'b0;
else if (refresh_cnt >= t_param_arf_period)
cs_refresh_req [s_cs] <= 1'b1;
else
cs_refresh_req [s_cs] <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Power Down Request
------------------------------------------------------------------------------*/
// register no command signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
no_command_r1 <= 1'b0;
end
else
begin
no_command_r1 <= tbp_empty;
end
end
// power down counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_cnt <= 0;
end
else
begin
if ((!tbp_empty && no_command_r1) || self_rfsh_req) // negative edge detector
power_down_cnt <= 3;
else if (tbp_empty && power_down_cnt != {PDN_COUNTER_WIDTH{1'b1}} && ctl_cal_success)
power_down_cnt <= power_down_cnt + 1'b1;
end
end
// power down request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_chip_req <= 0;
end
else
begin
if (t_param_pdn_period == 0) // when auto power down cycles is set to '0', auto power down mode will be disabled
power_down_chip_req <= 0;
else
begin
if (!tbp_empty || self_rfsh_req) // we need to make sure power down request to go low as fast as possible to avoid unnecessary power down
power_down_chip_req <= 0;
else if (power_down_chip_req == 0)
begin
if (power_down_cnt >= t_param_pdn_period && !(|doing_zqcal))
power_down_chip_req <= {CFG_MEM_IF_CHIP{1'b1}};
else
power_down_chip_req <= 0;
end
else if (!(power_down_cnt >= t_param_pdn_period))
power_down_chip_req <= 0;
end
end
end
assign power_down_chip_req_combi = power_down_chip_req & {CFG_MEM_IF_CHIP{tbp_empty}} & {CFG_MEM_IF_CHIP{~(|refresh_chip_req)}};
/*------------------------------------------------------------------------------
[END] Power Saving Rank Monitor
------------------------------------------------------------------------------*/
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_tbp
#( parameter
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
CFG_ENABLE_SHADOW_TBP = 0,
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary encoded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_DATA_ID_WIDTH = 10,
CFG_REG_REQ = 0,
CFG_REG_GRANT = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_DISABLE_READ_REODERING = 0,
CFG_DISABLE_PRIORITY = 0,
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_TYPE = 3,
T_PARAM_ACT_TO_RDWR_WIDTH = 4,
T_PARAM_ACT_TO_ACT_WIDTH = 4,
T_PARAM_ACT_TO_PCH_WIDTH = 4,
T_PARAM_RD_TO_PCH_WIDTH = 4,
T_PARAM_WR_TO_PCH_WIDTH = 4,
T_PARAM_PCH_TO_VALID_WIDTH = 4,
T_PARAM_RD_AP_TO_VALID_WIDTH = 4,
T_PARAM_WR_AP_TO_VALID_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
// Cmd gen interface
tbp_full,
tbp_empty,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// Arbiter interface
row_req,
act_req,
pch_req,
row_grant,
act_grant,
pch_grant,
col_req,
rd_req,
wr_req,
col_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_read,
tbp_write,
tbp_precharge,
tbp_activate,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_age,
tbp_priority,
tbp_rmw_correct,
tbp_rmw_partial,
sb_tbp_precharge_all,
sb_do_precharge_all,
// Timer value
t_param_act_to_rdwr,
t_param_act_to_act,
t_param_act_to_pch,
t_param_rd_to_pch,
t_param_wr_to_pch,
t_param_pch_to_valid,
t_param_rd_ap_to_valid,
t_param_wr_ap_to_valid,
// Misc interface
tbp_bank_active,
tbp_timer_ready,
tbp_load,
data_complete,
// Config interface
cfg_reorder_data,
cfg_starve_limit,
cfg_type
);
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam TBP_COUNTER_OFFSET = (CFG_REG_GRANT) ? 2 : 1;
localparam RDWR_AP_TO_VALID_WIDTH = (T_PARAM_RD_AP_TO_VALID_WIDTH > T_PARAM_WR_AP_TO_VALID_WIDTH) ? T_PARAM_RD_AP_TO_VALID_WIDTH : T_PARAM_WR_AP_TO_VALID_WIDTH;
localparam COL_TIMER_WIDTH = T_PARAM_ACT_TO_RDWR_WIDTH;
localparam ROW_TIMER_WIDTH = (T_PARAM_ACT_TO_ACT_WIDTH > RDWR_AP_TO_VALID_WIDTH) ? T_PARAM_ACT_TO_ACT_WIDTH : RDWR_AP_TO_VALID_WIDTH;
localparam TRC_TIMER_WIDTH = T_PARAM_ACT_TO_ACT_WIDTH;
// Start of port declaration
input ctl_clk;
input ctl_reset_n;
output tbp_full;
output tbp_empty;
input cmd_gen_load;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
input cmd_gen_write;
input cmd_gen_read;
input [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
input [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
input cmd_gen_priority;
input cmd_gen_rmw_correct;
input cmd_gen_rmw_partial;
input cmd_gen_autopch;
input cmd_gen_complete;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output [CFG_CTL_TBP_NUM-1:0] row_req;
output [CFG_CTL_TBP_NUM-1:0] act_req;
output [CFG_CTL_TBP_NUM-1:0] pch_req;
input [CFG_CTL_TBP_NUM-1:0] row_grant;
input [CFG_CTL_TBP_NUM-1:0] act_grant;
input [CFG_CTL_TBP_NUM-1:0] pch_grant;
output [CFG_CTL_TBP_NUM-1:0] col_req;
output [CFG_CTL_TBP_NUM-1:0] rd_req;
output [CFG_CTL_TBP_NUM-1:0] wr_req;
input [CFG_CTL_TBP_NUM-1:0] col_grant;
input [CFG_CTL_TBP_NUM-1:0] rd_grant;
input [CFG_CTL_TBP_NUM-1:0] wr_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_row_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_col_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_act_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_pch_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_rd_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_wr_grant;
input or_row_grant;
input or_col_grant;
output [CFG_CTL_TBP_NUM-1:0] tbp_read;
output [CFG_CTL_TBP_NUM-1:0] tbp_write;
output [CFG_CTL_TBP_NUM-1:0] tbp_precharge;
output [CFG_CTL_TBP_NUM-1:0] tbp_activate;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
output [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
output [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_ap;
output [CFG_CTL_TBP_NUM-1:0] tbp_burst_chop;
output [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
output [CFG_CTL_TBP_NUM-1:0] tbp_priority;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
input [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
input [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] t_param_act_to_rdwr;
input [T_PARAM_ACT_TO_ACT_WIDTH-1:0] t_param_act_to_act;
input [T_PARAM_ACT_TO_PCH_WIDTH-1:0] t_param_act_to_pch;
input [T_PARAM_RD_TO_PCH_WIDTH-1:0] t_param_rd_to_pch;
input [T_PARAM_WR_TO_PCH_WIDTH-1:0] t_param_wr_to_pch;
input [T_PARAM_PCH_TO_VALID_WIDTH-1:0] t_param_pch_to_valid;
input [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] t_param_rd_ap_to_valid;
input [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] t_param_wr_ap_to_valid;
output [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
output [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
output [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input [CFG_PORT_WIDTH_REORDER_DATA-1:0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] cfg_starve_limit;
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
// End of port declaration
// Logic operators
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load;
wire [CFG_CTL_TBP_NUM-1:0] load_tbp;
reg [CFG_CTL_TBP_NUM-1:0] load_tbp_index;
wire [CFG_CTL_TBP_NUM-1:0] flush_tbp;
reg [CFG_CTL_TBP_NUM-1:0] precharge_tbp;
reg [CFG_CTL_TBP_NUM-1:0] row_req;
reg [CFG_CTL_TBP_NUM-1:0] act_req;
reg [CFG_CTL_TBP_NUM-1:0] pch_req;
reg [CFG_CTL_TBP_NUM-1:0] col_req;
reg [CFG_CTL_TBP_NUM-1:0] rd_req;
reg [CFG_CTL_TBP_NUM-1:0] wr_req;
reg int_tbp_full;
wire int_tbp_empty;
reg [CFG_CTL_TBP_NUM-1:0] valid;
wire [CFG_CTL_TBP_NUM-1:0] valid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] write;
reg [CFG_CTL_TBP_NUM-1:0] read;
wire [CFG_CTL_TBP_NUM-1:0] precharge;
wire [CFG_CTL_TBP_NUM-1:0] activate;
reg [CFG_INT_SIZE_WIDTH-1:0] size [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] autopch;
reg [CFG_LOCAL_ID_WIDTH-1:0] localid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] priority_a;
reg [CFG_CTL_TBP_NUM-1:0] activated;
reg [CFG_CTL_TBP_NUM-1:0] activated_p;
reg [CFG_CTL_TBP_NUM-1:0] activated_combi;
reg [CFG_CTL_TBP_NUM-1:0] precharged;
reg [CFG_CTL_TBP_NUM-1:0] precharged_combi;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_r;
wire [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush_r [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] done;
reg [CFG_CTL_TBP_NUM-1:0] done_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete;
reg [CFG_CTL_TBP_NUM-1:0] complete_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_wr;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_wr;
reg [CFG_CTL_TBP_NUM-1:0] wst;
reg [CFG_CTL_TBP_NUM-1:0] wst_p;
reg [CFG_CTL_TBP_NUM-1:0] ssb;
reg [CFG_CTL_TBP_NUM-1:0] ssbr;
reg [CFG_CTL_TBP_NUM-1:0] ap;
reg [CFG_CTL_TBP_NUM-1:0] real_ap;
reg [CFG_CTL_TBP_NUM-1:0] rmw_correct;
reg [CFG_CTL_TBP_NUM-1:0] rmw_partial;
reg [CFG_CTL_TBP_NUM-1:0] require_flush;
reg [CFG_CTL_TBP_NUM-1:0] require_flush_calc;
reg [CFG_CTL_TBP_NUM-1:0] require_pch_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] require_pch;
reg [CFG_CTL_TBP_NUM-1:0] burst_chop;
reg [CFG_CTL_TBP_NUM-1:0] age [CFG_CTL_TBP_NUM-1:0];
reg [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] starvation [CFG_CTL_TBP_NUM-1:0];
// bit vectors
reg [CFG_CTL_TBP_NUM-1:0] apvo_combi; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvo; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvc_combi; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] apvc; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] or_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_rpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_cpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbv;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbvt;
wire [CFG_CTL_TBP_NUM-1:0] tbp_read;
wire [CFG_CTL_TBP_NUM-1:0] tbp_write;
wire [CFG_CTL_TBP_NUM-1:0] tbp_ap;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
wire [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
wire [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
wire [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
wire [CFG_CTL_TBP_NUM-1:0] tbp_priority;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
wire [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
reg [CFG_MEM_IF_CHIP-1:0] bank_active;
reg [CFG_MEM_IF_CHIP-1:0] timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] int_bank_active [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] int_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_shadow_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] same_command_read;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_diff_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_command_read;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_diff_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank;
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_diff_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] pre_calculated_same_shadow_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [COL_TIMER_WIDTH-1:0] col_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] col_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] col_timer_pre_ready;
reg [ROW_TIMER_WIDTH-1:0] row_timer_combi [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] row_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] row_timer_pre_ready;
reg [TRC_TIMER_WIDTH-1:0] trc_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready_combi;
reg [CFG_CTL_TBP_NUM-1:0] pch_ready;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_ap_to_valid_greater_than_trc_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_ap_to_valid_greater_than_trc_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_to_pch_greater_than_row_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_to_pch_greater_than_row_timer;
reg compare_t_param_act_to_rdwr_less_than_offset;
reg compare_t_param_act_to_act_less_than_offset;
reg compare_t_param_act_to_pch_less_than_offset;
reg compare_t_param_rd_to_pch_less_than_offset;
reg compare_t_param_wr_to_pch_less_than_offset;
reg compare_t_param_pch_to_valid_less_than_offset;
reg compare_t_param_rd_ap_to_valid_less_than_offset;
reg compare_t_param_wr_ap_to_valid_less_than_offset;
reg compare_offset_t_param_act_to_rdwr_less_than_0;
reg compare_offset_t_param_act_to_rdwr_less_than_1;
reg [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] offset_t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_ACT_WIDTH-1:0] offset_t_param_act_to_act;
reg [T_PARAM_ACT_TO_PCH_WIDTH-1:0] offset_t_param_act_to_pch;
reg [T_PARAM_RD_TO_PCH_WIDTH-1:0] offset_t_param_rd_to_pch;
reg [T_PARAM_WR_TO_PCH_WIDTH-1:0] offset_t_param_wr_to_pch;
reg [T_PARAM_PCH_TO_VALID_WIDTH-1:0] offset_t_param_pch_to_valid;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] offset_t_param_rd_ap_to_valid;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] offset_t_param_wr_ap_to_valid;
reg [CFG_CTL_TBP_NUM-1:0] can_act;
reg [CFG_CTL_TBP_NUM-1:0] can_pch;
reg [CFG_CTL_TBP_NUM-1:0] can_rd;
reg [CFG_CTL_TBP_NUM-1:0] can_wr;
reg [CFG_CTL_TBP_NUM-1:0] finish_tbp;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] flush_shadow_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] shadow_row_timer [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_pre_ready;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_ready;
wire one = 1'b1;
wire zero = 1'b0;
integer i;
integer j;
genvar k;
//----------------------------------------------------------------------------------------------------
// Output port assignments
//----------------------------------------------------------------------------------------------------
assign tbp_read = read;
assign tbp_write = write;
assign tbp_ap = real_ap;
assign tbp_burst_chop = burst_chop;
assign tbp_precharge = precharge;
assign tbp_activate = activate;
assign tbp_priority = priority_a;
assign tbp_rmw_correct = rmw_correct;
assign tbp_rmw_partial = rmw_partial;
generate
begin
for(k=0; k<CFG_CTL_TBP_NUM; k=k+1)
begin : tbp_name
assign tbp_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = chipsel[k];
assign tbp_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = bank [k];
assign tbp_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = row [k];
assign tbp_col [(k*CFG_MEM_IF_COL_WIDTH)+CFG_MEM_IF_COL_WIDTH-1:k*CFG_MEM_IF_COL_WIDTH] = col [k];
assign tbp_localid[(k*CFG_LOCAL_ID_WIDTH)+CFG_LOCAL_ID_WIDTH-1:k*CFG_LOCAL_ID_WIDTH] = localid[k];
assign tbp_dataid [(k*CFG_DATA_ID_WIDTH)+CFG_DATA_ID_WIDTH-1:k*CFG_DATA_ID_WIDTH] = dataid [k];
assign tbp_age [(k*CFG_CTL_TBP_NUM)+CFG_CTL_TBP_NUM-1:k*CFG_CTL_TBP_NUM] = age [k];
assign tbp_size [(k*CFG_INT_SIZE_WIDTH)+CFG_INT_SIZE_WIDTH-1:k*CFG_INT_SIZE_WIDTH] = size [k];
end
for(k=0; k<CFG_CTL_SHADOW_TBP_NUM; k=k+1)
begin : tbp_shadow_name
if (CFG_ENABLE_SHADOW_TBP)
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = shadow_chipsel[k];
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = shadow_bank [k];
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = shadow_row [k];
end
else
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = 0;
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = 0;
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = 0;
end
end
end
endgenerate
assign tbp_full = int_tbp_full;
assign tbp_empty = int_tbp_empty;
assign int_tbp_empty = &(valid ^~ done); // empty if valid and done are the same
assign load_tbp = (~int_tbp_full & cmd_gen_load) ? load_tbp_index : 0;
assign flush_tbp = open_row_pass_flush_r | finish_tbp | (done & precharge_tbp);
assign tbp_load = load_tbp;
assign tbp_bank_active = bank_active;
assign tbp_timer_ready = timer_ready;
assign precharge = activated;
assign activate = ~activated;
//----------------------------------------------------------------------------------------------------
// TBP General Functions
//----------------------------------------------------------------------------------------------------
assign valid_combi = (valid | load_tbp) & ~flush_tbp;
// Decide which TBP to load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
load_tbp_index <= 0;
end
else
begin
load_tbp_index <= ~valid_combi & (valid_combi + 1);
end
end
// Assert when TBP is full to prevent further load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tbp_full <= 0;
end
else
begin
int_tbp_full <= &valid_combi;
end
end
//----------------------------------------------------------------------------------------------------
// Finish TBP
//----------------------------------------------------------------------------------------------------
// Logic to determine when can we flush a done TBP
// in non-shadow TBP case, we can only flush once the timer finished counting
// in shadow TBP case, we can flush once it is pushed into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
finish_tbp[i] = push_tbp[i] | (done[i] & precharged[i] & row_timer_pre_ready[i]);
end
else
begin
finish_tbp[i] = done[i] & precharged[i] & row_timer_pre_ready[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Shadow TBP Logic
//----------------------------------------------------------------------------------------------------
// Determine when can we flush TBP
assign flush_shadow_tbp = shadow_valid & shadow_row_timer_pre_ready;
// Determine when it's ready to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_tbp[i]) // TBP might flush before shadow TBP is still allocated
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if ((col_grant[i] && real_ap[i]) || (pch_grant[i] && done[i])) // indicate ready to push TBP once TBP is done
begin
ready_to_push_tbp_combi[i] = 1'b1;
end
else
begin
ready_to_push_tbp_combi[i] = ready_to_push_tbp[i];
end
end
else
begin
ready_to_push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= ready_to_push_tbp_combi[i];
end
end
end
// Determine when to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
push_tbp_combi[i] = 1'b0;
end
else if (ready_to_push_tbp_combi[i] && shadow_row_timer_pre_ready[i]) // prevent pushing into an allocated shadow TBP
begin
push_tbp_combi[i] = 1'b1;
end
else
begin
push_tbp_combi[i] = push_tbp[i];
end
end
else
begin
push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= push_tbp_combi[i];
end
end
end
// Shadow TBP information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp_combi[i])
begin
shadow_chipsel[i] <= chipsel[i];
shadow_bank [i] <= bank [i];
shadow_row [i] <= row [i];
end
end
else
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_shadow_tbp[i])
begin
shadow_valid[i] <= 1'b0;
end
else if (push_tbp[i])
begin
shadow_valid[i] <= 1'b1;
end
end
else
begin
shadow_valid[i] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i])
begin
if (!row_timer_pre_ready[i] || !trc_timer_pre_ready[i])
begin
// Decide to take the larger timer value between row/trc timer
if (row_timer[i] > trc_timer[i])
begin
shadow_row_timer[i] <= row_timer[i] - 1'b1;
end
else
begin
shadow_row_timer[i] <= trc_timer[i] - 1'b1;
end
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b1;
shadow_row_timer_ready [i] <= 1'b1;
end
end
else
begin
if (shadow_row_timer[i] != 0)
begin
shadow_row_timer[i] <= shadow_row_timer[i] - 1'b1;
end
if (shadow_row_timer[i] <= 1)
begin
shadow_row_timer_ready[i] <= 1'b1;
end
if (shadow_row_timer[i] <= 2)
begin
shadow_row_timer_pre_ready[i] <= 1'b1;
end
end
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Request logic
//----------------------------------------------------------------------------------------------------
// Can_* logic for request logic, indicate whether TBP can request now
// Can activate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_act[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (activated_combi[i]) // activated, so there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (col_grant[i]) //done, there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (load_tbp[i]) // new TBP command, assume no open-row-pass (handled by statement above)
begin
can_act[i] <= 1'b1;
end
else if
(
!done[i] && valid[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
)
// precharge or precharge all command, re-enable since it is not done
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_act[i] <= 1'b1;
end
end
end
end
// Can precharge
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= one; // there is no logic required for precharge, keeping this for future use
end
end
end
// Can read
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_rd[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_rd[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't read since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_rd[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_rd[i] <= 1'b1;
end
end
end
end
// Can write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_wr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_wr[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't write since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_wr[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_wr[i] <= 1'b1;
end
end
end
end
// Row request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_req[i] = act_req[i] | pch_req[i];
end
end
// Column request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_req[i] = rd_req[i] | wr_req[i];
end
end
// Individual activate, precharge, read and write request logic
always @ (*)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
act_req[i] = nor_rpv[i] & nor_sbv[i] & nor_sbvt[i] & ~or_wrt[i] & can_act[i];
pch_req[i] = require_pch[i] & pch_ready[i] & can_pch[i];
rd_req [i] = nor_cpv[i] & can_rd[i] & complete_rd[i];
wr_req [i] = nor_cpv[i] & can_wr[i] & complete_wr[i];
end
end
//----------------------------------------------------------------------------------------------------
// Valid logic
//----------------------------------------------------------------------------------------------------
// Indicates that current TBP is valid after load an invalid after flush
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
valid[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
valid[i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// TBP information
//----------------------------------------------------------------------------------------------------
// Keeps information from cmd_gen after load
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
chipsel [i] <= 0;
bank [i] <= 0;
row [i] <= 0;
col [i] <= 0;
write [i] <= 0;
read [i] <= 0;
size [i] <= 0;
autopch [i] <= 0;
localid [i] <= 0;
dataid [i] <= 0;
rmw_correct[i] <= 0;
rmw_partial[i] <= 0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
chipsel [i] <= cmd_gen_chipsel;
bank [i] <= cmd_gen_bank;
row [i] <= cmd_gen_row;
col [i] <= cmd_gen_col;
write [i] <= cmd_gen_write;
read [i] <= cmd_gen_read;
size [i] <= cmd_gen_size;
autopch [i] <= cmd_gen_autopch;
localid [i] <= cmd_gen_localid;
dataid [i] <= cmd_gen_dataid;
rmw_correct[i] <= cmd_gen_rmw_correct;
rmw_partial[i] <= cmd_gen_rmw_partial;
end
end
end
// Priority information
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
priority_a[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_DISABLE_PRIORITY == 1)
begin
priority_a[i] <= zero;
end
else
begin
if (load_tbp[i])
begin
if (cfg_reorder_data) // priority will be ignored when data reordering is OFF
begin
priority_a[i] <= cmd_gen_priority;
end
else
begin
priority_a[i] <= 1'b0;
end
end
else if (starvation[i] == cfg_starve_limit) // assert priority when starvation limit is reached
begin
priority_a[i] <= 1'b1;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Row dependency vector
//----------------------------------------------------------------------------------------------------
// RPV, TBP is only allowed to request row command when RPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !push_tbp[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && (same_chip_bank_row[j] || (same_chip_bank[j] && (rmw_partial[j] || rmw_correct[j])))) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && same_chip_bank[j]) ||
(!cfg_reorder_data && valid[j] && same_chip_bank[j])
)
)
// (INTER_ROW) Set RPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set RPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// This is to prevent activate going to the later RMW commands
// (INTER_BANK) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (NON_REORDER) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs, to allow command reordering
begin
rpv_combi[i][j] = 1'b1;
end
else
begin
rpv_combi[i][j] = 1'b0;
end
end
else if (flush_tbp[j] || push_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
rpv_combi[i][j] = 1'b0;
end
else
begin
rpv_combi[i][j] = rpv[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (load_tbp[i])
begin
if (!flush_shadow_tbp[j] && ((shadow_valid[j] && same_shadow_chip_bank[j]) || (push_tbp[j] && same_chip_bank[j])))
// Set Shadow RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else
begin
shadow_rpv_combi[i][j] = 1'b0;
end
end
else if (push_tbp[j] && rpv[i][j])
// If there is a push_tbp and RPV is set to '1'
// We need to shift RPV to Shadow RPV
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else if (flush_shadow_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
shadow_rpv_combi[i][j] = 1'b0;
end
else
begin
shadow_rpv_combi[i][j] = shadow_rpv[i][j];
end
end
else
begin
shadow_rpv_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= ~|{shadow_rpv_combi[i], rpv_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
rpv[i][j] <= 1'b0;
end
else
begin
rpv[i][j] <= rpv_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= shadow_rpv_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Column dependency vector
//----------------------------------------------------------------------------------------------------
// CPV, TBP is only allowed to request column command when CPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !col_grant[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank_row[j] || rmw_partial[j] || rmw_correct[j] || same_command_read[j])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank [j] || rmw_partial[j] || rmw_correct[j] || same_command_read[j])) ||
(!cfg_reorder_data && valid[j] && !done[j])
)
)
// (INTER_ROW) Set CPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_ROW) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (INTER_BANK) Set CPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (INTER_BANK) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_BANK) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (NON_REORDER) Set CPV to '1' when a new TBP is loaded, all column command must be executed in order
begin
cpv_combi[i][j] = 1'b1;
end
else
begin
cpv_combi[i][j] = 1'b0;
end
end
else if (col_grant[j])
// (INTER_ROW) Set CPV to '0' after col_grant
// (INTER_BANK) Set CPV to '0' after col_grant
begin
cpv_combi[i][j] = 1'b0;
end
else
begin
cpv_combi[i][j] = cpv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
cpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= ~|cpv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
cpv[i][j] <= 1'b0;
end
else
begin
cpv[i][j] <= cpv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Activate related logic
//----------------------------------------------------------------------------------------------------
// Open-row-pass flush logic
// after a granted command and WST (open row pass to another TBP with same page from just granted command) OR
// after a done command and WST (open row pass to another TBP with same page from a done command with page open)
// Logic to determine which not-done TBP should be flushed to perform open-row-pass
always @ (*)
begin
not_done_tbp_row_pass_flush = col_grant & wst_p;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= not_done_tbp_row_pass_flush[i];
end
end
end
// Logic to determine which done TBP should be flushed to perform open-row-pass
always @ (*)
begin
done_tbp_row_pass_flush = done & wst_p & ~row_grant & ~precharge_tbp;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (done_tbp_row_pass_flush_r[i])
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
else
begin
done_tbp_row_pass_flush_r[i] <= done_tbp_row_pass_flush[i];
end
end
end
end
// Using done_tbp_row_pass_flush_r to improve timing
// it's acceptable to add one clock cycle latency when performing open-row-pass from a done command
// [REMARK] there is potential to optimize the flush logic (for done-open-row-pass case), because flush_tbp depends on open_row_pass_flush logic
assign open_row_pass_flush = not_done_tbp_row_pass_flush | done_tbp_row_pass_flush;
// Open-row-pass logic, TBP will pass related information to same page command (increase efficiency)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass[i] = |open_row_pass_flush && or_wrt[i] && |(wrt[i] & open_row_pass_flush);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= 1'b0;
open_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= open_row_pass [i];
open_row_pass_flush_r[i] <= open_row_pass_flush[i];
end
end
end
// Activated logic
// indicate that current TBP is activated by activate command or open-row-pass
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (act_grant[i] || open_row_pass[i])
begin
activated_combi[i] = 1'b1;
end
else
begin
activated_combi[i] = 1'b0;
end
end
end
// activated need not to be validated with valid
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated [i] <= 1'b0;
activated_p[i] <= 1'b0;
end
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated_p[i] <= activated_combi[i]; // activated pulse
if (flush_tbp[i] || pch_grant[i])
begin
activated[i] <= 1'b0;
end
else if (precharge_tbp[i])
begin
activated[i] <= 1'b0;
end
else if (activated_combi[i])
begin
activated[i] <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Precharge related logic
//----------------------------------------------------------------------------------------------------
// Precharge all logic
// indicate which TBP is precharged cause of sideband precharge all command
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharge_tbp[i] = sb_tbp_precharge_all[i];
end
end
// Precharge logic
// indicate which TBP is precharged
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
precharged_combi[i] = 1'b0;
end
else if (activated_combi[i] && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW")
// Only required in INTER-ROW reordering case since TBP might request precharge after TBP load
// due to TBP interlock case
begin
precharged_combi[i] = 1'b0;
end
else if (col_grant[i] && real_ap[i])
begin
precharged_combi[i] = 1'b1;
end
else if (pch_grant[i])
begin
precharged_combi[i] = 1'b1;
end
else
begin
precharged_combi[i] = precharged[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= precharged_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Auto-precharge related logic
//----------------------------------------------------------------------------------------------------
// Auto precharge related logic, to determine which TBP should be closed or kept open
// OPP - autoprecharge when there is another command to same chip-bank different row
// CPP - do not autoprecharge when there is another command to the same chip-bank-row
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
apvo_combi[i] = 1'b0;
apvc_combi[i] = 1'b0;
end
else if
(
(load_tbp[i] && CFG_DATA_REORDERING_TYPE == "INTER_ROW") || // load self
(
(|load_tbp && !load_tbp[i]) && // load other TBP
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb[i]) ||
(!cfg_reorder_data && !ssb[i])
)
)
)
// (INTER_ROW) update multiple times whenever there is a load so that it'll get the latest AP info
// (INTER_BANK) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
// (NON_REORDER) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
begin
if
(
(load_tbp[i] && |(valid & same_chip_bank_diff_row) && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_diff_row[i])
)
// (INTER_ROW) on self load, set to '1' if other valid TBP is same-chip-bank-diff-row with self
// set to '1' if there is a new command with same-chip-bank-diff-row with current TBP
begin
apvo_combi[i] = 1'b1;
end
else
begin
apvo_combi[i] = apvo[i];
end
if ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_row[i])
// set to '1' if there is a new command with same-chip-bank-row with current TBP
begin
apvc_combi[i] = 1'b1;
end
else
begin
apvc_combi[i] = apvc[i];
end
end
else
begin
apvo_combi[i] = apvo[i];
apvc_combi[i] = apvc[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= 1'b0;
apvc[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= apvo_combi[i];
apvc[i] <= apvc_combi[i];
end
end
end
// Auto precharge
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (apvc[i]) // keeping a page open have higher priority that keeping a close page (improve efficiency)
begin
ap[i] = 1'b0;
end
else if (apvo[i])
begin
ap[i] = 1'b1;
end
else
begin
ap[i] = autopch[i] | require_flush[i];
end
end
end
// Real auto-precharge
// purpose is to make pipelining easier in the future (if needed)
always @ (*)
begin
real_ap = ap;
end
//----------------------------------------------------------------------------------------------------
// Done logic
//----------------------------------------------------------------------------------------------------
// Indicate that current TBP has finished issuing column command
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (flush_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (col_grant[i])
begin
done_combi[i] = 1'b1;
end
else
begin
done_combi[i] = done[i];
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= done_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Complete logic
//----------------------------------------------------------------------------------------------------
// Indicate that the data for current TBP is complete and ready to be issued
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
if (cmd_gen_read)
begin
complete_combi_rd[i] = cmd_gen_complete;
complete_combi_wr[i] = 1'b0;
end
else
begin
complete_combi_rd[i] = 1'b0;
complete_combi_wr[i] = cmd_gen_complete;
end
end
else if (write[i] && !complete[i])
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = data_complete[i];
end
else
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = complete_wr[i];
end
end
end
always @ (*)
begin
complete_combi = complete_combi_rd | complete_combi_wr;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
complete <= 0;
complete_rd <= 0;
complete_wr <= 0;
end
else
begin
complete <= complete_combi;
complete_rd <= complete_combi_rd;
complete_wr <= complete_combi_wr;
end
end
//----------------------------------------------------------------------------------------------------
// Same bank vector logic
//----------------------------------------------------------------------------------------------------
// This bit vector (same bank vector) is to stop a TBP from requesting activate when another row in the same chip-bank was granted
// SBV stops TBP from requesting activate when there is another same-chip-bank-diff-row was granted
// prevents activate to and activated bank
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
// There is no need to SBV in INTER_BANK case
sbv_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if
(
(load_tbp[i] && !flush_tbp[j] && (activated[j] || activated_combi[j]) && same_chip_bank_diff_row[j]) ||
(activated_combi[j] && valid[i] && pre_calculated_same_chip_bank_diff_row [i][j])
)
// Set SBV to '1' if new TBP is same-chip-bank-diff-row with other existing TBP
// Set SBV to '1' if there is a row_grant or open-row-pass to other existing TBP with same-chip-bank-diff-row
begin
sbv_combi[i][j] = 1'b1;
end
else if (flush_tbp[j] || pch_grant[j] || precharge_tbp[j])
// Set SBV to '0' if there is a flush to other TBP
// Set SBV to '0' if there is a precharge to other TBP
// Set SBV to '0' if there is a precharge all command from sideband
begin
sbv_combi[i][j] = 1'b0;
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= ~|sbv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbv[i][j] <= 1'b0;
end
else
begin
sbv[i][j] <= sbv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank timer vector logic
//----------------------------------------------------------------------------------------------------
// SBTV stops TBP from requesting activate when the timer for same-chip-bank is still running
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_tbp[i])
begin
sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j])
begin
sbvt_combi[i][j] = 1'b0;
end
else if
(
(pch_grant[j] || (col_grant[j] && real_ap[j])) &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when there is a precharge/auto-precharge to same-chip-bank address
begin
sbvt_combi[i][j] = 1'b1;
end
else if
(
precharged[j] && valid[j] &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when same-chip-bank address TBP is still in precharge state
begin
sbvt_combi[i][j] = ~row_timer_pre_ready[j];
end
else
begin
sbvt_combi[i][j] = zero;
end
end
else
begin
sbvt_combi[i][j] = sbvt[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
shadow_sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_shadow_tbp[j])
begin
shadow_sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j] && sbvt[i][j])
begin
shadow_sbvt_combi[i][j] = 1'b1;
end
else if (valid[i] && shadow_valid[j] && pre_calculated_same_shadow_chip_bank[i][j])
// Set to 'timer-pre-ready' when own TBP is valid, shadow TBP is valid and same chip-bank address
begin
shadow_sbvt_combi[i][j] = ~shadow_row_timer_pre_ready[j];
end
else
begin
shadow_sbvt_combi[i][j] = shadow_sbvt[i][j];
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbvt[i] <= ~|{shadow_sbvt_combi[i], sbvt_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbvt[i][j] <= 1'b0;
end
else
begin
sbvt[i][j] <= sbvt_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= shadow_sbvt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssb[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssb[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank[i])
begin
ssb[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank row logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank-row with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssbr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssbr[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank_row[i])
begin
ssbr[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will send transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will pass current TBP information (timing/page) over to other TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i]) // Reset back to '0'
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && precharged_combi[i] && done_combi[i]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && precharged_combi[i] ) ||
(!cfg_reorder_data && precharged_combi[i])
)
// Set to '0' when there is a precharge to current TBP, after a precharge, it's not possible to perform open-row-pass anymore
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if (open_row_pass_flush[i]) // make sure open-row-pass only asserts for one clock cycle
begin
wst_p[i] <= 1'b0;
end
else if
(
load_tbp[j] && same_chip_bank_row[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[i] && !(precharged_combi[i] && done_combi[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [i] && !(precharged_combi[i] )) ||
(!cfg_reorder_data && !ssb[i] && !precharged_combi[i])
)
)
// Set to '1' when there is a new TBP being loaded, with same-chip-bank-row with current TBP
// make sure current TBP is not precharged so that information can be pass over to same-chip-bank-row TBP
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
// (INTER_BANK) make sure SSB is not set (only set WST once)
// (NON_REORDER) make sure SSB is not set (only set WST once)
begin
wst [i] <= 1'b1;
wst_p[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will receive transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will receive TBP information (timing/page) from other TBP (also tells which TBP it is receiving from)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if
(
load_tbp[i] && !flush_tbp[j] && valid[j] && same_chip_bank_row[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[j]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [j]) ||
(!cfg_reorder_data && !ssb[j])
)
)
// Set to '1' when there is a new TBp being loaded, with same-chip-bank-row with other existing TBP
// provided other TBP is valid and not precharged
// (INTER_BANK) make sure SSB of other TBP is not set, to handle row interrupt case
begin
wrt_combi[i][j] = 1'b1;
end
else if (flush_tbp[j])
begin
wrt_combi[i][j] = 1'b0;
end
else
begin
wrt_combi[i][j] = wrt[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
wrt [i] <= 0;
or_wrt [i] <= 1'b0;
nor_wrt[i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
or_wrt [i] <= |wrt_combi[i];
nor_wrt[i] <= ~|wrt_combi[i];
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin
if (i == j)
wrt[i][j] <= 1'b0;
else
wrt[i][j] <= wrt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require flush logic
//----------------------------------------------------------------------------------------------------
// On demand flush selection, command with same chip-bank-diff-row first, we dont want to precharge twice
// if there are none, flush cmd to diff chip-bank, we might have cmd to the same row in tbp already
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_flush[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_CTL_TBP_NUM == 1)
begin
require_flush[i] <= cmd_gen_load;
end
else
begin
if (|flush_tbp) // tbp will not be full on the next clock cycle
begin
require_flush[i] <= 1'b0;
end
else if (int_tbp_full && cmd_gen_load)
begin
if (same_chip_bank_row[i])
require_flush[i] <= 1'b0;
else
require_flush[i] <= 1'b1;
end
else
begin
require_flush[i] <= 1'b0;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require precharge logic
//----------------------------------------------------------------------------------------------------
// Precharge request logic, to clear up lockup state in TBP
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
require_pch_combi[i][j] = zero;
end
else
begin
if (i == j)
begin
require_pch_combi[i][j] = 1'b0;
end
else if (activated[i] && !done[i])
begin
if (cpv[i][j] && sbv[j][i])
begin
require_pch_combi[i][j] = 1'b1;
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
require_pch[i] <= 1'b0;
end
else
begin
// included real_ap since real_ap is part of precharge request (!apvc so that it will deassert pch_req when not needed)
require_pch[i] <= |require_pch_combi[i] | (done[i] & real_ap[i] & !apvc_combi[i]);
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Address/command comparison logic
//----------------------------------------------------------------------------------------------------
// Command comparator
always @ (*)
begin
if (CFG_DISABLE_READ_REODERING) // logic only enabled when parameter is set to '1'
begin
same_command_read = cmd_gen_same_read_cmd;
end
else
begin
same_command_read = {CFG_CTL_TBP_NUM{zero}};
end
end
always @ (*)
begin
same_shadow_command_read = {CFG_CTL_SHADOW_TBP_NUM{zero}};
end
// Address comparator
always @(*)
begin
same_chip_bank = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr;
same_chip_bank_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & cmd_gen_same_row_addr;
same_chip_bank_diff_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & ~cmd_gen_same_row_addr;
end
always @ (*)
begin
same_shadow_chip_bank = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr;
same_shadow_chip_bank_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & cmd_gen_same_shadow_row_addr;
same_shadow_chip_bank_diff_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & ~cmd_gen_same_shadow_row_addr;
end
// Registered version, to improve fMAX
generate
begin
genvar i_tbp;
genvar j_tbp;
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop
for (j_tbp = 0;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= same_chip_bank_diff_row [j_tbp];
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= same_chip_bank_row [j_tbp];
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
end
else if (load_tbp [j_tbp])
begin
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] != cmd_gen_row)
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] == cmd_gen_row)
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank)
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
begin
if (row [i_tbp] != row [j_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
end
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop_shadow
for (j_tbp = 0;j_tbp < CFG_CTL_SHADOW_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop_shadow
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
if (push_tbp [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_shadow_chip_bank [j_tbp];
end
else if (push_tbp [j_tbp])
begin
if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == shadow_chipsel [j_tbp] && bank [i_tbp] == shadow_bank [j_tbp])
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Bank specific timer related logic
//----------------------------------------------------------------------------------------------------
// Offset timing paramter to achieve accurate timing gap between commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 0;
compare_t_param_act_to_act_less_than_offset <= 0;
compare_t_param_act_to_pch_less_than_offset <= 0;
compare_t_param_rd_to_pch_less_than_offset <= 0;
compare_t_param_wr_to_pch_less_than_offset <= 0;
compare_t_param_pch_to_valid_less_than_offset <= 0;
compare_t_param_rd_ap_to_valid_less_than_offset <= 0;
compare_t_param_wr_ap_to_valid_less_than_offset <= 0;
compare_offset_t_param_act_to_rdwr_less_than_0 <= 0;
compare_offset_t_param_act_to_rdwr_less_than_1 <= 0;
end
else
begin
if (t_param_act_to_rdwr > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b1;
end
if (t_param_act_to_act > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_act_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_act_less_than_offset <= 1'b1;
end
if (t_param_act_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b1;
end
if (t_param_rd_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b1;
end
if (t_param_wr_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b1;
end
if (t_param_pch_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b1;
end
if (t_param_rd_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b1;
end
if (t_param_wr_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b1;
end
if (offset_t_param_act_to_rdwr <= 0)
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b0;
end
if (offset_t_param_act_to_rdwr <= 1)
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
offset_t_param_act_to_rdwr <= 0;
offset_t_param_act_to_act <= 0;
offset_t_param_act_to_pch <= 0;
offset_t_param_rd_to_pch <= 0;
offset_t_param_wr_to_pch <= 0;
offset_t_param_pch_to_valid <= 0;
offset_t_param_rd_ap_to_valid <= 0;
offset_t_param_wr_ap_to_valid <= 0;
end
else
begin
if (!compare_t_param_act_to_rdwr_less_than_offset)
begin
offset_t_param_act_to_rdwr <= t_param_act_to_rdwr - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_rdwr <= 0;
end
if (!compare_t_param_act_to_act_less_than_offset)
begin
offset_t_param_act_to_act <= t_param_act_to_act - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_act <= 0;
end
if (!compare_t_param_act_to_pch_less_than_offset)
begin
offset_t_param_act_to_pch <= t_param_act_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_pch <= 0;
end
if (!compare_t_param_rd_to_pch_less_than_offset)
begin
offset_t_param_rd_to_pch <= t_param_rd_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_to_pch <= 0;
end
if (!compare_t_param_wr_to_pch_less_than_offset)
begin
offset_t_param_wr_to_pch <= t_param_wr_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_to_pch <= 0;
end
if (!compare_t_param_pch_to_valid_less_than_offset)
begin
offset_t_param_pch_to_valid <= t_param_pch_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_pch_to_valid <= 0;
end
if (!compare_t_param_rd_ap_to_valid_less_than_offset)
begin
offset_t_param_rd_ap_to_valid <= t_param_rd_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_ap_to_valid <= 0;
end
if (!compare_t_param_wr_ap_to_valid_less_than_offset)
begin
offset_t_param_wr_ap_to_valid <= t_param_wr_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_ap_to_valid <= 0;
end
end
end
// Pre-calculated logic to improve timing, for row_timer and trc_timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
compare_t_param_rd_to_pch_greater_than_row_timer [i] <= 1'b0;
compare_t_param_wr_to_pch_greater_than_row_timer [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_REG_GRANT == 0 && open_row_pass[i])
begin
if (t_param_rd_ap_to_valid > ((trc_timer[log2_open_row_pass_flush[i]] > 1) ? (trc_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[log2_open_row_pass_flush[i]] > 1) ? (trc_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[log2_open_row_pass_flush[i]] > 1) ? (row_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[log2_open_row_pass_flush[i]] > 1) ? (row_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
else if (CFG_REG_GRANT == 1 && open_row_pass_r[i])
begin
if (t_param_rd_ap_to_valid > ((trc_timer[log2_open_row_pass_flush_r[i]] > 1) ? (trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[log2_open_row_pass_flush_r[i]] > 1) ? (trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[log2_open_row_pass_flush_r[i]] > 1) ? (row_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[log2_open_row_pass_flush_r[i]] > 1) ? (row_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
else
begin
if (t_param_rd_ap_to_valid > ((trc_timer[i] > 1) ? (trc_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[i] > 1) ? (trc_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
end
end
end
// Column timer logic
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b0;
col_timer_pre_ready[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (row_grant[i])
begin
if (compare_t_param_act_to_rdwr_less_than_offset)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b1;
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer [i] <= offset_t_param_act_to_rdwr;
if (compare_offset_t_param_act_to_rdwr_less_than_0)
begin
col_timer_ready [i] <= 1'b1;
end
else
begin
col_timer_ready [i] <= 1'b0;
end
if (compare_offset_t_param_act_to_rdwr_less_than_1)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
else
begin
if (col_timer[i] != 0)
begin
col_timer[i] <= col_timer[i] - 1'b1;
end
if (col_timer[i] <= 1)
begin
col_timer_ready[i] <= 1'b1;
end
else
begin
col_timer_ready[i] <= 1'b0;
end
if (col_timer[i] <= 2)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
end
// log2 result of open-row-pass-flush, to be used during timer information pass
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush[i] = log2(open_row_pass_flush & wrt[i]);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= log2_open_row_pass_flush[i];
end
end
end
// Row timer logic
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (trc_timer[i] <= 1)
begin
trc_timer_pre_ready_combi[i] = 1'b1;
end
else
begin
trc_timer_pre_ready_combi[i] = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if
(
(CFG_REG_GRANT == 0 && open_row_pass [i]) ||
(CFG_REG_GRANT == 1 && open_row_pass_r[i])
)
begin
if (CFG_REG_GRANT == 0 && !trc_timer_pre_ready_combi[log2_open_row_pass_flush[i]])
begin
trc_timer [i] <= trc_timer[log2_open_row_pass_flush[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if (CFG_REG_GRANT == 1 && !trc_timer_pre_ready[log2_open_row_pass_flush_r[i]])
begin
trc_timer [i] <= trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
end
else if (act_grant[i])
begin
trc_timer [i] <= offset_t_param_act_to_act;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (trc_timer[i] != 0)
begin
trc_timer[i] <= trc_timer[i] - 1'b1;
end
if (trc_timer[i] <= 1)
begin
trc_timer_ready[i] <= 1'b1;
end
if (trc_timer[i] <= 2)
begin
trc_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (rd_grant[i])
begin
if (real_ap[i])
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_ap_to_valid > trc_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_ap_to_valid;
end
else
begin
row_timer_combi[i] = trc_timer[i] - 1'b1;
end
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else if (wr_grant[i])
begin
if (real_ap[i])
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_ap_to_valid > trc_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_ap_to_valid;
end
else
begin
row_timer_combi[i] = trc_timer[i] - 1'b1;
end
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else
begin
if (row_timer[i] != 0)
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
else
begin
row_timer_combi[i] = 0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if
(
(CFG_REG_GRANT == 0 && open_row_pass [i]) ||
(CFG_REG_GRANT == 1 && open_row_pass_r[i])
)
begin
if (CFG_REG_GRANT == 0)
begin
row_timer [i] <= row_timer_combi[log2_open_row_pass_flush[i]];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else if (CFG_REG_GRANT == 1 && !row_timer_pre_ready[log2_open_row_pass_flush_r[i]])
begin
row_timer [i] <= row_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
row_timer [i] <= 1'b0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
end
else if (act_grant[i])
begin
if (compare_t_param_act_to_pch_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRAS after precharge command
row_timer [i] <= offset_t_param_act_to_pch;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (pch_grant[i])
begin
if (compare_t_param_pch_to_valid_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRP after precharge command
row_timer [i] <= offset_t_param_pch_to_valid;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (col_grant[i])
begin
row_timer [i] <= row_timer_combi[i];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (row_timer[i] != 0)
begin
row_timer[i] <= row_timer[i] - 1'b1;
end
if (row_timer[i] <= 1)
begin
row_timer_ready[i] <= 1'b1;
end
if (row_timer[i] <= 2)
begin
row_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
// Logic to let precharge request logic that it is ready to request now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
pch_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i] || open_row_pass_r[i] || pch_grant[i] || col_grant[i])
// disable pch_ready after open-row-pass and grant
// since precharge is not needed immediately after TBP is loaded
begin
pch_ready[i] <= 1'b0;
end
else if (row_timer_pre_ready[i])
begin
pch_ready[i] <= 1'b1;
end
else
begin
pch_ready[i] <= 1'b0;
end
end
end
end
// Logic to let sideband know which chip contains active banks
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_bank_active[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i && valid[j])
begin
if (sb_tbp_precharge_all[j])
begin
int_bank_active[i][j] <= 1'b0;
end
else if (precharged_combi[j])
begin
int_bank_active[i][j] <= 1'b0;
end
else if (activated_combi[j])
begin
int_bank_active[i][j] <= 1'b1;
end
end
else
begin
int_bank_active[i][j] <= 1'b0; // else default to '0'
end
end
end
end
end
// Logic to let sideband know which chip contains running timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i)
begin
if (col_grant[j] || row_grant[j])
begin
int_timer_ready[i][j] <= 1'b0;
end
else if (trc_timer_pre_ready[j] && row_timer_pre_ready[j])
begin
int_timer_ready[i][j] <= 1'b1;
end
else
begin
int_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (shadow_chipsel[j] == i)
begin
if (push_tbp[j])
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
else if (shadow_row_timer_pre_ready[j])
begin
int_shadow_timer_ready[i][j] <= 1'b1;
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
else
begin
int_shadow_timer_ready[i][j] <= one;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
bank_active[i] = |int_bank_active[i];
timer_ready[i] = &{int_shadow_timer_ready[i], int_timer_ready[i]};
end
end
//----------------------------------------------------------------------------------------------------
// Age logic
//----------------------------------------------------------------------------------------------------
// To tell the current age of each TBP entry
// so that arbiter will be able to grant the oldest entry (if there is a tie-break)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
age[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
age[i][j] <= 1'b0;
end
else
begin
if (load_tbp[i])
if (!flush_tbp[j] && (valid[j]))
age[i][j] <= 1'b1;
else
age[i][j] <= 1'b0;
else if (flush_tbp[j])
age[i][j] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Starvation logic
//----------------------------------------------------------------------------------------------------
// Logic will increments when there is a col_grant to other TBP
// will cause priority to be asserted when the count reaches starvation threshold
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
starvation[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i] || done[i]) // stop starvation count when the current TBP is done
starvation[i] <= 0;
else if (|col_grant && starvation[i] < cfg_starve_limit)
starvation[i] <= starvation[i]+1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Burst chop logic
//----------------------------------------------------------------------------------------------------
// Logic to determine whether we will issue burst chop in DDR3 mode only
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size <= 2'd2 && cmd_gen_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
burst_chop [i] <= 1'b1;
else if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 4)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 8)
begin
// Burst chop is not available in quarter rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_timing_param #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 3, // max will be 4 in 4n prefetch architecture?
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// Output - derived timing parameters width
T_PARAM_ACT_TO_RDWR_WIDTH = 6, // temporary
T_PARAM_ACT_TO_PCH_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_BC_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_PCH_WIDTH = 6, // temporary
T_PARAM_RD_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_BC_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_PCH_WIDTH = 6, // temporary
T_PARAM_WR_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_ALL_TO_VALID_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 6, // temporary
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_ARF_TO_VALID_WIDTH = 8, // temporary
T_PARAM_PDN_TO_VALID_WIDTH = 6, // temporary
T_PARAM_SRF_TO_VALID_WIDTH = 10, // temporary
T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10, // temporary
T_PARAM_ARF_PERIOD_WIDTH = 13, // temporary
T_PARAM_PDN_PERIOD_WIDTH = 16, // temporary
T_PARAM_POWER_SAVING_EXIT_WIDTH = 6 // temporary
)
(
ctl_clk,
ctl_reset_n,
// Input - configuration
cfg_burst_length,
cfg_type,
// Input - memory timing parameter
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_tmrd,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_auto_pd_cycles,
cfg_power_saving_exit_cycles,
// Input - extra derived timing parameter
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// Output - derived timing parameters
t_param_act_to_rdwr,
t_param_act_to_pch,
t_param_act_to_act,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
t_param_rd_to_pch,
t_param_rd_ap_to_valid,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_wr_to_pch,
t_param_wr_ap_to_valid,
t_param_pch_to_valid,
t_param_pch_all_to_valid,
t_param_act_to_act_diff_bank,
t_param_four_act_to_act,
t_param_arf_to_valid,
t_param_pdn_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_arf_period,
t_param_pdn_period,
t_param_power_saving_exit
);
input ctl_clk;
input ctl_reset_n;
// Input - configuration
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
// Input - memory timing parameter
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// Output - derived timing parameters
output [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
output [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
output [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
output [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
output [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
output [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
output [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
output [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
output [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
output [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
output [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
output [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
output [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
output [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
output [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
output [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
output [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
output [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
output [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
output [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
output [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
output [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
output [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
output [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
output [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
output [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
output [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
output [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output
reg [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
reg [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
reg [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
reg [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
reg [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
reg [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
reg [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
reg [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
reg [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
reg [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
reg [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
reg [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
reg [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
reg [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
reg [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
reg [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
reg [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
reg [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
reg [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
reg [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Calculation
//
// Important Note:
//
// - Added "cfg_extra_ctl_clk_*" ports into our timing parameter calculation in order for us to
// tweak the timing parameter gaps in the future without changing the code
//
// - This will be very useful in HIP implementation
//
// - "cfg_extra_ctl_clk_*" must be set in term of controller clock cycles
//
//--------------------------------------------------------------------------------------------------------
// DIV is a divider for our timing parameters, DIV will be '1' in fullrate, '2' in halfrate
// and '4' in quarter rate
localparam DIV = CFG_DWIDTH_RATIO / 2;
// Use the following table to determine the optimum timing parameter
// ==========================================================================================================
// || Controller Rate || Arbiter Type || Command Transition || Remainder DIV || Offset ||
// ==========================================================================================================
// || FR || Don't care || Don't care || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || No || Yes ||
// -- HR -----------------------------------------------------------------------------------
// || || || Row -> Col || No || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || Yes* || Yes ||
// -- QR -----------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes* || No ||
// ----------------------------------------------------------------------------------------------------------
// Footnote:
// * for calculation with remainder of '3' only
//---------------------------------------------------
// Remainder calculation
//---------------------------------------------------
// We need to remove the extra clock cycle in half and quarter rate
// for two subsequent different commands but remain for two subsequent same commands
// example of two subsequent different commands: ROW-TO-COL, COL-TO-ROW
// example of two subsequent same commands: ROW-TO-ROW, COL-TO-COL
// Self to self command require DIV
localparam DIV_ROW_TO_ROW = DIV;
localparam DIV_COL_TO_COL = DIV;
localparam DIV_SB_TO_SB = DIV;
localparam DIV_ROW_TO_COL = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? DIV : 1 // Only need DIV in ROWCOL arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_COL_TO_ROW = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? DIV : 1 // Only need DIV in COLROW arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_SB_TO_ROW = DIV_COL_TO_ROW; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Remainder offset calculation
//---------------------------------------------------
// In QR, odd number calculation will only need to add extra offset when calculation's remainder is > 2
// Self to self command's remainder offset will be 0
localparam DIV_ROW_TO_ROW_OFFSET = 0;
localparam DIV_COL_TO_COL_OFFSET = 0;
localparam DIV_SB_TO_SB_OFFSET = 0;
localparam DIV_ROW_TO_COL_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_COL_TO_ROW_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_SB_TO_ROW_OFFSET = DIV_COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Offset calculation
//---------------------------------------------------
// We need to offset timing parameter due to HR 1T and QR 2T support
// this is because we can issue a row and column command in one controller clock cycle
// Self to self command doesn't require offset
localparam ROW_TO_ROW_OFFSET = 0;
localparam COL_TO_COL_OFFSET = 0;
localparam SB_TO_SB_OFFSET = 0;
localparam ROW_TO_COL_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? 0 : 1 // Need offset in ROWCOL arbiter mode
)
);
localparam COL_TO_ROW_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? 0 : 1 // Need offset in COLROW arbiter mode
)
);
localparam SB_TO_ROW_OFFSET = COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//----------------------------------------------------------------------------------------------------
// Common timing parameters, not memory type specific
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_act_to_rdwr <= 0;
t_param_act_to_pch <= 0;
t_param_act_to_act <= 0;
t_param_pch_to_valid <= 0;
t_param_act_to_act_diff_bank <= 0;
t_param_four_act_to_act <= 0;
t_param_arf_to_valid <= 0;
t_param_pdn_to_valid <= 0;
t_param_srf_to_valid <= 0;
t_param_arf_period <= 0;
t_param_pdn_period <= 0;
t_param_power_saving_exit <= 0;
end
else
begin
// Set act_to_rdwr to '0' when additive latency is enabled
if (cfg_add_lat >= (cfg_trcd - 1))
t_param_act_to_rdwr <= 0 + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ;
else
t_param_act_to_rdwr <= ((cfg_trcd - cfg_add_lat) / DIV) + (((cfg_trcd - cfg_add_lat) % DIV_ROW_TO_COL) > DIV_ROW_TO_COL_OFFSET ? 1 : 0) + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ; // ACT to RD/WR - tRCD
t_param_act_to_pch <= (cfg_tras / DIV) + ((cfg_tras % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_pch ; // ACT to PCH - tRAS
t_param_act_to_act <= (cfg_trc / DIV) + ((cfg_trc % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act ; // ACT to ACT (same bank) - tRC
t_param_pch_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_to_valid ; // PCH to ACT - tRP
t_param_act_to_act_diff_bank <= (cfg_trrd / DIV) + ((cfg_trrd % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act_diff_bank; // ACT to ACT (diff banks) - tRRD
t_param_four_act_to_act <= (cfg_tfaw / DIV) + ((cfg_tfaw % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_four_act_to_act ; // Valid window for 4 ACT - tFAW
t_param_arf_to_valid <= (cfg_trfc / DIV) + ((cfg_trfc % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_arf_to_valid ; // ARF to VALID - tRFC
t_param_pdn_to_valid <= (cfg_pdn_exit_cycles / DIV) + ((cfg_pdn_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pdn_to_valid ; // PDN to VALID - normally 3 clock cycles
t_param_srf_to_valid <= (cfg_self_rfsh_exit_cycles / DIV) + ((cfg_self_rfsh_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_srf_to_valid ; // SRF to VALID - normally 200 clock cycles
t_param_arf_period <= (cfg_trefi / DIV) + ((cfg_trefi % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_arf_period ; // ARF period - tREFI
t_param_pdn_period <= cfg_auto_pd_cycles + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_pdn_period ; // PDN count after TBP is empty - specified by user
t_param_power_saving_exit <= (cfg_power_saving_exit_cycles / DIV) + ((cfg_power_saving_exit_cycles % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET ; // SRF and PDN exit cycles
end
end
//----------------------------------------------------------------------------------------------------
// Memory type specific timing parameters
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_rd_to_rd <= 0;
t_param_rd_to_rd_diff_chip <= 0;
t_param_rd_to_wr <= 0;
t_param_rd_to_wr_bc <= 0;
t_param_rd_to_wr_diff_chip <= 0;
t_param_rd_to_pch <= 0;
t_param_rd_ap_to_valid <= 0;
t_param_wr_to_wr <= 0;
t_param_wr_to_wr_diff_chip <= 0;
t_param_wr_to_rd <= 0;
t_param_wr_to_rd_bc <= 0;
t_param_wr_to_rd_diff_chip <= 0;
t_param_wr_to_pch <= 0;
t_param_wr_ap_to_valid <= 0;
t_param_pch_all_to_valid <= 0;
t_param_srf_to_zq_cal <= 0;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR1)
begin
// DDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR2)
begin
// DDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 1, (RL - WL) will always be '1'
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 1) / DIV) + ((((cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR3)
begin
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - RL - WL + (BL/4) + 2
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + max(cfg_trtp, 4)) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + max(tRTP or 4)
t_param_rd_ap_to_valid <= ((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - Same as WR to RD
t_param_wr_to_rd_diff_chip <= (((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) / DIV) + ((((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRP
t_param_srf_to_zq_cal <= ((cfg_self_rfsh_exit_cycles / 2) / DIV) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - SRF exit time divided by 2
end
else if (cfg_type == `MMR_TYPE_LPDDR1)
begin
// LPDDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_LPDDR2)
begin
// LPDDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) / DIV) + ((((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
end
end
// Function to determine max of 2 inputs
localparam MAX_FUNCTION_PORT_WIDTH = (CFG_PORT_WIDTH_TRTP > CFG_PORT_WIDTH_TWTR) ? CFG_PORT_WIDTH_TRTP : CFG_PORT_WIDTH_TWTR;
function [MAX_FUNCTION_PORT_WIDTH - 1 : 0] max;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value1;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value2;
begin
if (value1 > value2)
max = value1;
else
max = value2;
end
endfunction
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Calculation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
module alt_mem_ddrx_wdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 16,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 5,
CFG_DATA_ID_WIDTH = 4,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_TBP_NUM = 8,
CFG_BUFFER_ADDR_WIDTH = 10,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_WDATA_REG = 0,
CFG_PARTIAL_BE_PER_WORD_ENABLE = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_enable_ecc_code_overwrites,
cfg_interface_width,
// command generator & TBP command load interface / cmd update interface
wdatap_free_id_valid,
wdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
tbp_load_index,
proc_size,
// input interface data channel / buffer write interface
wr_data_mem_full,
write_data_en,
write_data,
byte_en,
// notify TBP interface
data_complete,
data_rmw_complete,
data_partial_be,
// AFI interface / buffer read interface
doing_write,
dataid,
dataid_vector,
rdwr_data_valid,
rmw_correct,
rmw_partial,
doing_write_first,
dataid_first,
dataid_vector_first,
rdwr_data_valid_first,
rmw_correct_first,
rmw_partial_first,
doing_write_first_vector,
rdwr_data_valid_first_vector,
doing_write_last,
dataid_last,
dataid_vector_last,
rdwr_data_valid_last,
rmw_correct_last,
rmw_partial_last,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_dm,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
// RMW fifo interface, from rdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_BURSTCOUNT_TRACKING_WIDTH = CFG_BUFFER_ADDR_WIDTH+1;
localparam CFG_RMWFIFO_ECC_DBE_WIDTH = CFG_ECC_MULTIPLES;
localparam CFG_RMWFIFO_ECC_CODE_WIDTH = CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RMWFIFO_ECC_DBE_WIDTH + CFG_RMWFIFO_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_ADDR_WIDTH = (CFG_INT_SIZE_WIDTH == 1) ? CFG_INT_SIZE_WIDTH : CFG_INT_SIZE_WIDTH-1;
localparam CFG_LOCAL_BE_WIDTH = CFG_LOCAL_DATA_WIDTH / 8;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS; // to get the correct DM width based on x4 or x8 mode
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
localparam CFG_WR_DATA_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DATA_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
localparam CFG_WR_DM_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DM_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
// -----------------------------
// port declaration
// -----------------------------
// clock and reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
output wdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
// command generator & TBP command load interface / cmd update interface
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_write;
input [CFG_TBP_NUM-1:0] tbp_load_index;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
output wr_data_mem_full;
input write_data_en;
input [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
input [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
output [CFG_TBP_NUM-1:0] data_complete;
output data_rmw_complete; // broadcast to TBP's
output data_partial_be;
// AFI interface / buffer read interface
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
input doing_write_first;
input [CFG_DATA_ID_WIDTH-1:0] dataid_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_first;
input rdwr_data_valid_first;
input rmw_correct_first;
input rmw_partial_first;
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write_first_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid_first_vector;
input doing_write_last;
input [CFG_DATA_ID_WIDTH-1:0] dataid_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_last;
input rdwr_data_valid_last;
input rmw_correct_last;
input rmw_partial_last;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
output wdatap_rmw_partial;
output wdatap_rmw_correct;
output [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
output [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
input rmwfifo_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
input [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
wire [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
wire wdatap_free_id_valid;
wire wdatap_int_free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_free_id_dataid_vector;
// command generator & TBP command load interface / cmd update interface
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire [CFG_TBP_NUM-1:0] tbp_load_index;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
wire wr_data_mem_full;
wire write_data_en;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
// AFI interface / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
reg [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// signal declaration
// -----------------------------
// configuration
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
// command generator & TBP command load interface / cmd update interface
wire wdatap_cmdload_ready;
wire wdatap_cmdload_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_cmdload_dataid;
wire [CFG_TBP_NUM-1:0] wdatap_cmdload_tbp_index;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_cmdload_burstcount;
// input interface data channel / buffer write interface
wire wdatap_datawrite_ready;
wire wdatap_datawrite_valid;
wire wdatap_datawrite_accepted;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_datawrite_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] wdatap_datawrite_be;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_datawrite_dm;
reg [CFG_LOCAL_DM_WIDTH-1:0] int_datawrite_dm;
wire wdatap_datawrite_partial_dm;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_datawrite_address;
reg [CFG_ECC_MULTIPLES-1:0] int_datawrite_partial_dm;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] wdatap_tbp_data_ready;
wire wdatap_tbp_data_partial_be;
// AFI interface data channel / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_r;
wire wdatap_dataread_valid_first;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_first;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid_first_vector;
wire wdatap_dataread_valid_last;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_last;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_datavalid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_correct_data;
reg wdatap_dataread_rmw_partial;
reg wdatap_dataread_rmw_correct;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_dm;
wire [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_dataread_address;
wire wdatap_dataread_done;
wire wdatap_dataread_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_buffer_data;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_buffer_dm;
wire wdatap_free_id_get_ready;
wire wdatap_allocated_put_ready;
wire wdatap_allocated_put_valid;
wire wdatap_update_data_dataid_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_update_data_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_update_data_dataid_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_next_burstcount;
wire wdatap_notify_data_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_notify_data_burstcount_consumed;
// buffer read/write signals
wire wdatap_buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffwrite_address;
wire wdatap_buffread_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffread_address;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_input;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_output;
wire rmwfifo_output_read;
wire rmwfifo_output_valid;
reg rmwfifo_output_valid_r;
wire rmwfifo_output_valid_pulse;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_output_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_output_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_output_ecc_code;
reg [CFG_LOCAL_DATA_WIDTH-1:0] rmw_merged_data;
reg rmw_correct_r;
reg rmw_partial_r;
wire rmwfifo_ready;
// debug signals, for assertions
wire err_rmwfifo_overflow;
// -----------------------------
// module definition
// -----------------------------
// renaming port names to more meaningfull internal names
assign wdatap_cmdload_valid = ~proc_busy & proc_load & proc_write & proc_load_dataid;
assign wdatap_cmdload_tbp_index = tbp_load_index;
assign wdatap_cmdload_burstcount = proc_size;
assign wdatap_cmdload_dataid = wdatap_free_id_dataid;
assign wr_data_mem_full = ~wdatap_datawrite_ready;
assign wdatap_datawrite_valid = write_data_en;
assign wdatap_datawrite_data = write_data;
assign wdatap_datawrite_be = byte_en; // we need to replicate
assign data_complete = wdatap_tbp_data_ready;
assign data_rmw_complete = rmwfifo_output_valid_pulse; // broadcast to all TBP's
assign data_partial_be = wdatap_tbp_data_partial_be;
assign wdatap_dataread_valid = doing_write & rdwr_data_valid & ~rmw_correct;
assign wdatap_dataread_dataid = dataid;
assign wdatap_dataread_dataid_vector = dataid_vector;
assign wdatap_dataread_valid_first = doing_write_first & rdwr_data_valid_first & ~rmw_correct_first;
assign wdatap_dataread_dataid_first = dataid_first;
assign wdatap_dataread_dataid_vector_first = dataid_vector_first;
assign wdatap_dataread_valid_first_vector = rdwr_data_valid_first_vector;
assign wdatap_dataread_valid_last = doing_write_last & rdwr_data_valid_last & ~rmw_correct_last ;
assign wdatap_dataread_dataid_last = dataid_last;
assign wdatap_dataread_dataid_vector_last = dataid_vector_last;
assign wdatap_data = wdatap_dataread_data;
assign wdatap_rmw_partial_data = wdatap_dataread_rmw_partial_data;
assign wdatap_rmw_correct_data = wdatap_dataread_rmw_correct_data;
assign wdatap_rmw_partial = wdatap_dataread_rmw_partial;
assign wdatap_rmw_correct = wdatap_dataread_rmw_correct;
assign wdatap_dm = wdatap_dataread_dm;
// internal signals
// flow control between free list & allocated list
assign wdatap_free_id_get_ready = wdatap_cmdload_valid;
assign wdatap_allocated_put_valid= wdatap_free_id_get_ready & wdatap_free_id_valid;
assign wdatap_free_id_valid = wdatap_int_free_id_valid & wdatap_cmdload_ready;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
cfg_dram_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH; // SPR:362973
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
//reset state ...
wdatap_dataread_dataid_r <= 0;
end
else
begin
//active state ...
wdatap_dataread_dataid_r <= wdatap_dataread_dataid;
end
end
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
wdatap_list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_free_id_get_ready),
.list_get_entry_valid (wdatap_int_free_id_valid),
.list_get_entry_id (wdatap_free_id_dataid),
.list_get_entry_id_vector (wdatap_free_id_dataid_vector),
// wdatap_dataread_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_dataread_ready),
.list_put_entry_valid (wdatap_dataread_done),
.list_put_entry_id (wdatap_dataread_dataid_r)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
wdatap_list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_notify_data_valid),
.list_get_entry_valid (wdatap_update_data_dataid_valid),
.list_get_entry_id (wdatap_update_data_dataid),
.list_get_entry_id_vector (wdatap_update_data_dataid_vector),
// wdatap_allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_allocated_put_ready),
.list_put_entry_valid (wdatap_allocated_put_valid),
.list_put_entry_id (wdatap_free_id_dataid)
);
alt_mem_ddrx_burst_tracking
# (
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH)
)
wdatap_burst_tracking_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// data burst interface
.burst_ready (wdatap_datawrite_ready),
.burst_valid (wdatap_datawrite_valid),
// burstcount counter sent to data_id_manager
.burst_pending_burstcount (wdatap_update_data_burstcount),
.burst_next_pending_burstcount (wdatap_update_data_next_burstcount),
// burstcount consumed by data_id_manager
.burst_consumed_valid (wdatap_notify_data_valid),
.burst_counsumed_burstcount (wdatap_notify_data_burstcount_consumed)
);
alt_mem_ddrx_dataid_manager
# (
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH),
.CFG_TBP_NUM (CFG_TBP_NUM),
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO)
)
wdatap_dataid_manager_inst
(
// clock & reset
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// configuration signals
.cfg_burst_length (cfg_burst_length),
.cfg_enable_ecc (cfg_enable_ecc),
.cfg_enable_auto_corr (cfg_enable_auto_corr),
.cfg_enable_no_dm (cfg_enable_no_dm),
// update cmd interface
.update_cmd_if_ready (wdatap_cmdload_ready),
.update_cmd_if_valid (wdatap_cmdload_valid),
.update_cmd_if_data_id (wdatap_cmdload_dataid),
.update_cmd_if_burstcount (wdatap_cmdload_burstcount),
.update_cmd_if_tbp_id (wdatap_cmdload_tbp_index),
// update data interface
.update_data_if_valid (wdatap_update_data_dataid_valid),
.update_data_if_data_id (wdatap_update_data_dataid),
.update_data_if_data_id_vector (wdatap_update_data_dataid_vector),
.update_data_if_burstcount (wdatap_update_data_burstcount),
.update_data_if_next_burstcount (wdatap_update_data_next_burstcount),
// notify data interface
.notify_data_if_valid (wdatap_notify_data_valid),
.notify_data_if_burstcount (wdatap_notify_data_burstcount_consumed),
// notify tbp interface
.notify_tbp_data_ready (wdatap_tbp_data_ready),
.notify_tbp_data_partial_be (wdatap_tbp_data_partial_be),
// buffer write address generate interface
.write_data_if_ready (wdatap_datawrite_ready),
.write_data_if_valid (wdatap_datawrite_valid),
.write_data_if_accepted (wdatap_datawrite_accepted),
.write_data_if_address (wdatap_datawrite_address),
.write_data_if_partial_dm (wdatap_datawrite_partial_dm),
// read data interface
.read_data_if_valid (wdatap_dataread_valid),
.read_data_if_data_id (wdatap_dataread_dataid),
.read_data_if_data_id_vector (wdatap_dataread_dataid_vector),
.read_data_if_valid_first (wdatap_dataread_valid_first),
.read_data_if_data_id_first (wdatap_dataread_dataid_first),
.read_data_if_data_id_vector_first (wdatap_dataread_dataid_vector_first),
.read_data_if_valid_first_vector (wdatap_dataread_valid_first_vector),
.read_data_if_valid_last (wdatap_dataread_valid_last),
.read_data_if_data_id_last (wdatap_dataread_dataid_last),
.read_data_if_data_id_vector_last (wdatap_dataread_dataid_vector_last),
.read_data_if_address (wdatap_dataread_address),
.read_data_if_datavalid (wdatap_dataread_datavalid),
.read_data_if_done (wdatap_dataread_done) // use with wdatap_dataread_dataid_r
);
genvar wdatap_m;
genvar wdatap_n;
generate
for (wdatap_m = 0;wdatap_m < CFG_DWIDTH_RATIO;wdatap_m = wdatap_m + 1)
begin : wdata_buffer_per_dwidth_ratio
for (wdatap_n = 0;wdatap_n < CFG_LOCAL_WLAT_GROUP;wdatap_n = wdatap_n + 1)
begin : wdata_buffer_per_dqs_group
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DATA_WIDTH_PER_DQS_GROUP)
)
wdatap_buffer_data_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (wdatap_datawrite_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)])
);
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DM_WIDTH_PER_DQS_GROUP)
)
wdatap_buffer_be_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (int_datawrite_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)])
);
end
end
endgenerate
//
// byteenables analysis & generation
//
// - generate partial byteenable signal, per DQ word or per local word
// - set unused interface width byteenables to either 0 or 1
//
genvar wdatap_j, wdatap_k;
generate
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1 [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0 [CFG_ECC_MULTIPLES-1:0];
assign wdatap_datawrite_partial_dm = |int_datawrite_partial_dm;
for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
begin : local_dm
always @ (*)
begin
if (CFG_MEM_IF_DQ_PER_DQS == 4)
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
end
else
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
end
end
end
for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1)
begin : gen_partial_be
wire dm_all_ones = &int_datawrite_dm_unused1[wdatap_j];
wire dm_all_zeros = ~(|int_datawrite_dm_unused0[wdatap_j]);
always @ (*)
begin
wdatap_datawrite_dm_widthratio [wdatap_j] = wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
end
for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
begin : gen_dm_unused_bits
always @ (*)
begin
if (wdatap_k < cfg_dram_dm_width)
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
end
else
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = {1'b1};
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = {1'b0};
end
end
end
always @ (*)
begin
// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
if (cfg_enable_no_dm)
begin
int_datawrite_partial_dm[wdatap_j] = ~dm_all_ones;
end
else
begin
int_datawrite_partial_dm[wdatap_j] = ~( dm_all_ones | dm_all_zeros );
end
if (cfg_enable_ecc)
begin
if (dm_all_zeros)
begin
// no ECC code will be written
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
else
begin
// higher unused be bit will be used for ECC word
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
end
end
else
begin
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
end
end
endgenerate
//
// rmw data fifo
//
// assume rmw data for 2 commands doesn't came back to back, causing rmwfifo_output_valid_pulse not to be generated for 2nd commands data
assign rmwfifo_output_valid_pulse = rmwfifo_output_valid & ~rmwfifo_output_valid_r;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rmwfifo_output_valid_r <= 1'b0;
rmw_correct_r <= 1'b0;
rmw_partial_r <= 1'b0;
end
else
begin
rmwfifo_output_valid_r <= rmwfifo_output_valid;
rmw_correct_r <= rmw_correct;
rmw_partial_r <= rmw_partial;
end
end
assign rmwfifo_input = {rmwfifo_ecc_code, rmwfifo_ecc_dbe, rmwfifo_data};
assign {rmwfifo_output_ecc_code, rmwfifo_output_ecc_dbe, rmwfifo_output_data} = rmwfifo_output;
assign rmwfifo_output_read = rmw_correct_r | (&wdatap_dataread_datavalid & rmw_partial_r); // wdatap_dataread_datavalid must be all high together in ECC case (afi_wlat same for all DQS group), limitation in 11.0sp1
assign err_rmwfifo_overflow = rmwfifo_data_valid & ~rmwfifo_ready;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_RMWDATA_FIFO_DATA_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_RMWDATA_FIFO_ADDR_WIDTH)
)
rmw_data_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rmwfifo_output_read),
.get_valid (rmwfifo_output_valid),
.get_data (rmwfifo_output),
.put_ready (rmwfifo_ready),
.put_valid (rmwfifo_data_valid),
.put_data (rmwfifo_input)
);
//
// rmw data merge block
//
genvar wdatap_i;
generate
for (wdatap_i = 0; wdatap_i < ((CFG_LOCAL_DM_WIDTH)); wdatap_i = wdatap_i + 1)
begin : gen_rmw_data_merge
always @ (*)
begin
if (wdatap_dataread_buffer_dm[wdatap_i])
begin
// data from wdatap buffer
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = wdatap_dataread_buffer_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
else
begin
// data from rmwfifo
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
end
end
endgenerate
//
// wdata output mux
//
// drives wdatap_data & wdatap_be from either of
// if cfg_enabled etc ?
// - wdatap buffer (~rmw_correct & ~rmw_partial)
// - rmwfifo (rmw_correct)
// - merged wdatap buffer & rmwfifo (rmw_partial)
//
generate
if (CFG_WDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_dataread_dm <= 0;
wdatap_dataread_data <= 0;
wdatap_dataread_rmw_partial_data <= 0;
wdatap_dataread_rmw_correct_data <= 0;
wdatap_dataread_rmw_partial <= 0;
wdatap_dataread_rmw_correct <= 0;
end
else
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data <= wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data <= rmw_merged_data;
wdatap_dataread_rmw_correct_data <= rmwfifo_output_data;
wdatap_dataread_rmw_partial <= rmw_partial_r;
wdatap_dataread_rmw_correct <= rmw_correct_r;
if (rmw_correct_r | rmw_partial_r)
begin
wdatap_dataread_dm <= {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm <= wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm <= wdatap_dataread_buffer_dm;
wdatap_dataread_data <= wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data <= 0;
wdatap_dataread_rmw_correct_data <= 0;
wdatap_dataread_rmw_partial <= 1'b0;
wdatap_dataread_rmw_correct <= 1'b0;
end
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_ecc_code <= 0;
wdatap_ecc_code_overwrite <= 0;
end
else
begin
wdatap_ecc_code <= rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r)
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = rmw_merged_data;
wdatap_dataread_rmw_correct_data = rmwfifo_output_data;
wdatap_dataread_rmw_partial = rmw_partial_r;
wdatap_dataread_rmw_correct = rmw_correct_r;
if (rmw_correct_r | rmw_partial_r)
begin
wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = 0;
wdatap_dataread_rmw_correct_data = 0;
wdatap_dataread_rmw_partial = 1'b0;
wdatap_dataread_rmw_correct = 1'b0;
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (*)
begin
wdatap_ecc_code = rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r)
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
endgenerate
endmodule
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 c3 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=3 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=3 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="0" clk2_divide_by=3 clk2_duty_cycle=50 clk2_multiply_by=2 clk2_phase_shift="0" clk3_divide_by=1 clk3_duty_cycle=50 clk3_multiply_by=2 clk3_phase_shift="1000" compensate_clock="CLK0" device_family="STRATIXIV" inclk0_input_frequency=20000 intended_device_family="Stratix IV" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_clk6="PORT_UNUSED" port_clk7="PORT_UNUSED" port_clk8="PORT_UNUSED" port_clk9="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" using_fbmimicbidir_port="OFF" width_clock=10
//VERSION_BEGIN 11.1 cbx_altclkbuf 2011:10:31:21:09:45:SJ cbx_altiobuf_bidir 2011:10:31:21:09:45:SJ cbx_altiobuf_in 2011:10:31:21:09:45:SJ cbx_altiobuf_out 2011:10:31:21:09:45:SJ cbx_altpll 2011:10:31:21:09:45:SJ cbx_altpll_avalon 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 11.1 cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 11.1 cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module DE4_SOPC_altpll_0_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //DE4_SOPC_altpll_0_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module DE4_SOPC_altpll_0_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
DE4_SOPC_altpll_0_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //DE4_SOPC_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=3 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=3 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="0" clk2_divide_by=3 clk2_duty_cycle=50 clk2_multiply_by=2 clk2_phase_shift="0" clk3_divide_by=1 clk3_duty_cycle=50 clk3_multiply_by=2 clk3_phase_shift="1000" compensate_clock="CLK0" device_family="STRATIXIV" inclk0_input_frequency=20000 intended_device_family="Stratix IV" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_clk6="PORT_UNUSED" port_clk7="PORT_UNUSED" port_clk8="PORT_UNUSED" port_clk9="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" using_fbmimicbidir_port="OFF" width_clock=10 areset clk inclk locked
//VERSION_BEGIN 11.1 cbx_altclkbuf 2011:10:31:21:09:45:SJ cbx_altiobuf_bidir 2011:10:31:21:09:45:SJ cbx_altiobuf_in 2011:10:31:21:09:45:SJ cbx_altiobuf_out 2011:10:31:21:09:45:SJ cbx_altpll 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
//synthesis_resources = reg 1 stratixiv_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104"} *)
module DE4_SOPC_altpll_0_altpll_2op2
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [9:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [9:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
stratixiv_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({4{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 3,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 2,
pll7.clk0_phase_shift = "0",
pll7.clk1_divide_by = 3,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 2,
pll7.clk1_phase_shift = "0",
pll7.clk2_divide_by = 3,
pll7.clk2_duty_cycle = 50,
pll7.clk2_multiply_by = 2,
pll7.clk2_phase_shift = "0",
pll7.clk3_divide_by = 1,
pll7.clk3_duty_cycle = 50,
pll7.clk3_multiply_by = 2,
pll7.clk3_phase_shift = "1000",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "stratixiv_pll";
assign
clk = wire_pll7_clk,
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //DE4_SOPC_altpll_0_altpll_2op2
//synthesis_resources = reg 6 stratixiv_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module DE4_SOPC_altpll_0
(
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [9:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
DE4_SOPC_altpll_0_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
DE4_SOPC_altpll_0_altpll_2op2 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //DE4_SOPC_altpll_0
//VALID FILE
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// DE4_SOPC_ddr2_0.v
// This file was auto-generated from alt_mem_if_ddr2_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 11.1 173 at 2012.08.31.13:48:24
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire [13:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [1:0] mem_ck, // .mem_ck
output wire [1:0] mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire [7:0] mem_dm, // .mem_dm
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
inout wire [63:0] mem_dq, // .mem_dq
inout wire [7:0] mem_dqs, // .mem_dqs
inout wire [7:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [24:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [255:0] avl_rdata, // .readdata
input wire [255:0] avl_wdata, // .writedata
input wire [31:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [3:0] avl_size, // .burstcount
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup // .rup
);
wire p0_addr_cmd_clk_clk; // p0:addr_cmd_clk -> m0:clk
wire [27:0] m0_phy_mux_afi_addr; // m0:phy_mux_addr -> p0:afi_addr
wire [1:0] m0_phy_mux_afi_odt; // m0:phy_mux_odt -> p0:afi_odt
wire [5:0] p0_afi_afi_wlat; // p0:afi_wlat -> m0:phy_mux_wlat
wire [1:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> m0:phy_mux_rdata_valid
wire [1:0] m0_phy_mux_afi_rdata_en_full; // m0:phy_mux_rdata_en_full -> p0:afi_rdata_en_full
wire [1:0] m0_phy_mux_afi_we_n; // m0:phy_mux_we_n -> p0:afi_we_n
wire [5:0] m0_phy_mux_afi_ba; // m0:phy_mux_ba -> p0:afi_ba
wire [1:0] m0_phy_mux_afi_cke; // m0:phy_mux_cke -> p0:afi_cke
wire [1:0] m0_phy_mux_afi_cs_n; // m0:phy_mux_cs_n -> p0:afi_cs_n
wire [255:0] m0_phy_mux_afi_wdata; // m0:phy_mux_wdata -> p0:afi_wdata
wire [1:0] m0_phy_mux_afi_rdata_en; // m0:phy_mux_rdata_en -> p0:afi_rdata_en
wire [1:0] m0_phy_mux_afi_cas_n; // m0:phy_mux_cas_n -> p0:afi_cas_n
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> m0:phy_mux_cal_success
wire [1:0] m0_phy_mux_afi_ras_n; // m0:phy_mux_ras_n -> p0:afi_ras_n
wire [5:0] p0_afi_afi_rlat; // p0:afi_rlat -> m0:phy_mux_rlat
wire [255:0] p0_afi_afi_rdata; // p0:afi_rdata -> m0:phy_mux_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> m0:phy_mux_cal_fail
wire [15:0] m0_phy_mux_afi_wdata_valid; // m0:phy_mux_wdata_valid -> p0:afi_wdata_valid
wire [15:0] m0_phy_mux_afi_dqs_burst; // m0:phy_mux_dqs_burst -> p0:afi_dqs_burst
wire [31:0] m0_phy_mux_afi_dm; // m0:phy_mux_dm -> p0:afi_dm
wire [5:0] m0_afi_afi_wlat; // m0:afi_wlat -> c0:afi_wlat
wire [1:0] m0_afi_afi_rdata_valid; // m0:afi_rdata_valid -> c0:afi_rdata_valid
wire m0_afi_afi_cal_success; // m0:afi_cal_success -> c0:afi_cal_success
wire [5:0] m0_afi_afi_rlat; // m0:afi_rlat -> c0:afi_rlat
wire [255:0] m0_afi_afi_rdata; // m0:afi_rdata -> c0:afi_rdata
wire m0_afi_afi_cal_fail; // m0:afi_cal_fail -> c0:afi_cal_fail
wire p0_avl_clk_clk; // p0:avl_clk -> s0:avl_clk
wire p0_avl_reset_reset; // p0:avl_reset_n -> s0:avl_reset_n
wire p0_scc_clk_clk; // p0:scc_clk -> s0:scc_clk
wire p0_scc_reset_reset; // p0:scc_reset_n -> s0:reset_n_scc_clk
wire [27:0] s0_afi_afi_addr; // s0:afi_addr -> m0:seq_mux_addr
wire [1:0] s0_afi_afi_odt; // s0:afi_odt -> m0:seq_mux_odt
wire [1:0] m0_seq_mux_afi_rdata_valid; // m0:seq_mux_rdata_valid -> s0:afi_rdata_valid
wire [1:0] s0_afi_afi_rdata_en_full; // s0:afi_rdata_en_full -> m0:seq_mux_rdata_en_full
wire [1:0] s0_afi_afi_we_n; // s0:afi_we_n -> m0:seq_mux_we_n
wire [5:0] s0_afi_afi_ba; // s0:afi_ba -> m0:seq_mux_ba
wire [1:0] s0_afi_afi_cke; // s0:afi_cke -> m0:seq_mux_cke
wire [1:0] s0_afi_afi_cs_n; // s0:afi_cs_n -> m0:seq_mux_cs_n
wire [255:0] s0_afi_afi_wdata; // s0:afi_wdata -> m0:seq_mux_wdata
wire [1:0] s0_afi_afi_rdata_en; // s0:afi_rdata_en -> m0:seq_mux_rdata_en
wire [1:0] s0_afi_afi_cas_n; // s0:afi_cas_n -> m0:seq_mux_cas_n
wire [1:0] s0_afi_afi_ras_n; // s0:afi_ras_n -> m0:seq_mux_ras_n
wire [255:0] m0_seq_mux_afi_rdata; // m0:seq_mux_rdata -> s0:afi_rdata
wire [15:0] s0_afi_afi_wdata_valid; // s0:afi_wdata_valid -> m0:seq_mux_wdata_valid
wire [15:0] s0_afi_afi_dqs_burst; // s0:afi_dqs_burst -> m0:seq_mux_dqs_burst
wire [31:0] s0_afi_afi_dm; // s0:afi_dm -> m0:seq_mux_dm
wire s0_mux_sel_mux_sel; // s0:phy_mux_sel -> m0:mux_sel
wire s0_phy_phy_cal_success; // s0:phy_cal_success -> p0:phy_cal_success
wire p0_phy_phy_reset_n; // p0:phy_reset_n -> s0:phy_reset_n
wire s0_phy_phy_cal_fail; // s0:phy_cal_fail -> p0:phy_cal_fail
wire [7:0] s0_phy_phy_read_increment_vfifo_qr; // s0:phy_read_increment_vfifo_qr -> p0:phy_read_increment_vfifo_qr
wire p0_phy_phy_clk; // p0:phy_clk -> s0:phy_clk
wire [5:0] s0_phy_phy_afi_rlat; // s0:phy_afi_rlat -> p0:phy_afi_rlat
wire [7:0] s0_phy_phy_read_increment_vfifo_hr; // s0:phy_read_increment_vfifo_hr -> p0:phy_read_increment_vfifo_hr
wire [7:0] s0_phy_phy_vfifo_rd_en_override; // s0:phy_vfifo_rd_en_override -> p0:phy_vfifo_rd_en_override
wire [255:0] p0_phy_phy_read_fifo_q; // p0:phy_read_fifo_q -> s0:phy_read_fifo_q
wire [4:0] s0_phy_phy_read_latency_counter; // s0:phy_read_latency_counter -> p0:phy_read_latency_counter
wire [7:0] s0_phy_phy_read_fifo_reset; // s0:phy_read_fifo_reset -> p0:phy_read_fifo_reset
wire [7:0] s0_phy_phy_read_increment_vfifo_fr; // s0:phy_read_increment_vfifo_fr -> p0:phy_read_increment_vfifo_fr
wire [31:0] s0_phy_phy_cal_debug_info; // s0:phy_cal_debug_info -> p0:phy_cal_debug_info
wire s0_phy_phy_reset_mem_stable; // s0:phy_reset_mem_stable -> p0:phy_reset_mem_stable
wire [5:0] s0_phy_phy_afi_wlat; // s0:phy_afi_wlat -> p0:phy_afi_wlat
wire [7:0] p0_calib_calib_skip_steps; // p0:calib_skip_steps -> s0:calib_skip_steps
wire [7:0] s0_scc_scc_dm_ena; // s0:scc_dm_ena -> p0:scc_dm_ena
wire [63:0] s0_scc_scc_dq_ena; // s0:scc_dq_ena -> p0:scc_dq_ena
wire [7:0] s0_scc_scc_dqs_ena; // s0:scc_dqs_ena -> p0:scc_dqs_ena
wire s0_scc_scc_upd; // s0:scc_upd -> p0:scc_upd
wire [7:0] p0_scc_capture_strobe_tracking; // p0:capture_strobe_tracking -> s0:capture_strobe_tracking
wire [7:0] s0_scc_scc_dqs_io_ena; // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
wire s0_scc_scc_data; // s0:scc_data -> p0:scc_data
wire [27:0] c0_afi_afi_addr; // c0:afi_addr -> m0:afi_addr
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> m0:afi_odt
wire c0_afi_afi_cal_req; // c0:afi_cal_req -> s0:afi_cal_req
wire [1:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> m0:afi_rdata_en_full
wire [1:0] c0_afi_afi_we_n; // c0:afi_we_n -> m0:afi_we_n
wire [5:0] c0_afi_afi_ba; // c0:afi_ba -> m0:afi_ba
wire [255:0] c0_afi_afi_wdata; // c0:afi_wdata -> m0:afi_wdata
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> m0:afi_cke
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> m0:afi_cs_n
wire [1:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> m0:afi_rdata_en
wire [1:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> m0:afi_cas_n
wire [1:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> m0:afi_ras_n
wire [1:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire c0_afi_afi_init_req; // c0:afi_init_req -> s0:afi_init_req
wire [15:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> m0:afi_wdata_valid
wire [15:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> m0:afi_dqs_burst
wire [31:0] c0_afi_afi_dm; // c0:afi_dm -> m0:afi_dm
wire [13:0] oct0_oct_sharing_parallelterminationcontrol; // oct0:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [13:0] oct0_oct_sharing_seriesterminationcontrol; // oct0:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll0_pll_sharing_pll_avl_clk; // pll0:pll_avl_clk -> p0:pll_avl_clk
wire pll0_pll_sharing_pll_config_clk; // pll0:pll_config_clk -> p0:pll_config_clk
wire pll0_pll_sharing_pll_addr_cmd_clk; // pll0:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll0_pll_sharing_pll_mem_clk; // pll0:pll_mem_clk -> p0:pll_mem_clk
wire pll0_pll_sharing_pll_locked; // pll0:pll_locked -> p0:pll_locked
wire pll0_pll_sharing_pll_write_clk_pre_phy_clk; // pll0:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll0_pll_sharing_pll_write_clk; // pll0:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll0:clk
wire [5:0] dll0_dll_sharing_dll_delayctrl; // dll0:dll_delayctrl -> p0:dll_delayctrl
DE4_SOPC_ddr2_0_pll0 pll0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.pll_mem_clk (pll0_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll0_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_write_clk_pre_phy_clk (pll0_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll0_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_locked (pll0_pll_sharing_pll_locked), // .pll_locked
.pll_avl_clk (pll0_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll0_pll_sharing_pll_config_clk) // .pll_config_clk
);
DE4_SOPC_ddr2_0_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.addr_cmd_clk (p0_addr_cmd_clk_clk), // addr_cmd_clk.clk
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.scc_reset_n (p0_scc_reset_reset), // scc_reset.reset_n
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (m0_phy_mux_afi_addr), // afi.afi_addr
.afi_ba (m0_phy_mux_afi_ba), // .afi_ba
.afi_cke (m0_phy_mux_afi_cke), // .afi_cke
.afi_cs_n (m0_phy_mux_afi_cs_n), // .afi_cs_n
.afi_ras_n (m0_phy_mux_afi_ras_n), // .afi_ras_n
.afi_we_n (m0_phy_mux_afi_we_n), // .afi_we_n
.afi_cas_n (m0_phy_mux_afi_cas_n), // .afi_cas_n
.afi_odt (m0_phy_mux_afi_odt), // .afi_odt
.afi_dqs_burst (m0_phy_mux_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (m0_phy_mux_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (m0_phy_mux_afi_wdata), // .afi_wdata
.afi_dm (m0_phy_mux_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (m0_phy_mux_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (m0_phy_mux_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.phy_clk (p0_phy_phy_clk), // phy.phy_clk
.phy_reset_n (p0_phy_phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (s0_phy_phy_read_latency_counter), // .phy_read_latency_counter
.phy_afi_wlat (s0_phy_phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (s0_phy_phy_afi_rlat), // .phy_afi_rlat
.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (s0_phy_phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_cal_success (s0_phy_phy_cal_success), // .phy_cal_success
.phy_cal_fail (s0_phy_phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (s0_phy_phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (s0_phy_phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (s0_phy_phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.phy_read_fifo_q (p0_phy_phy_read_fifo_q), // .phy_read_fifo_q
.calib_skip_steps (p0_calib_calib_skip_steps), // calib.calib_skip_steps
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.scc_upd (s0_scc_scc_upd), // .scc_upd
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll0_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll0_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_write_clk_pre_phy_clk (pll0_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll0_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_locked (pll0_pll_sharing_pll_locked), // .pll_locked
.pll_avl_clk (pll0_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll0_pll_sharing_pll_config_clk), // .pll_config_clk
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl), // dll_sharing.dll_delayctrl
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt) // .mem_odt
);
afi_mux_ddrx #(
.AFI_RATE_RATIO (2),
.AFI_ADDR_WIDTH (28),
.AFI_BANKADDR_WIDTH (6),
.AFI_CONTROL_WIDTH (2),
.AFI_CS_WIDTH (2),
.AFI_DM_WIDTH (32),
.AFI_DQ_WIDTH (256),
.AFI_ODT_WIDTH (2),
.AFI_WRITE_DQS_WIDTH (16),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6)
) m0 (
.clk (p0_addr_cmd_clk_clk), // clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (m0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (m0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (m0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (m0_afi_afi_cal_fail), // .afi_cal_fail
.afi_wlat (m0_afi_afi_wlat), // .afi_wlat
.afi_rlat (m0_afi_afi_rlat), // .afi_rlat
.seq_mux_addr (s0_afi_afi_addr), // seq_mux.afi_addr
.seq_mux_ba (s0_afi_afi_ba), // .afi_ba
.seq_mux_cke (s0_afi_afi_cke), // .afi_cke
.seq_mux_cs_n (s0_afi_afi_cs_n), // .afi_cs_n
.seq_mux_ras_n (s0_afi_afi_ras_n), // .afi_ras_n
.seq_mux_we_n (s0_afi_afi_we_n), // .afi_we_n
.seq_mux_cas_n (s0_afi_afi_cas_n), // .afi_cas_n
.seq_mux_odt (s0_afi_afi_odt), // .afi_odt
.seq_mux_dqs_burst (s0_afi_afi_dqs_burst), // .afi_dqs_burst
.seq_mux_wdata_valid (s0_afi_afi_wdata_valid), // .afi_wdata_valid
.seq_mux_wdata (s0_afi_afi_wdata), // .afi_wdata
.seq_mux_dm (s0_afi_afi_dm), // .afi_dm
.seq_mux_rdata (m0_seq_mux_afi_rdata), // .afi_rdata
.seq_mux_rdata_en (s0_afi_afi_rdata_en), // .afi_rdata_en
.seq_mux_rdata_en_full (s0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.seq_mux_rdata_valid (m0_seq_mux_afi_rdata_valid), // .afi_rdata_valid
.phy_mux_addr (m0_phy_mux_afi_addr), // phy_mux.afi_addr
.phy_mux_ba (m0_phy_mux_afi_ba), // .afi_ba
.phy_mux_cke (m0_phy_mux_afi_cke), // .afi_cke
.phy_mux_cs_n (m0_phy_mux_afi_cs_n), // .afi_cs_n
.phy_mux_ras_n (m0_phy_mux_afi_ras_n), // .afi_ras_n
.phy_mux_we_n (m0_phy_mux_afi_we_n), // .afi_we_n
.phy_mux_cas_n (m0_phy_mux_afi_cas_n), // .afi_cas_n
.phy_mux_odt (m0_phy_mux_afi_odt), // .afi_odt
.phy_mux_dqs_burst (m0_phy_mux_afi_dqs_burst), // .afi_dqs_burst
.phy_mux_wdata_valid (m0_phy_mux_afi_wdata_valid), // .afi_wdata_valid
.phy_mux_wdata (m0_phy_mux_afi_wdata), // .afi_wdata
.phy_mux_dm (m0_phy_mux_afi_dm), // .afi_dm
.phy_mux_rdata (p0_afi_afi_rdata), // .afi_rdata
.phy_mux_rdata_en (m0_phy_mux_afi_rdata_en), // .afi_rdata_en
.phy_mux_rdata_en_full (m0_phy_mux_afi_rdata_en_full), // .afi_rdata_en_full
.phy_mux_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.phy_mux_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.phy_mux_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.phy_mux_wlat (p0_afi_afi_wlat), // .afi_wlat
.phy_mux_rlat (p0_afi_afi_rlat), // .afi_rlat
.mux_sel (s0_mux_sel_mux_sel) // mux_sel.mux_sel
);
DE4_SOPC_ddr2_0_s0 s0 (
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.reset_n_scc_clk (p0_scc_reset_reset), // scc_reset.reset_n
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.scc_upd (s0_scc_scc_upd), // .scc_upd
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.afi_init_req (c0_afi_afi_init_req), // afi_init_cal_req.afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.phy_clk (p0_phy_phy_clk), // phy.phy_clk
.phy_reset_n (p0_phy_phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (s0_phy_phy_read_latency_counter), // .phy_read_latency_counter
.phy_afi_wlat (s0_phy_phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (s0_phy_phy_afi_rlat), // .phy_afi_rlat
.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (s0_phy_phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_cal_success (s0_phy_phy_cal_success), // .phy_cal_success
.phy_cal_fail (s0_phy_phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (s0_phy_phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (s0_phy_phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (s0_phy_phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.phy_read_fifo_q (p0_phy_phy_read_fifo_q), // .phy_read_fifo_q
.calib_skip_steps (p0_calib_calib_skip_steps), // calib.calib_skip_steps
.phy_mux_sel (s0_mux_sel_mux_sel), // mux_sel.mux_sel
.afi_clk (afi_clk), // afi_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_addr (s0_afi_afi_addr), // afi.afi_addr
.afi_ba (s0_afi_afi_ba), // .afi_ba
.afi_cke (s0_afi_afi_cke), // .afi_cke
.afi_cs_n (s0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (s0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (s0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (s0_afi_afi_cas_n), // .afi_cas_n
.afi_odt (s0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (s0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (s0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (s0_afi_afi_wdata), // .afi_wdata
.afi_dm (s0_afi_afi_dm), // .afi_dm
.afi_rdata (m0_seq_mux_afi_rdata), // .afi_rdata
.afi_rdata_en (s0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (s0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (m0_seq_mux_afi_rdata_valid) // .afi_rdata_valid
);
DE4_SOPC_ddr2_0_c0 c0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (c0_afi_afi_init_req), // .afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (m0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (m0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (m0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (m0_afi_afi_cal_fail), // .afi_cal_fail
.afi_wlat (m0_afi_afi_wlat), // .afi_wlat
.afi_rlat (m0_afi_afi_rlat), // .afi_rlat
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size) // .burstcount
);
altera_mem_if_oct_stratixiv #(
.OCT_TERM_CONTROL_WIDTH (14)
) oct0 (
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_stratixiv #(
.DLL_DELAY_CTRL_WIDTH (6),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (10),
.DLL_INPUT_FREQUENCY_PS_STR ("5000 ps")
) dll0 (
.clk (p0_dll_clk_clk), // clk.clk
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl) // dll_sharing.dll_delayctrl
);
endmodule
|
// DE4_SOPC_ddr2_0_c0.v
// This file was auto-generated from alt_mem_if_nextgen_ddr2_controller_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 11.1 173 at 2012.08.31.13:49:30
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_c0 (
input wire afi_reset_n, // afi_reset.reset_n
input wire afi_clk, // afi_clk.clk
input wire afi_half_clk, // afi_half_clk.clk
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
output wire [27:0] afi_addr, // afi.afi_addr
output wire [5:0] afi_ba, // .afi_ba
output wire [1:0] afi_cke, // .afi_cke
output wire [1:0] afi_cs_n, // .afi_cs_n
output wire [1:0] afi_ras_n, // .afi_ras_n
output wire [1:0] afi_we_n, // .afi_we_n
output wire [1:0] afi_cas_n, // .afi_cas_n
output wire [1:0] afi_odt, // .afi_odt
output wire [1:0] afi_mem_clk_disable, // .afi_mem_clk_disable
output wire afi_init_req, // .afi_init_req
output wire afi_cal_req, // .afi_cal_req
output wire [15:0] afi_dqs_burst, // .afi_dqs_burst
output wire [15:0] afi_wdata_valid, // .afi_wdata_valid
output wire [255:0] afi_wdata, // .afi_wdata
output wire [31:0] afi_dm, // .afi_dm
input wire [255:0] afi_rdata, // .afi_rdata
output wire [1:0] afi_rdata_en, // .afi_rdata_en
output wire [1:0] afi_rdata_en_full, // .afi_rdata_en_full
input wire [1:0] afi_rdata_valid, // .afi_rdata_valid
input wire afi_cal_success, // .afi_cal_success
input wire afi_cal_fail, // .afi_cal_fail
input wire [5:0] afi_wlat, // .afi_wlat
input wire [5:0] afi_rlat, // .afi_rlat
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [24:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [255:0] avl_rdata, // .readdata
input wire [255:0] avl_wdata, // .writedata
input wire [31:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [3:0] avl_size // .burstcount
);
wire a0_native_st_itf_wr_data_begin; // a0:itf_wr_data_begin -> ng0:itf_wr_data_begin
wire a0_native_st_itf_rd_data_ready; // a0:itf_rd_data_ready -> ng0:itf_rd_data_ready
wire [255:0] a0_native_st_itf_wr_data; // a0:itf_wr_data -> ng0:itf_wr_data
wire ng0_native_st_itf_rd_data_error; // ng0:itf_rd_data_error -> a0:itf_rd_data_error
wire ng0_native_st_itf_rd_data_begin; // ng0:itf_rd_data_begin -> a0:itf_rd_data_begin
wire [7:0] a0_native_st_itf_wr_data_id; // a0:itf_wr_data_id -> ng0:itf_wr_data_id
wire ng0_native_st_itf_cmd_ready; // ng0:itf_cmd_ready -> a0:itf_cmd_ready
wire a0_native_st_itf_wr_data_last; // a0:itf_wr_data_last -> ng0:itf_wr_data_last
wire [31:0] a0_native_st_itf_wr_data_byte_en; // a0:itf_wr_data_byte_en -> ng0:itf_wr_data_byte_en
wire [24:0] a0_native_st_itf_cmd_address; // a0:itf_cmd_address -> ng0:itf_cmd_address
wire a0_native_st_itf_cmd_valid; // a0:itf_cmd_valid -> ng0:itf_cmd_valid
wire a0_native_st_itf_wr_data_valid; // a0:itf_wr_data_valid -> ng0:itf_wr_data_valid
wire a0_native_st_itf_cmd_autopercharge; // a0:itf_cmd_autopercharge -> ng0:itf_cmd_autopercharge
wire ng0_native_st_itf_rd_data_last; // ng0:itf_rd_data_last -> a0:itf_rd_data_last
wire [255:0] ng0_native_st_itf_rd_data; // ng0:itf_rd_data -> a0:itf_rd_data
wire [3:0] a0_native_st_itf_cmd_burstlen; // a0:itf_cmd_burstlen -> ng0:itf_cmd_burstlen
wire ng0_native_st_itf_rd_data_valid; // ng0:itf_rd_data_valid -> a0:itf_rd_data_valid
wire a0_native_st_itf_cmd_multicast; // a0:itf_cmd_multicast -> ng0:itf_cmd_multicast
wire [7:0] a0_native_st_itf_cmd_id; // a0:itf_cmd_id -> ng0:itf_cmd_id
wire ng0_native_st_itf_wr_data_ready; // ng0:itf_wr_data_ready -> a0:itf_wr_data_ready
wire [7:0] ng0_native_st_itf_rd_data_id; // ng0:itf_rd_data_id -> a0:itf_rd_data_id
wire a0_native_st_itf_cmd; // a0:itf_cmd -> ng0:itf_cmd
wire a0_native_st_itf_cmd_priority; // a0:itf_cmd_priority -> ng0:itf_cmd_priority
alt_mem_if_nextgen_ddr2_controller_core #(
.MEM_IF_ADDR_WIDTH (14),
.MEM_IF_ROW_ADDR_WIDTH (14),
.MEM_IF_COL_ADDR_WIDTH (10),
.MEM_IF_DM_WIDTH (8),
.MEM_IF_DQS_WIDTH (8),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_BANKADDR_WIDTH (3),
.MEM_IF_DQ_WIDTH (64),
.MEM_IF_CLK_PAIR_COUNT (2),
.MEM_TRC (11),
.MEM_TRAS (8),
.MEM_TRCD (3),
.MEM_TRP (3),
.MEM_TREFI (1560),
.MEM_TRFC (26),
.MEM_TWR (3),
.MEM_TFAW (8),
.MEM_TRRD (2),
.MEM_TRTP (2),
.MEM_IF_ODT_WIDTH (1),
.MEM_WTCL_INT (5),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT (3),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT (3),
.CTL_RD_TO_PCH_EXTRA_CLK (0),
.MEM_TCL (6),
.MEM_TMRD_CK (5),
.MEM_TWTR (3),
.CSR_ADDR_WIDTH (8),
.CSR_DATA_WIDTH (32),
.CSR_BE_WIDTH (4),
.AVL_ADDR_WIDTH (25),
.AVL_BE_WIDTH (32),
.AVL_DATA_WIDTH (256),
.AVL_SIZE_WIDTH (4),
.DWIDTH_RATIO (4),
.CTL_ODT_ENABLED (1),
.CTL_OUTPUT_REGD (0),
.CTL_ECC_MULTIPLES_16_24_40_72 (1),
.CTL_REGDIMM_ENABLED (0),
.CTL_TBP_NUM (1),
.CTL_USR_REFRESH (0),
.CFG_TYPE (1),
.CFG_INTERFACE_WIDTH (64),
.CFG_BURST_LENGTH (4),
.CFG_ADDR_ORDER (0),
.CFG_PDN_EXIT_CYCLES (3),
.CFG_POWER_SAVING_EXIT_CYCLES (5),
.CFG_MEM_CLK_ENTRY_CYCLES (10),
.CFG_SELF_RFSH_EXIT_CYCLES (200),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (1),
.CFG_PORT_WIDTH_READ_ODT_CHIP (1),
.CFG_WRITE_ODT_CHIP (1),
.CFG_READ_ODT_CHIP (0),
.LOCAL_CS_WIDTH (0),
.CFG_CLR_INTR (0),
.CFG_ENABLE_NO_DM (0),
.MEM_ADD_LAT (0),
.MEM_AUTO_PD_CYCLES (0),
.CFG_REORDER_DATA (0),
.CFG_STARVE_LIMIT (10),
.CTL_CSR_ENABLED (0),
.CTL_ECC_ENABLED (0),
.CTL_ECC_AUTO_CORRECTION_ENABLED (0),
.CTL_ENABLE_BURST_INTERRUPT (0),
.CTL_ENABLE_BURST_TERMINATE (0),
.LOCAL_ID_WIDTH (8),
.RDBUFFER_ADDR_WIDTH (7),
.WRBUFFER_ADDR_WIDTH (6),
.CFG_DATA_REORDERING_TYPE ("INTER_BANK"),
.AFI_RATE_RATIO (2),
.AFI_ADDR_WIDTH (28),
.AFI_BANKADDR_WIDTH (6),
.AFI_CONTROL_WIDTH (2),
.AFI_CS_WIDTH (2),
.AFI_DM_WIDTH (32),
.AFI_DQ_WIDTH (256),
.AFI_ODT_WIDTH (2),
.AFI_WRITE_DQS_WIDTH (16),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6)
) ng0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.afi_clk (afi_clk), // afi_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.itf_cmd_ready (ng0_native_st_itf_cmd_ready), // native_st.itf_cmd_ready
.itf_cmd_valid (a0_native_st_itf_cmd_valid), // .itf_cmd_valid
.itf_cmd (a0_native_st_itf_cmd), // .itf_cmd
.itf_cmd_address (a0_native_st_itf_cmd_address), // .itf_cmd_address
.itf_cmd_burstlen (a0_native_st_itf_cmd_burstlen), // .itf_cmd_burstlen
.itf_cmd_id (a0_native_st_itf_cmd_id), // .itf_cmd_id
.itf_cmd_priority (a0_native_st_itf_cmd_priority), // .itf_cmd_priority
.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), // .itf_cmd_autopercharge
.itf_cmd_multicast (a0_native_st_itf_cmd_multicast), // .itf_cmd_multicast
.itf_wr_data_ready (ng0_native_st_itf_wr_data_ready), // .itf_wr_data_ready
.itf_wr_data_valid (a0_native_st_itf_wr_data_valid), // .itf_wr_data_valid
.itf_wr_data (a0_native_st_itf_wr_data), // .itf_wr_data
.itf_wr_data_byte_en (a0_native_st_itf_wr_data_byte_en), // .itf_wr_data_byte_en
.itf_wr_data_begin (a0_native_st_itf_wr_data_begin), // .itf_wr_data_begin
.itf_wr_data_last (a0_native_st_itf_wr_data_last), // .itf_wr_data_last
.itf_wr_data_id (a0_native_st_itf_wr_data_id), // .itf_wr_data_id
.itf_rd_data_ready (a0_native_st_itf_rd_data_ready), // .itf_rd_data_ready
.itf_rd_data_valid (ng0_native_st_itf_rd_data_valid), // .itf_rd_data_valid
.itf_rd_data (ng0_native_st_itf_rd_data), // .itf_rd_data
.itf_rd_data_error (ng0_native_st_itf_rd_data_error), // .itf_rd_data_error
.itf_rd_data_begin (ng0_native_st_itf_rd_data_begin), // .itf_rd_data_begin
.itf_rd_data_last (ng0_native_st_itf_rd_data_last), // .itf_rd_data_last
.itf_rd_data_id (ng0_native_st_itf_rd_data_id), // .itf_rd_data_id
.afi_addr (afi_addr), // afi.afi_addr
.afi_ba (afi_ba), // .afi_ba
.afi_cke (afi_cke), // .afi_cke
.afi_cs_n (afi_cs_n), // .afi_cs_n
.afi_ras_n (afi_ras_n), // .afi_ras_n
.afi_we_n (afi_we_n), // .afi_we_n
.afi_cas_n (afi_cas_n), // .afi_cas_n
.afi_odt (afi_odt), // .afi_odt
.afi_mem_clk_disable (afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (afi_init_req), // .afi_init_req
.afi_cal_req (afi_cal_req), // .afi_cal_req
.afi_dqs_burst (afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (afi_wdata), // .afi_wdata
.afi_dm (afi_dm), // .afi_dm
.afi_rdata (afi_rdata), // .afi_rdata
.afi_rdata_en (afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (afi_cal_success), // .afi_cal_success
.afi_cal_fail (afi_cal_fail), // .afi_cal_fail
.afi_wlat (afi_wlat), // .afi_wlat
.afi_rlat (afi_rlat), // .afi_rlat
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (8'b00000000), // (terminated)
.csr_be (4'b0000), // (terminated)
.csr_wdata (32'b00000000000000000000000000000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0) // (terminated)
);
alt_mem_ddrx_mm_st_converter #(
.AVL_SIZE_WIDTH (4),
.AVL_ADDR_WIDTH (25),
.AVL_DATA_WIDTH (256),
.LOCAL_ID_WIDTH (8),
.CFG_DWIDTH_RATIO (4)
) a0 (
.ctl_clk (afi_clk), // afi_clk.clk
.ctl_reset_n (afi_reset_n), // afi_reset.reset_n
.ctl_half_clk (afi_half_clk), // afi_half_clk.clk
.ctl_half_clk_reset_n (afi_reset_n), // afi_half_reset.reset_n
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size), // .burstcount
.itf_cmd_ready (ng0_native_st_itf_cmd_ready), // native_st.itf_cmd_ready
.itf_cmd_valid (a0_native_st_itf_cmd_valid), // .itf_cmd_valid
.itf_cmd (a0_native_st_itf_cmd), // .itf_cmd
.itf_cmd_address (a0_native_st_itf_cmd_address), // .itf_cmd_address
.itf_cmd_burstlen (a0_native_st_itf_cmd_burstlen), // .itf_cmd_burstlen
.itf_cmd_id (a0_native_st_itf_cmd_id), // .itf_cmd_id
.itf_cmd_priority (a0_native_st_itf_cmd_priority), // .itf_cmd_priority
.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), // .itf_cmd_autopercharge
.itf_cmd_multicast (a0_native_st_itf_cmd_multicast), // .itf_cmd_multicast
.itf_wr_data_ready (ng0_native_st_itf_wr_data_ready), // .itf_wr_data_ready
.itf_wr_data_valid (a0_native_st_itf_wr_data_valid), // .itf_wr_data_valid
.itf_wr_data (a0_native_st_itf_wr_data), // .itf_wr_data
.itf_wr_data_byte_en (a0_native_st_itf_wr_data_byte_en), // .itf_wr_data_byte_en
.itf_wr_data_begin (a0_native_st_itf_wr_data_begin), // .itf_wr_data_begin
.itf_wr_data_last (a0_native_st_itf_wr_data_last), // .itf_wr_data_last
.itf_wr_data_id (a0_native_st_itf_wr_data_id), // .itf_wr_data_id
.itf_rd_data_ready (a0_native_st_itf_rd_data_ready), // .itf_rd_data_ready
.itf_rd_data_valid (ng0_native_st_itf_rd_data_valid), // .itf_rd_data_valid
.itf_rd_data (ng0_native_st_itf_rd_data), // .itf_rd_data
.itf_rd_data_error (ng0_native_st_itf_rd_data_error), // .itf_rd_data_error
.itf_rd_data_begin (ng0_native_st_itf_rd_data_begin), // .itf_rd_data_begin
.itf_rd_data_last (ng0_native_st_itf_rd_data_last), // .itf_rd_data_last
.itf_rd_data_id (ng0_native_st_itf_rd_data_id), // .itf_rd_data_id
.local_multicast (1'b0), // (terminated)
.local_autopch_req (1'b0), // (terminated)
.local_priority (1'b0) // (terminated)
);
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************
// File name: addr_cmd_ldc_pad.v
//
// Address/command pad using leveling hardware.
// See comments in addr_cmd_ldc_pads.v for details.
//
// *****************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad (
pll_afi_clk,
pll_hr_clk,
pll_c2p_write_clk,
pll_write_clk,
dll_delayctrl_in,
afi_datain,
mem_dataout
);
// *****************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in
// from higher level wrapper with the controller and driver
parameter AFI_DATA_WIDTH = "";
parameter MEM_DATA_WIDTH = "";
parameter DLL_WIDTH = "";
parameter REGISTER_C2P = "";
localparam DDR_MULT = AFI_DATA_WIDTH / MEM_DATA_WIDTH / 2;
// *****************************************************************
// BEGIN PORT SECTION
input pll_afi_clk;
input pll_hr_clk;
input pll_c2p_write_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_DATA_WIDTH-1:0] afi_datain;
output [MEM_DATA_WIDTH-1:0] mem_dataout;
// *****************************************************************
// BEGIN SIGNALS SECTION
wire [2 * DDR_MULT * MEM_DATA_WIDTH - 1:0] hr_data;
wire [1 * DDR_MULT * MEM_DATA_WIDTH - 1:0] fr_data;
reg [MEM_DATA_WIDTH - 1:0] fr_data_reg;
// *****************************************************************
// The AFI domain is the half-rate domain.
// Register the C2P boundary if needed.
generate
if (REGISTER_C2P == "false") begin
assign hr_data = afi_datain;
end else begin
reg [2 * DDR_MULT * MEM_DATA_WIDTH - 1:0] tmp_hr_data_reg;
always @(posedge pll_afi_clk) begin
tmp_hr_data_reg <= afi_datain;
end
assign hr_data = tmp_hr_data_reg;
end
endgenerate
// *****************************************************************
// Half-rate to full-rate conversion using half-rate register
DE4_SOPC_ddr2_0_p0_simple_ddio_out # (
.DATA_WIDTH (MEM_DATA_WIDTH),
.OUTPUT_FULL_DATA_WIDTH (MEM_DATA_WIDTH),
.USE_CORE_LOGIC ("false"),
.HALF_RATE_MODE ("true")
) hr_to_fr (
.clk (pll_c2p_write_clk),
.datain (hr_data),
.dataout (fr_data),
.reset_n (1'b1)
);
generate
genvar i;
for (i = 0; i < MEM_DATA_WIDTH; i = i + 1)
begin: sdio_out
wire [3:0] delayed_clks;
wire leveling_clk;
// We instantiate one leveling delay chain and clock phase select
// block per pin. The fitter merges these blocks as needed
// to maximize pin placement flexibility.
stratixv_leveling_delay_chain # (
.physical_clock_source ("dqs")
) ldc (
.clkin (pll_write_clk),
.delayctrlin (dll_delayctrl_in),
.clkout (delayed_clks)
);
stratixv_clk_phase_select # (
.physical_clock_source ("add_cmd"),
.use_phasectrlin ("false"),
.invert_phase ("false"),
.phase_setting (0)
) cps (
.clkin (delayed_clks),
.clkout (leveling_clk)
);
// Output data goes through the SDIO register to phase-align it
// with the leveling clock which has the property of center-
// aligning the addr/cmd signals with the ck/ck# clock.
always @(posedge leveling_clk) begin
fr_data_reg[i] = fr_data[i];
end
assign mem_dataout[i] = fr_data_reg[i];
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************
// File name: addr_cmd_ldc_pads.v
//
// Address/command pads using PHY clock and leveling hardware.
//
// Inputs are addr/cmd signals in the AFI domain.
//
// Outputs are addr/cmd signals that can be readily connected to
// top-level ports going out to external memory.
//
// This version offers higher performance than previous generation
// of addr/cmd pads. To highlight the differences:
//
// 1) We use the PHY clock tree to clock the addr/cmd I/Os, instead
// of core clock. The PHY clock tree has much smaller clock skew
// compared to the core clock, giving us more timing margin.
//
// 2) The PHY clock tree drives a leveling delay chain which
// generates both the CK/CK# clock and the launch clock for the
// addr/cmd signals. The similarity between the CK/CK# path and
// the addr/cmd signal paths reduces timing margin loss due to
// min/max. Previous generation uses separate PLL output counter
// and global networks for CK/CK# and addr/cmd signals.
//
// Important clock signals:
//
// pll_afi_clk -- AFI clock. Only used by 1/4-rate designs to
// convert 1/4 addr/cmd signals to 1/2 rate, or
// when REGISTER_C2P is true.
//
// pll_c2p_write_clk -- Half-rate clock that clocks the HR registers
// for 1/2-rate to full rate conversion. Only
// used in 1/4 rate and 1/2 rate designs.
// This signal must come from the PHY clock.
//
// pll_write_clk -- Full-rate clock that goes into the leveling
// delay chain and then used to clock the SDIO
// register (or DDIO_OUT) and for CK/CK# generation.
// This signal must come from the PHY clock.
//
// *****************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pads (
reset_n,
reset_n_afi_clk,
pll_afi_clk,
pll_mem_clk,
pll_hr_clk,
pll_c2p_write_clk,
pll_write_clk,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
dll_delayctrl_in,
enable_mem_clk,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_ck,
phy_mem_ck_n
);
// *****************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in
// from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter DLL_WIDTH = "";
parameter REGISTER_C2P = "";
// Width of the addr/cmd signals going out to the external memory
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
// Width of the addr/cmd signals coming in from the AFI
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
// *****************************************************************
// BEGIN PORT SECTION
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_hr_clk;
input pll_c2p_write_clk;
input phy_ddio_addr_cmd_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [MEM_CK_WIDTH-1:0] enable_mem_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
// *****************************************************************
// Instantiate pads for every a/c signal
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_ADDRESS_WIDTH),
.MEM_DATA_WIDTH (MEM_ADDRESS_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uaddress_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_address),
.mem_dataout (phy_mem_address)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_BANK_WIDTH),
.MEM_DATA_WIDTH (MEM_BANK_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ubank_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_bank),
.mem_dataout (phy_mem_bank)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CHIP_SELECT_WIDTH),
.MEM_DATA_WIDTH (MEM_CHIP_SELECT_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ucs_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_cs_n),
.mem_dataout (phy_mem_cs_n)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CLK_EN_WIDTH),
.MEM_DATA_WIDTH (MEM_CLK_EN_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ucke_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_cke),
.mem_dataout (phy_mem_cke)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_ODT_WIDTH),
.MEM_DATA_WIDTH (MEM_ODT_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uodt_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_odt),
.mem_dataout (phy_mem_odt)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CONTROL_WIDTH),
.MEM_DATA_WIDTH (MEM_CONTROL_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uwe_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_we_n),
.mem_dataout (phy_mem_we_n)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CONTROL_WIDTH),
.MEM_DATA_WIDTH (MEM_CONTROL_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uras_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_ras_n),
.mem_dataout (phy_mem_ras_n)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CONTROL_WIDTH),
.MEM_DATA_WIDTH (MEM_CONTROL_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ucas_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_cas_n),
.mem_dataout (phy_mem_cas_n)
);
// *****************************************************************
// Instantiate CK/CK# generation circuitry if needed
genvar clock_width;
generate
for (clock_width = 0; clock_width < MEM_CK_WIDTH; clock_width = clock_width + 1)
begin: clock_gen
wire [MEM_CK_WIDTH-1:0] mem_ck_ddio_out;
wire [3:0] delayed_clks;
wire leveling_clk;
stratixv_leveling_delay_chain # (
.physical_clock_source ("dqs")
) ldc (
.clkin (pll_write_clk),
.delayctrlin (dll_delayctrl_in),
.clkout (delayed_clks)
);
stratixv_clk_phase_select # (
.physical_clock_source ("add_cmd"),
.use_phasectrlin ("false"),
.invert_phase ("false"),
.phase_setting (0)
) cps (
.clkin (delayed_clks),
.clkout (leveling_clk)
);
altddio_out # (
.extend_oe_disable ("UNUSED"),
.intended_device_family (DEVICE_FAMILY),
.invert_output ("OFF"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) umem_ck_pad (
.aclr (1'b0),
.aset (1'b0),
.datain_h (1'b0),
.datain_l (1'b1),
.dataout (mem_ck_ddio_out[clock_width]),
.oe (enable_mem_clk[clock_width]),
.outclock (leveling_clk),
.outclocken (1'b1)
);
DE4_SOPC_ddr2_0_p0_clock_pair_generator uclk_generator (
.datain (mem_ck_ddio_out[clock_width]),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_addr_cmd_pads(
reset_n,
reset_n_afi_clk,
pll_afi_clk,
pll_mem_clk,
pll_c2p_write_clk,
pll_write_clk,
pll_hr_clk,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
dll_delayctrl_in,
enable_mem_clk,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_hr_clk;
input pll_c2p_write_clk;
input phy_ddio_addr_cmd_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [MEM_CK_WIDTH-1:0] enable_mem_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
wire [MEM_ADDRESS_WIDTH-1:0] address_l;
wire [MEM_ADDRESS_WIDTH-1:0] address_h;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] cke_h;
wire [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address_hr = phy_ddio_address;
wire [AFI_BANK_WIDTH-1:0] phy_ddio_bank_hr = phy_ddio_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_hr = phy_ddio_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke_hr = phy_ddio_cke;
wire [AFI_ODT_WIDTH-1:0] phy_ddio_odt_hr = phy_ddio_odt;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n_hr = phy_ddio_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n_hr = phy_ddio_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n_hr = phy_ddio_we_n;
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_l;
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_h;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_l;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_h;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_h;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_l;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_h;
// each signal has a high and a low portion,
// connecting to the high and low inputs of the DDIO_OUT,
// for the purpose of creating double data rate
assign phy_ddio_address_l = phy_ddio_address_hr[MEM_ADDRESS_WIDTH-1:0];
assign phy_ddio_bank_l = phy_ddio_bank_hr[MEM_BANK_WIDTH-1:0];
assign phy_ddio_cke_l = phy_ddio_cke_hr[MEM_CLK_EN_WIDTH-1:0];
assign phy_ddio_odt_l = phy_ddio_odt_hr[MEM_ODT_WIDTH-1:0];
assign phy_ddio_cs_n_l = phy_ddio_cs_n_hr[MEM_CHIP_SELECT_WIDTH-1:0];
assign phy_ddio_we_n_l = phy_ddio_we_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_ras_n_l = phy_ddio_ras_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_cas_n_l = phy_ddio_cas_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_address_h = phy_ddio_address_hr[2*MEM_ADDRESS_WIDTH-1:MEM_ADDRESS_WIDTH];
assign phy_ddio_bank_h = phy_ddio_bank_hr[2*MEM_BANK_WIDTH-1:MEM_BANK_WIDTH];
assign phy_ddio_cke_h = phy_ddio_cke_hr[2*MEM_CLK_EN_WIDTH-1:MEM_CLK_EN_WIDTH];
assign phy_ddio_odt_h = phy_ddio_odt_hr[2*MEM_ODT_WIDTH-1:MEM_ODT_WIDTH];
assign phy_ddio_cs_n_h = phy_ddio_cs_n_hr[2*MEM_CHIP_SELECT_WIDTH-1:MEM_CHIP_SELECT_WIDTH];
assign phy_ddio_we_n_h = phy_ddio_we_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_ras_n_h = phy_ddio_ras_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_cas_n_h = phy_ddio_cas_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign address_l = phy_ddio_address_l;
assign address_h = phy_ddio_address_h;
altddio_out uaddress_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (address_l),
.datain_l (address_h),
.dataout (phy_mem_address),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uaddress_pad.extend_oe_disable = "UNUSED",
uaddress_pad.intended_device_family = DEVICE_FAMILY,
uaddress_pad.invert_output = "OFF",
uaddress_pad.lpm_hint = "UNUSED",
uaddress_pad.lpm_type = "altddio_out",
uaddress_pad.oe_reg = "UNUSED",
uaddress_pad.power_up_high = "OFF",
uaddress_pad.width = MEM_ADDRESS_WIDTH;
altddio_out ubank_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_bank_l),
.datain_l (phy_ddio_bank_h),
.dataout (phy_mem_bank),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ubank_pad.extend_oe_disable = "UNUSED",
ubank_pad.intended_device_family = DEVICE_FAMILY,
ubank_pad.invert_output = "OFF",
ubank_pad.lpm_hint = "UNUSED",
ubank_pad.lpm_type = "altddio_out",
ubank_pad.oe_reg = "UNUSED",
ubank_pad.power_up_high = "OFF",
ubank_pad.width = MEM_BANK_WIDTH;
assign cs_n_l = phy_ddio_cs_n_l;
assign cs_n_h = phy_ddio_cs_n_h;
altddio_out ucs_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (cs_n_l),
.datain_l (cs_n_h),
.dataout (phy_mem_cs_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucs_n_pad.extend_oe_disable = "UNUSED",
ucs_n_pad.intended_device_family = DEVICE_FAMILY,
ucs_n_pad.invert_output = "OFF",
ucs_n_pad.lpm_hint = "UNUSED",
ucs_n_pad.lpm_type = "altddio_out",
ucs_n_pad.oe_reg = "UNUSED",
ucs_n_pad.power_up_high = "OFF",
ucs_n_pad.width = MEM_CHIP_SELECT_WIDTH;
assign cke_l = phy_ddio_cke_l;
assign cke_h = phy_ddio_cke_h;
altddio_out ucke_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (cke_l),
.datain_l (cke_h),
.dataout (phy_mem_cke),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucke_pad.extend_oe_disable = "UNUSED",
ucke_pad.intended_device_family = DEVICE_FAMILY,
ucke_pad.invert_output = "OFF",
ucke_pad.lpm_hint = "UNUSED",
ucke_pad.lpm_type = "altddio_out",
ucke_pad.oe_reg = "UNUSED",
ucke_pad.power_up_high = "OFF",
ucke_pad.width = MEM_CLK_EN_WIDTH;
altddio_out uodt_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_odt_l),
.datain_l (phy_ddio_odt_h),
.dataout (phy_mem_odt),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uodt_pad.extend_oe_disable = "UNUSED",
uodt_pad.intended_device_family = DEVICE_FAMILY,
uodt_pad.invert_output = "OFF",
uodt_pad.lpm_hint = "UNUSED",
uodt_pad.lpm_type = "altddio_out",
uodt_pad.oe_reg = "UNUSED",
uodt_pad.power_up_high = "OFF",
uodt_pad.width = MEM_ODT_WIDTH;
altddio_out uwe_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_we_n_l),
.datain_l (phy_ddio_we_n_h),
.dataout (phy_mem_we_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uwe_n_pad.extend_oe_disable = "UNUSED",
uwe_n_pad.intended_device_family = DEVICE_FAMILY,
uwe_n_pad.invert_output = "OFF",
uwe_n_pad.lpm_hint = "UNUSED",
uwe_n_pad.lpm_type = "altddio_out",
uwe_n_pad.oe_reg = "UNUSED",
uwe_n_pad.power_up_high = "OFF",
uwe_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out uras_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_ras_n_l),
.datain_l (phy_ddio_ras_n_h),
.dataout (phy_mem_ras_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uras_n_pad.extend_oe_disable = "UNUSED",
uras_n_pad.intended_device_family = DEVICE_FAMILY,
uras_n_pad.invert_output = "OFF",
uras_n_pad.lpm_hint = "UNUSED",
uras_n_pad.lpm_type = "altddio_out",
uras_n_pad.oe_reg = "UNUSED",
uras_n_pad.power_up_high = "OFF",
uras_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out ucas_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_cas_n_l),
.datain_l (phy_ddio_cas_n_h),
.dataout (phy_mem_cas_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucas_n_pad.extend_oe_disable = "UNUSED",
ucas_n_pad.intended_device_family = DEVICE_FAMILY,
ucas_n_pad.invert_output = "OFF",
ucas_n_pad.lpm_hint = "UNUSED",
ucas_n_pad.lpm_type = "altddio_out",
ucas_n_pad.oe_reg = "UNUSED",
ucas_n_pad.power_up_high = "OFF",
ucas_n_pad.width = MEM_CONTROL_WIDTH;
wire mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
assign mem_ck_source = pll_mem_clk;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (1'b1),
.datain_l (1'b0),
.dataout (mem_ck[clock_width]),
.oe (enable_mem_clk[clock_width]),
.outclock (mem_ck_source),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
DE4_SOPC_ddr2_0_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
strobe_ena_hr_clock_in,
strobe_ena_clock_in,
capture_strobe_ena,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
dll_delayctrl_in
);
input [6-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input strobe_ena_hr_clock_in;
input strobe_ena_clock_in;
input [1-1:0] capture_strobe_ena;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [14-1:0] parallelterminationcontrol_in;
input [14-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_ddio_3reg_stratixiv altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.strobe_ena_clock_in( strobe_ena_clock_in),
.capture_strobe_ena( capture_strobe_ena),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.OUTPUT_DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.OUTPUT_DQ_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 200;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "5000 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "HIGH";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 2;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 7200;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.DLL_WIDTH = 6;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "low";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "true";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Stratix IV" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 11.1 cbx_altiobuf_out 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_io_obuf 2 stratixiv_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module DE4_SOPC_ddr2_0_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] oe_b;
wire [0:0] oe_w;
stratixiv_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(oe_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "stratixiv_io_obuf";
stratixiv_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.shift_series_termination_control = "false",
obufa_0.lpm_type = "stratixiv_io_obuf";
stratixiv_pseudo_diff_out pseudo_diffa_0
(
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]));
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_b = 1'b1,
oe_w = 1'b1;
endmodule //DE4_SOPC_ddr2_0_p0_clock_pair_generator
//VALID FILE
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
(* altera_attribute = "-name ALLOW_SYNCH_CTRL_USAGE ON;-name AUTO_CLOCK_ENABLE_RECOGNITION ON" *)
module DE4_SOPC_ddr2_0_p0_flop_mem(
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
parameter READ_DATA_WIDTH = "";
input wr_clk;
input wr_en;
input [WRITE_ADDR_WIDTH-1:0] wr_addr;
input [WRITE_DATA_WIDTH-1:0] wr_data;
input rd_reset_n;
input rd_clk;
input rd_en;
input [READ_ADDR_WIDTH-1:0] rd_addr;
output [READ_DATA_WIDTH-1:0] rd_data;
wire [WRITE_MEM_DEPTH-1:0] wr_decode;
wire [WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
wire [READ_DATA_WIDTH-1:0] mux_data_out;
// declare a memory with WRITE_MEM_DEPTH entries
// each entry contains a data size of WRITE_DATA_WIDTH
reg [WRITE_DATA_WIDTH-1:0] data_stored [0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
reg [READ_DATA_WIDTH-1:0] rd_data;
always @(posedge wr_clk)
begin
if(wr_en)
data_stored[wr_addr] <= wr_data;
end
generate
genvar entry;
for (entry=0; entry < WRITE_MEM_DEPTH; entry=entry+1)
begin: mem_location
assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry];
end
endgenerate
// mux to select the correct output data based on read address
lpm_mux uread_mux(
.sel (rd_addr),
.data (all_data),
.result (mux_data_out)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam uread_mux.lpm_size = READ_MEM_DEPTH;
defparam uread_mux.lpm_type = "LPM_MUX";
defparam uread_mux.lpm_width = READ_DATA_WIDTH;
defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
always @(posedge rd_clk)
begin
rd_data <= mux_data_out;
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: fr_cycle_shifter.v
//
// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
// "__" means don't-care.
//
// shift_by dataout in current cycle dataout in next clock cycle
// 00 {T3, T2, T1, T0} {__, __, __, __}
// 01 {T2, T1, T0, __} {__, __, __, T3}
// 10 {T1, T0, __, __} {__, __, T3, T2}
// 11 {T0, __, __, __} {__, T3, T2, T1}
//
// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
// (i.e. you can only shift by 0 or 1 fr-cycle).
// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
//
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_hr_to_fr(
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk)
begin
q_h0 <= d_h0;
q_l0 <= d_l0;
q_h1 <= d_h1;
q_l1 <= d_l1;
end
always @(negedge clk)
begin
q_l0_neg <= q_l0;
q_l1_neg <= q_l1;
end
assign q0 = clk ? q_l0_neg : q_h0;
assign q1 = clk ? q_l1_neg : q_h1;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
module DE4_SOPC_ddr2_0_p0_memphy(
global_reset_n,
soft_reset_n,
reset_request_n,
ctl_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_cke,
afi_cs_n,
afi_ba,
afi_cas_n,
afi_odt,
afi_ras_n,
afi_we_n,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wlat,
afi_rlat,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_cal_debug_info,
afi_ctl_refresh_done,
afi_ctl_long_idle,
afi_seq_busy,
afi_cal_success,
afi_cal_fail,
mem_a,
mem_ba,
mem_ck,
mem_ck_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dq,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
phy_reset_n,
phy_read_latency_counter,
phy_afi_wlat,
phy_afi_rlat,
phy_num_write_fr_cycle_shifts,
phy_read_increment_vfifo_fr,
phy_read_increment_vfifo_hr,
phy_read_increment_vfifo_qr,
phy_reset_mem_stable,
phy_cal_debug_info,
phy_read_fifo_reset,
phy_vfifo_rd_en_override,
phy_read_fifo_q,
calib_skip_steps,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DEBUG_INFO_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_MAX_WRITE_LATENCY_COUNT_WIDTH = "";
parameter AFI_MAX_READ_LATENCY_COUNT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter AFI_RATE_RATIO = "";
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
// Read Datapath parameters for timing purposes
parameter NUM_SUBGROUP_PER_READ_DQS = "";
parameter QVLD_EXTRA_FLOP_STAGES = "";
parameter QVLD_WR_ADDRESS_OFFSET = "";
// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture
parameter READ_VALID_FIFO_SIZE = "";
parameter READ_FIFO_SIZE = "";
// Latency calibration parameters
parameter MAX_LATENCY_COUNT_WIDTH = "";
parameter MAX_READ_LATENCY = "";
// Write Datapath
// The sequencer uses this value to control write latency during calibration
parameter MAX_WRITE_LATENCY_COUNT_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
// Add register stage between core and periphery for C2P transfers
parameter REGISTER_C2P = "";
// Address/Command Datapath
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
parameter MEM_T_RL = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Local parameters
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Read valid predication parameters
localparam READ_VALID_FIFO_WRITE_MEM_DEPTH = READ_VALID_FIFO_SIZE / 2; // write operates on half rate clock
localparam READ_VALID_FIFO_READ_MEM_DEPTH = READ_VALID_FIFO_SIZE; // valid-read-prediction operates on full rate clock
localparam READ_VALID_FIFO_PER_DQS_WIDTH = 1; // valid fifo output is a full-rate signal
localparam READ_VALID_FIFO_WIDTH = READ_VALID_FIFO_PER_DQS_WIDTH * MEM_READ_DQS_WIDTH;
localparam READ_VALID_FIFO_WRITE_ADDR_WIDTH = ceil_log2(READ_VALID_FIFO_WRITE_MEM_DEPTH);
localparam READ_VALID_FIFO_READ_ADDR_WIDTH = ceil_log2(READ_VALID_FIFO_READ_MEM_DEPTH);
// Data resynchronization FIFO
localparam READ_FIFO_WRITE_MEM_DEPTH = READ_FIFO_SIZE / 2; // data is written on half rate clock
localparam READ_FIFO_READ_MEM_DEPTH = READ_FIFO_SIZE / 2; // data is read out on half rate clock
localparam READ_FIFO_WRITE_ADDR_WIDTH = ceil_log2(READ_FIFO_WRITE_MEM_DEPTH);
localparam READ_FIFO_READ_ADDR_WIDTH = ceil_log2(READ_FIFO_READ_MEM_DEPTH);
// Sequencer parameters
localparam SEQ_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
localparam SEQ_BANK_WIDTH = AFI_BANK_WIDTH;
localparam SEQ_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
localparam SEQ_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
localparam SEQ_ODT_WIDTH = AFI_ODT_WIDTH;
localparam SEQ_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
localparam SEQ_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
localparam SEQ_DATA_WIDTH = AFI_DATA_WIDTH;
localparam SEQ_DQS_WIDTH = AFI_DQS_WIDTH;
localparam MAX_LATENCY_COUNT_WIDTH_SAFE = (MAX_LATENCY_COUNT_WIDTH < 5)? 5 : MAX_LATENCY_COUNT_WIDTH;
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output reset_request_n; // When 1, PLL is out of lock
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [AFI_ADDRESS_WIDTH-1:0] afi_addr; // address
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_BANK_WIDTH-1:0] afi_ba;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [MEM_CK_WIDTH-1:0] afi_mem_clk_disable;
input [AFI_DQS_WIDTH-1:0] afi_dqs_burst;
output [AFI_MAX_WRITE_LATENCY_COUNT_WIDTH-1:0] afi_wlat;
output [AFI_MAX_READ_LATENCY_COUNT_WIDTH-1:0] afi_rlat;
// Write data interface
input [AFI_DATA_WIDTH-1:0] afi_wdata; // write data
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm; // write data mask
// Read data interface
output [AFI_DATA_WIDTH-1:0] afi_rdata; // read data
input [AFI_RATE_RATIO-1:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [AFI_RATE_RATIO-1:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [AFI_RATE_RATIO-1:0] afi_rdata_valid; // read data valid
// Status interface
input afi_cal_success; // calibration success
input afi_cal_fail; // calibration failure
output [AFI_DEBUG_INFO_WIDTH - 1:0] afi_cal_debug_info;
input [MEM_CHIP_SELECT_WIDTH-1:0] afi_ctl_refresh_done;
input [MEM_CHIP_SELECT_WIDTH-1:0] afi_ctl_long_idle;
output [MEM_CHIP_SELECT_WIDTH-1:0] afi_seq_busy;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_CHIP_SELECT_WIDTH-1:0] mem_cs_n;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output phy_reset_n;
input [MAX_LATENCY_COUNT_WIDTH-1:0] phy_read_latency_counter;
input [AFI_MAX_WRITE_LATENCY_COUNT_WIDTH-1:0] phy_afi_wlat;
input [AFI_MAX_READ_LATENCY_COUNT_WIDTH-1:0] phy_afi_rlat;
input [MEM_WRITE_DQS_WIDTH*2-1:0] phy_num_write_fr_cycle_shifts;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_fr;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_hr;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_qr;
input phy_reset_mem_stable;
input [AFI_DEBUG_INFO_WIDTH - 1:0] phy_cal_debug_info;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_fifo_reset;
input [MEM_READ_DQS_WIDTH-1:0] phy_vfifo_rd_en_override;
output [AFI_DATA_WIDTH-1:0] phy_read_fifo_q;
output [CALIB_REG_WIDTH-1:0] calib_skip_steps;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
// DLL Interface
output dll_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
wire [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
wire [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
localparam DDIO_PHY_DQ_WIDTH = DOUBLE_MEM_DQ_WIDTH;
wire [DDIO_PHY_DQ_WIDTH-1:0] ddio_phy_dq;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
wire [AFI_DATA_WIDTH-1:0] afi_rdata;
wire [AFI_RATE_RATIO-1:0] afi_rdata_valid;
wire [SEQ_ADDRESS_WIDTH-1:0] seq_mux_address;
wire [SEQ_BANK_WIDTH-1:0] seq_mux_bank;
wire [SEQ_CHIP_SELECT_WIDTH-1:0] seq_mux_cs_n;
wire [SEQ_CLK_EN_WIDTH-1:0] seq_mux_cke;
wire [SEQ_ODT_WIDTH-1:0] seq_mux_odt;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_ras_n;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_cas_n;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_we_n;
wire [SEQ_DQS_WIDTH-1:0] seq_mux_dqs_en;
wire [SEQ_DATA_WIDTH-1:0] seq_mux_wdata;
wire [SEQ_DQS_WIDTH-1:0] seq_mux_wdata_valid;
wire [SEQ_DATA_MASK_WIDTH-1:0] seq_mux_dm;
wire seq_mux_rdata_en;
wire [SEQ_DATA_WIDTH-1:0] mux_seq_rdata;
wire mux_seq_rdata_valid;
wire mux_sel;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_resync_clk;
wire [READ_VALID_FIFO_WIDTH-1:0] dqs_enable_ctrl;
wire [AFI_DQS_WIDTH-1:0] force_oct_off;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire csr_soft_reset_req;
wire [MEM_READ_DQS_WIDTH-1:0] dqs_edge_detect;
wire [MEM_CK_WIDTH-1:0] afi_mem_clk_disable;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = (FAST_SIM_MODEL ? 1'b1 : 1'b0);
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifndef SYNTH_FOR_SIM
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifndef SYNTH_FOR_SIM
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifndef SYNTH_FOR_SIM
// synthesis read_comments_as_HDL off
`endif
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.csr_soft_reset_req (csr_soft_reset_req),
.reset_request_n (reset_request_n),
.ctl_reset_n (ctl_reset_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
wire scc_data;
wire [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
wire [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
wire [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
wire [MEM_DM_WIDTH - 1:0] scc_dm_ena;
wire scc_upd;
wire [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
assign calib_skip_steps = seq_calib_init_reg;
assign afi_cal_debug_info = phy_cal_debug_info;
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign afi_wlat = phy_afi_wlat;
assign afi_rlat = phy_afi_rlat;
// ********************************************************************************************************************************
// The address and command datapath is responsible for adding any flop stages/extra logic that may be required between the AFI
// interface and the output DDIOs.
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_addr_cmd_datapath uaddr_cmd_datapath(
.clk (pll_addr_cmd_clk),
.reset_n (reset_n_afi_clk[1]),
.afi_address (afi_addr),
.afi_bank (afi_ba),
.afi_cs_n (afi_cs_n),
.afi_cke (afi_cke),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_cas_n (afi_cas_n),
.afi_we_n (afi_we_n),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n)
);
defparam uaddr_cmd_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_datapath.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uaddr_cmd_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uaddr_cmd_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uaddr_cmd_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uaddr_cmd_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uaddr_cmd_datapath.NUM_AC_FR_CYCLE_SHIFTS = NUM_AC_FR_CYCLE_SHIFTS;
// ********************************************************************************************************************************
// The write datapath is responsible for adding any flop stages/extra logic that may be required between the AFI interface
// and the output DDIOs.
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_write_datapath uwrite_datapath(
.pll_afi_clk (pll_afi_clk),
.reset_n (reset_n_afi_clk[2]),
.force_oct_off (force_oct_off),
.phy_ddio_oct_ena (phy_ddio_oct_ena),
.afi_dqs_en (afi_dqs_burst),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_dm (afi_dm),
.phy_ddio_dq (phy_ddio_dq),
.phy_ddio_dqs_en (phy_ddio_dqs_en),
.phy_ddio_wrdata_en (phy_ddio_wrdata_en),
.phy_ddio_wrdata_mask (phy_ddio_wrdata_mask),
.seq_num_write_fr_cycle_shifts (phy_num_write_fr_cycle_shifts)
);
defparam uwrite_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uwrite_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uwrite_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uwrite_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uwrite_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uwrite_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uwrite_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uwrite_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uwrite_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uwrite_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uwrite_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uwrite_datapath.NUM_WRITE_PATH_FLOP_STAGES = NUM_WRITE_PATH_FLOP_STAGES;
defparam uwrite_datapath.NUM_WRITE_FR_CYCLE_SHIFTS = NUM_WRITE_FR_CYCLE_SHIFTS;
// ********************************************************************************************************************************
// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_read_datapath uread_datapath(
.reset_n_afi_clk (reset_n_afi_clk[3]),
.reset_n_resync_clk (reset_n_resync_clk),
.seq_read_fifo_reset (phy_read_fifo_reset),
.pll_afi_clk (pll_afi_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.read_capture_clk (read_capture_clk),
.ddio_phy_dq (ddio_phy_dq),
.seq_read_latency_counter (phy_read_latency_counter),
.seq_read_increment_vfifo_fr (phy_read_increment_vfifo_fr),
.seq_read_increment_vfifo_hr (phy_read_increment_vfifo_hr),
.seq_read_increment_vfifo_qr (phy_read_increment_vfifo_qr),
.force_oct_off (force_oct_off),
.dqs_enable_ctrl (dqs_enable_ctrl),
.afi_rdata_en (afi_rdata_en),
.afi_rdata_en_full (afi_rdata_en_full),
.afi_rdata (afi_rdata),
.phy_mux_read_fifo_q (phy_read_fifo_q),
.afi_rdata_valid (afi_rdata_valid),
.seq_calib_init (seq_calib_init_reg),
.dqs_edge_detect (dqs_edge_detect)
);
defparam uread_datapath.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uread_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uread_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uread_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uread_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uread_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uread_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uread_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uread_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uread_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uread_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uread_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uread_datapath.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
defparam uread_datapath.MAX_READ_LATENCY = MAX_READ_LATENCY;
defparam uread_datapath.READ_FIFO_READ_MEM_DEPTH = READ_FIFO_READ_MEM_DEPTH;
defparam uread_datapath.READ_FIFO_READ_ADDR_WIDTH = READ_FIFO_READ_ADDR_WIDTH;
defparam uread_datapath.READ_FIFO_WRITE_MEM_DEPTH = READ_FIFO_WRITE_MEM_DEPTH;
defparam uread_datapath.READ_FIFO_WRITE_ADDR_WIDTH = READ_FIFO_WRITE_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_SIZE = READ_VALID_FIFO_SIZE;
defparam uread_datapath.READ_VALID_FIFO_READ_MEM_DEPTH = READ_VALID_FIFO_READ_MEM_DEPTH;
defparam uread_datapath.READ_VALID_FIFO_READ_ADDR_WIDTH = READ_VALID_FIFO_READ_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_WRITE_MEM_DEPTH = READ_VALID_FIFO_WRITE_MEM_DEPTH;
defparam uread_datapath.READ_VALID_FIFO_WRITE_ADDR_WIDTH = READ_VALID_FIFO_WRITE_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_PER_DQS_WIDTH = READ_VALID_FIFO_PER_DQS_WIDTH;
defparam uread_datapath.NUM_SUBGROUP_PER_READ_DQS = NUM_SUBGROUP_PER_READ_DQS;
defparam uread_datapath.MEM_T_RL = MEM_T_RL;
defparam uread_datapath.CALIB_REG_WIDTH = CALIB_REG_WIDTH;
defparam uread_datapath.QVLD_EXTRA_FLOP_STAGES = QVLD_EXTRA_FLOP_STAGES;
defparam uread_datapath.QVLD_WR_ADDRESS_OFFSET = QVLD_WR_ADDRESS_OFFSET;
defparam uread_datapath.FAST_SIM_MODEL = FAST_SIM_MODEL;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_new_io_pads uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
// Address and Command
.phy_ddio_addr_cmd_clk (pll_addr_cmd_clk),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
// Write
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.phy_ddio_dq (phy_ddio_dq),
.phy_ddio_dqs_en (phy_ddio_dqs_en),
.phy_ddio_oct_ena (phy_ddio_oct_ena),
.dqs_enable_ctrl (dqs_enable_ctrl),
.phy_ddio_wrdata_en (phy_ddio_wrdata_en),
.phy_ddio_wrdata_mask (phy_ddio_wrdata_mask),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
// Read
.dll_phy_delayctrl (dll_phy_delayctrl),
.ddio_phy_dq (ddio_phy_dq),
.read_capture_clk (read_capture_clk)
,
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd),
.enable_mem_clk (~afi_mem_clk_disable),
.capture_strobe_tracking (capture_strobe_tracking)
);
defparam uio_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uio_pads.OCT_SERIES_TERM_CONTROL_WIDTH = OCT_SERIES_TERM_CONTROL_WIDTH;
defparam uio_pads.OCT_PARALLEL_TERM_CONTROL_WIDTH = OCT_PARALLEL_TERM_CONTROL_WIDTH;
defparam uio_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uio_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uio_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uio_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uio_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uio_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uio_pads.MEM_DQS_WIDTH = MEM_DQS_WIDTH;
defparam uio_pads.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uio_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uio_pads.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uio_pads.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uio_pads.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uio_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uio_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uio_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uio_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uio_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uio_pads.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uio_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uio_pads.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uio_pads.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uio_pads.DLL_DELAY_CTRL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uio_pads.REGISTER_C2P = REGISTER_C2P;
defparam uio_pads.DQS_ENABLE_CTRL_WIDTH = READ_VALID_FIFO_WIDTH;
defparam uio_pads.ALTDQDQS_INPUT_FREQ = ALTDQDQS_INPUT_FREQ;
defparam uio_pads.ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = ALTDQDQS_DELAY_CHAIN_BUFFER_MODE;
defparam uio_pads.ALTDQDQS_DQS_PHASE_SETTING = ALTDQDQS_DQS_PHASE_SETTING;
defparam uio_pads.ALTDQDQS_DQS_PHASE_SHIFT = ALTDQDQS_DQS_PHASE_SHIFT;
defparam uio_pads.ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING;
defparam uio_pads.FAST_SIM_MODEL = FAST_SIM_MODEL;
assign csr_soft_reset_req = 1'b0;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10036
module DE4_SOPC_ddr2_0_p0_new_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
pll_dqs_ena_clk,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_oct_ena,
dqs_enable_ctrl,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
ddio_phy_dq,
read_capture_clk,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
enable_mem_clk,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter REGISTER_C2P = "";
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter DQS_ENABLE_CTRL_WIDTH = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter FAST_SIM_MODEL = "";
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
localparam HALF_AFI_DQS_WIDTH = AFI_DQS_WIDTH / 2;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input phy_ddio_addr_cmd_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
input [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
input [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [DQS_ENABLE_CTRL_WIDTH-1:0] dqs_enable_ctrl;
input [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
input [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
localparam DDIO_PHY_DQ_WIDTH = DOUBLE_MEM_DQ_WIDTH;
output [DDIO_PHY_DQ_WIDTH-1:0] ddio_phy_dq;
output [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input scc_upd;
input [MEM_CK_WIDTH-1:0] enable_mem_clk;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire hr_clk = pll_afi_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
reg [AFI_DATA_WIDTH-1:0] phy_ddio_dq_int;
reg [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_int;
reg [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_int;
reg [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_int;
reg [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_int;
generate
if (REGISTER_C2P == "false") begin
always @(*) begin
phy_ddio_dq_int <= phy_ddio_dq;
phy_ddio_wrdata_en_int <= phy_ddio_wrdata_en;
phy_ddio_wrdata_mask_int <= phy_ddio_wrdata_mask;
phy_ddio_dqs_en_int <= phy_ddio_dqs_en;
phy_ddio_oct_ena_int <= phy_ddio_oct_ena;
end
end else begin
always @(posedge pll_afi_clk) begin
phy_ddio_dq_int <= phy_ddio_dq;
phy_ddio_wrdata_en_int <= phy_ddio_wrdata_en;
phy_ddio_wrdata_mask_int <= phy_ddio_wrdata_mask;
phy_ddio_dqs_en_int <= phy_ddio_dqs_en;
phy_ddio_oct_ena_int <= phy_ddio_oct_ena;
end
end
endgenerate
DE4_SOPC_ddr2_0_p0_addr_cmd_pads uaddr_cmd_pads(
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.phy_ddio_addr_cmd_clk (phy_ddio_addr_cmd_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.enable_mem_clk (enable_mem_clk),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DDIO_PHY_DQ_WIDTH = DDIO_PHY_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_l;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_h;
assign phy_ddio_oe_l = phy_ddio_wrdata_en_int[HALF_AFI_DQS_WIDTH-1:0];
assign phy_ddio_oe_h = phy_ddio_wrdata_en_int[AFI_DQS_WIDTH-1:HALF_AFI_DQS_WIDTH];
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
wire dqs_busout;
// The phy_ddio_dq_int bus is the write data for all DQS groups in one
// AFI cycle. The bus is ordered by time slow and subordered by
// DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// The following extracts write data targeting the current DQS
// group.
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS_WITH_DM)];
DE4_SOPC_ddr2_0_p0_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (pll_mem_clk),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (hr_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.strobe_ena_clock_in (pll_dqs_ena_clk),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dq [(DQDQS_DDIO_PHY_DQ_WIDTH*(i+1)-1) : DQDQS_DDIO_PHY_DQ_WIDTH*i]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
.write_data_in ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
.write_oe_in ({ {DQDQS_DATA_WIDTH{phy_ddio_oe_h[i]}}, {DQDQS_DATA_WIDTH{phy_ddio_oe_l[i]}} }),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena ({phy_ddio_dqs_en_int[i+NUM_OF_DQDQS], phy_ddio_dqs_en_int[i]}),
.oct_ena_in ({phy_ddio_oct_ena_int[i+NUM_OF_DQDQS], phy_ddio_oct_ena_int[i]}),
.capture_strobe_ena (dqs_enable_ctrl[i]),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.dll_delayctrl_in (dll_phy_delayctrl)
);
defparam ubidir_dq_dqs.ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = FAST_SIM_MODEL;
assign read_capture_clk[i] = ~dqs_busout;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: read_datapath.v
// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
// altera message_off 10036
module DE4_SOPC_ddr2_0_p0_read_datapath(
reset_n_afi_clk,
seq_read_fifo_reset,
reset_n_resync_clk,
pll_dqs_ena_clk,
read_capture_clk,
ddio_phy_dq,
pll_afi_clk,
seq_read_latency_counter,
seq_read_increment_vfifo_fr,
seq_read_increment_vfifo_hr,
seq_read_increment_vfifo_qr,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
phy_mux_read_fifo_q,
force_oct_off,
dqs_enable_ctrl,
afi_rdata_valid,
seq_calib_init,
dqs_edge_detect
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
// PHY-Memory Interface
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
// Read Datapath
parameter MAX_LATENCY_COUNT_WIDTH = "";
parameter MAX_READ_LATENCY = "";
parameter READ_FIFO_READ_MEM_DEPTH = "";
parameter READ_FIFO_READ_ADDR_WIDTH = "";
parameter READ_FIFO_WRITE_MEM_DEPTH = "";
parameter READ_FIFO_WRITE_ADDR_WIDTH = "";
parameter READ_VALID_FIFO_SIZE = "";
parameter READ_VALID_FIFO_READ_MEM_DEPTH = "";
parameter READ_VALID_FIFO_READ_ADDR_WIDTH = "";
parameter READ_VALID_FIFO_WRITE_MEM_DEPTH = "";
parameter READ_VALID_FIFO_WRITE_ADDR_WIDTH = "";
parameter READ_VALID_FIFO_PER_DQS_WIDTH = "";
parameter NUM_SUBGROUP_PER_READ_DQS = "";
parameter MEM_T_RL = "";
parameter QVLD_EXTRA_FLOP_STAGES = "";
parameter QVLD_WR_ADDRESS_OFFSET = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter FAST_SIM_MODEL = "";
// Local parameters
localparam RATE_MULT = 2;
localparam MAKE_FIFOS_IN_ALTDQDQS = "false";
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam DDIO_PHY_DQ_WIDTH = DOUBLE_MEM_DQ_WIDTH;
localparam DQ_GROUP_WIDTH = MEM_DQ_WIDTH / MEM_READ_DQS_WIDTH;
localparam USE_NUM_SUBGROUP_PER_READ_DQS = FAST_SIM_MODEL ? 1 : NUM_SUBGROUP_PER_READ_DQS;
localparam AFI_DQ_GROUP_DATA_WIDTH = AFI_DATA_WIDTH / MEM_READ_DQS_WIDTH;
localparam DDIO_DQ_GROUP_DATA_WIDTH = DDIO_PHY_DQ_WIDTH / MEM_READ_DQS_WIDTH;
localparam DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP = DDIO_PHY_DQ_WIDTH / (MEM_READ_DQS_WIDTH * USE_NUM_SUBGROUP_PER_READ_DQS);
localparam VFIFO_RATE_MULT = 1;
localparam READ_FIFO_DQ_GROUP_OUTPUT_WIDTH = 4 * DQ_GROUP_WIDTH;
localparam OCT_ON_DELAY = (MEM_T_RL > 4) ? ((MEM_T_RL - 4) / 2) : 0;
localparam OCT_OFF_DELAY = (MEM_T_RL + 6) / 2;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input reset_n_afi_clk;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_fifo_reset; // reset from sequencer to read and write pointers of the data resynchronization FIFO
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input reset_n_resync_clk;
input pll_dqs_ena_clk;
input [DDIO_PHY_DQ_WIDTH-1:0] ddio_phy_dq;
input pll_afi_clk;
input [MAX_LATENCY_COUNT_WIDTH-1:0] seq_read_latency_counter;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr; // increment valid prediction FIFO write pointer by an extra full rate cycle
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr; // increment valid prediction FIFO write pointer by an extra half rate cycle
// in full rate core, both will mean an extra full rate cycle
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_qr; // increment valid prediction FIFO write pointer by an extra quarter rate cycle.
// not used in full/half rate core
input afi_rdata_en;
input afi_rdata_en_full;
output [AFI_DATA_WIDTH-1:0] afi_rdata;
output afi_rdata_valid;
// read data (no reordering) for indepedently FIFO calibrations (multiple FIFOs for multiple DQS groups)
output [AFI_DATA_WIDTH-1:0] phy_mux_read_fifo_q;
output [AFI_DQS_WIDTH-1:0] force_oct_off;
output [MEM_READ_DQS_WIDTH*READ_VALID_FIFO_PER_DQS_WIDTH-1:0] dqs_enable_ctrl;
output [MEM_READ_DQS_WIDTH-1:0] dqs_edge_detect;
input [CALIB_REG_WIDTH-1:0] seq_calib_init;
// Mark the following register as a keeper because the pin_map.tcl
// script uses it as anchor for finding the AFI clock
reg afi_rdata_valid /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
reg [1:0] qvld_num_fr_cycle_shift [MEM_READ_DQS_WIDTH-1:0];
wire [MEM_READ_DQS_WIDTH*READ_VALID_FIFO_PER_DQS_WIDTH-1:0] qvld;
wire [MEM_READ_DQS_WIDTH-1:0] read_valid;
wire [MEM_READ_DQS_WIDTH-1:0] valid_predict_clk;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_valid_predict_clk;
reg [MEM_READ_DQS_WIDTH-1:0] reset_n_fifo_write_side;
reg [MEM_READ_DQS_WIDTH-1:0] reset_n_fifo_wraddress;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk_pos;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk_neg;
reg [MEM_READ_DQS_WIDTH-1:0] read_capture_clk_div2;
wire [AFI_DATA_WIDTH-1:0] read_fifo_output;
wire read_fifo_read_clk = pll_afi_clk;
wire reset_n_read_fifo_read_clk = reset_n_afi_clk;
wire seq_calib_skip_vfifo;
assign seq_calib_skip_vfifo = seq_calib_init[3];
// *******************************************************************************************************************
// VALID PREDICTION
// Read request (afi_rdata_en) is generated on the AFI clock domain (pll_afi_clk).
// Read data is captured on the read_capture_clk domain (output clock from I/O).
// The purpose of valid prediction is to determine which read_capture_clk cycle valid data will be returned to the core
// after the request is issued on pll_afi_clk; this is essentially the latency between read request seen on
// AFI interface and valid data available at the output of ALTDQ_DQS.
// The clock domain crossing between pll_afi_clk and read_capture_clk is handled by a FIFO (uread_valid_fifo).
// The pll_afi_clk controls the write side of the FIFO and the read_capture_clk controls the read side.
// The pll_afi_clk writes into the FIFO on every clock cycle. When there is no read request, it writes a 0;
// when there is a read request, it writes a 1 (refer to as a token) into the FIFO.
// The read_capture_clk reads from the FIFO every clock cycle, whenever it reads a token, it means that valid data
// is available during that cycle. Each token represents 1 cycle of valid data.
// In full rate, BL=2, 1 read results in 1 AFI cycle of valid data, controller asserts afi_rdata_en for 1 cycle
// In full rate, BL=4, 1 read results in 2 AFI cycles of valid data, controller asserts afi_rdata_en for 2 cycles
// In full rate, BL=8, 1 read results in 4 AFI cycles of valid data, controller asserts afi_rdata_en for 4 cycles
// In half rate, BL=2, not supported
// In half rate, BL=4, 1 read results in 1 AFI cycle of valid data, controller asserts afi_rdata_en for 1 cycle
// In half rate, BL=8, 1 read results in 2 AFI cycle of valid data, controller asserts afi_rdata_en for 2 cycles
// In full rate, 1 afi_rdata_en cycle = 1 token
// In half rate, 1 afi_rdata_en cycle = 2 tokens
//
// After reset is released, the relationship between the read and write pointers can be arbitrary.
// During calibration, the sequencer keeps incrementing the write pointer (both the sequencer and write pointer operates
// on pll_afi_clk) until the correct latency has been tuned.
// *******************************************************************************************************************
assign valid_predict_clk = {MEM_READ_DQS_WIDTH{pll_dqs_ena_clk}};
assign reset_n_valid_predict_clk = {MEM_READ_DQS_WIDTH{reset_n_resync_clk}};
generate
if (MAKE_FIFOS_IN_ALTDQDQS != "true")
begin
genvar dqsgroup, vfifo_i;
for (dqsgroup=0; dqsgroup<MEM_READ_DQS_WIDTH; dqsgroup=dqsgroup+1)
begin: read_valid_predict
wire [VFIFO_RATE_MULT-1:0] vfifo_out_per_dqs;
reg [READ_VALID_FIFO_WRITE_ADDR_WIDTH-1:0] qvld_wr_address;
reg [READ_VALID_FIFO_READ_ADDR_WIDTH-1:0] qvld_rd_address;
`ifndef SYNTH_FOR_SIM
// synthesis translate_off
`endif
wire [ceil_log2(READ_VALID_FIFO_SIZE)-1:0] qvld_wr_address_offset;
assign qvld_wr_address_offset = qvld_rd_address + QVLD_WR_ADDRESS_OFFSET;
`ifndef SYNTH_FOR_SIM
// synthesis translate_on
`endif
wire qvld_increment_wr_address = seq_read_increment_vfifo_hr[dqsgroup];
// In half rate, 1 afi_rdata_en_full cycle = 2 tokens, qvld_in[0] and qvld_in[1]
// In 1/4 rate, 1 afi_rdata_en_full cycle = 4 tokens, qvld_in[0..3]
// etc.
// Tokens are written at AFI clock rate but read at full rate.
// During calibration the latency needs to be tuned at full rate granularity.
// For example, in half rate, in the base case, 1 afi_rdata_en_full will result
// in two tokens in write address 0, that means read address 0 and read address 1
// will both have tokens. If the sequencer request to increase the latency by
// full rate cycle, the write side first writes 10 into write address 0, then
// it writes 01 into write address 1; this means there are tokens in read
// address 1 and read address 2.
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
`ifndef SYNTH_FOR_SIM
// synthesis translate_off
`endif
qvld_num_fr_cycle_shift[dqsgroup] <= {1'b0, ((seq_calib_skip_vfifo) ? qvld_wr_address_offset[0] : 1'b0)};
`ifndef SYNTH_FOR_SIM
// synthesis translate_on
// synthesis read_comments_as_HDL on
// qvld_num_fr_cycle_shift[dqsgroup] <= 2'b00;
// synthesis read_comments_as_HDL off
`endif
end else begin
if (seq_read_increment_vfifo_fr[dqsgroup]) begin
qvld_num_fr_cycle_shift[dqsgroup] <= 2'b01;
end else if (seq_read_increment_vfifo_hr[dqsgroup]) begin
qvld_num_fr_cycle_shift[dqsgroup] <= 2'b00;
end
end
end
wire [RATE_MULT-1:0] qvld_in;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uread_fr_cycle_shifter(
.clk (pll_afi_clk),
.reset_n (reset_n_afi_clk),
.shift_by (qvld_num_fr_cycle_shift[dqsgroup]),
.datain ({RATE_MULT{afi_rdata_en_full}}),
.dataout (qvld_in));
defparam uread_fr_cycle_shifter.DATA_WIDTH = 1;
wire vfifo_read_clk = valid_predict_clk[dqsgroup];
wire vfifo_read_clk_reset_n = reset_n_valid_predict_clk[dqsgroup];
always @(posedge pll_afi_clk)
begin
`ifndef SYNTH_FOR_SIM
// synthesis translate_off
`endif
if (~reset_n_afi_clk) begin
qvld_wr_address <= (seq_calib_skip_vfifo) ? (qvld_wr_address_offset >> ceil_log2(RATE_MULT)) : {READ_VALID_FIFO_WRITE_ADDR_WIDTH{1'b0}};
`ifndef SYNTH_FOR_SIM
// synthesis translate_on
// synthesis read_comments_as_HDL on
// if (~reset_n_afi_clk) begin
// qvld_wr_address <= {READ_VALID_FIFO_WRITE_ADDR_WIDTH{1'b0}};
// synthesis read_comments_as_HDL off
`endif
end else begin
qvld_wr_address <= qvld_increment_wr_address ? (qvld_wr_address + 2'd2) : (qvld_wr_address + 2'd1);
end
end
always @(posedge vfifo_read_clk or negedge vfifo_read_clk_reset_n)
begin
if (~vfifo_read_clk_reset_n)
qvld_rd_address <= {READ_VALID_FIFO_READ_ADDR_WIDTH{1'b0}};
else
qvld_rd_address <= qvld_rd_address + 1'b1;
end
wire [VFIFO_RATE_MULT-1:0] vfifo_out_per_dqs_tmp;
DE4_SOPC_ddr2_0_p0_flop_mem uread_valid_fifo(
.wr_clk (pll_afi_clk),
.wr_en (1'b1),
.wr_addr (qvld_wr_address),
.wr_data (qvld_in),
.rd_reset_n (vfifo_read_clk_reset_n),
.rd_clk (vfifo_read_clk),
.rd_en (1'b1),
.rd_addr (qvld_rd_address),
.rd_data (vfifo_out_per_dqs_tmp)
);
defparam uread_valid_fifo.WRITE_MEM_DEPTH = READ_VALID_FIFO_WRITE_MEM_DEPTH;
defparam uread_valid_fifo.WRITE_ADDR_WIDTH = READ_VALID_FIFO_WRITE_ADDR_WIDTH;
defparam uread_valid_fifo.WRITE_DATA_WIDTH = RATE_MULT;
defparam uread_valid_fifo.READ_MEM_DEPTH = READ_VALID_FIFO_READ_MEM_DEPTH;
defparam uread_valid_fifo.READ_ADDR_WIDTH = READ_VALID_FIFO_READ_ADDR_WIDTH;
defparam uread_valid_fifo.READ_DATA_WIDTH = VFIFO_RATE_MULT;
// These extra flop stages are added to the output of the VFIFO
// These adds delay without expanding the VFIFO size
// Expanding the VFIFO size (also means bigger address counters) to 32 causes timing failures
for (vfifo_i=0; vfifo_i<VFIFO_RATE_MULT; vfifo_i=vfifo_i+1)
begin: qvld_extra_flop
reg [QVLD_EXTRA_FLOP_STAGES-1:0] vfifo_out_per_dqs_r;
always @(posedge vfifo_read_clk)
begin
vfifo_out_per_dqs_r <= {vfifo_out_per_dqs_r[QVLD_EXTRA_FLOP_STAGES-2:0], vfifo_out_per_dqs_tmp[vfifo_i]};
end
assign vfifo_out_per_dqs[vfifo_i] = vfifo_out_per_dqs_r[QVLD_EXTRA_FLOP_STAGES-1];
end
wire [READ_VALID_FIFO_PER_DQS_WIDTH-1:0] qvld_per_dqs = vfifo_out_per_dqs;
// Map per-dqs vfifo output bus to the per-interface vfifo output bus.
for (vfifo_i=0; vfifo_i<READ_VALID_FIFO_PER_DQS_WIDTH; vfifo_i=vfifo_i+1)
begin: map_qvld_per_dqs_to_qvld
assign qvld[dqsgroup+(vfifo_i*MEM_READ_DQS_WIDTH)] = qvld_per_dqs[vfifo_i];
end
end
end
endgenerate
assign dqs_enable_ctrl = qvld;
reg [MAX_READ_LATENCY-1:0] latency_shifter;
reg [MAX_READ_LATENCY-1:0] full_latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
full_latency_shifter <= {MAX_READ_LATENCY{1'b0}};
latency_shifter <= {MAX_READ_LATENCY{1'b0}};
end
else begin
full_latency_shifter <= {full_latency_shifter[MAX_READ_LATENCY-2:0], afi_rdata_en_full};
latency_shifter <= {latency_shifter[MAX_READ_LATENCY-2:0], afi_rdata_en};
end
end
generate
if (MAKE_FIFOS_IN_ALTDQDQS != "true")
begin
genvar dqs_count, subgroup, dq_count, timeslot;
for (dqs_count=0; dqs_count<MEM_READ_DQS_WIDTH; dqs_count=dqs_count+1)
begin: read_buffering
wire [USE_NUM_SUBGROUP_PER_READ_DQS-1:0] wren;
wire [USE_NUM_SUBGROUP_PER_READ_DQS-1:0] wren_neg;
wire read_enable;
wire [READ_FIFO_DQ_GROUP_OUTPUT_WIDTH-1:0] read_fifo_output_per_dqs;
// Perform read data mapping from ddio_phy_dq to ddio_phy_dq_per_dqs.
//
// The ddio_phy_dq bus is the read data coming out of the DDIO, and so
// is 2x the interface data width. The bus is ordered by DQS group
// and sub-ordered by time slot:
//
// D1_T1, D1_T0, D0_T1, D0_T0
//
// The ddio_phy_dq_per_dqs bus is a subset of the ddio_phy_dq bus that
// is specific to the current DQS group. Like ddio_phy_dq, it's ordered
// by time slot:
//
// D0_T1, D0_T0
wire [DDIO_DQ_GROUP_DATA_WIDTH-1:0] ddio_phy_dq_per_dqs;
assign ddio_phy_dq_per_dqs = ddio_phy_dq[(DDIO_DQ_GROUP_DATA_WIDTH*(dqs_count+1)-1) : (DDIO_DQ_GROUP_DATA_WIDTH*dqs_count)];
DE4_SOPC_ddr2_0_p0_read_valid_selector uread_valid_selector(
.reset_n (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.latency_shifter (latency_shifter),
.latency_counter (seq_read_latency_counter),
.read_enable (),
.read_valid (read_valid[dqs_count])
);
defparam uread_valid_selector.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
DE4_SOPC_ddr2_0_p0_read_valid_selector uread_valid_full_selector(
.reset_n (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.latency_shifter (full_latency_shifter),
.latency_counter (seq_read_latency_counter),
.read_enable (read_enable),
.read_valid ()
);
defparam uread_valid_full_selector.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
reset_n_fifo_write_side[dqs_count] <= 1'b0;
reset_n_fifo_wraddress[dqs_count] <= 1'b0;
end
else begin
reset_n_fifo_write_side[dqs_count] <= ~seq_read_fifo_reset[dqs_count];
reset_n_fifo_wraddress[dqs_count] <= ~seq_read_fifo_reset[dqs_count];
end
end
wire [READ_FIFO_DQ_GROUP_OUTPUT_WIDTH-1:0] read_fifo_output_per_dqs_tmp;
always @(posedge read_capture_clk[dqs_count] or negedge reset_n_fifo_write_side[dqs_count])
begin
if (~reset_n_fifo_write_side[dqs_count])
read_capture_clk_div2[dqs_count] <= 1'b0;
else
read_capture_clk_div2[dqs_count] <= ~read_capture_clk_div2[dqs_count];
end
`ifndef SIMGEN
assign #10 read_capture_clk_pos[dqs_count] = read_capture_clk_div2[dqs_count];
`else
DE4_SOPC_ddr2_0_p0_sim_delay #(
.delay(10)
)
sim_delay_inst(
.o(read_capture_clk_pos[dqs_count]),
.i(read_capture_clk_div2[dqs_count]),
);
`endif
assign read_capture_clk_neg[dqs_count] = ~read_capture_clk_pos[dqs_count];
for (subgroup=0; subgroup<USE_NUM_SUBGROUP_PER_READ_DQS; subgroup=subgroup+1)
begin: read_subgroup
assign wren[subgroup] = 1'b1;
assign wren_neg[subgroup] = 1'b1;
reg [READ_FIFO_WRITE_ADDR_WIDTH-1:0] wraddress /* synthesis dont_merge */;
reg [READ_FIFO_WRITE_ADDR_WIDTH-1:0] wraddress_neg /* synthesis dont_merge */;
// The clock is read_capture_clk while reset_n_fifo_wraddress is a signal synchronous to
// the AFI clk domain but asynchronous to read_capture_clk. reset_n_fifo_wraddress goes
// '0' when either the system is reset, or when the sequencer asserts seq_read_fifo_reset.
// By design we ensure that wren has been '0' for at least one cycle when reset_n_fifo_wraddress
// is deasserted (i.e. '0' -> '1'). When wren is '0', the input and output of the
// wraddress registers are both '0', so there's no risk of metastability due to reset
// recovery.
always @(posedge read_capture_clk_pos[dqs_count] or negedge reset_n_fifo_wraddress[dqs_count])
begin
if (~reset_n_fifo_wraddress[dqs_count])
wraddress <= {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}};
else if (wren[subgroup])
begin
if (READ_FIFO_WRITE_MEM_DEPTH == 2 ** READ_FIFO_WRITE_ADDR_WIDTH)
wraddress <= wraddress + 1'b1;
else
wraddress <= (wraddress == READ_FIFO_WRITE_MEM_DEPTH - 1) ? {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}} : wraddress + 1'b1;
end
end
always @(posedge read_capture_clk_neg[dqs_count] or negedge reset_n_fifo_wraddress[dqs_count])
begin
if (~reset_n_fifo_wraddress[dqs_count])
wraddress_neg <= {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}};
else if (wren_neg[subgroup])
begin
if (READ_FIFO_WRITE_MEM_DEPTH == 2 ** READ_FIFO_WRITE_ADDR_WIDTH)
wraddress_neg <= wraddress_neg + 1'b1;
else
wraddress_neg <= (wraddress_neg == READ_FIFO_WRITE_MEM_DEPTH - 1) ? {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}} : wraddress_neg + 1'b1;
end
end
reg [READ_FIFO_READ_ADDR_WIDTH-1:0] rdaddress /* synthesis dont_merge */;
always @(posedge read_fifo_read_clk)
begin
if (seq_read_fifo_reset[dqs_count])
rdaddress <= {READ_FIFO_READ_ADDR_WIDTH{1'b0}};
else if (read_enable)
begin
if (READ_FIFO_READ_MEM_DEPTH == 2 ** READ_FIFO_READ_ADDR_WIDTH)
rdaddress <= rdaddress + 1'b1;
else
rdaddress <= (rdaddress == READ_FIFO_READ_MEM_DEPTH - 1) ? {READ_FIFO_READ_ADDR_WIDTH{1'b0}} : rdaddress + 1'b1;
end
end
DE4_SOPC_ddr2_0_p0_flop_mem uread_fifo(
.wr_clk (read_capture_clk_pos[dqs_count]),
.wr_en (wren[subgroup]),
.wr_addr (wraddress),
.wr_data (ddio_phy_dq_per_dqs[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup)]),
.rd_reset_n (reset_n_read_fifo_read_clk),
.rd_clk (read_fifo_read_clk),
.rd_en (read_enable),
.rd_addr (rdaddress),
.rd_data (read_fifo_output_per_dqs_tmp[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup)])
);
defparam uread_fifo.WRITE_MEM_DEPTH = READ_FIFO_WRITE_MEM_DEPTH;
defparam uread_fifo.WRITE_ADDR_WIDTH = READ_FIFO_WRITE_ADDR_WIDTH;
defparam uread_fifo.WRITE_DATA_WIDTH = DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP;
defparam uread_fifo.READ_MEM_DEPTH = READ_FIFO_READ_MEM_DEPTH;
defparam uread_fifo.READ_ADDR_WIDTH = READ_FIFO_READ_ADDR_WIDTH;
defparam uread_fifo.READ_DATA_WIDTH = READ_FIFO_DQ_GROUP_OUTPUT_WIDTH / (USE_NUM_SUBGROUP_PER_READ_DQS * 2);
DE4_SOPC_ddr2_0_p0_flop_mem uread_fifo_neg(
.wr_clk (read_capture_clk_neg[dqs_count]),
.wr_en (wren_neg[subgroup]),
.wr_addr (wraddress_neg),
.wr_data (ddio_phy_dq_per_dqs[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup)]),
.rd_reset_n (reset_n_read_fifo_read_clk),
.rd_clk (read_fifo_read_clk),
.rd_en (read_enable),
.rd_addr (rdaddress),
.rd_data (read_fifo_output_per_dqs_tmp[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1+DDIO_DQ_GROUP_DATA_WIDTH) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup+DDIO_DQ_GROUP_DATA_WIDTH)])
);
defparam uread_fifo_neg.WRITE_MEM_DEPTH = READ_FIFO_WRITE_MEM_DEPTH;
defparam uread_fifo_neg.WRITE_ADDR_WIDTH = READ_FIFO_WRITE_ADDR_WIDTH;
defparam uread_fifo_neg.WRITE_DATA_WIDTH = DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP;
defparam uread_fifo_neg.READ_MEM_DEPTH = READ_FIFO_READ_MEM_DEPTH;
defparam uread_fifo_neg.READ_ADDR_WIDTH = READ_FIFO_READ_ADDR_WIDTH;
defparam uread_fifo_neg.READ_DATA_WIDTH = READ_FIFO_DQ_GROUP_OUTPUT_WIDTH / (USE_NUM_SUBGROUP_PER_READ_DQS * 2);
end
assign read_fifo_output_per_dqs = read_fifo_output_per_dqs_tmp;
// Perform mapping from read_fifo_output_per_dqs to read_fifo_output
//
// The read_fifo_output_per_dqs bus is the read data coming out of the read FIFO.
// It has the read data for the current dqs group. In FR, it has 2x the
// width of a dqs group on the interface. In HR, it has 4x the width of
// a dqs group on the interface. The bus is ordered by time slot:
//
// FR: D0_T1, D0_T0
// HR: D0_T3, D0_T2, D0_T1, D0_T0
//
// The read_fifo_output bus is the read data from read fifo. In FR, it has
// the same width as ddio_phy_dq (i.e. 2x interface width). In HR, it has
// 4x the interface width. The bus is ordered by time slot and
// sub-ordered by DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
for (timeslot=0; timeslot<4; timeslot=timeslot+1)
begin: read_mapping_timeslot
wire [DQ_GROUP_WIDTH-1:0] rdata = read_fifo_output_per_dqs[DQ_GROUP_WIDTH * (timeslot + 1) - 1 : DQ_GROUP_WIDTH * timeslot];
assign read_fifo_output[DQ_GROUP_WIDTH * (dqs_count + 1) + MEM_DQ_WIDTH * timeslot - 1 : DQ_GROUP_WIDTH * dqs_count + MEM_DQ_WIDTH * timeslot] = rdata;
end
end
end else begin
// Read FIFOS are instantiated in ALTDQDQS. Just pass through to afi_rdata.
genvar dqs_count, timeslot;
for (dqs_count=0; dqs_count<MEM_READ_DQS_WIDTH; dqs_count=dqs_count+1)
begin: read_mapping_dqsgroup
wire [DDIO_DQ_GROUP_DATA_WIDTH-1:0] ddio_phy_dq_per_dqs;
assign ddio_phy_dq_per_dqs = ddio_phy_dq[(DDIO_DQ_GROUP_DATA_WIDTH*(dqs_count+1)-1) : (DDIO_DQ_GROUP_DATA_WIDTH*dqs_count)];
for (timeslot=0; timeslot<4; timeslot=timeslot+1)
begin: read_mapping_timeslot
wire [DQ_GROUP_WIDTH-1:0] rdata = ddio_phy_dq_per_dqs[DQ_GROUP_WIDTH * (timeslot + 1) - 1 : DQ_GROUP_WIDTH * timeslot];
assign read_fifo_output[MEM_DQ_WIDTH * timeslot + DQ_GROUP_WIDTH * (dqs_count + 1) - 1 : MEM_DQ_WIDTH * timeslot + DQ_GROUP_WIDTH * dqs_count] = rdata;
end
end
for (dqs_count=0; dqs_count<MEM_READ_DQS_WIDTH; dqs_count=dqs_count+1)
begin: read_buffering
DE4_SOPC_ddr2_0_p0_read_valid_selector uread_valid_selector(
.reset_n (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.latency_shifter (latency_shifter),
.latency_counter ({1'b0, seq_read_latency_counter[MAX_LATENCY_COUNT_WIDTH-1:1]}),
.read_enable (),
.read_valid (read_valid[dqs_count])
);
defparam uread_valid_selector.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
end
end
endgenerate
// Data from read-fifo is synchronous to the AFI clock and so can be sent
// directly to the afi_rdata bus.
assign afi_rdata = read_fifo_output;
// Perform data re-mapping from afi_rdata to phy_mux_read_fifo_q
//
// The afi_rdata bus is the read data going out to the AFI. In FR, it has
// the same width as ddio_phy_dq (i.e. 2x interface width). In HR, it has
// 4x the interface width. The bus is ordered by time slot and
// sub-ordered by DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// The phy_mux_read_fifo_q bus is the read data going into the sequencer
// for calibration. It has the same width as afi_rdata. The bus is ordered
// by DQS group, and sub-ordered by time slot:
//
// FR: D1_T1, D1_T0, D0_T1, D0_T0
// HR: D1_T3, D1_T2, D1_T1, D1_T0, D0_T3, D0_T2, D0_T1, D0_T0
//
//As of Nov 1 2010, the NIOS sequencer doesn't use the phy_mux_read_fifo_q signal.
generate
genvar k, t;
for (k=0; k<MEM_READ_DQS_WIDTH; k=k+1)
begin: read_mapping_for_seq
wire [AFI_DQ_GROUP_DATA_WIDTH-1:0] rdata_per_dqs_group;
for (t=0; t<RATE_MULT*2; t=t+1)
begin: build_rdata_per_dqs_group
wire [DQ_GROUP_WIDTH-1:0] rdata_t = afi_rdata[DQ_GROUP_WIDTH * (k+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * k + MEM_DQ_WIDTH * t];
assign rdata_per_dqs_group[(t+1)*DQ_GROUP_WIDTH-1:t*DQ_GROUP_WIDTH] = rdata_t;
end
assign phy_mux_read_fifo_q[(k+1)*AFI_DQ_GROUP_DATA_WIDTH-1 : k*AFI_DQ_GROUP_DATA_WIDTH] = rdata_per_dqs_group;
end
endgenerate
// Generate an AFI read valid signal from all the read valid signals from all FIFOs
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
afi_rdata_valid <= 1'b0;
end else begin
afi_rdata_valid <= &read_valid;
end
end
reg [AFI_DQS_WIDTH-1:0] force_oct_off;
generate
genvar oct_num;
for (oct_num = 0; oct_num < AFI_DQS_WIDTH; oct_num = oct_num + 1)
begin : oct_gen
reg [OCT_OFF_DELAY-1:0] rdata_en_r /* synthesis dont_merge */;
wire [OCT_OFF_DELAY:0] rdata_en_shifter;
assign rdata_en_shifter = {rdata_en_r,afi_rdata_en_full};
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk)
begin
rdata_en_r <= {OCT_OFF_DELAY{1'b0}};
force_oct_off[oct_num] <= 1'b0;
end
else
begin
rdata_en_r <= {rdata_en_r[OCT_OFF_DELAY-2:0],afi_rdata_en_full};
force_oct_off[oct_num] <= ~(|rdata_en_shifter[OCT_OFF_DELAY:OCT_ON_DELAY]);
end
end
end
endgenerate
// Track if any DQS edges were captured as method of determining if the interface is
// alive during debug.
wire [MEM_READ_DQS_WIDTH-1:0] dqs_detect_reset_n;
reg [MEM_READ_DQS_WIDTH-1:0] dqs_edge_detect_reg;
generate
genvar dqs_detect_count;
for (dqs_detect_count=0; dqs_detect_count<MEM_READ_DQS_WIDTH; dqs_detect_count=dqs_detect_count+1)
begin: dqs_detection
always @(posedge read_capture_clk_pos[dqs_detect_count] or negedge reset_n_fifo_write_side[dqs_detect_count])
if (~reset_n_fifo_write_side[dqs_detect_count])
dqs_edge_detect_reg[dqs_detect_count] <= 0;
else
dqs_edge_detect_reg[dqs_detect_count] <= 1;
end
endgenerate
assign dqs_edge_detect = dqs_edge_detect_reg;
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module DE4_SOPC_ddr2_0_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
reset_request_n,
ctl_reset_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
input csr_soft_reset_req;
output reset_request_n;
output ctl_reset_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign reset_request_n = pll_locked;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n & (!csr_soft_reset_req);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 5;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
DE4_SOPC_ddr2_0_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (ctl_reset_n)
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 5;
DE4_SOPC_ddr2_0_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
DE4_SOPC_ddr2_0_p0_reset_sync ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************
// File name: simple_ddio_out.v
//
// This module can be used to double the data rate of the datain
// bus. Outputs at the dataout. Conversion is either done in soft
// logic or using hard ddio blocks in I/O periphery.
//
// Example 1:
//
// datain = {T1, T0} at clk cycle x, where each Ty is a data item
// with width DATA_WIDTH
//
// dataout = {T0} at positive phase of clk cycle x
// dataout = {T1} at negative phase of clk cycle x
//
// In this case, set OUTPUT_FULL_DATA_WIDTH == DATA_WIDTH.
//
//
// Example 2:
//
// datain = {T3, T2, T1, T0} at clk cycle x, where each Ty is a data
// item with width DATA_WIDTH
//
// dataout = {T1, T0} at positive phase of clk cycle x
// dataout = {T3, T2} at negative phase of clk cycle x
//
// dataout can then be fed into another ddio_out stage for further
// rate doubling, as in example 1.
//
// Note that in this case, OUTPUT_FULL_DATA_WIDTH == 2 * DATA_WIDTH
//
//
// Parameter Descriptions:
// =======================
//
// DATA_WIDTH - see examples above
//
// OUTPUT_FULL_DATA_WIDTH - see examples above
//
// USE_CORE_LOGIC - specifies whether to use core logic, or to
// ("true"|"false") use hard ddio_out blocks in the I/O periphery.
//
// HALF_RATE_MODE - specifies whether the hard ddio_out is in
// ("true"|"false") "half-rate" mode or not. Only applicable
// when USE_CORE_LOGIC is "false".
//
// REG_POST_RESET_HIGH - specifies whether the ddio registers
// ("true"|"false") should come out as logic-1 or logic-0
// after reset.
//
// REGISTER_OUTPUT - Specifies whether the output is registered.
// ("true"|"false") If "true", an extra FF (clocked by dr_clk
// and reset by dr_reset_n) is synthesized at
// the output. Only applicable when
// USE_CORE_LOGIC is "true".
//
// USE_EXTRA_OUTPUT_REG - Specifies whether the soft logic structure
// generated resembles the Stratix IV 3 register
// structure. Only applicable when
// USE_CORE_LOGIC is "true".
//
// *****************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_simple_ddio_out(
clk,
reset_n,
dr_clk,
dr_reset_n,
datain,
dataout
);
// *****************************************************************
// BEGIN PARAMETER SECTION
parameter DATA_WIDTH = "";
parameter OUTPUT_FULL_DATA_WIDTH = "";
parameter USE_CORE_LOGIC = "";
parameter REG_POST_RESET_HIGH = "false";
parameter HALF_RATE_MODE = ""; //only applicable when USE_CORE_LOGIC is "false"
parameter REGISTER_OUTPUT = "false"; //only applicable when USE_CORE_LOGIC is "true"
parameter USE_EXTRA_OUTPUT_REG = "false"; //only applicable when USE_CORE_LOGIC is "true"
localparam OUTPUT_WIDTH_MULT = OUTPUT_FULL_DATA_WIDTH / DATA_WIDTH;
localparam INPUT_WIDTH_MULT = OUTPUT_WIDTH_MULT * 2;
localparam INPUT_FULL_DATA_WIDTH = DATA_WIDTH * INPUT_WIDTH_MULT;
localparam HARD_DDIO_ASYNC_MODE = (REG_POST_RESET_HIGH == "true") ? "preset" : "clear";
localparam HARD_DDIO_POWER_UP = (REG_POST_RESET_HIGH == "true") ? "high" : "low";
// END PARAMETER SECTION
// *****************************************************************
input clk;
input reset_n;
input [INPUT_FULL_DATA_WIDTH-1:0] datain;
output [OUTPUT_FULL_DATA_WIDTH-1:0] dataout;
input dr_clk; //only used when USE_CORE_LOGIC and REGISTER_OUTPUT are "true"
input dr_reset_n; //only used when USE_CORE_LOGIC and REGISTER_OUTPUT are "true"
generate
genvar i, j, k;
if (USE_CORE_LOGIC == "true") begin
//Use core logic to implement ddio_out.
//This is always the 2-flop implementation regardless of HALF_RATE_MODE setting
reg [INPUT_FULL_DATA_WIDTH-1:0] datain_r;
reg [INPUT_FULL_DATA_WIDTH-1:0] datain_rr;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {INPUT_FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {INPUT_FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
if (USE_EXTRA_OUTPUT_REG == "true") begin
always @(negedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true") begin
datain_rr <= {INPUT_FULL_DATA_WIDTH{1'b1}};
end
else begin
datain_rr <= {INPUT_FULL_DATA_WIDTH{1'b0}};
end
end else begin
datain_rr <= datain_r;
end
end
end
wire [OUTPUT_FULL_DATA_WIDTH-1:0] dataout_wire;
for (i=0; i<OUTPUT_WIDTH_MULT; i=i+1)
begin: ddio_group
for (j=0; j<DATA_WIDTH; j=j+1)
begin: sig
if (USE_EXTRA_OUTPUT_REG == "true") begin
//wire delay is to avoid glitch during sim which makes things harder to see.
//in reality glitches are unimportant as long as paths between output
//and next flop meet timing.
wire t0 = datain_r[i*DATA_WIDTH+j];
wire #1 t1 = datain_rr[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
wire #1 muxsel = clk;
//There's a timing path from from muxsel to the target FF fed by dataout.
//If the clock signal driving muxsel is a global signal (which is likely),
//the router won't try to insert delay to fix hold. We therefore insert
//lcell buffers to help hold timing.
wire muxsel_buff_out /* synthesis syn_noprune syn_preserve = 1 */;
lcell muxsel_buff(.in(muxsel), .out(muxsel_buff_out)) /* synthesis syn_noprune syn_preserve = 1 */;
assign dataout_wire[i*DATA_WIDTH+j] = (muxsel_buff_out == 1'b0) ? t0 : t1;
end
else begin
//wire delay is to avoid glitch during sim which makes things harder to see.
//in reality glitches are unimportant as long as paths between output
//and next flop meet timing.
wire t0 = datain_r[i*DATA_WIDTH+j];
wire #1 t1 = datain_r[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
wire #1 muxsel = clk;
//There's a timing path from from muxsel to the target FF fed by dataout.
//If the clock signal driving muxsel is a global signal (which is likely),
//the router won't try to insert delay to fix hold. We therefore insert
//lcell buffers to help hold timing.
wire muxsel_buff_out /* synthesis syn_noprune syn_preserve = 1 */;
lcell muxsel_buff(.in(muxsel), .out(muxsel_buff_out)) /* synthesis syn_noprune syn_preserve = 1 */;
assign dataout_wire[i*DATA_WIDTH+j] = (muxsel_buff_out == 1'b1) ? t0 : t1;
end
end
end
//register output if needed
if (REGISTER_OUTPUT == "false") begin
assign dataout = dataout_wire;
end else begin
reg [OUTPUT_FULL_DATA_WIDTH-1:0] dataout_r /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge dr_clk or negedge dr_reset_n)
begin
if (~dr_reset_n) begin
if (REG_POST_RESET_HIGH == "true")
dataout_r <= {OUTPUT_FULL_DATA_WIDTH{1'b1}};
else
dataout_r <= {OUTPUT_FULL_DATA_WIDTH{1'b0}};
end else begin
dataout_r <= dataout_wire;
end
end
assign dataout = dataout_r;
end
end else begin
//Use ddio_out at the I/O periphery of the device
for (i=0; i<OUTPUT_WIDTH_MULT; i=i+1)
begin: ddio_group
for (j=0; j<DATA_WIDTH; j=j+1)
begin: sig
wire t0;
wire t1;
//3-flop half-rate ddio_outs have reversed output ordering
if (HALF_RATE_MODE == "true") begin
assign t0 = datain[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
assign t1 = datain[i*DATA_WIDTH+j];
end else begin
assign t0 = datain[i*DATA_WIDTH+j];
assign t1 = datain[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
end
//NOTE that arriaiigx doesn't support half-rate ddio_out (arriaiigz does).
stratixiv_ddio_out ddio_o (
.areset(~reset_n),
.datainhi(t0),
.datainlo(t1),
.dataout(dataout[i*DATA_WIDTH+j]),
.clkhi (clk),
.clklo (clk),
.muxsel (clk)
);
defparam
ddio_o.use_new_clocking_model = "true",
ddio_o.half_rate_mode = HALF_RATE_MODE,
ddio_o.power_up = HARD_DDIO_POWER_UP,
ddio_o.async_mode = HARD_DDIO_ASYNC_MODE;
end
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_write_datapath(
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
seq_num_write_fr_cycle_shifts
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
localparam DQ_GROUP_WIDTH = MEM_DQ_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam DM_GROUP_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
input pll_afi_clk;
input reset_n;
input [AFI_DQS_WIDTH-1:0] force_oct_off;
output [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [AFI_DQS_WIDTH-1:0] afi_dqs_en;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
output [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
output [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
output [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
input [MEM_WRITE_DQS_WIDTH * 2 - 1:0] seq_num_write_fr_cycle_shifts;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_pre_shift;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
generate
genvar stage;
if (NUM_WRITE_PATH_FLOP_STAGES == 0)
begin
assign phy_ddio_dq_pre_shift = afi_wdata;
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en;
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid;
assign phy_ddio_wrdata_mask_pre_shift = afi_dm;
end
else
begin
reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
// phy_ddio_wrdata_mask is tied low during calibration
// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
// sclr pin is very slow and causes timing failures
(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
always @(posedge pll_afi_clk)
begin
afi_wdata_r[0] <= afi_wdata;
afi_dqs_en_r[0] <= afi_dqs_en;
afi_wdata_valid_r[0] <= afi_wdata_valid;
afi_dm_r[0] <= afi_dm;
end
for (stage = 1; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge pll_afi_clk)
begin
afi_wdata_r[stage] <= afi_wdata_r[stage-1];
afi_dqs_en_r[stage] <= afi_dqs_en_r[stage-1];
afi_wdata_valid_r[stage] <= afi_wdata_valid_r[stage-1];
afi_dm_r[stage] <= afi_dm_r[stage-1];
end
end
assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
end
endgenerate
wire [AFI_DQS_WIDTH-1:0] oct_ena;
wire [MEM_WRITE_DQS_WIDTH-1:0] dqs_en_t1 = phy_ddio_dqs_en[MEM_WRITE_DQS_WIDTH * 2 - 1 : MEM_WRITE_DQS_WIDTH * 1];
wire [MEM_WRITE_DQS_WIDTH-1:0] dqs_en_t0 = phy_ddio_dqs_en[MEM_WRITE_DQS_WIDTH * 1 - 1 : MEM_WRITE_DQS_WIDTH * 0];
reg [MEM_WRITE_DQS_WIDTH-1:0] dqs_en_t0_r;
always @(posedge pll_afi_clk)
dqs_en_t0_r <= dqs_en_t0;
assign oct_ena = ~{dqs_en_t1, dqs_en_t1 | dqs_en_t0_r | dqs_en_t0};
assign phy_ddio_oct_ena_pre_shift = oct_ena & ~force_oct_off;
generate
genvar i, t;
for (i=0; i<MEM_WRITE_DQS_WIDTH; i=i+1)
begin: bs_wr_grp
wire [1:0] seq_num_write_fr_cycle_shifts_per_group = seq_num_write_fr_cycle_shifts[2 * (i + 1) - 1 : i * 2];
wire [1:0] shift_fr_cycle =
(NUM_WRITE_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 3) ? 2'b11 : (
seq_num_write_fr_cycle_shifts_per_group))));
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_oct_ena_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_oct_ena;
wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq_pre_shift;
wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en;
wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask_pre_shift;
wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter dq_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_dq_pre_shift),
.dataout (grp_dq)
);
defparam dq_shifter.DATA_WIDTH = (DQ_GROUP_WIDTH * 2);
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter wrdata_mask_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_wrdata_mask_pre_shift),
.dataout (grp_wrdata_mask)
);
defparam wrdata_mask_shifter.DATA_WIDTH = (DM_GROUP_WIDTH * 2);
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter wrdata_en_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_wrdata_en_pre_shift),
.dataout (grp_wrdata_en)
);
defparam wrdata_en_shifter.DATA_WIDTH = 1;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter dqs_en_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_dqs_en_pre_shift),
.dataout (grp_dqs_en)
);
defparam dqs_en_shifter.DATA_WIDTH = 1;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter oct_ena_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_oct_ena_pre_shift),
.dataout (grp_oct_ena)
);
defparam oct_ena_shifter.DATA_WIDTH = 1;
for (t=0; t<RATE_MULT*2; t=t+1)
begin: extract_ddr_grp
wire [DQ_GROUP_WIDTH-1:0] dq_t_pre_shift = phy_ddio_dq_pre_shift[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t];
assign grp_dq_pre_shift[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH] = dq_t_pre_shift;
wire [DQ_GROUP_WIDTH-1:0] dq_t = grp_dq[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH];
assign phy_ddio_dq[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t] = dq_t;
wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t_pre_shift = phy_ddio_wrdata_mask_pre_shift[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t];
assign grp_wrdata_mask_pre_shift[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH] = wrdata_mask_t_pre_shift;
wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t = grp_wrdata_mask[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH];
assign phy_ddio_wrdata_mask[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t] = wrdata_mask_t;
end
for (t=0; t<RATE_MULT; t=t+1)
begin: extract_sdr_grp
assign grp_oct_ena_pre_shift[t] = phy_ddio_oct_ena_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_oct_ena[i + MEM_WRITE_DQS_WIDTH * t] = grp_oct_ena[t];
assign grp_dqs_en_pre_shift[t] = phy_ddio_dqs_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_dqs_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_dqs_en[t];
assign grp_wrdata_en_pre_shift[t] = phy_ddio_wrdata_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_wrdata_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_wrdata_en[t];
end
end
endgenerate
endmodule
|
// DE4_SOPC_ddr2_0_s0.v
// This file was auto-generated from qsys_sequencer_110_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 11.1 173 at 2012.08.31.13:49:16
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_s0 (
input wire avl_clk, // avl_clk.clk
input wire avl_reset_n, // avl_reset.reset_n
input wire phy_clk, // phy.phy_clk
input wire phy_reset_n, // .phy_reset_n
output wire [4:0] phy_read_latency_counter, // .phy_read_latency_counter
output wire [5:0] phy_afi_wlat, // .phy_afi_wlat
output wire [5:0] phy_afi_rlat, // .phy_afi_rlat
output wire [7:0] phy_read_increment_vfifo_fr, // .phy_read_increment_vfifo_fr
output wire [7:0] phy_read_increment_vfifo_hr, // .phy_read_increment_vfifo_hr
output wire [7:0] phy_read_increment_vfifo_qr, // .phy_read_increment_vfifo_qr
output wire phy_reset_mem_stable, // .phy_reset_mem_stable
output wire phy_cal_success, // .phy_cal_success
output wire phy_cal_fail, // .phy_cal_fail
output wire [31:0] phy_cal_debug_info, // .phy_cal_debug_info
output wire [7:0] phy_read_fifo_reset, // .phy_read_fifo_reset
output wire [7:0] phy_vfifo_rd_en_override, // .phy_vfifo_rd_en_override
input wire [255:0] phy_read_fifo_q, // .phy_read_fifo_q
output wire phy_mux_sel, // mux_sel.mux_sel
input wire [7:0] calib_skip_steps, // calib.calib_skip_steps
input wire afi_clk, // afi_clk.clk
input wire afi_reset_n, // afi_reset.reset_n
output wire [27:0] afi_addr, // afi.afi_addr
output wire [5:0] afi_ba, // .afi_ba
output wire [1:0] afi_cs_n, // .afi_cs_n
output wire [1:0] afi_cke, // .afi_cke
output wire [1:0] afi_odt, // .afi_odt
output wire [1:0] afi_ras_n, // .afi_ras_n
output wire [1:0] afi_cas_n, // .afi_cas_n
output wire [1:0] afi_we_n, // .afi_we_n
output wire [15:0] afi_dqs_burst, // .afi_dqs_burst
output wire [255:0] afi_wdata, // .afi_wdata
output wire [15:0] afi_wdata_valid, // .afi_wdata_valid
output wire [31:0] afi_dm, // .afi_dm
output wire [1:0] afi_rdata_en, // .afi_rdata_en
output wire [1:0] afi_rdata_en_full, // .afi_rdata_en_full
input wire [255:0] afi_rdata, // .afi_rdata
input wire [1:0] afi_rdata_valid, // .afi_rdata_valid
output wire scc_data, // scc.scc_data
output wire [7:0] scc_dqs_ena, // .scc_dqs_ena
output wire [7:0] scc_dqs_io_ena, // .scc_dqs_io_ena
output wire [63:0] scc_dq_ena, // .scc_dq_ena
output wire [7:0] scc_dm_ena, // .scc_dm_ena
output wire scc_upd, // .scc_upd
input wire [7:0] capture_strobe_tracking, // .capture_strobe_tracking
input wire afi_init_req, // afi_init_cal_req.afi_init_req
input wire afi_cal_req, // .afi_cal_req
input wire scc_clk, // scc_clk.clk
input wire reset_n_scc_clk // scc_reset.reset_n
);
wire cpu_inst_data_master_waitrequest; // cpu_inst_data_master_translator:av_waitrequest -> cpu_inst:d_waitrequest
wire [31:0] cpu_inst_data_master_writedata; // cpu_inst:d_writedata -> cpu_inst_data_master_translator:av_writedata
wire [19:0] cpu_inst_data_master_address; // cpu_inst:d_address -> cpu_inst_data_master_translator:av_address
wire cpu_inst_data_master_write; // cpu_inst:d_write -> cpu_inst_data_master_translator:av_write
wire cpu_inst_data_master_read; // cpu_inst:d_read -> cpu_inst_data_master_translator:av_read
wire [31:0] cpu_inst_data_master_readdata; // cpu_inst_data_master_translator:av_readdata -> cpu_inst:d_readdata
wire [3:0] cpu_inst_data_master_byteenable; // cpu_inst:d_byteenable -> cpu_inst_data_master_translator:av_byteenable
wire cpu_inst_instruction_master_waitrequest; // cpu_inst_instruction_master_translator:av_waitrequest -> cpu_inst:i_waitrequest
wire [16:0] cpu_inst_instruction_master_address; // cpu_inst:i_address -> cpu_inst_instruction_master_translator:av_address
wire cpu_inst_instruction_master_read; // cpu_inst:i_read -> cpu_inst_instruction_master_translator:av_read
wire [31:0] cpu_inst_instruction_master_readdata; // cpu_inst_instruction_master_translator:av_readdata -> cpu_inst:i_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_phy_mgr_inst:avl_waitrequest -> sequencer_phy_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_phy_mgr_inst_avl_translator:av_writedata -> sequencer_phy_mgr_inst:avl_writedata
wire [12:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_phy_mgr_inst_avl_translator:av_address -> sequencer_phy_mgr_inst:avl_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_phy_mgr_inst_avl_translator:av_write -> sequencer_phy_mgr_inst:avl_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_phy_mgr_inst_avl_translator:av_read -> sequencer_phy_mgr_inst:avl_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_phy_mgr_inst:avl_readdata -> sequencer_phy_mgr_inst_avl_translator:av_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_data_mgr_inst:avl_waitrequest -> sequencer_data_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_data_mgr_inst_avl_translator:av_writedata -> sequencer_data_mgr_inst:avl_writedata
wire [12:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_data_mgr_inst_avl_translator:av_address -> sequencer_data_mgr_inst:avl_address
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_data_mgr_inst_avl_translator:av_write -> sequencer_data_mgr_inst:avl_write
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_data_mgr_inst_avl_translator:av_read -> sequencer_data_mgr_inst:avl_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_data_mgr_inst:avl_readdata -> sequencer_data_mgr_inst_avl_translator:av_readdata
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_rw_mgr_inst:avl_waitrequest -> sequencer_rw_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_rw_mgr_inst_avl_translator:av_writedata -> sequencer_rw_mgr_inst:avl_writedata
wire [12:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_rw_mgr_inst_avl_translator:av_address -> sequencer_rw_mgr_inst:avl_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_rw_mgr_inst_avl_translator:av_write -> sequencer_rw_mgr_inst:avl_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_rw_mgr_inst_avl_translator:av_read -> sequencer_rw_mgr_inst:avl_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_rw_mgr_inst:avl_readdata -> sequencer_rw_mgr_inst_avl_translator:av_readdata
wire [31:0] sequencer_mem_s1_translator_avalon_anti_slave_0_writedata; // sequencer_mem_s1_translator:av_writedata -> sequencer_mem:s1_writedata
wire [11:0] sequencer_mem_s1_translator_avalon_anti_slave_0_address; // sequencer_mem_s1_translator:av_address -> sequencer_mem:s1_address
wire sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect; // sequencer_mem_s1_translator:av_chipselect -> sequencer_mem:s1_chipselect
wire sequencer_mem_s1_translator_avalon_anti_slave_0_clken; // sequencer_mem_s1_translator:av_clken -> sequencer_mem:s1_clken
wire sequencer_mem_s1_translator_avalon_anti_slave_0_write; // sequencer_mem_s1_translator:av_write -> sequencer_mem:s1_write
wire [31:0] sequencer_mem_s1_translator_avalon_anti_slave_0_readdata; // sequencer_mem:s1_readdata -> sequencer_mem_s1_translator:av_readdata
wire [3:0] sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable; // sequencer_mem_s1_translator:av_byteenable -> sequencer_mem:s1_be
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_scc_mgr_inst:avl_waitrequest -> sequencer_scc_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_scc_mgr_inst_avl_translator:av_writedata -> sequencer_scc_mgr_inst:avl_writedata
wire [12:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_scc_mgr_inst_avl_translator:av_address -> sequencer_scc_mgr_inst:avl_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_scc_mgr_inst_avl_translator:av_write -> sequencer_scc_mgr_inst:avl_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_scc_mgr_inst_avl_translator:av_read -> sequencer_scc_mgr_inst:avl_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_scc_mgr_inst:avl_readdata -> sequencer_scc_mgr_inst_avl_translator:av_readdata
wire sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_reg_file_inst:avl_waitrequest -> sequencer_reg_file_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_reg_file_inst_avl_translator:av_writedata -> sequencer_reg_file_inst:avl_writedata
wire [12:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_reg_file_inst_avl_translator:av_address -> sequencer_reg_file_inst:avl_address
wire sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_reg_file_inst_avl_translator:av_write -> sequencer_reg_file_inst:avl_write
wire sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_reg_file_inst_avl_translator:av_read -> sequencer_reg_file_inst:avl_read
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_reg_file_inst:avl_readdata -> sequencer_reg_file_inst_avl_translator:av_readdata
wire [3:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable; // sequencer_reg_file_inst_avl_translator:av_byteenable -> sequencer_reg_file_inst:avl_be
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_data_mgr_inst_avl_translator:uav_waitrequest -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_data_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_data_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_data_mgr_inst_avl_translator:uav_address
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_data_mgr_inst_avl_translator:uav_write
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_data_mgr_inst_avl_translator:uav_lock
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_data_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_data_mgr_inst_avl_translator:uav_readdata -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_data_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_data_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_data_mgr_inst_avl_translator:uav_byteenable
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [75:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [75:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [19:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [75:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [75:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
wire [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
wire [19:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_mem_s1_translator:uav_address
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_mem_s1_translator:uav_write
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_mem_s1_translator:uav_read
wire [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
wire [3:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [75:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [75:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [75:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [75:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [75:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [75:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata
wire [19:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [75:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [75:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [74:0] cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [74:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [74:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [74:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [74:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [74:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [74:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [74:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux_003:reset, cpu_inst:reset_n, cpu_inst_data_master_translator:reset, cpu_inst_data_master_translator_avalon_universal_master_0_agent:reset, cpu_inst_instruction_master_translator:reset, cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, sequencer_data_mgr_inst:avl_reset_n, sequencer_data_mgr_inst_avl_translator:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_mem:reset1, sequencer_mem_s1_translator:reset, sequencer_mem_s1_translator_avalon_universal_slave_0_agent:reset, sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_phy_mgr_inst:avl_reset_n, sequencer_phy_mgr_inst_avl_translator:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_reg_file_inst:avl_reset_n, sequencer_reg_file_inst_avl_translator:reset, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_rw_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst_avl_translator:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_scc_mgr_inst:avl_reset_n, sequencer_scc_mgr_inst_avl_translator:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [74:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [74:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [74:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [74:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
wire [5:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
wire cmd_xbar_demux_src4_endofpacket; // cmd_xbar_demux:src4_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src4_valid; // cmd_xbar_demux:src4_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src4_startofpacket; // cmd_xbar_demux:src4_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [74:0] cmd_xbar_demux_src4_data; // cmd_xbar_demux:src4_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src4_channel; // cmd_xbar_demux:src4_channel -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src5_endofpacket; // cmd_xbar_demux:src5_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src5_valid; // cmd_xbar_demux:src5_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src5_startofpacket; // cmd_xbar_demux:src5_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [74:0] cmd_xbar_demux_src5_data; // cmd_xbar_demux:src5_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src5_channel; // cmd_xbar_demux:src5_channel -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux_003:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
wire [74:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux_003:sink1_data
wire [5:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux_003:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [74:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [5:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [74:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [5:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [74:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [5:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [74:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
wire [5:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [74:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
wire [74:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
wire [5:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
wire [74:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
wire [5:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [74:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [5:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [74:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [74:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
wire [5:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
wire rsp_xbar_demux_003_src1_ready; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_003:src1_ready
wire cmd_xbar_demux_src0_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src0_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [74:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [5:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_demux_src1_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src1_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [74:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [5:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_demux_src2_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [74:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [5:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [74:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_003_src_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [74:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [5:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_src4_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [74:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [5:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_src5_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [74:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [5:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire [31:0] cpu_inst_d_irq_irq; // irq_mapper:sender_irq -> cpu_inst:d_irq
altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst cpu_inst (
.clk (avl_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (cpu_inst_data_master_address), // data_master.address
.d_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.d_read (cpu_inst_data_master_read), // .read
.d_readdata (cpu_inst_data_master_readdata), // .readdata
.d_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.d_write (cpu_inst_data_master_write), // .write
.d_writedata (cpu_inst_data_master_writedata), // .writedata
.i_address (cpu_inst_instruction_master_address), // instruction_master.address
.i_read (cpu_inst_instruction_master_read), // .read
.i_readdata (cpu_inst_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_inst_d_irq_irq), // d_irq.irq
.no_ci_readra () // custom_instruction_master.readra
);
sequencer_scc_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_IF_READ_DQS_WIDTH (8),
.MEM_IF_WRITE_DQS_WIDTH (8),
.MEM_IF_DQ_WIDTH (64),
.MEM_IF_DM_WIDTH (8),
.DLL_DELAY_CHAIN_LENGTH (10),
.FAMILY ("STRATIXIV"),
.DQS_TRK_ENABLED (0),
.DUAL_WRITE_CLOCK (0)
) sequencer_scc_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.scc_clk (scc_clk), // scc_clk.clk
.scc_reset_n (reset_n_scc_clk), // scc_reset.reset_n
.scc_data (scc_data), // scc.scc_data
.scc_dqs_ena (scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (scc_dm_ena), // .scc_dm_ena
.scc_upd (scc_upd), // .scc_upd
.capture_strobe_tracking (capture_strobe_tracking), // .capture_strobe_tracking
.afi_init_req (afi_init_req), // afi_init_cal_req.afi_init_req
.afi_cal_req (afi_cal_req) // .afi_cal_req
);
sequencer_reg_file #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.AVL_NUM_SYMBOLS (4),
.AVL_SYMBOL_WIDTH (8),
.REGISTER_RDATA (0),
.NUM_REGFILE_WORDS (16)
) sequencer_reg_file_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.avl_be (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable) // .byteenable
);
sequencer_phy_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (5),
.MEM_IF_READ_DQS_WIDTH (8),
.AFI_DQ_WIDTH (256),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (13),
.CALIB_LFIFO_OFFSET (5),
.CALIB_REG_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (5),
.MEM_T_RL (6),
.CTL_REGDIMM_ENABLED (0)
) sequencer_phy_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.phy_clk (phy_clk), // phy.phy_clk
.phy_reset_n (phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (phy_read_latency_counter), // .phy_read_latency_counter
.phy_afi_wlat (phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (phy_afi_rlat), // .phy_afi_rlat
.phy_read_increment_vfifo_fr (phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_cal_success (phy_cal_success), // .phy_cal_success
.phy_cal_fail (phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.phy_read_fifo_q (phy_read_fifo_q), // .phy_read_fifo_q
.calib_skip_steps (calib_skip_steps), // calib.calib_skip_steps
.phy_mux_sel (phy_mux_sel) // mux_sel.mux_sel
);
sequencer_data_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (5),
.MEM_READ_DQS_WIDTH (8),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (13),
.CALIB_LFIFO_OFFSET (5),
.CALIB_SKIP_STEPS_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (5),
.MEM_T_RL (6),
.CTL_REGDIMM_ENABLED (0),
.SEQUENCER_VERSION (11)
) sequencer_data_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest) // .waitrequest
);
rw_manager_ddr2 #(
.RATE ("Half"),
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_ADDRESS_WIDTH (14),
.MEM_CONTROL_WIDTH (1),
.MEM_DQ_WIDTH (64),
.MEM_DM_WIDTH (8),
.MEM_NUMBER_OF_RANKS (1),
.MEM_CLK_EN_WIDTH (1),
.MEM_BANK_WIDTH (3),
.MEM_ODT_WIDTH (1),
.MEM_CHIP_SELECT_WIDTH (1),
.MEM_READ_DQS_WIDTH (8),
.MEM_WRITE_DQS_WIDTH (8),
.AFI_RATIO (2),
.AC_BUS_WIDTH (26),
.HCX_COMPAT_MODE (0),
.DEVICE_FAMILY ("STRATIXIV"),
.AC_ROM_INIT_FILE_NAME ("DE4_SOPC_ddr2_0_s0_AC_ROM.hex"),
.INST_ROM_INIT_FILE_NAME ("DE4_SOPC_ddr2_0_s0_inst_ROM.hex")
) sequencer_rw_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.afi_clk (afi_clk), // afi_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_addr (afi_addr), // afi.afi_addr
.afi_ba (afi_ba), // .afi_ba
.afi_cs_n (afi_cs_n), // .afi_cs_n
.afi_cke (afi_cke), // .afi_cke
.afi_odt (afi_odt), // .afi_odt
.afi_ras_n (afi_ras_n), // .afi_ras_n
.afi_cas_n (afi_cas_n), // .afi_cas_n
.afi_we_n (afi_we_n), // .afi_we_n
.afi_dqs_burst (afi_dqs_burst), // .afi_dqs_burst
.afi_wdata (afi_wdata), // .afi_wdata
.afi_wdata_valid (afi_wdata_valid), // .afi_wdata_valid
.afi_dm (afi_dm), // .afi_dm
.afi_rdata_en (afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata (afi_rdata), // .afi_rdata
.afi_rdata_valid (afi_rdata_valid), // .afi_rdata_valid
.csr_clk (), // csr.csr_clk
.csr_ena (), // .csr_ena
.csr_dout_phy (), // .csr_dout_phy
.csr_dout () // .csr_dout
);
altera_mem_if_sequencer_mem_no_ifdef_params #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (12),
.AVL_NUM_SYMBOLS (4),
.AVL_SYMBOL_WIDTH (8),
.MEM_SIZE (11264),
.INIT_FILE ("DE4_SOPC_ddr2_0_s0_sequencer_mem.hex")
) sequencer_mem (
.clk1 (avl_clk), // clk1.clk
.reset1 (rst_controller_reset_out_reset), // reset1.reset
.s1_address (sequencer_mem_s1_translator_avalon_anti_slave_0_address), // s1.address
.s1_write (sequencer_mem_s1_translator_avalon_anti_slave_0_write), // .write
.s1_writedata (sequencer_mem_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.s1_readdata (sequencer_mem_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.s1_be (sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.s1_chipselect (sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.s1_clken (sequencer_mem_s1_translator_avalon_anti_slave_0_clken) // .clken
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_inst_data_master_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.av_read (cpu_inst_data_master_read), // .read
.av_readdata (cpu_inst_data_master_readdata), // .readdata
.av_write (cpu_inst_data_master_write), // .write
.av_writedata (cpu_inst_data_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_inst_instruction_master_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_inst_instruction_master_read), // .read
.av_readdata (cpu_inst_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_phy_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_data_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_rw_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_mem_s1_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_mem_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_mem_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (sequencer_mem_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_mem_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (sequencer_mem_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_scc_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_reg_file_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (67),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.ST_CHANNEL_W (6),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src1_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src1_valid), // .valid
.cp_data (cmd_xbar_demux_src1_data), // .data
.cp_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src1_channel), // .channel
.rf_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.PKT_BEGIN_BURST (67),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.ST_DATA_W (75),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3)
) cpu_inst_instruction_master_translator_avalon_universal_master_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_003_src1_valid), // rp.valid
.rp_data (rsp_xbar_demux_003_src1_data), // .data
.rp_channel (rsp_xbar_demux_003_src1_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_003_src1_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.PKT_BEGIN_BURST (67),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.ST_DATA_W (75),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7)
) cpu_inst_data_master_translator_avalon_universal_master_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (67),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.ST_CHANNEL_W (6),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src2_valid), // .valid
.cp_data (cmd_xbar_demux_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src2_channel), // .channel
.rf_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (67),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.ST_CHANNEL_W (6),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_mem_s1_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_003_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_003_src_valid), // .valid
.cp_data (cmd_xbar_mux_003_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_003_src_channel), // .channel
.rf_sink_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (67),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.ST_CHANNEL_W (6),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src4_valid), // .valid
.cp_data (cmd_xbar_demux_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src4_channel), // .channel
.rf_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (67),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.ST_CHANNEL_W (6),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src0_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src0_valid), // .valid
.cp_data (cmd_xbar_demux_src0_data), // .data
.cp_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src0_channel), // .channel
.rf_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (67),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (68),
.PKT_DEST_ID_H (73),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (74),
.ST_CHANNEL_W (6),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src5_valid), // .valid
.cp_data (cmd_xbar_demux_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src5_channel), // .channel
.rf_sink_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
DE4_SOPC_ddr2_0_s0_addr_router addr_router (
.sink_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_addr_router_001 addr_router_001 (
.sink_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router (
.sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_001 (
.sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_002 (
.sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router_003 id_router_003 (
.sink_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_004 (
.sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_005 (
.sink_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~avl_reset_n), // reset_in0.reset
.clk (avl_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux cmd_xbar_demux (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_src4_valid), // .valid
.src4_data (cmd_xbar_demux_src4_data), // .data
.src4_channel (cmd_xbar_demux_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_src5_valid), // .valid
.src5_data (cmd_xbar_demux_src5_data), // .data
.src5_channel (cmd_xbar_demux_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_src5_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_001_src_ready), // sink.ready
.sink_channel (addr_router_001_src_channel), // .channel
.sink_data (addr_router_001_src_data), // .data
.sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.sink_valid (addr_router_001_src_valid), // .valid
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_mux_003 cmd_xbar_mux_003 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src3_valid), // .valid
.sink0_channel (cmd_xbar_demux_src3_channel), // .channel
.sink0_data (cmd_xbar_demux_src3_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_001 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_002 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_rsp_xbar_demux_003 rsp_xbar_demux_003 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.src1_data (rsp_xbar_demux_003_src1_data), // .data
.src1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_004 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_005 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_rsp_xbar_mux rsp_xbar_mux (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_irq_mapper irq_mapper (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sender_irq (cpu_inst_d_irq_irq) // sender.irq
);
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_log_module (
// inputs:
clk,
data,
strobe,
valid
)
;
input clk;
input [ 7: 0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen ("DE4_SOPC_debug_uart_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite (text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush (text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_debug_uart_log, which is an e_log
DE4_SOPC_debug_uart_log_module DE4_SOPC_debug_uart_log
(
.clk (clk),
.data (fifo_wdata),
.strobe (fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_debug_uart_sim_scfifo_w the_DE4_SOPC_debug_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_drom_module (
// inputs:
clk,
incr_addr,
reset_n,
// outputs:
new_rom,
num_bytes,
q,
safe
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 31: 0] num_bytes;
output [ 7: 0] q;
output safe;
input clk;
input incr_addr;
input reset_n;
reg [ 11: 0] address;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [2047: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
wire [ 31: 0] num_bytes;
reg pre;
wire [ 7: 0] q;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign q = mem_array[address];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_pre <= 0;
d2_pre <= 0;
d3_pre <= 0;
d4_pre <= 0;
d5_pre <= 0;
d6_pre <= 0;
d7_pre <= 0;
d8_pre <= 0;
d9_pre <= 0;
new_rom <= 0;
end
else
begin
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end
end
assign num_bytes = mutex[1];
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b0 ; // '
assign safe = (address < mutex[1]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin // dont worry about null _stream.dat file
address <= 0;
mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
if (incr_addr && safe) address <= address + 1;
if (mutex[0] && !safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
mutex_handle = $fopen ("DE4_SOPC_debug_uart_input_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared!");
end else begin
// sleep until next reset, do not bash mutex.
wait (!reset_n);
end
end // OK to bash mutex.
if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
if (mutex_handle) begin
$readmemh ("DE4_SOPC_debug_uart_input_mutex.dat", mutex);
end
if (mutex[0] && !safe) begin
// read stream into mem_array after current characters are gone!
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemb("DE4_SOPC_debug_uart_input_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_debug_uart_drom, which is an e_drom
DE4_SOPC_debug_uart_drom_module DE4_SOPC_debug_uart_drom
(
.clk (clk),
.incr_addr (fifo_rd_d),
.new_rom (new_rom),
.num_bytes (num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_debug_uart_sim_scfifo_r the_DE4_SOPC_debug_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE4_SOPC_debug_uart_scfifo_w the_DE4_SOPC_debug_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE4_SOPC_debug_uart_scfifo_r the_DE4_SOPC_debug_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE4_SOPC_debug_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE4_SOPC_debug_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE4_SOPC_debug_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// DE4_SOPC_debug_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE4_SOPC_debug_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {{{32- 8}{1'b0}},read_mux_out};
assign out_port = data_out;
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_onchip_memory_MIPS (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../initial.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "initial.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 8192,
// the_altsyncram.numwords_a = 8192,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 13;
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrfull,
wrusedw
)
;
output [ 31: 0] q;
output rdempty;
output rdfull;
output [ 3: 0] rdusedw;
output wrfull;
output [ 3: 0] wrusedw;
input aclr;
input [ 31: 0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
wire int_rdfull;
wire int_wrfull;
wire [ 31: 0] q;
wire rdempty;
wire rdfull;
wire [ 3: 0] rdusedw;
wire wrfull;
wire [ 3: 0] wrusedw;
assign wrfull = (wrusedw >= 16-3) | int_wrfull;
assign rdfull = (rdusedw >= 16-3) | int_rdfull;
dcfifo dual_clock_fifo
(
.aclr (aclr),
.data (data),
.q (q),
.rdclk (rdclk),
.rdempty (rdempty),
.rdfull (int_rdfull),
.rdreq (rdreq),
.rdusedw (rdusedw),
.wrclk (wrclk),
.wrfull (int_wrfull),
.wrreq (wrreq),
.wrusedw (wrusedw)
);
defparam dual_clock_fifo.add_ram_output_register = "OFF",
dual_clock_fifo.clocks_are_synchronized = "FALSE",
dual_clock_fifo.intended_device_family = "STRATIXIV",
dual_clock_fifo.lpm_numwords = 16,
dual_clock_fifo.lpm_showahead = "OFF",
dual_clock_fifo.lpm_type = "dcfifo",
dual_clock_fifo.lpm_width = 32,
dual_clock_fifo.lpm_widthu = 4,
dual_clock_fifo.overflow_checking = "ON",
dual_clock_fifo.underflow_checking = "ON",
dual_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_dcfifo_with_controls (
// inputs:
data,
rdclk,
rdclk_control_slave_address,
rdclk_control_slave_read,
rdclk_control_slave_write,
rdclk_control_slave_writedata,
rdreq,
rdreset_n,
wrclk,
wrreq,
wrreset_n,
// outputs:
q,
rdclk_control_slave_irq,
rdclk_control_slave_readdata,
rdempty,
wrfull,
wrlevel
)
;
output [ 31: 0] q;
output rdclk_control_slave_irq;
output [ 31: 0] rdclk_control_slave_readdata;
output rdempty;
output wrfull;
output [ 4: 0] wrlevel;
input [ 31: 0] data;
input rdclk;
input [ 2: 0] rdclk_control_slave_address;
input rdclk_control_slave_read;
input rdclk_control_slave_write;
input [ 31: 0] rdclk_control_slave_writedata;
input rdreq;
input rdreset_n;
input wrclk;
input wrreq;
input wrreset_n;
wire [ 31: 0] q;
reg rdclk_control_slave_almostempty_n_reg;
wire rdclk_control_slave_almostempty_pulse;
wire rdclk_control_slave_almostempty_signal;
reg [ 4: 0] rdclk_control_slave_almostempty_threshold_register;
reg rdclk_control_slave_almostfull_n_reg;
wire rdclk_control_slave_almostfull_pulse;
wire rdclk_control_slave_almostfull_signal;
reg [ 4: 0] rdclk_control_slave_almostfull_threshold_register;
reg rdclk_control_slave_empty_n_reg;
wire rdclk_control_slave_empty_pulse;
wire rdclk_control_slave_empty_signal;
reg rdclk_control_slave_event_almostempty_q;
wire rdclk_control_slave_event_almostempty_signal;
reg rdclk_control_slave_event_almostfull_q;
wire rdclk_control_slave_event_almostfull_signal;
reg rdclk_control_slave_event_empty_q;
wire rdclk_control_slave_event_empty_signal;
reg rdclk_control_slave_event_full_q;
wire rdclk_control_slave_event_full_signal;
reg rdclk_control_slave_event_overflow_q;
wire rdclk_control_slave_event_overflow_signal;
wire [ 5: 0] rdclk_control_slave_event_register;
reg rdclk_control_slave_event_underflow_q;
wire rdclk_control_slave_event_underflow_signal;
reg rdclk_control_slave_full_n_reg;
wire rdclk_control_slave_full_pulse;
wire rdclk_control_slave_full_signal;
reg [ 5: 0] rdclk_control_slave_ienable_register;
wire rdclk_control_slave_irq;
wire [ 4: 0] rdclk_control_slave_level_register;
wire [ 31: 0] rdclk_control_slave_read_mux;
reg [ 31: 0] rdclk_control_slave_readdata;
reg rdclk_control_slave_status_almostempty_q;
wire rdclk_control_slave_status_almostempty_signal;
reg rdclk_control_slave_status_almostfull_q;
wire rdclk_control_slave_status_almostfull_signal;
reg rdclk_control_slave_status_empty_q;
wire rdclk_control_slave_status_empty_signal;
reg rdclk_control_slave_status_full_q;
wire rdclk_control_slave_status_full_signal;
reg rdclk_control_slave_status_overflow_q;
wire rdclk_control_slave_status_overflow_signal;
wire [ 5: 0] rdclk_control_slave_status_register;
reg rdclk_control_slave_status_underflow_q;
wire rdclk_control_slave_status_underflow_signal;
wire [ 4: 0] rdclk_control_slave_threshold_writedata;
wire rdempty;
wire rdfull;
wire [ 4: 0] rdlevel;
wire rdoverflow;
wire rdunderflow;
wire [ 3: 0] rdusedw;
wire wrfull;
wire [ 4: 0] wrlevel;
wire wrreq_valid;
wire [ 3: 0] wrusedw;
//the_dcfifo, which is an e_instance
DE4_SOPC_receive_fifo_dual_clock_fifo the_dcfifo
(
.aclr (~wrreset_n),
.data (data),
.q (q),
.rdclk (rdclk),
.rdempty (rdempty),
.rdfull (rdfull),
.rdreq (rdreq),
.rdusedw (rdusedw),
.wrclk (wrclk),
.wrfull (wrfull),
.wrreq (wrreq_valid),
.wrusedw (wrusedw)
);
assign wrlevel = {1'b0,
wrusedw};
assign wrreq_valid = wrreq & ~wrfull;
assign rdlevel = {1'b0,
rdusedw};
assign rdoverflow = wrreq & rdfull;
assign rdunderflow = rdreq & rdempty;
assign rdclk_control_slave_threshold_writedata = (rdclk_control_slave_writedata < 1) ? 1 :
(rdclk_control_slave_writedata > 12) ? 12 :
rdclk_control_slave_writedata[4 : 0];
assign rdclk_control_slave_event_almostfull_signal = rdclk_control_slave_almostfull_pulse;
assign rdclk_control_slave_event_almostempty_signal = rdclk_control_slave_almostempty_pulse;
assign rdclk_control_slave_status_almostfull_signal = rdclk_control_slave_almostfull_signal;
assign rdclk_control_slave_status_almostempty_signal = rdclk_control_slave_almostempty_signal;
assign rdclk_control_slave_event_full_signal = rdclk_control_slave_full_pulse;
assign rdclk_control_slave_event_empty_signal = rdclk_control_slave_empty_pulse;
assign rdclk_control_slave_status_full_signal = rdclk_control_slave_full_signal;
assign rdclk_control_slave_status_empty_signal = rdclk_control_slave_empty_signal;
assign rdclk_control_slave_event_overflow_signal = rdoverflow;
assign rdclk_control_slave_event_underflow_signal = rdunderflow;
assign rdclk_control_slave_status_overflow_signal = rdoverflow;
assign rdclk_control_slave_status_underflow_signal = rdunderflow;
assign rdclk_control_slave_empty_signal = rdempty;
assign rdclk_control_slave_empty_pulse = rdclk_control_slave_empty_signal & rdclk_control_slave_empty_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_empty_n_reg <= 0;
else
rdclk_control_slave_empty_n_reg <= !rdclk_control_slave_empty_signal;
end
assign rdclk_control_slave_full_signal = rdfull;
assign rdclk_control_slave_full_pulse = rdclk_control_slave_full_signal & rdclk_control_slave_full_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_full_n_reg <= 0;
else
rdclk_control_slave_full_n_reg <= !rdclk_control_slave_full_signal;
end
assign rdclk_control_slave_almostempty_signal = rdlevel <= rdclk_control_slave_almostempty_threshold_register;
assign rdclk_control_slave_almostempty_pulse = rdclk_control_slave_almostempty_signal & rdclk_control_slave_almostempty_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostempty_n_reg <= 0;
else
rdclk_control_slave_almostempty_n_reg <= !rdclk_control_slave_almostempty_signal;
end
assign rdclk_control_slave_almostfull_signal = rdlevel >= rdclk_control_slave_almostfull_threshold_register;
assign rdclk_control_slave_almostfull_pulse = rdclk_control_slave_almostfull_signal & rdclk_control_slave_almostfull_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostfull_n_reg <= 0;
else
rdclk_control_slave_almostfull_n_reg <= !rdclk_control_slave_almostfull_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostempty_threshold_register <= 1;
else if ((rdclk_control_slave_address == 5) & rdclk_control_slave_write)
rdclk_control_slave_almostempty_threshold_register <= rdclk_control_slave_threshold_writedata;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostfull_threshold_register <= 12;
else if ((rdclk_control_slave_address == 4) & rdclk_control_slave_write)
rdclk_control_slave_almostfull_threshold_register <= rdclk_control_slave_threshold_writedata;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_ienable_register <= 0;
else if ((rdclk_control_slave_address == 3) & rdclk_control_slave_write)
rdclk_control_slave_ienable_register <= rdclk_control_slave_writedata[5 : 0];
end
assign rdclk_control_slave_level_register = rdlevel;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_underflow_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[5])
rdclk_control_slave_event_underflow_q <= 0;
else if (rdclk_control_slave_event_underflow_signal)
rdclk_control_slave_event_underflow_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_overflow_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[4])
rdclk_control_slave_event_overflow_q <= 0;
else if (rdclk_control_slave_event_overflow_signal)
rdclk_control_slave_event_overflow_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_almostempty_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[3])
rdclk_control_slave_event_almostempty_q <= 0;
else if (rdclk_control_slave_event_almostempty_signal)
rdclk_control_slave_event_almostempty_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_almostfull_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[2])
rdclk_control_slave_event_almostfull_q <= 0;
else if (rdclk_control_slave_event_almostfull_signal)
rdclk_control_slave_event_almostfull_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_empty_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[1])
rdclk_control_slave_event_empty_q <= 0;
else if (rdclk_control_slave_event_empty_signal)
rdclk_control_slave_event_empty_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_full_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[0])
rdclk_control_slave_event_full_q <= 0;
else if (rdclk_control_slave_event_full_signal)
rdclk_control_slave_event_full_q <= -1;
end
assign rdclk_control_slave_event_register = {rdclk_control_slave_event_underflow_q,
rdclk_control_slave_event_overflow_q,
rdclk_control_slave_event_almostempty_q,
rdclk_control_slave_event_almostfull_q,
rdclk_control_slave_event_empty_q,
rdclk_control_slave_event_full_q};
assign rdclk_control_slave_irq = | (rdclk_control_slave_event_register & rdclk_control_slave_ienable_register);
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_underflow_q <= 0;
else
rdclk_control_slave_status_underflow_q <= rdclk_control_slave_status_underflow_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_overflow_q <= 0;
else
rdclk_control_slave_status_overflow_q <= rdclk_control_slave_status_overflow_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_almostempty_q <= 0;
else
rdclk_control_slave_status_almostempty_q <= rdclk_control_slave_status_almostempty_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_almostfull_q <= 0;
else
rdclk_control_slave_status_almostfull_q <= rdclk_control_slave_status_almostfull_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_empty_q <= 0;
else
rdclk_control_slave_status_empty_q <= rdclk_control_slave_status_empty_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_full_q <= 0;
else
rdclk_control_slave_status_full_q <= rdclk_control_slave_status_full_signal;
end
assign rdclk_control_slave_status_register = {rdclk_control_slave_status_underflow_q,
rdclk_control_slave_status_overflow_q,
rdclk_control_slave_status_almostempty_q,
rdclk_control_slave_status_almostfull_q,
rdclk_control_slave_status_empty_q,
rdclk_control_slave_status_full_q};
assign rdclk_control_slave_read_mux = ({32 {(rdclk_control_slave_address == 0)}} & rdclk_control_slave_level_register) |
({32 {(rdclk_control_slave_address == 1)}} & rdclk_control_slave_status_register) |
({32 {(rdclk_control_slave_address == 2)}} & rdclk_control_slave_event_register) |
({32 {(rdclk_control_slave_address == 3)}} & rdclk_control_slave_ienable_register) |
({32 {(rdclk_control_slave_address == 4)}} & rdclk_control_slave_almostfull_threshold_register) |
({32 {(rdclk_control_slave_address == 5)}} & rdclk_control_slave_almostempty_threshold_register) |
({32 {(~((rdclk_control_slave_address == 0))) && (~((rdclk_control_slave_address == 1))) && (~((rdclk_control_slave_address == 2))) && (~((rdclk_control_slave_address == 3))) && (~((rdclk_control_slave_address == 4))) && (~((rdclk_control_slave_address == 5)))}} & rdclk_control_slave_level_register);
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_readdata <= 0;
else if (rdclk_control_slave_read)
rdclk_control_slave_readdata <= rdclk_control_slave_read_mux;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm (
// inputs:
avalonst_data,
// outputs:
avalonmm_data
)
;
output [ 31: 0] avalonmm_data;
input [ 31: 0] avalonst_data;
wire [ 31: 0] avalonmm_data;
assign avalonmm_data[7 : 0] = avalonst_data[31 : 24];
assign avalonmm_data[15 : 8] = avalonst_data[23 : 16];
assign avalonmm_data[23 : 16] = avalonst_data[15 : 8];
assign avalonmm_data[31 : 24] = avalonst_data[7 : 0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_dual_clock_fifo_for_other_info (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q
)
;
output [ 9: 0] q;
input aclr;
input [ 9: 0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
wire [ 9: 0] q;
dcfifo dual_clock_fifo
(
.aclr (aclr),
.data (data),
.q (q),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq)
);
defparam dual_clock_fifo.add_ram_output_register = "OFF",
dual_clock_fifo.clocks_are_synchronized = "FALSE",
dual_clock_fifo.intended_device_family = "STRATIXIV",
dual_clock_fifo.lpm_numwords = 16,
dual_clock_fifo.lpm_showahead = "OFF",
dual_clock_fifo.lpm_type = "dcfifo",
dual_clock_fifo.lpm_width = 10,
dual_clock_fifo.lpm_widthu = 4,
dual_clock_fifo.overflow_checking = "ON",
dual_clock_fifo.underflow_checking = "ON",
dual_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm_other_info (
// inputs:
avalonst_other_info,
// outputs:
avalonmm_other_info
)
;
output [ 31: 0] avalonmm_other_info;
input [ 9: 0] avalonst_other_info;
wire [ 7: 0] avalonmm_channel;
wire [ 5: 0] avalonmm_empty;
wire avalonmm_eop;
wire [ 7: 0] avalonmm_error;
wire [ 31: 0] avalonmm_other_info;
wire avalonmm_sop;
assign avalonmm_sop = avalonst_other_info[0];
assign avalonmm_eop = avalonst_other_info[1];
assign avalonmm_empty = {4'b0,
avalonst_other_info[3 : 2]};
assign avalonmm_channel = 8'b0;
assign avalonmm_error = {2'b0,
avalonst_other_info[9 : 4]};
assign avalonmm_other_info = {8'b0,
avalonmm_error,
avalonmm_channel,
avalonmm_empty,
avalonmm_eop,
avalonmm_sop};
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo (
// inputs:
avalonmm_read_slave_address,
avalonmm_read_slave_read,
avalonst_sink_data,
avalonst_sink_empty,
avalonst_sink_endofpacket,
avalonst_sink_error,
avalonst_sink_startofpacket,
avalonst_sink_valid,
rdclk_control_slave_address,
rdclk_control_slave_read,
rdclk_control_slave_write,
rdclk_control_slave_writedata,
rdclock,
rdreset_n,
wrclock,
wrreset_n,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonst_sink_ready,
rdclk_control_slave_irq,
rdclk_control_slave_readdata
)
;
output [ 31: 0] avalonmm_read_slave_readdata;
output avalonmm_read_slave_waitrequest;
output avalonst_sink_ready;
output rdclk_control_slave_irq;
output [ 31: 0] rdclk_control_slave_readdata;
input avalonmm_read_slave_address;
input avalonmm_read_slave_read;
input [ 31: 0] avalonst_sink_data;
input [ 1: 0] avalonst_sink_empty;
input avalonst_sink_endofpacket;
input [ 5: 0] avalonst_sink_error;
input avalonst_sink_startofpacket;
input avalonst_sink_valid;
input [ 2: 0] rdclk_control_slave_address;
input rdclk_control_slave_read;
input rdclk_control_slave_write;
input [ 31: 0] rdclk_control_slave_writedata;
input rdclock;
input rdreset_n;
input wrclock;
input wrreset_n;
wire [ 31: 0] avalonmm_map_data_out;
wire [ 31: 0] avalonmm_other_info_map_out;
reg avalonmm_read_slave_address_delayed;
reg avalonmm_read_slave_read_delayed;
wire [ 31: 0] avalonmm_read_slave_readdata;
wire avalonmm_read_slave_waitrequest;
wire [ 31: 0] avalonst_map_data_in;
wire [ 9: 0] avalonst_other_info_map_in;
wire avalonst_sink_ready;
wire [ 31: 0] data;
wire deassert_waitrequest;
wire no_stop_write;
reg no_stop_write_d1;
wire [ 31: 0] q;
wire rdclk;
wire rdclk_control_slave_irq;
wire [ 31: 0] rdclk_control_slave_readdata;
wire rdempty;
wire rdreq;
wire rdreq_driver;
wire ready_0;
wire ready_1;
wire ready_selector;
wire wrclk;
wire wrfull;
wire [ 4: 0] wrlevel;
wire wrreq;
//the_dcfifo_with_controls, which is an e_instance
DE4_SOPC_receive_fifo_dcfifo_with_controls the_dcfifo_with_controls
(
.data (data),
.q (q),
.rdclk (rdclk),
.rdclk_control_slave_address (rdclk_control_slave_address),
.rdclk_control_slave_irq (rdclk_control_slave_irq),
.rdclk_control_slave_read (rdclk_control_slave_read),
.rdclk_control_slave_readdata (rdclk_control_slave_readdata),
.rdclk_control_slave_write (rdclk_control_slave_write),
.rdclk_control_slave_writedata (rdclk_control_slave_writedata),
.rdempty (rdempty),
.rdreq (rdreq),
.rdreset_n (rdreset_n),
.wrclk (wrclk),
.wrfull (wrfull),
.wrlevel (wrlevel),
.wrreq (wrreq),
.wrreset_n (wrreset_n)
);
//out, which is an e_avalon_slave
assign deassert_waitrequest = avalonmm_read_slave_address & avalonmm_read_slave_read;
assign avalonmm_read_slave_waitrequest = !deassert_waitrequest & rdempty;
//the_map_avalonst_to_avalonmm, which is an e_instance
DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm the_map_avalonst_to_avalonmm
(
.avalonmm_data (avalonmm_map_data_out),
.avalonst_data (avalonst_map_data_in)
);
assign wrclk = wrclock;
assign rdclk = rdclock;
assign rdreq_driver = (avalonmm_read_slave_address == 0) & avalonmm_read_slave_read;
assign avalonst_map_data_in = q;
assign rdreq = rdreq_driver;
assign data = avalonst_sink_data;
assign wrreq = avalonst_sink_valid & no_stop_write_d1;
assign no_stop_write = (ready_selector & ready_1) | (!ready_selector & ready_0);
assign ready_1 = !wrfull;
assign ready_0 = !wrfull & !avalonst_sink_valid;
assign ready_selector = wrlevel < 12;
always @(posedge wrclk or negedge wrreset_n)
begin
if (wrreset_n == 0)
no_stop_write_d1 <= 0;
else
no_stop_write_d1 <= no_stop_write;
end
assign avalonst_sink_ready = no_stop_write & no_stop_write_d1;
//the_dcfifo_other_info, which is an e_instance
DE4_SOPC_receive_fifo_dual_clock_fifo_for_other_info the_dcfifo_other_info
(
.aclr (~wrreset_n),
.data ({avalonst_sink_error,
avalonst_sink_empty,
avalonst_sink_endofpacket,
avalonst_sink_startofpacket}),
.q (avalonst_other_info_map_in),
.rdclk (rdclk),
.rdreq ((avalonmm_read_slave_address == 0) & avalonmm_read_slave_read),
.wrclk (wrclk),
.wrreq (avalonst_sink_valid & no_stop_write_d1)
);
//the_map_avalonst_to_avalonmm_other_info, which is an e_instance
DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm_other_info the_map_avalonst_to_avalonmm_other_info
(
.avalonmm_other_info (avalonmm_other_info_map_out),
.avalonst_other_info (avalonst_other_info_map_in)
);
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
avalonmm_read_slave_address_delayed <= 0;
else
avalonmm_read_slave_address_delayed <= avalonmm_read_slave_address;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
avalonmm_read_slave_read_delayed <= 0;
else
avalonmm_read_slave_read_delayed <= avalonmm_read_slave_read;
end
assign avalonmm_read_slave_readdata = ({32 {((avalonmm_read_slave_address_delayed == 1) & avalonmm_read_slave_read_delayed)}} & avalonmm_other_info_map_out) |
({32 {((avalonmm_read_slave_address_delayed == 0) & avalonmm_read_slave_read_delayed)}} & avalonmm_map_data_out);
//in, which is an e_atlantic_slave
//out_csr, which is an e_avalon_slave
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_Switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 15: 0] in_port;
input reset_n;
wire clk_en;
wire [ 15: 0] data_in;
wire [ 15: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 16}{1'b0}},read_mux_out};
end
assign data_in = in_port;
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_log_module (
// inputs:
clk,
data,
strobe,
valid
)
;
input clk;
input [ 7: 0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen ("DE4_SOPC_terminal_uart_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite (text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush (text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 8: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 8: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_terminal_uart_log, which is an e_log
DE4_SOPC_terminal_uart_log_module DE4_SOPC_terminal_uart_log
(
.clk (clk),
.data (fifo_wdata),
.strobe (fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {9{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 8: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 8: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_terminal_uart_sim_scfifo_w the_DE4_SOPC_terminal_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 512,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 9,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_drom_module (
// inputs:
clk,
incr_addr,
reset_n,
// outputs:
new_rom,
num_bytes,
q,
safe
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 31: 0] num_bytes;
output [ 7: 0] q;
output safe;
input clk;
input incr_addr;
input reset_n;
reg [ 11: 0] address;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [2047: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
wire [ 31: 0] num_bytes;
reg pre;
wire [ 7: 0] q;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign q = mem_array[address];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_pre <= 0;
d2_pre <= 0;
d3_pre <= 0;
d4_pre <= 0;
d5_pre <= 0;
d6_pre <= 0;
d7_pre <= 0;
d8_pre <= 0;
d9_pre <= 0;
new_rom <= 0;
end
else
begin
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end
end
assign num_bytes = mutex[1];
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b0 ; // '
assign safe = (address < mutex[1]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin // dont worry about null _stream.dat file
address <= 0;
mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
if (incr_addr && safe) address <= address + 1;
if (mutex[0] && !safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
mutex_handle = $fopen ("DE4_SOPC_terminal_uart_input_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared!");
end else begin
// sleep until next reset, do not bash mutex.
wait (!reset_n);
end
end // OK to bash mutex.
if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
if (mutex_handle) begin
$readmemh ("DE4_SOPC_terminal_uart_input_mutex.dat", mutex);
end
if (mutex[0] && !safe) begin
// read stream into mem_array after current characters are gone!
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemb("DE4_SOPC_terminal_uart_input_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_terminal_uart_drom, which is an e_drom
DE4_SOPC_terminal_uart_drom_module DE4_SOPC_terminal_uart_drom
(
.clk (clk),
.incr_addr (fifo_rd_d),
.new_rom (new_rom),
.num_bytes (num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_terminal_uart_sim_scfifo_r the_DE4_SOPC_terminal_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 8: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE4_SOPC_terminal_uart_scfifo_w the_DE4_SOPC_terminal_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE4_SOPC_terminal_uart_scfifo_r the_DE4_SOPC_terminal_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {6{1'b0}},(10'h200 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE4_SOPC_terminal_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE4_SOPC_terminal_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE4_SOPC_terminal_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 9,
// DE4_SOPC_terminal_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE4_SOPC_terminal_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module DE4_SOPC_timing_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [31: 0] in_data,
input in_error,
input in_startofpacket,
input in_endofpacket,
input [ 1: 0] in_empty,
// Interface: out
input out_ready,
output reg out_valid,
output reg [31: 0] out_data,
output reg out_error,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 1: 0] out_empty
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [36: 0] in_payload;
wire [36: 0] out_payload;
wire in_ready_wire;
wire out_valid_wire;
wire [ 3: 0] fifo_fill;
reg [ 0: 0] ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
{out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
end
// ---------------------------------------------------------------------
//| FIFO
// ---------------------------------------------------------------------
DE4_SOPC_timing_adapter_fifo DE4_SOPC_timing_adapter_fifo
(
.clk (clk),
.reset_n (reset_n),
.in_ready (),
.in_valid (in_valid),
.in_data (in_payload),
.out_ready (ready[0]),
.out_valid (out_valid_wire),
.out_data (out_payload),
.fill_level (fifo_fill)
);
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
in_ready = (fifo_fill < 4 );
out_valid = out_valid_wire;
ready[0] = out_ready;
end
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module DE4_SOPC_timing_adapter_1 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [31: 0] in_data,
input [ 5: 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [ 1: 0] in_empty,
// Interface: out
input out_ready,
output reg out_valid,
output reg [31: 0] out_data,
output reg [ 5: 0] out_error,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 1: 0] out_empty
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [41: 0] in_payload;
reg [41: 0] out_payload;
reg [ 1: 0] ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
{out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
end
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
ready[1] = out_ready;
out_valid = in_valid && ready[0];
out_payload = in_payload;
in_ready = ready[0];
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ready[1-1:0] <= 0;
end else begin
ready[1-1:0] <= ready[1:1];
end
end
endmodule
|
// --------------------------------------------------------------------------------
// | simple_atlantic_fifo
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module DE4_SOPC_timing_adapter_fifo (
output reg [ 3: 0] fill_level ,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [36: 0] in_data,
// Interface: data_out
input out_ready,
output reg out_valid,
output reg [36: 0] out_data
);
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
parameter DEPTH = 8;
parameter DATA_WIDTH = 37;
parameter ADDR_WIDTH = 3;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] next_wr_addr;
reg [ADDR_WIDTH-1:0] next_rd_addr;
reg [ADDR_WIDTH-1:0] mem_rd_addr;
reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
reg empty;
reg full;
reg [0:0] out_ready_vector;
// ---------------------------------------------------------------------
//| FIFO Status
// ---------------------------------------------------------------------
always @* begin
// out_valid = !empty;
out_ready_vector[0] = out_ready;
in_ready = !full;
next_wr_addr = wr_addr + 1'b1;
next_rd_addr = rd_addr + 1'b1;
fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
fill_level[ADDR_WIDTH] = 0;
if (full)
fill_level = DEPTH[ADDR_WIDTH:0];
end
// ---------------------------------------------------------------------
//| Manage Pointers
// ---------------------------------------------------------------------
always @ (negedge reset_n, posedge clk) begin
if (!reset_n) begin
wr_addr <= 0;
rd_addr <= 0;
empty <= 1;
rd_addr <= 0;
full <= 0;
out_valid <= 0;
end else begin
out_valid <= !empty;
if (in_ready && in_valid) begin
wr_addr <= next_wr_addr;
empty <= 0;
if (next_wr_addr == rd_addr)
full <= 1;
end
if (out_ready_vector[0] && out_valid) begin
rd_addr <= next_rd_addr;
full <= 0;
if (next_rd_addr == wr_addr) begin
empty <= 1;
out_valid <= 0;
end
end
if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
full <= full;
empty <= empty;
end
end
end // always @ (negedge reset_n, posedge clk)
always @* begin
mem_rd_addr = rd_addr;
if (out_ready && out_valid) begin
mem_rd_addr = next_rd_addr;
end
end
// ---------------------------------------------------------------------
//| Infer Memory
// ---------------------------------------------------------------------
always @ (posedge clk) begin
if (in_ready && in_valid)
mem[wr_addr] <= in_data;
out_data <= mem[mem_rd_addr];
end
endmodule // simple_atlantic_fifo
// synthesis translate_off
// --------------------------------------------------------------------------------
// | test bench
// --------------------------------------------------------------------------------
module test_DE4_SOPC_timing_adapter_fifo;
parameter DEPTH = 8;
parameter DATA_WIDTH = 37;
parameter ADDR_WIDTH = 3;
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
localparam CLOCK_HALF_PERIOD = 10;
localparam CLOCK_PERIOD = 2*CLOCK_HALF_PERIOD;
localparam RESET_TIME = 25;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg clk = 0;
reg reset_n = 0;
reg test_success = 1;
reg success = 1;
wire in_ready;
reg in_valid;
reg [DATA_WIDTH-1:0] in_data;
reg out_ready;
wire out_valid;
wire [DATA_WIDTH-1:0] out_data;
reg [DATA_WIDTH-1:0] next_out_data;
// ---------------------------------------------------------------------
//| DUT
// ---------------------------------------------------------------------
DE4_SOPC_timing_adapter_fifo dut (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data)
);
// ---------------------------------------------------------------------
//| Clock & Reset
// ---------------------------------------------------------------------
initial begin
reset_n = 0;
#RESET_TIME;
reset_n = 1;
end
always begin
#CLOCK_HALF_PERIOD;
clk <= ~clk;
end
// ---------------------------------------------------------------------
//| Data Source
// ---------------------------------------------------------------------
always @(posedge clk) begin
if (reset_n == 0)
in_data <= 0;
else
if (in_ready && in_valid)
in_data <= in_data + 1;
end
// ---------------------------------------------------------------------
//| Data Sink
// ---------------------------------------------------------------------
always @(posedge clk) begin
if (reset_n == 0)
next_out_data <= 0;
else
if (out_ready && out_valid) begin
test_assert ("Data Error",out_data == next_out_data);
next_out_data <= next_out_data + 1;
end
end
// ---------------------------------------------------------------------
//| Main Test
// ---------------------------------------------------------------------
initial begin
test_exactly_full_and_empty();
test_random();
$finish;
end
// ---------------------------------------------------------------------
//| Test exactly full and empty
// ---------------------------------------------------------------------
task test_exactly_full_and_empty;
begin
test_success = 1;
wait (reset_n == 1);
@(posedge clk);
empty_the_fifo();
test_assert ("Empty: should be ready", in_ready == 1);
test_assert ("Empty: should not be valid", out_valid == 0);
@(posedge clk);
in_valid <= 1;
out_ready <= 0;
@(posedge clk);
in_valid <= 0;
@(posedge clk);
in_valid <= 1;
#1;
test_assert ("Almost Empty: should be ready", in_ready == 1);
test_assert ("Almost Empty: should be valid", out_valid == 1);
repeat (DEPTH-2) @(posedge clk);
#1;
test_assert ("Almost Full: should be ready", in_ready == 1);
test_assert ("Almost Full: should be valid", out_valid == 1);
@(posedge clk);
#1;
test_assert ("Full: should be NOT ready", in_ready == 0);
test_assert ("Full: should be valid", out_valid == 1);
in_valid <= 0;
out_ready <= 0;
@(posedge clk);
#1;
test_assert ("Still Full: should be NOT ready", in_ready == 0);
test_assert ("Still Full: should be valid", out_valid == 1);
in_valid <= 0;
out_ready <= 1;
@(posedge clk);
#1;
test_assert ("Almost Full: should be ready", in_ready == 1);
test_assert ("Almost Full 2: should be valid", out_valid == 1);
repeat (DEPTH-2) @(posedge clk);
#1;
test_assert ("Almost Empty: should be ready", in_ready == 1);
test_assert ("Almost Empty 2: should be valid", out_valid == 1);
@(posedge clk);
#1;
test_assert ("Empty: should be ready", in_ready == 1);
test_assert ("Empty 2: should not be valid", out_valid == 0);
endtest("test_exactly_full_and_empty");
end
endtask
// ---------------------------------------------------------------------
//| Test random in & out rates
// ---------------------------------------------------------------------
task test_random;
begin
test_success = 1;
repeat(20 * DEPTH) begin
@(posedge clk);
in_valid <= ($random(23) && 1);
out_ready <= ($random(23) && 1);
end
endtest("test_random");
end
endtask // test_exactly_full_and_empty
// ---------------------------------------------------------------------
//| Empty the FIFO
// ---------------------------------------------------------------------
task empty_the_fifo;
begin
in_valid <= 0;
out_ready <= 1;
repeat (DEPTH) @(posedge clk);
out_ready = 0;
end
endtask
// ---------------------------------------------------------------------
//| AssertFail
// ---------------------------------------------------------------------
task test_assert;
input [256:0] message;
input condition;
begin
if (! condition) begin
$display("(sim)%t: %s",$time, message);
success = 0;
test_success = 0;
end
end
endtask
// ---------------------------------------------------------------------
//| End Test
// ---------------------------------------------------------------------
task endtest;
input [256:0] message;
begin
if (test_success) begin
$display("(sim)%t: %-40s: Pass",$time, message);
end else begin
$display("(sim)%t: %-40s: Fail",$time, message);
end
success = success & test_success;
end
endtask
endmodule
// synthesis translate_on
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q,
usedw
)
;
output empty;
output full;
output [ 31: 0] q;
output [ 3: 0] usedw;
input aclr;
input clock;
input [ 31: 0] data;
input rdreq;
input wrreq;
wire empty;
wire full;
wire [ 31: 0] q;
wire [ 3: 0] usedw;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.usedw (usedw),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.intended_device_family = "STRATIXIV",
single_clock_fifo.lpm_numwords = 16,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 32,
single_clock_fifo.lpm_widthu = 4,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrclk_control_slave_address,
wrclk_control_slave_read,
wrclk_control_slave_write,
wrclk_control_slave_writedata,
wrreq,
// outputs:
empty,
full,
q,
wrclk_control_slave_irq,
wrclk_control_slave_readdata
)
;
output empty;
output full;
output [ 31: 0] q;
output wrclk_control_slave_irq;
output [ 31: 0] wrclk_control_slave_readdata;
input clock;
input [ 31: 0] data;
input rdreq;
input reset_n;
input [ 2: 0] wrclk_control_slave_address;
input wrclk_control_slave_read;
input wrclk_control_slave_write;
input [ 31: 0] wrclk_control_slave_writedata;
input wrreq;
wire empty;
wire full;
wire [ 4: 0] level;
wire overflow;
wire [ 31: 0] q;
wire underflow;
wire [ 3: 0] usedw;
reg wrclk_control_slave_almostempty_n_reg;
wire wrclk_control_slave_almostempty_pulse;
wire wrclk_control_slave_almostempty_signal;
reg [ 4: 0] wrclk_control_slave_almostempty_threshold_register;
reg wrclk_control_slave_almostfull_n_reg;
wire wrclk_control_slave_almostfull_pulse;
wire wrclk_control_slave_almostfull_signal;
reg [ 4: 0] wrclk_control_slave_almostfull_threshold_register;
reg wrclk_control_slave_empty_n_reg;
wire wrclk_control_slave_empty_pulse;
wire wrclk_control_slave_empty_signal;
reg wrclk_control_slave_event_almostempty_q;
wire wrclk_control_slave_event_almostempty_signal;
reg wrclk_control_slave_event_almostfull_q;
wire wrclk_control_slave_event_almostfull_signal;
reg wrclk_control_slave_event_empty_q;
wire wrclk_control_slave_event_empty_signal;
reg wrclk_control_slave_event_full_q;
wire wrclk_control_slave_event_full_signal;
reg wrclk_control_slave_event_overflow_q;
wire wrclk_control_slave_event_overflow_signal;
wire [ 5: 0] wrclk_control_slave_event_register;
reg wrclk_control_slave_event_underflow_q;
wire wrclk_control_slave_event_underflow_signal;
reg wrclk_control_slave_full_n_reg;
wire wrclk_control_slave_full_pulse;
wire wrclk_control_slave_full_signal;
reg [ 5: 0] wrclk_control_slave_ienable_register;
wire wrclk_control_slave_irq;
wire [ 4: 0] wrclk_control_slave_level_register;
wire [ 31: 0] wrclk_control_slave_read_mux;
reg [ 31: 0] wrclk_control_slave_readdata;
reg wrclk_control_slave_status_almostempty_q;
wire wrclk_control_slave_status_almostempty_signal;
reg wrclk_control_slave_status_almostfull_q;
wire wrclk_control_slave_status_almostfull_signal;
reg wrclk_control_slave_status_empty_q;
wire wrclk_control_slave_status_empty_signal;
reg wrclk_control_slave_status_full_q;
wire wrclk_control_slave_status_full_signal;
reg wrclk_control_slave_status_overflow_q;
wire wrclk_control_slave_status_overflow_signal;
wire [ 5: 0] wrclk_control_slave_status_register;
reg wrclk_control_slave_status_underflow_q;
wire wrclk_control_slave_status_underflow_signal;
wire [ 4: 0] wrclk_control_slave_threshold_writedata;
wire wrreq_valid;
//the_scfifo, which is an e_instance
DE4_SOPC_transmit_fifo_single_clock_fifo the_scfifo
(
.aclr (~reset_n),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.usedw (usedw),
.wrreq (wrreq_valid)
);
assign level = {full,
usedw};
assign wrreq_valid = wrreq & ~full;
assign overflow = wrreq & full;
assign underflow = rdreq & empty;
assign wrclk_control_slave_threshold_writedata = (wrclk_control_slave_writedata < 1) ? 1 :
(wrclk_control_slave_writedata > 15) ? 15 :
wrclk_control_slave_writedata[4 : 0];
assign wrclk_control_slave_event_almostfull_signal = wrclk_control_slave_almostfull_pulse;
assign wrclk_control_slave_event_almostempty_signal = wrclk_control_slave_almostempty_pulse;
assign wrclk_control_slave_status_almostfull_signal = wrclk_control_slave_almostfull_signal;
assign wrclk_control_slave_status_almostempty_signal = wrclk_control_slave_almostempty_signal;
assign wrclk_control_slave_event_full_signal = wrclk_control_slave_full_pulse;
assign wrclk_control_slave_event_empty_signal = wrclk_control_slave_empty_pulse;
assign wrclk_control_slave_status_full_signal = wrclk_control_slave_full_signal;
assign wrclk_control_slave_status_empty_signal = wrclk_control_slave_empty_signal;
assign wrclk_control_slave_event_overflow_signal = overflow;
assign wrclk_control_slave_event_underflow_signal = underflow;
assign wrclk_control_slave_status_overflow_signal = overflow;
assign wrclk_control_slave_status_underflow_signal = underflow;
assign wrclk_control_slave_empty_signal = empty;
assign wrclk_control_slave_empty_pulse = wrclk_control_slave_empty_signal & wrclk_control_slave_empty_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_empty_n_reg <= 0;
else
wrclk_control_slave_empty_n_reg <= !wrclk_control_slave_empty_signal;
end
assign wrclk_control_slave_full_signal = full;
assign wrclk_control_slave_full_pulse = wrclk_control_slave_full_signal & wrclk_control_slave_full_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_full_n_reg <= 0;
else
wrclk_control_slave_full_n_reg <= !wrclk_control_slave_full_signal;
end
assign wrclk_control_slave_almostempty_signal = level <= wrclk_control_slave_almostempty_threshold_register;
assign wrclk_control_slave_almostempty_pulse = wrclk_control_slave_almostempty_signal & wrclk_control_slave_almostempty_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostempty_n_reg <= 0;
else
wrclk_control_slave_almostempty_n_reg <= !wrclk_control_slave_almostempty_signal;
end
assign wrclk_control_slave_almostfull_signal = level >= wrclk_control_slave_almostfull_threshold_register;
assign wrclk_control_slave_almostfull_pulse = wrclk_control_slave_almostfull_signal & wrclk_control_slave_almostfull_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostfull_n_reg <= 0;
else
wrclk_control_slave_almostfull_n_reg <= !wrclk_control_slave_almostfull_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostempty_threshold_register <= 1;
else if ((wrclk_control_slave_address == 5) & wrclk_control_slave_write)
wrclk_control_slave_almostempty_threshold_register <= wrclk_control_slave_threshold_writedata;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostfull_threshold_register <= 15;
else if ((wrclk_control_slave_address == 4) & wrclk_control_slave_write)
wrclk_control_slave_almostfull_threshold_register <= wrclk_control_slave_threshold_writedata;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_ienable_register <= 0;
else if ((wrclk_control_slave_address == 3) & wrclk_control_slave_write)
wrclk_control_slave_ienable_register <= wrclk_control_slave_writedata[5 : 0];
end
assign wrclk_control_slave_level_register = level;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_underflow_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[5])
wrclk_control_slave_event_underflow_q <= 0;
else if (wrclk_control_slave_event_underflow_signal)
wrclk_control_slave_event_underflow_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_overflow_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[4])
wrclk_control_slave_event_overflow_q <= 0;
else if (wrclk_control_slave_event_overflow_signal)
wrclk_control_slave_event_overflow_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_almostempty_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[3])
wrclk_control_slave_event_almostempty_q <= 0;
else if (wrclk_control_slave_event_almostempty_signal)
wrclk_control_slave_event_almostempty_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_almostfull_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[2])
wrclk_control_slave_event_almostfull_q <= 0;
else if (wrclk_control_slave_event_almostfull_signal)
wrclk_control_slave_event_almostfull_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_empty_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[1])
wrclk_control_slave_event_empty_q <= 0;
else if (wrclk_control_slave_event_empty_signal)
wrclk_control_slave_event_empty_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_full_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[0])
wrclk_control_slave_event_full_q <= 0;
else if (wrclk_control_slave_event_full_signal)
wrclk_control_slave_event_full_q <= -1;
end
assign wrclk_control_slave_event_register = {wrclk_control_slave_event_underflow_q,
wrclk_control_slave_event_overflow_q,
wrclk_control_slave_event_almostempty_q,
wrclk_control_slave_event_almostfull_q,
wrclk_control_slave_event_empty_q,
wrclk_control_slave_event_full_q};
assign wrclk_control_slave_irq = | (wrclk_control_slave_event_register & wrclk_control_slave_ienable_register);
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_underflow_q <= 0;
else
wrclk_control_slave_status_underflow_q <= wrclk_control_slave_status_underflow_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_overflow_q <= 0;
else
wrclk_control_slave_status_overflow_q <= wrclk_control_slave_status_overflow_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_almostempty_q <= 0;
else
wrclk_control_slave_status_almostempty_q <= wrclk_control_slave_status_almostempty_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_almostfull_q <= 0;
else
wrclk_control_slave_status_almostfull_q <= wrclk_control_slave_status_almostfull_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_empty_q <= 0;
else
wrclk_control_slave_status_empty_q <= wrclk_control_slave_status_empty_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_full_q <= 0;
else
wrclk_control_slave_status_full_q <= wrclk_control_slave_status_full_signal;
end
assign wrclk_control_slave_status_register = {wrclk_control_slave_status_underflow_q,
wrclk_control_slave_status_overflow_q,
wrclk_control_slave_status_almostempty_q,
wrclk_control_slave_status_almostfull_q,
wrclk_control_slave_status_empty_q,
wrclk_control_slave_status_full_q};
assign wrclk_control_slave_read_mux = ({32 {(wrclk_control_slave_address == 0)}} & wrclk_control_slave_level_register) |
({32 {(wrclk_control_slave_address == 1)}} & wrclk_control_slave_status_register) |
({32 {(wrclk_control_slave_address == 2)}} & wrclk_control_slave_event_register) |
({32 {(wrclk_control_slave_address == 3)}} & wrclk_control_slave_ienable_register) |
({32 {(wrclk_control_slave_address == 4)}} & wrclk_control_slave_almostfull_threshold_register) |
({32 {(wrclk_control_slave_address == 5)}} & wrclk_control_slave_almostempty_threshold_register) |
({32 {(~((wrclk_control_slave_address == 0))) && (~((wrclk_control_slave_address == 1))) && (~((wrclk_control_slave_address == 2))) && (~((wrclk_control_slave_address == 3))) && (~((wrclk_control_slave_address == 4))) && (~((wrclk_control_slave_address == 5)))}} & wrclk_control_slave_level_register);
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_readdata <= 0;
else if (wrclk_control_slave_read)
wrclk_control_slave_readdata <= wrclk_control_slave_read_mux;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst (
// inputs:
avalonmm_data,
// outputs:
avalonst_data
)
;
output [ 31: 0] avalonst_data;
input [ 31: 0] avalonmm_data;
wire [ 31: 0] avalonst_data;
assign avalonst_data[31 : 24] = avalonmm_data[7 : 0];
assign avalonst_data[23 : 16] = avalonmm_data[15 : 8];
assign avalonst_data[15 : 8] = avalonmm_data[23 : 16];
assign avalonst_data[7 : 0] = avalonmm_data[31 : 24];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_single_clock_fifo_for_other_info (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
q
)
;
output [ 4: 0] q;
input aclr;
input clock;
input [ 4: 0] data;
input rdreq;
input wrreq;
wire [ 4: 0] q;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.intended_device_family = "STRATIXIV",
single_clock_fifo.lpm_numwords = 16,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 5,
single_clock_fifo.lpm_widthu = 4,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst_other_info (
// inputs:
auto_clr,
avalonmm_other_info,
clock,
enable,
reset_n,
// outputs:
avalonst_other_info
)
;
output [ 4: 0] avalonst_other_info;
input auto_clr;
input [ 31: 0] avalonmm_other_info;
input clock;
input enable;
input reset_n;
wire [ 4: 0] avalonst_other_info;
wire [ 1: 0] empty;
reg [ 1: 0] empty_q;
wire eop;
reg eop_q;
wire error;
reg error_q;
wire sop;
reg sop_q;
assign error = avalonmm_other_info[16];
assign empty = avalonmm_other_info[3 : 2];
assign sop = avalonmm_other_info[0];
assign eop = avalonmm_other_info[1];
assign avalonst_other_info = {error_q,
empty_q,
eop_q,
sop_q};
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
sop_q <= 0;
else if (enable | auto_clr)
if (auto_clr)
sop_q <= 0;
else
sop_q <= sop;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
eop_q <= 0;
else if (enable | auto_clr)
if (auto_clr)
eop_q <= 0;
else
eop_q <= eop;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
empty_q <= 0;
else if (enable)
empty_q <= empty;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
error_q <= 0;
else if (enable)
error_q <= error;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_map_fifo_other_info_to_avalonst (
// inputs:
data_in,
// outputs:
avalonst_source_empty,
avalonst_source_endofpacket,
avalonst_source_error,
avalonst_source_startofpacket
)
;
output [ 1: 0] avalonst_source_empty;
output avalonst_source_endofpacket;
output avalonst_source_error;
output avalonst_source_startofpacket;
input [ 4: 0] data_in;
wire [ 1: 0] avalonst_source_empty;
wire avalonst_source_endofpacket;
wire avalonst_source_error;
wire avalonst_source_startofpacket;
assign {avalonst_source_error,
avalonst_source_empty,
avalonst_source_endofpacket,
avalonst_source_startofpacket} = data_in;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo (
// inputs:
avalonmm_write_slave_address,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
avalonst_source_ready,
reset_n,
wrclk_control_slave_address,
wrclk_control_slave_read,
wrclk_control_slave_write,
wrclk_control_slave_writedata,
wrclock,
// outputs:
avalonmm_write_slave_waitrequest,
avalonst_source_data,
avalonst_source_empty,
avalonst_source_endofpacket,
avalonst_source_error,
avalonst_source_startofpacket,
avalonst_source_valid,
wrclk_control_slave_irq,
wrclk_control_slave_readdata
)
;
output avalonmm_write_slave_waitrequest;
output [ 31: 0] avalonst_source_data;
output [ 1: 0] avalonst_source_empty;
output avalonst_source_endofpacket;
output avalonst_source_error;
output avalonst_source_startofpacket;
output avalonst_source_valid;
output wrclk_control_slave_irq;
output [ 31: 0] wrclk_control_slave_readdata;
input avalonmm_write_slave_address;
input avalonmm_write_slave_write;
input [ 31: 0] avalonmm_write_slave_writedata;
input avalonst_source_ready;
input reset_n;
input [ 2: 0] wrclk_control_slave_address;
input wrclk_control_slave_read;
input wrclk_control_slave_write;
input [ 31: 0] wrclk_control_slave_writedata;
input wrclock;
wire [ 31: 0] avalonmm_map_data_in;
wire avalonmm_write_slave_waitrequest;
wire [ 31: 0] avalonst_map_data_out;
wire [ 4: 0] avalonst_other_info;
wire [ 31: 0] avalonst_source_data;
wire [ 1: 0] avalonst_source_empty;
wire avalonst_source_endofpacket;
wire avalonst_source_error;
wire avalonst_source_startofpacket;
reg avalonst_source_valid;
wire clock;
wire [ 31: 0] data;
wire empty;
wire full;
wire [ 31: 0] q;
wire [ 4: 0] q_i;
wire rdreq;
wire rdreq_i;
wire wrclk_control_slave_irq;
wire [ 31: 0] wrclk_control_slave_readdata;
wire wrreq;
wire wrreq_driver;
//the_scfifo_with_controls, which is an e_instance
DE4_SOPC_transmit_fifo_scfifo_with_controls the_scfifo_with_controls
(
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.reset_n (reset_n),
.wrclk_control_slave_address (wrclk_control_slave_address),
.wrclk_control_slave_irq (wrclk_control_slave_irq),
.wrclk_control_slave_read (wrclk_control_slave_read),
.wrclk_control_slave_readdata (wrclk_control_slave_readdata),
.wrclk_control_slave_write (wrclk_control_slave_write),
.wrclk_control_slave_writedata (wrclk_control_slave_writedata),
.wrreq (wrreq)
);
//in, which is an e_avalon_slave
assign avalonmm_write_slave_waitrequest = full;
//the_map_avalonmm_to_avalonst, which is an e_instance
DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst the_map_avalonmm_to_avalonst
(
.avalonmm_data (avalonmm_map_data_in),
.avalonst_data (avalonst_map_data_out)
);
assign wrreq_driver = (avalonmm_write_slave_address == 0) & avalonmm_write_slave_write;
assign avalonmm_map_data_in = avalonmm_write_slave_writedata;
assign wrreq = wrreq_driver;
assign data = avalonst_map_data_out;
assign clock = wrclock;
//the_scfifo_other_info, which is an e_instance
DE4_SOPC_transmit_fifo_single_clock_fifo_for_other_info the_scfifo_other_info
(
.aclr (~reset_n),
.clock (clock),
.data (avalonst_other_info),
.q (q_i),
.rdreq (rdreq_i),
.wrreq (wrreq_driver & ~full)
);
//the_map_avalonmm_to_avalonst_other_info, which is an e_instance
DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst_other_info the_map_avalonmm_to_avalonst_other_info
(
.auto_clr (wrreq_driver & !full),
.avalonmm_other_info (avalonmm_write_slave_writedata),
.avalonst_other_info (avalonst_other_info),
.clock (clock),
.enable ((avalonmm_write_slave_address == 1) & avalonmm_write_slave_write),
.reset_n (reset_n)
);
//the_map_fifo_other_info_to_avalonst, which is an e_instance
DE4_SOPC_transmit_fifo_map_fifo_other_info_to_avalonst the_map_fifo_other_info_to_avalonst
(
.avalonst_source_empty (avalonst_source_empty),
.avalonst_source_endofpacket (avalonst_source_endofpacket),
.avalonst_source_error (avalonst_source_error),
.avalonst_source_startofpacket (avalonst_source_startofpacket),
.data_in (q_i)
);
assign avalonst_source_data = q;
assign rdreq = !empty & avalonst_source_ready;
assign rdreq_i = rdreq;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
avalonst_source_valid <= 0;
else
avalonst_source_valid <= !empty & avalonst_source_ready;
end
//out, which is an e_atlantic_master
//in_csr, which is an e_avalon_slave
endmodule
|
// megafunction wizard: %Triple Speed Ethernet v11.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// altera_tse_mac_pcs_pma
// ============================================================
// Generated by Triple Speed Ethernet 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2012 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module DE4_SOPC_tse_mac (
ff_tx_data,
ff_tx_eop,
ff_tx_err,
ff_tx_mod,
ff_tx_sop,
ff_tx_wren,
ff_tx_clk,
ff_rx_rdy,
ff_rx_clk,
address,
read,
writedata,
write,
clk,
reset,
mdio_in,
rxp,
ref_clk,
ff_tx_rdy,
ff_rx_data,
ff_rx_dval,
ff_rx_eop,
ff_rx_mod,
ff_rx_sop,
rx_err,
readdata,
waitrequest,
mdio_out,
mdio_oen,
mdc,
led_an,
led_char_err,
led_link,
led_disp_err,
txp,
rx_recovclkout);
input [31:0] ff_tx_data;
input ff_tx_eop;
input ff_tx_err;
input [1:0] ff_tx_mod;
input ff_tx_sop;
input ff_tx_wren;
input ff_tx_clk;
input ff_rx_rdy;
input ff_rx_clk;
input [7:0] address;
input read;
input [31:0] writedata;
input write;
input clk;
input reset;
input mdio_in;
input rxp;
input ref_clk;
output ff_tx_rdy;
output [31:0] ff_rx_data;
output ff_rx_dval;
output ff_rx_eop;
output [1:0] ff_rx_mod;
output ff_rx_sop;
output [5:0] rx_err;
output [31:0] readdata;
output waitrequest;
output mdio_out;
output mdio_oen;
output mdc;
output led_an;
output led_char_err;
output led_link;
output led_disp_err;
output txp;
output rx_recovclkout;
altera_tse_mac_pcs_pma altera_tse_mac_pcs_pma_inst(
.ff_tx_data(ff_tx_data),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_wren(ff_tx_wren),
.ff_tx_clk(ff_tx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_rx_clk(ff_rx_clk),
.address(address),
.read(read),
.writedata(writedata),
.write(write),
.clk(clk),
.reset(reset),
.mdio_in(mdio_in),
.rxp(rxp),
.ref_clk(ref_clk),
.ff_tx_rdy(ff_tx_rdy),
.ff_rx_data(ff_rx_data),
.ff_rx_dval(ff_rx_dval),
.ff_rx_eop(ff_rx_eop),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.rx_err(rx_err),
.readdata(readdata),
.waitrequest(waitrequest),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen),
.mdc(mdc),
.led_an(led_an),
.led_char_err(led_char_err),
.led_link(led_link),
.led_disp_err(led_disp_err),
.txp(txp),
.rx_recovclkout(rx_recovclkout));
defparam
altera_tse_mac_pcs_pma_inst.ENABLE_MAGIC_DETECT = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_MDIO = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_SHIFT16 = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_SUP_ADDR = 0,
altera_tse_mac_pcs_pma_inst.CORE_VERSION = 16'h0b01,
altera_tse_mac_pcs_pma_inst.CRC32GENDELAY = 6,
altera_tse_mac_pcs_pma_inst.MDIO_CLK_DIV = 40,
altera_tse_mac_pcs_pma_inst.ENA_HASH = 0,
altera_tse_mac_pcs_pma_inst.USE_SYNC_RESET = 1,
altera_tse_mac_pcs_pma_inst.STAT_CNT_ENA = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_EXTENDED_STAT_REG = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_HD_LOGIC = 0,
altera_tse_mac_pcs_pma_inst.REDUCED_INTERFACE_ENA = 0,
altera_tse_mac_pcs_pma_inst.CRC32S1L2_EXTERN = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_GMII_LOOPBACK = 0,
altera_tse_mac_pcs_pma_inst.CRC32DWIDTH = 8,
altera_tse_mac_pcs_pma_inst.CUST_VERSION = 0,
altera_tse_mac_pcs_pma_inst.RESET_LEVEL = 8'h01,
altera_tse_mac_pcs_pma_inst.CRC32CHECK16BIT = 8'h00,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_FLOW_CTRL = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_TXADDR_SET = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_RX_VLAN = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_TX_VLAN = 0,
altera_tse_mac_pcs_pma_inst.SYNCHRONIZER_DEPTH = 4,
altera_tse_mac_pcs_pma_inst.EG_FIFO = 2048,
altera_tse_mac_pcs_pma_inst.EG_ADDR = 11,
altera_tse_mac_pcs_pma_inst.ING_FIFO = 2048,
altera_tse_mac_pcs_pma_inst.ENABLE_ENA = 32,
altera_tse_mac_pcs_pma_inst.ING_ADDR = 11,
altera_tse_mac_pcs_pma_inst.RAM_TYPE = "AUTO",
altera_tse_mac_pcs_pma_inst.INSERT_TA = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MACLITE = 0,
altera_tse_mac_pcs_pma_inst.MACLITE_GIGE = 0,
altera_tse_mac_pcs_pma_inst.PHY_IDENTIFIER = 32'h00000000,
altera_tse_mac_pcs_pma_inst.DEV_VERSION = 16'h0b01,
altera_tse_mac_pcs_pma_inst.ENABLE_SGMII = 0,
altera_tse_mac_pcs_pma_inst.DEVICE_FAMILY = "STRATIXIV",
altera_tse_mac_pcs_pma_inst.EXPORT_PWRDN = 0,
altera_tse_mac_pcs_pma_inst.TRANSCEIVER_OPTION = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_ALT_RECONFIG = 0;
endmodule
// =========================================================
// Triple Speed Ethernet Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, Triple Speed Ethernet Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="Triple Speed Ethernet MegaCore Function" version="11.1" build="173" iptb_version="1.3.0 Build 173" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.TSEMVCModel" active_core="altera_tse_mac_pcs_pma" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "atlanticSinkClockRate" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "atlanticSinkClockSource" value="unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "atlanticSourceClockRate" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "atlanticSourceClockSource" value="unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalonSlaveClockRate" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalonSlaveClockSource" value="unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalonStNeighbours" value="unassigned=unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "channel_count" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "core_variation" value="MAC_PCS" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "core_version" value="2817" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "crc32dwidth" value="8" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "crc32gendelay" value="6" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "crc32s1l2_extern" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "cust_version" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "dataBitsPerSymbol" value="8" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "dev_version" value="2817" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "deviceFamily" value="STRATIXIV" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "deviceFamilyName" value="Stratix IV" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "eg_addr" value="11" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "eg_fifo" value="2048" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "ena_hash" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_alt_reconfig" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_clk_sharing" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_ena" value="32" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "enable_fifoless" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_gmii_loopback" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_hd_logic" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mac_flow_ctrl" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mac_txaddr_set" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mac_vlan" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_maclite" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_magic_detect" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_multi_channel" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_pkt_class" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_pma" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_reg_sharing" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_sgmii" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_shift16" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_sup_addr" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_use_internal_fifo" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "export_calblkclk" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "export_pwrdn" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "ext_stat_cnt_ena" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "gigeAdvanceMode" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "ifGMII" value="MII_GMII" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ifPCSuseEmbeddedSerdes" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "ing_addr" value="11" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "ing_fifo" value="2048" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "insert_ta" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "maclite_gige" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "max_channels" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "mdio_clk_div" value="40" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "phy_identifier" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ramType" value="AUTO" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "sopcSystemTopLevelName" value="system" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "starting_channel_number" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "stat_cnt_ena" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "timingAdapterName" value="timingAdapter" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "toolContext" value="SOPC_BUILDER" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "transceiver_type" value="LVDS_IO" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "uiEgFIFOSize" value="2048 x 32 Bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "uiHostClockFrequency" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "uiIngFIFOSize" value="2048 x 32 Bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "uiMACFIFO" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiMACOptions" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiMDIOFreq" value="0.0 MHz" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "uiMIIInterfaceOptions" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiPCSInterface" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiPCSInterfaceOptions" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "useLvds" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "useMAC" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "useMDIO" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "usePCS" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "use_sync_reset" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="VERILOG" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "testbench">
// Retrieval info: <PRIVATE name = "variation_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_name" value="DE4_SOPC" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "output_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="SOPC_BUILDER" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "constraint_file_generator">
// Retrieval info: <PRIVATE name = "variation_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "instance_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "output_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "modelsim_script_generator">
// Retrieval info: <PRIVATE name = "variation_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "instance_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "europa_executor">
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Stratix IV" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="DE4_SOPC_tse_mac.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "modelsim_wave_script_plugin">
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "nativelink">
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="DE4_SOPC_tse_mac_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
// #####################################################################################
// # Copyright (C) 1991-2008 Altera Corporation
// # Any megafunction design, and related netlist (encrypted or decrypted),
// # support information, device programming or simulation file, and any other
// # associated documentation or information provided by Altera or a partner
// # under Altera's Megafunction Partnership Program may be used only
// # to program PLD devices (but not masked PLD devices) from Altera. Any
// # other use of such megafunction design, netlist, support information,
// # device programming or simulation file, or any other related documentation
// # or information is prohibited for any other purpose, including, but not
// # limited to modification, reverse engineering, de-compiling, or use with
// # any other silicon devices, unless such use is explicitly licensed under
// # a separate agreement with Altera or a megafunction partner. Title to the
// # intellectual property, including patents, copyrights, trademarks, trade
// # secrets, or maskworks, embodied in any such megafunction design, netlist,
// # support information, device programming or simulation file, or any other
// # related documentation or information provided by Altera or a megafunction
// # partner, remains with Altera, the megafunction partner, or their respective
// # licensors. No other licenses, including any licenses needed under any third
// # party's intellectual property, are provided herein.
// #####################################################################################
// #####################################################################################
// # Loopback module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Fri Aug 31 13:47:54 2012 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module DE4_SOPC_tse_mac_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_versionRom (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../version.hex";
output [ 31: 0] readdata;
input [ 2: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input debugaccess;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write & debugaccess;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 5,
the_altsyncram.numwords_a = 5,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 3;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "version.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 5,
// the_altsyncram.numwords_a = 5,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Thu Aug 16 11:48:36 BST 2012
//
// Method conflict info:
// Method: asi_stream_in
// Conflict-free: asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
// Conflicts: asi_stream_in
//
// Method: asi_stream_in_ready
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_r
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_g
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_b
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_hsd
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_vsd
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
//
// Ports:
// Name I/O size props
// asi_stream_in_ready O 1
// coe_tpadlcd_mtl_r O 8 reg
// coe_tpadlcd_mtl_g O 8 reg
// coe_tpadlcd_mtl_b O 8 reg
// coe_tpadlcd_mtl_hsd O 1 reg
// coe_tpadlcd_mtl_vsd O 1 reg
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// asi_stream_in_data I 24
// asi_stream_in_valid I 1
// asi_stream_in_startofpacket I 1
// asi_stream_in_endofpacket I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkAvalonStream2MTL_LCD24bit(csi_clockreset_clk,
csi_clockreset_reset_n,
asi_stream_in_data,
asi_stream_in_valid,
asi_stream_in_startofpacket,
asi_stream_in_endofpacket,
asi_stream_in_ready,
coe_tpadlcd_mtl_r,
coe_tpadlcd_mtl_g,
coe_tpadlcd_mtl_b,
coe_tpadlcd_mtl_hsd,
coe_tpadlcd_mtl_vsd);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method asi_stream_in
input [23 : 0] asi_stream_in_data;
input asi_stream_in_valid;
input asi_stream_in_startofpacket;
input asi_stream_in_endofpacket;
// value method asi_stream_in_ready
output asi_stream_in_ready;
// value method coe_tpadlcd_mtl_r
output [7 : 0] coe_tpadlcd_mtl_r;
// value method coe_tpadlcd_mtl_g
output [7 : 0] coe_tpadlcd_mtl_g;
// value method coe_tpadlcd_mtl_b
output [7 : 0] coe_tpadlcd_mtl_b;
// value method coe_tpadlcd_mtl_hsd
output coe_tpadlcd_mtl_hsd;
// value method coe_tpadlcd_mtl_vsd
output coe_tpadlcd_mtl_vsd;
// signals for module outputs
wire [7 : 0] coe_tpadlcd_mtl_b, coe_tpadlcd_mtl_g, coe_tpadlcd_mtl_r;
wire asi_stream_in_ready, coe_tpadlcd_mtl_hsd, coe_tpadlcd_mtl_vsd;
// inlined wires
wire [26 : 0] streamIn_d_dw$wget;
// register lcdtiming_hsd
reg lcdtiming_hsd;
wire lcdtiming_hsd$D_IN, lcdtiming_hsd$EN;
// register lcdtiming_pixel_out
reg [24 : 0] lcdtiming_pixel_out;
wire [24 : 0] lcdtiming_pixel_out$D_IN;
wire lcdtiming_pixel_out$EN;
// register lcdtiming_vsd
reg lcdtiming_vsd;
wire lcdtiming_vsd$D_IN, lcdtiming_vsd$EN;
// register lcdtiming_x
reg [11 : 0] lcdtiming_x;
wire [11 : 0] lcdtiming_x$D_IN;
wire lcdtiming_x$EN;
// register lcdtiming_y
reg [11 : 0] lcdtiming_y;
wire [11 : 0] lcdtiming_y$D_IN;
wire lcdtiming_y$EN;
// ports of submodule lcdtiming_pixel_buf
wire [24 : 0] lcdtiming_pixel_buf$D_IN, lcdtiming_pixel_buf$D_OUT;
wire lcdtiming_pixel_buf$CLR,
lcdtiming_pixel_buf$DEQ,
lcdtiming_pixel_buf$EMPTY_N,
lcdtiming_pixel_buf$ENQ,
lcdtiming_pixel_buf$FULL_N;
// ports of submodule streamIn_f
wire [25 : 0] streamIn_f$D_IN, streamIn_f$D_OUT;
wire streamIn_f$CLR,
streamIn_f$DEQ,
streamIn_f$EMPTY_N,
streamIn_f$ENQ,
streamIn_f$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_connect_stream_to_lcd_interface,
CAN_FIRE_RL_lcdtiming_every_clock_cycle,
CAN_FIRE_RL_streamIn_push_data_into_fifo,
CAN_FIRE_asi_stream_in,
WILL_FIRE_RL_connect_stream_to_lcd_interface,
WILL_FIRE_RL_lcdtiming_every_clock_cycle,
WILL_FIRE_RL_streamIn_push_data_into_fifo,
WILL_FIRE_asi_stream_in;
// remaining internal signals
wire [7 : 0] IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40;
wire NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59,
lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65,
lcdtiming_x_SLT_1009___d66;
// action method asi_stream_in
assign CAN_FIRE_asi_stream_in = 1'd1 ;
assign WILL_FIRE_asi_stream_in = 1'd1 ;
// value method asi_stream_in_ready
assign asi_stream_in_ready = streamIn_f$FULL_N ;
// value method coe_tpadlcd_mtl_r
assign coe_tpadlcd_mtl_r = lcdtiming_pixel_out[24:17] ;
// value method coe_tpadlcd_mtl_g
assign coe_tpadlcd_mtl_g = lcdtiming_pixel_out[16:9] ;
// value method coe_tpadlcd_mtl_b
assign coe_tpadlcd_mtl_b = lcdtiming_pixel_out[8:1] ;
// value method coe_tpadlcd_mtl_hsd
assign coe_tpadlcd_mtl_hsd = lcdtiming_hsd ;
// value method coe_tpadlcd_mtl_vsd
assign coe_tpadlcd_mtl_vsd = lcdtiming_vsd ;
// submodule lcdtiming_pixel_buf
FIFO2 #(.width(32'd25),
.guarded(32'd1)) lcdtiming_pixel_buf(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(lcdtiming_pixel_buf$D_IN),
.ENQ(lcdtiming_pixel_buf$ENQ),
.DEQ(lcdtiming_pixel_buf$DEQ),
.CLR(lcdtiming_pixel_buf$CLR),
.D_OUT(lcdtiming_pixel_buf$D_OUT),
.FULL_N(lcdtiming_pixel_buf$FULL_N),
.EMPTY_N(lcdtiming_pixel_buf$EMPTY_N));
// submodule streamIn_f
FIFOL1 #(.width(32'd26)) streamIn_f(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(streamIn_f$D_IN),
.ENQ(streamIn_f$ENQ),
.DEQ(streamIn_f$DEQ),
.CLR(streamIn_f$CLR),
.D_OUT(streamIn_f$D_OUT),
.FULL_N(streamIn_f$FULL_N),
.EMPTY_N(streamIn_f$EMPTY_N));
// rule RL_connect_stream_to_lcd_interface
assign CAN_FIRE_RL_connect_stream_to_lcd_interface =
streamIn_f$EMPTY_N && lcdtiming_pixel_buf$FULL_N ;
assign WILL_FIRE_RL_connect_stream_to_lcd_interface =
CAN_FIRE_RL_connect_stream_to_lcd_interface ;
// rule RL_lcdtiming_every_clock_cycle
assign CAN_FIRE_RL_lcdtiming_every_clock_cycle = 1'd1 ;
assign WILL_FIRE_RL_lcdtiming_every_clock_cycle = 1'd1 ;
// rule RL_streamIn_push_data_into_fifo
assign CAN_FIRE_RL_streamIn_push_data_into_fifo =
streamIn_f$FULL_N && asi_stream_in_valid &&
streamIn_d_dw$wget[26] ;
assign WILL_FIRE_RL_streamIn_push_data_into_fifo =
CAN_FIRE_RL_streamIn_push_data_into_fifo ;
// inlined wires
assign streamIn_d_dw$wget =
{ 1'd1,
asi_stream_in_data,
asi_stream_in_startofpacket,
asi_stream_in_endofpacket } ;
// register lcdtiming_hsd
assign lcdtiming_hsd$D_IN = (lcdtiming_x ^ 12'h800) >= 12'd2032 ;
assign lcdtiming_hsd$EN = 1'd1 ;
// register lcdtiming_pixel_out
assign lcdtiming_pixel_out$D_IN =
{ IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40,
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 } ;
assign lcdtiming_pixel_out$EN = 1'd1 ;
// register lcdtiming_vsd
assign lcdtiming_vsd$D_IN = (lcdtiming_y ^ 12'h800) >= 12'd2038 ;
assign lcdtiming_vsd$EN = 1'd1 ;
// register lcdtiming_x
assign lcdtiming_x$D_IN =
lcdtiming_x_SLT_1009___d66 ? lcdtiming_x + 12'd1 : 12'd4050 ;
assign lcdtiming_x$EN = 1'd1 ;
// register lcdtiming_y
assign lcdtiming_y$D_IN =
((lcdtiming_y ^ 12'h800) < 12'd2549) ?
lcdtiming_y + 12'd1 :
12'd4073 ;
assign lcdtiming_y$EN = !lcdtiming_x_SLT_1009___d66 ;
// submodule lcdtiming_pixel_buf
assign lcdtiming_pixel_buf$D_IN = streamIn_f$D_OUT[25:1] ;
assign lcdtiming_pixel_buf$ENQ =
CAN_FIRE_RL_connect_stream_to_lcd_interface ;
assign lcdtiming_pixel_buf$DEQ =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 &&
lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ;
assign lcdtiming_pixel_buf$CLR = 1'b0 ;
// submodule streamIn_f
assign streamIn_f$D_IN = streamIn_d_dw$wget[25:0] ;
assign streamIn_f$ENQ = CAN_FIRE_RL_streamIn_push_data_into_fifo ;
assign streamIn_f$DEQ = CAN_FIRE_RL_connect_stream_to_lcd_interface ;
assign streamIn_f$CLR = 1'b0 ;
// remaining internal signals
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[24:17] :
8'd255) :
8'd0 ;
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[16:9] :
8'd0) :
8'd0 ;
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[8:1] :
8'd0) :
8'd0 ;
assign NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 =
!lcdtiming_y[11] && (lcdtiming_y ^ 12'h800) < 12'd2528 &&
!lcdtiming_x[11] &&
(lcdtiming_x ^ 12'h800) < 12'd2848 ;
assign lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 =
lcdtiming_pixel_buf$EMPTY_N &&
lcdtiming_pixel_buf$D_OUT[0] ==
(lcdtiming_x == 12'd0 && lcdtiming_y == 12'd0) ;
assign lcdtiming_x_SLT_1009___d66 = (lcdtiming_x ^ 12'h800) < 12'd3057 ;
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
lcdtiming_x <= `BSV_ASSIGNMENT_DELAY 12'd4050;
lcdtiming_y <= `BSV_ASSIGNMENT_DELAY 12'd4073;
end
else
begin
if (lcdtiming_x$EN)
lcdtiming_x <= `BSV_ASSIGNMENT_DELAY lcdtiming_x$D_IN;
if (lcdtiming_y$EN)
lcdtiming_y <= `BSV_ASSIGNMENT_DELAY lcdtiming_y$D_IN;
end
if (lcdtiming_hsd$EN)
lcdtiming_hsd <= `BSV_ASSIGNMENT_DELAY lcdtiming_hsd$D_IN;
if (lcdtiming_pixel_out$EN)
lcdtiming_pixel_out <= `BSV_ASSIGNMENT_DELAY lcdtiming_pixel_out$D_IN;
if (lcdtiming_vsd$EN)
lcdtiming_vsd <= `BSV_ASSIGNMENT_DELAY lcdtiming_vsd$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
lcdtiming_hsd = 1'h0;
lcdtiming_pixel_out = 25'h0AAAAAA;
lcdtiming_vsd = 1'h0;
lcdtiming_x = 12'hAAA;
lcdtiming_y = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkAvalonStream2MTL_LCD24bit
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Thu Aug 16 15:00:30 BST 2012
//
// Method conflict info:
// Method: avs_s0
// Conflict-free: avs_s0_readdata,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced before (restricted): avs_s0_waitrequest
// Conflicts: avs_s0
//
// Method: avs_s0_readdata
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: avs_s0_waitrequest
// Conflict-free: avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): avs_s0
//
// Method: aso_stream_out_data
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out_valid
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced before (restricted): aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket
// Conflicts: aso_stream_out
//
// Method: aso_stream_out_startofpacket
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out_endofpacket
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: coe_ssram_adv
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_ssram_bwa_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_bwb_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_ce_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_cke_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_ssram_oe_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_we_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_a
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_d_out
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_d
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_cke_n,
// coe_flash_clk,
// coe_touch
// Sequenced before (restricted): coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_oe_n,
// coe_flash_we_n
// Conflicts: coe_fsm_d
//
// Method: coe_fsm_dout_req
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_adv_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_ce_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_clk
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_flash_oe_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_we_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_touch
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n
// Conflicts: coe_touch
//
//
// Ports:
// Name I/O size props
// avs_s0_readdata O 32
// avs_s0_waitrequest O 1
// aso_stream_out_data O 24
// aso_stream_out_valid O 1
// aso_stream_out_startofpacket O 1
// aso_stream_out_endofpacket O 1
// coe_ssram_adv O 1 const
// coe_ssram_bwa_n O 1
// coe_ssram_bwb_n O 1
// coe_ssram_ce_n O 1
// coe_ssram_cke_n O 1 const
// coe_ssram_oe_n O 1
// coe_ssram_we_n O 1
// coe_fsm_a O 25
// coe_fsm_d_out O 16
// coe_fsm_dout_req O 1
// coe_flash_adv_n O 1
// coe_flash_ce_n O 1
// coe_flash_clk O 1 const
// coe_flash_oe_n O 1
// coe_flash_we_n O 1
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// avs_s0_address I 25 reg
// avs_s0_writedata I 32 reg
// avs_s0_write I 1
// avs_s0_read I 1
// avs_s0_byteenable I 4 reg
// aso_stream_out_ready I 1
// coe_fsm_d_in I 16
// coe_touch_x1 I 10
// coe_touch_y1 I 9
// coe_touch_x2 I 10
// coe_touch_y2 I 9
// coe_touch_count_gesture I 10
// coe_touch_touch_valid I 1
//
// Combinational paths from inputs to outputs:
// (avs_s0_write, avs_s0_read) -> avs_s0_waitrequest
// aso_stream_out_ready -> aso_stream_out_data
// aso_stream_out_ready -> aso_stream_out_valid
// aso_stream_out_ready -> aso_stream_out_startofpacket
// aso_stream_out_ready -> aso_stream_out_endofpacket
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkMTL_Framebuffer_Flash(csi_clockreset_clk,
csi_clockreset_reset_n,
avs_s0_address,
avs_s0_writedata,
avs_s0_write,
avs_s0_read,
avs_s0_byteenable,
avs_s0_readdata,
avs_s0_waitrequest,
aso_stream_out_data,
aso_stream_out_valid,
aso_stream_out_ready,
aso_stream_out_startofpacket,
aso_stream_out_endofpacket,
coe_ssram_adv,
coe_ssram_bwa_n,
coe_ssram_bwb_n,
coe_ssram_ce_n,
coe_ssram_cke_n,
coe_ssram_oe_n,
coe_ssram_we_n,
coe_fsm_a,
coe_fsm_d_out,
coe_fsm_d_in,
coe_fsm_dout_req,
coe_flash_adv_n,
coe_flash_ce_n,
coe_flash_clk,
coe_flash_oe_n,
coe_flash_we_n,
coe_touch_x1,
coe_touch_y1,
coe_touch_x2,
coe_touch_y2,
coe_touch_count_gesture,
coe_touch_touch_valid);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method avs_s0
input [24 : 0] avs_s0_address;
input [31 : 0] avs_s0_writedata;
input avs_s0_write;
input avs_s0_read;
input [3 : 0] avs_s0_byteenable;
// value method avs_s0_readdata
output [31 : 0] avs_s0_readdata;
// value method avs_s0_waitrequest
output avs_s0_waitrequest;
// value method aso_stream_out_data
output [23 : 0] aso_stream_out_data;
// value method aso_stream_out_valid
output aso_stream_out_valid;
// action method aso_stream_out
input aso_stream_out_ready;
// value method aso_stream_out_startofpacket
output aso_stream_out_startofpacket;
// value method aso_stream_out_endofpacket
output aso_stream_out_endofpacket;
// value method coe_ssram_adv
output coe_ssram_adv;
// value method coe_ssram_bwa_n
output coe_ssram_bwa_n;
// value method coe_ssram_bwb_n
output coe_ssram_bwb_n;
// value method coe_ssram_ce_n
output coe_ssram_ce_n;
// value method coe_ssram_cke_n
output coe_ssram_cke_n;
// value method coe_ssram_oe_n
output coe_ssram_oe_n;
// value method coe_ssram_we_n
output coe_ssram_we_n;
// value method coe_fsm_a
output [24 : 0] coe_fsm_a;
// value method coe_fsm_d_out
output [15 : 0] coe_fsm_d_out;
// action method coe_fsm_d
input [15 : 0] coe_fsm_d_in;
// value method coe_fsm_dout_req
output coe_fsm_dout_req;
// value method coe_flash_adv_n
output coe_flash_adv_n;
// value method coe_flash_ce_n
output coe_flash_ce_n;
// value method coe_flash_clk
output coe_flash_clk;
// value method coe_flash_oe_n
output coe_flash_oe_n;
// value method coe_flash_we_n
output coe_flash_we_n;
// action method coe_touch
input [9 : 0] coe_touch_x1;
input [8 : 0] coe_touch_y1;
input [9 : 0] coe_touch_x2;
input [8 : 0] coe_touch_y2;
input [9 : 0] coe_touch_count_gesture;
input coe_touch_touch_valid;
// signals for module outputs
wire [31 : 0] avs_s0_readdata;
wire [24 : 0] coe_fsm_a;
wire [23 : 0] aso_stream_out_data;
wire [15 : 0] coe_fsm_d_out;
wire aso_stream_out_endofpacket,
aso_stream_out_startofpacket,
aso_stream_out_valid,
avs_s0_waitrequest,
coe_flash_adv_n,
coe_flash_ce_n,
coe_flash_clk,
coe_flash_oe_n,
coe_flash_we_n,
coe_fsm_dout_req,
coe_ssram_adv,
coe_ssram_bwa_n,
coe_ssram_bwb_n,
coe_ssram_ce_n,
coe_ssram_cke_n,
coe_ssram_oe_n,
coe_ssram_we_n;
// inlined wires
wire [24 : 0] pixel_engine_lcd_stream_data_dw$wget;
wire [15 : 0] mem_fsm_dout_dw$wget;
wire avalon_slave_avalonwait$wget,
avalon_slave_avalonwait_end_read$whas,
avalon_slave_avalonwait_end_write$whas,
mem_flash_ce_n_dw$wget,
mem_flash_we_n_dw$wget,
mem_fsm_a_w$whas,
mem_fsm_dout_dw$whas,
mem_fsm_dout_req_dw$wget,
mem_ssram_ce_pw$whas;
// register avalon_slave_ignore_further_requests
reg avalon_slave_ignore_further_requests;
wire avalon_slave_ignore_further_requests$D_IN,
avalon_slave_ignore_further_requests$EN;
// register mem_flash_timer
reg [3 : 0] mem_flash_timer;
wire [3 : 0] mem_flash_timer$D_IN;
wire mem_flash_timer$EN;
// register pixel_engine_addr
reg [24 : 0] pixel_engine_addr;
wire [24 : 0] pixel_engine_addr$D_IN;
wire pixel_engine_addr$EN;
// register pixel_engine_char_addr
reg [24 : 0] pixel_engine_char_addr;
wire [24 : 0] pixel_engine_char_addr$D_IN;
wire pixel_engine_char_addr$EN;
// register pixel_engine_char_base
reg [24 : 0] pixel_engine_char_base;
wire [24 : 0] pixel_engine_char_base$D_IN;
wire pixel_engine_char_base$EN;
// register pixel_engine_char_ctr
reg pixel_engine_char_ctr;
wire pixel_engine_char_ctr$D_IN, pixel_engine_char_ctr$EN;
// register pixel_engine_char_end
reg [24 : 0] pixel_engine_char_end;
wire [24 : 0] pixel_engine_char_end$D_IN;
wire pixel_engine_char_end$EN;
// register pixel_engine_char_x_pos
reg [2 : 0] pixel_engine_char_x_pos;
wire [2 : 0] pixel_engine_char_x_pos$D_IN;
wire pixel_engine_char_x_pos$EN;
// register pixel_engine_char_x_two_char
reg [5 : 0] pixel_engine_char_x_two_char;
wire [5 : 0] pixel_engine_char_x_two_char$D_IN;
wire pixel_engine_char_x_two_char$EN;
// register pixel_engine_char_y
reg [24 : 0] pixel_engine_char_y;
wire [24 : 0] pixel_engine_char_y$D_IN;
wire pixel_engine_char_y$EN;
// register pixel_engine_cursor_pos
reg [15 : 0] pixel_engine_cursor_pos;
wire [15 : 0] pixel_engine_cursor_pos$D_IN;
wire pixel_engine_cursor_pos$EN;
// register pixel_engine_fb_blend
reg [31 : 0] pixel_engine_fb_blend;
wire [31 : 0] pixel_engine_fb_blend$D_IN;
wire pixel_engine_fb_blend$EN;
// register pixel_engine_flash_col
reg [5 : 0] pixel_engine_flash_col;
wire [5 : 0] pixel_engine_flash_col$D_IN;
wire pixel_engine_flash_col$EN;
// register pixel_engine_font_y
reg [3 : 0] pixel_engine_font_y;
wire [3 : 0] pixel_engine_font_y$D_IN;
wire pixel_engine_font_y$EN;
// register prev_touch_info
reg [47 : 0] prev_touch_info;
wire [47 : 0] prev_touch_info$D_IN;
wire prev_touch_info$EN;
// ports of submodule avalon_control_reg_resp
wire [32 : 0] avalon_control_reg_resp$D_IN, avalon_control_reg_resp$D_OUT;
wire avalon_control_reg_resp$CLR,
avalon_control_reg_resp$DEQ,
avalon_control_reg_resp$EMPTY_N,
avalon_control_reg_resp$ENQ,
avalon_control_reg_resp$FULL_N;
// ports of submodule avalon_mem_resp
wire [32 : 0] avalon_mem_resp$D_IN, avalon_mem_resp$D_OUT;
wire avalon_mem_resp$CLR,
avalon_mem_resp$DEQ,
avalon_mem_resp$EMPTY_N,
avalon_mem_resp$ENQ,
avalon_mem_resp$FULL_N;
// ports of submodule avalon_req
wire [61 : 0] avalon_req$D_IN, avalon_req$D_OUT;
wire avalon_req$CLR,
avalon_req$DEQ,
avalon_req$EMPTY_N,
avalon_req$ENQ,
avalon_req$FULL_N;
// ports of submodule avalon_slave_outbuf
wire [62 : 0] avalon_slave_outbuf$D_IN, avalon_slave_outbuf$D_OUT;
wire avalon_slave_outbuf$CLR,
avalon_slave_outbuf$DEQ,
avalon_slave_outbuf$EMPTY_N,
avalon_slave_outbuf$ENQ,
avalon_slave_outbuf$FULL_N;
// ports of submodule lower_16b_returned
wire [16 : 0] lower_16b_returned$D_IN, lower_16b_returned$D_OUT;
wire lower_16b_returned$CLR,
lower_16b_returned$DEQ,
lower_16b_returned$EMPTY_N,
lower_16b_returned$ENQ;
// ports of submodule mem_pipe0
wire [16 : 0] mem_pipe0$D_IN, mem_pipe0$D_OUT;
wire mem_pipe0$CLR,
mem_pipe0$DEQ,
mem_pipe0$EMPTY_N,
mem_pipe0$ENQ,
mem_pipe0$FULL_N;
// ports of submodule mem_pipe1
wire [16 : 0] mem_pipe1$D_IN, mem_pipe1$D_OUT;
wire mem_pipe1$CLR,
mem_pipe1$DEQ,
mem_pipe1$EMPTY_N,
mem_pipe1$ENQ,
mem_pipe1$FULL_N;
// ports of submodule mem_pipe2
wire [16 : 0] mem_pipe2$D_IN, mem_pipe2$D_OUT;
wire mem_pipe2$CLR,
mem_pipe2$DEQ,
mem_pipe2$EMPTY_N,
mem_pipe2$ENQ,
mem_pipe2$FULL_N;
// ports of submodule mem_req
wire [44 : 0] mem_req$D_IN, mem_req$D_OUT;
wire mem_req$CLR, mem_req$DEQ, mem_req$EMPTY_N, mem_req$ENQ, mem_req$FULL_N;
// ports of submodule mem_resp
wire [16 : 0] mem_resp$D_IN, mem_resp$D_OUT;
wire mem_resp$CLR,
mem_resp$DEQ,
mem_resp$EMPTY_N,
mem_resp$ENQ,
mem_resp$FULL_N;
// ports of submodule mem_upper_16b_request
wire [44 : 0] mem_upper_16b_request$D_IN, mem_upper_16b_request$D_OUT;
wire mem_upper_16b_request$CLR,
mem_upper_16b_request$DEQ,
mem_upper_16b_request$EMPTY_N,
mem_upper_16b_request$ENQ;
// ports of submodule pixel_engine_char_colour
wire [9 : 0] pixel_engine_char_colour$D_IN, pixel_engine_char_colour$D_OUT;
wire pixel_engine_char_colour$CLR,
pixel_engine_char_colour$DEQ,
pixel_engine_char_colour$EMPTY_N,
pixel_engine_char_colour$ENQ,
pixel_engine_char_colour$FULL_N;
// ports of submodule pixel_engine_char_pixel
wire [9 : 0] pixel_engine_char_pixel$D_IN, pixel_engine_char_pixel$D_OUT;
wire pixel_engine_char_pixel$CLR,
pixel_engine_char_pixel$DEQ,
pixel_engine_char_pixel$EMPTY_N,
pixel_engine_char_pixel$ENQ,
pixel_engine_char_pixel$FULL_N;
// ports of submodule pixel_engine_char_pos
wire [15 : 0] pixel_engine_char_pos$D_IN, pixel_engine_char_pos$D_OUT;
wire pixel_engine_char_pos$CLR,
pixel_engine_char_pos$DEQ,
pixel_engine_char_pos$EMPTY_N,
pixel_engine_char_pos$ENQ,
pixel_engine_char_pos$FULL_N;
// ports of submodule pixel_engine_chars_read
wire pixel_engine_chars_read$CLR,
pixel_engine_chars_read$DEQ,
pixel_engine_chars_read$D_IN,
pixel_engine_chars_read$D_OUT,
pixel_engine_chars_read$EMPTY_N,
pixel_engine_chars_read$ENQ,
pixel_engine_chars_read$FULL_N;
// ports of submodule pixel_engine_font_y_pos
wire [3 : 0] pixel_engine_font_y_pos$D_IN, pixel_engine_font_y_pos$D_OUT;
wire pixel_engine_font_y_pos$CLR,
pixel_engine_font_y_pos$DEQ,
pixel_engine_font_y_pos$EMPTY_N,
pixel_engine_font_y_pos$ENQ,
pixel_engine_font_y_pos$FULL_N;
// ports of submodule pixel_engine_fontbits
wire [7 : 0] pixel_engine_fontbits$D_IN, pixel_engine_fontbits$D_OUT;
wire pixel_engine_fontbits$CLR,
pixel_engine_fontbits$DEQ,
pixel_engine_fontbits$EMPTY_N,
pixel_engine_fontbits$ENQ,
pixel_engine_fontbits$FULL_N;
// ports of submodule pixel_engine_fontrom_rom
wire [11 : 0] pixel_engine_fontrom_rom$v_addr;
wire [7 : 0] pixel_engine_fontrom_rom$v_data;
wire pixel_engine_fontrom_rom$v_en;
// ports of submodule pixel_engine_fontrom_seq_fifo
wire pixel_engine_fontrom_seq_fifo$CLR,
pixel_engine_fontrom_seq_fifo$DEQ,
pixel_engine_fontrom_seq_fifo$D_IN,
pixel_engine_fontrom_seq_fifo$EMPTY_N,
pixel_engine_fontrom_seq_fifo$ENQ,
pixel_engine_fontrom_seq_fifo$FULL_N;
// ports of submodule pixel_engine_pixpos
wire [1 : 0] pixel_engine_pixpos$D_IN, pixel_engine_pixpos$D_OUT;
wire pixel_engine_pixpos$CLR,
pixel_engine_pixpos$DEQ,
pixel_engine_pixpos$EMPTY_N,
pixel_engine_pixpos$ENQ,
pixel_engine_pixpos$FULL_N;
// ports of submodule pixel_engine_req
wire [61 : 0] pixel_engine_req$D_IN, pixel_engine_req$D_OUT;
wire pixel_engine_req$CLR,
pixel_engine_req$DEQ,
pixel_engine_req$EMPTY_N,
pixel_engine_req$ENQ,
pixel_engine_req$FULL_N;
// ports of submodule pixel_engine_ssram_req
wire [61 : 0] pixel_engine_ssram_req$D_IN, pixel_engine_ssram_req$D_OUT;
wire pixel_engine_ssram_req$CLR,
pixel_engine_ssram_req$DEQ,
pixel_engine_ssram_req$EMPTY_N,
pixel_engine_ssram_req$ENQ,
pixel_engine_ssram_req$FULL_N;
// ports of submodule pixel_engine_ssram_resp
wire [31 : 0] pixel_engine_ssram_resp$D_IN, pixel_engine_ssram_resp$D_OUT;
wire pixel_engine_ssram_resp$CLR,
pixel_engine_ssram_resp$DEQ,
pixel_engine_ssram_resp$EMPTY_N,
pixel_engine_ssram_resp$ENQ,
pixel_engine_ssram_resp$FULL_N;
// ports of submodule pixel_engine_two_chars
wire [31 : 0] pixel_engine_two_chars$D_IN, pixel_engine_two_chars$D_OUT;
wire pixel_engine_two_chars$CLR,
pixel_engine_two_chars$DEQ,
pixel_engine_two_chars$EMPTY_N,
pixel_engine_two_chars$ENQ,
pixel_engine_two_chars$FULL_N;
// ports of submodule response_for_avalon
wire response_for_avalon$CLR,
response_for_avalon$DEQ,
response_for_avalon$D_IN,
response_for_avalon$D_OUT,
response_for_avalon$EMPTY_N,
response_for_avalon$ENQ,
response_for_avalon$FULL_N;
// ports of submodule touch
wire [47 : 0] touch$D_IN, touch$D_OUT;
wire touch$CLR, touch$DEQ, touch$EMPTY_N, touch$ENQ, touch$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_arbitrate_requests,
CAN_FIRE_RL_avalon_request_splitter,
CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests,
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests,
CAN_FIRE_RL_avalon_slave_wire_up_avalonwait,
CAN_FIRE_RL_forward_upper_bytes,
CAN_FIRE_RL_mem_forward_requests_flash,
CAN_FIRE_RL_mem_forward_requests_ssram,
CAN_FIRE_RL_mem_pipe_stage_0,
CAN_FIRE_RL_mem_pipe_stage_1,
CAN_FIRE_RL_mem_pipe_stage_2,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_pixel_engine_buffer_characters_read,
CAN_FIRE_RL_pixel_engine_char_pixels,
CAN_FIRE_RL_pixel_engine_demux_two_chars,
CAN_FIRE_RL_pixel_engine_forward_pixel_values,
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut,
CAN_FIRE_RL_pixel_engine_request_char_values,
CAN_FIRE_RL_pixel_engine_request_pixel_values,
CAN_FIRE_RL_receive_mem_responses,
CAN_FIRE_RL_return_control_register_response,
CAN_FIRE_RL_return_mem_response,
CAN_FIRE_aso_stream_out,
CAN_FIRE_avs_s0,
CAN_FIRE_coe_fsm_d,
CAN_FIRE_coe_touch,
WILL_FIRE_RL_arbitrate_requests,
WILL_FIRE_RL_avalon_request_splitter,
WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests,
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests,
WILL_FIRE_RL_avalon_slave_wire_up_avalonwait,
WILL_FIRE_RL_forward_upper_bytes,
WILL_FIRE_RL_mem_forward_requests_flash,
WILL_FIRE_RL_mem_forward_requests_ssram,
WILL_FIRE_RL_mem_pipe_stage_0,
WILL_FIRE_RL_mem_pipe_stage_1,
WILL_FIRE_RL_mem_pipe_stage_2,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_pixel_engine_buffer_characters_read,
WILL_FIRE_RL_pixel_engine_char_pixels,
WILL_FIRE_RL_pixel_engine_demux_two_chars,
WILL_FIRE_RL_pixel_engine_forward_pixel_values,
WILL_FIRE_RL_pixel_engine_mkConnectionGetPut,
WILL_FIRE_RL_pixel_engine_request_char_values,
WILL_FIRE_RL_pixel_engine_request_pixel_values,
WILL_FIRE_RL_receive_mem_responses,
WILL_FIRE_RL_return_control_register_response,
WILL_FIRE_RL_return_mem_response,
WILL_FIRE_aso_stream_out,
WILL_FIRE_avs_s0,
WILL_FIRE_coe_fsm_d,
WILL_FIRE_coe_touch;
// inputs to muxes for submodule ports
wire [61 : 0] MUX_pixel_engine_ssram_req$enq_1__VAL_1,
MUX_pixel_engine_ssram_req$enq_1__VAL_2;
wire [44 : 0] MUX_mem_req$enq_1__VAL_1;
wire [16 : 0] MUX_mem_resp$enq_1__VAL_1, MUX_mem_resp$enq_1__VAL_2;
wire [15 : 0] MUX_mem_fsm_dout_dw$wset_1__VAL_2;
wire MUX_avalon_slave_datareturned$wset_1__SEL_1,
MUX_mem_fsm_a_w$wset_1__SEL_1,
MUX_mem_resp$enq_1__SEL_1;
// remaining internal signals
reg [23 : 0] IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654,
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652;
wire [49 : 0] IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55;
wire [31 : 0] IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669,
b__h14135;
wire [25 : 0] x__h13071, x_addr__h13123;
wire [24 : 0] IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645,
next_addr__h3065,
next_char_y___2__h3016,
next_char_y__h2903,
x1_avValue_addr__h12990,
x__h3050,
y__h3053;
wire [8 : 0] minus__h3867,
minus__h4723,
minus__h5121,
minus__h5335,
minus__h5712,
minus__h5926,
sum__h3311,
sum__h3767,
sum__h4866,
sum__h5021,
sum__h5457,
sum__h5612;
wire [7 : 0] a__h3765,
a__h3866,
a__h5019,
a__h5120,
a__h5610,
a__h5711,
b__h3310,
b__h3766,
b__h4865,
b__h5020,
b__h5456,
b__h5611,
bitmap_col_chan_b__h3300,
bitmap_col_chan_g__h3299,
bitmap_col_chan_r__h3298,
char__h6798,
char_alpha__h3227,
x__h2840,
x__h7183;
wire [5 : 0] next_x_two_char_addr__h2897, next_x_two_char_addr__h2901;
wire [3 : 0] IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668,
next_font_y___2__h2969;
wire [2 : 0] x__h7767;
wire [1 : 0] IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710;
wire IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611,
mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345,
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706,
response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529,
x__h7731;
// action method avs_s0
assign CAN_FIRE_avs_s0 = 1'd1 ;
assign WILL_FIRE_avs_s0 = 1'd1 ;
// value method avs_s0_readdata
assign avs_s0_readdata =
avalon_slave_avalonwait_end_read$whas ?
b__h14135 :
32'hDEADDEAD ;
// value method avs_s0_waitrequest
assign avs_s0_waitrequest =
avs_s0_read && !avalon_slave_avalonwait_end_read$whas ||
avs_s0_write && !avalon_slave_avalonwait_end_write$whas ;
// value method aso_stream_out_data
assign aso_stream_out_data =
(!CAN_FIRE_RL_pixel_engine_forward_pixel_values ||
!pixel_engine_lcd_stream_data_dw$wget[24]) ?
24'd0 :
pixel_engine_lcd_stream_data_dw$wget[23:0] ;
// value method aso_stream_out_valid
assign aso_stream_out_valid =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_lcd_stream_data_dw$wget[24] ;
// action method aso_stream_out
assign CAN_FIRE_aso_stream_out = 1'd1 ;
assign WILL_FIRE_aso_stream_out = 1'd1 ;
// value method aso_stream_out_startofpacket
assign aso_stream_out_startofpacket =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[1] ;
// value method aso_stream_out_endofpacket
assign aso_stream_out_endofpacket =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[0] ;
// value method coe_ssram_adv
assign coe_ssram_adv = 1'd0 ;
// value method coe_ssram_bwa_n
assign coe_ssram_bwa_n =
!IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710[0] ;
// value method coe_ssram_bwb_n
assign coe_ssram_bwb_n =
!IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710[1] ;
// value method coe_ssram_ce_n
assign coe_ssram_ce_n = !mem_ssram_ce_pw$whas ;
// value method coe_ssram_cke_n
assign coe_ssram_cke_n = 1'd0 ;
// value method coe_ssram_oe_n
assign coe_ssram_oe_n = mem_fsm_dout_dw$whas && mem_fsm_dout_req_dw$wget ;
// value method coe_ssram_we_n
assign coe_ssram_we_n =
!CAN_FIRE_RL_mem_forward_requests_ssram || !mem_req$D_OUT[44] ;
// value method coe_fsm_a
assign coe_fsm_a = mem_fsm_a_w$whas ? mem_req$D_OUT[40:16] : 25'd0 ;
// value method coe_fsm_d_out
assign coe_fsm_d_out =
mem_fsm_dout_dw$whas ? mem_fsm_dout_dw$wget : 16'hDEAD ;
// action method coe_fsm_d
assign CAN_FIRE_coe_fsm_d = 1'd1 ;
assign WILL_FIRE_coe_fsm_d = 1'd1 ;
// value method coe_fsm_dout_req
assign coe_fsm_dout_req = mem_fsm_dout_dw$whas && mem_fsm_dout_req_dw$wget ;
// value method coe_flash_adv_n
assign coe_flash_adv_n = !MUX_mem_fsm_a_w$wset_1__SEL_1 ;
// value method coe_flash_ce_n
assign coe_flash_ce_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_flash_ce_n_dw$wget ;
// value method coe_flash_clk
assign coe_flash_clk = 1'd0 ;
// value method coe_flash_oe_n
assign coe_flash_oe_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_req$D_OUT[44] ;
// value method coe_flash_we_n
assign coe_flash_we_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_flash_we_n_dw$wget ;
// action method coe_touch
assign CAN_FIRE_coe_touch = 1'd1 ;
assign WILL_FIRE_coe_touch = 1'd1 ;
// submodule avalon_control_reg_resp
FIFO1 #(.width(32'd33),
.guarded(32'd1)) avalon_control_reg_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_control_reg_resp$D_IN),
.ENQ(avalon_control_reg_resp$ENQ),
.DEQ(avalon_control_reg_resp$DEQ),
.CLR(avalon_control_reg_resp$CLR),
.D_OUT(avalon_control_reg_resp$D_OUT),
.FULL_N(avalon_control_reg_resp$FULL_N),
.EMPTY_N(avalon_control_reg_resp$EMPTY_N));
// submodule avalon_mem_resp
FIFO1 #(.width(32'd33),
.guarded(32'd1)) avalon_mem_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_mem_resp$D_IN),
.ENQ(avalon_mem_resp$ENQ),
.DEQ(avalon_mem_resp$DEQ),
.CLR(avalon_mem_resp$CLR),
.D_OUT(avalon_mem_resp$D_OUT),
.FULL_N(avalon_mem_resp$FULL_N),
.EMPTY_N(avalon_mem_resp$EMPTY_N));
// submodule avalon_req
FIFO2 #(.width(32'd62),
.guarded(32'd1)) avalon_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_req$D_IN),
.ENQ(avalon_req$ENQ),
.DEQ(avalon_req$DEQ),
.CLR(avalon_req$CLR),
.D_OUT(avalon_req$D_OUT),
.FULL_N(avalon_req$FULL_N),
.EMPTY_N(avalon_req$EMPTY_N));
// submodule avalon_slave_outbuf
FIFO2 #(.width(32'd63),
.guarded(32'd1)) avalon_slave_outbuf(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_slave_outbuf$D_IN),
.ENQ(avalon_slave_outbuf$ENQ),
.DEQ(avalon_slave_outbuf$DEQ),
.CLR(avalon_slave_outbuf$CLR),
.D_OUT(avalon_slave_outbuf$D_OUT),
.FULL_N(avalon_slave_outbuf$FULL_N),
.EMPTY_N(avalon_slave_outbuf$EMPTY_N));
// submodule lower_16b_returned
FIFO2 #(.width(32'd17),
.guarded(32'd0)) lower_16b_returned(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(lower_16b_returned$D_IN),
.ENQ(lower_16b_returned$ENQ),
.DEQ(lower_16b_returned$DEQ),
.CLR(lower_16b_returned$CLR),
.D_OUT(lower_16b_returned$D_OUT),
.FULL_N(),
.EMPTY_N(lower_16b_returned$EMPTY_N));
// submodule mem_pipe0
FIFOL1 #(.width(32'd17)) mem_pipe0(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe0$D_IN),
.ENQ(mem_pipe0$ENQ),
.DEQ(mem_pipe0$DEQ),
.CLR(mem_pipe0$CLR),
.D_OUT(mem_pipe0$D_OUT),
.FULL_N(mem_pipe0$FULL_N),
.EMPTY_N(mem_pipe0$EMPTY_N));
// submodule mem_pipe1
FIFOL1 #(.width(32'd17)) mem_pipe1(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe1$D_IN),
.ENQ(mem_pipe1$ENQ),
.DEQ(mem_pipe1$DEQ),
.CLR(mem_pipe1$CLR),
.D_OUT(mem_pipe1$D_OUT),
.FULL_N(mem_pipe1$FULL_N),
.EMPTY_N(mem_pipe1$EMPTY_N));
// submodule mem_pipe2
FIFOL1 #(.width(32'd17)) mem_pipe2(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe2$D_IN),
.ENQ(mem_pipe2$ENQ),
.DEQ(mem_pipe2$DEQ),
.CLR(mem_pipe2$CLR),
.D_OUT(mem_pipe2$D_OUT),
.FULL_N(mem_pipe2$FULL_N),
.EMPTY_N(mem_pipe2$EMPTY_N));
// submodule mem_req
FIFOL1 #(.width(32'd45)) mem_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_req$D_IN),
.ENQ(mem_req$ENQ),
.DEQ(mem_req$DEQ),
.CLR(mem_req$CLR),
.D_OUT(mem_req$D_OUT),
.FULL_N(mem_req$FULL_N),
.EMPTY_N(mem_req$EMPTY_N));
// submodule mem_resp
FIFOL1 #(.width(32'd17)) mem_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_resp$D_IN),
.ENQ(mem_resp$ENQ),
.DEQ(mem_resp$DEQ),
.CLR(mem_resp$CLR),
.D_OUT(mem_resp$D_OUT),
.FULL_N(mem_resp$FULL_N),
.EMPTY_N(mem_resp$EMPTY_N));
// submodule mem_upper_16b_request
FIFO2 #(.width(32'd45),
.guarded(32'd0)) mem_upper_16b_request(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_upper_16b_request$D_IN),
.ENQ(mem_upper_16b_request$ENQ),
.DEQ(mem_upper_16b_request$DEQ),
.CLR(mem_upper_16b_request$CLR),
.D_OUT(mem_upper_16b_request$D_OUT),
.FULL_N(),
.EMPTY_N(mem_upper_16b_request$EMPTY_N));
// submodule pixel_engine_char_colour
FIFO2 #(.width(32'd10),
.guarded(32'd1)) pixel_engine_char_colour(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_colour$D_IN),
.ENQ(pixel_engine_char_colour$ENQ),
.DEQ(pixel_engine_char_colour$DEQ),
.CLR(pixel_engine_char_colour$CLR),
.D_OUT(pixel_engine_char_colour$D_OUT),
.FULL_N(pixel_engine_char_colour$FULL_N),
.EMPTY_N(pixel_engine_char_colour$EMPTY_N));
// submodule pixel_engine_char_pixel
FIFO2 #(.width(32'd10),
.guarded(32'd1)) pixel_engine_char_pixel(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_pixel$D_IN),
.ENQ(pixel_engine_char_pixel$ENQ),
.DEQ(pixel_engine_char_pixel$DEQ),
.CLR(pixel_engine_char_pixel$CLR),
.D_OUT(pixel_engine_char_pixel$D_OUT),
.FULL_N(pixel_engine_char_pixel$FULL_N),
.EMPTY_N(pixel_engine_char_pixel$EMPTY_N));
// submodule pixel_engine_char_pos
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) pixel_engine_char_pos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_pos$D_IN),
.ENQ(pixel_engine_char_pos$ENQ),
.DEQ(pixel_engine_char_pos$DEQ),
.CLR(pixel_engine_char_pos$CLR),
.D_OUT(pixel_engine_char_pos$D_OUT),
.FULL_N(pixel_engine_char_pos$FULL_N),
.EMPTY_N(pixel_engine_char_pos$EMPTY_N));
// submodule pixel_engine_chars_read
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_chars_read(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_chars_read$D_IN),
.ENQ(pixel_engine_chars_read$ENQ),
.DEQ(pixel_engine_chars_read$DEQ),
.CLR(pixel_engine_chars_read$CLR),
.D_OUT(pixel_engine_chars_read$D_OUT),
.FULL_N(pixel_engine_chars_read$FULL_N),
.EMPTY_N(pixel_engine_chars_read$EMPTY_N));
// submodule pixel_engine_font_y_pos
FIFO2 #(.width(32'd4),
.guarded(32'd1)) pixel_engine_font_y_pos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_font_y_pos$D_IN),
.ENQ(pixel_engine_font_y_pos$ENQ),
.DEQ(pixel_engine_font_y_pos$DEQ),
.CLR(pixel_engine_font_y_pos$CLR),
.D_OUT(pixel_engine_font_y_pos$D_OUT),
.FULL_N(pixel_engine_font_y_pos$FULL_N),
.EMPTY_N(pixel_engine_font_y_pos$EMPTY_N));
// submodule pixel_engine_fontbits
FIFO2 #(.width(32'd8),
.guarded(32'd1)) pixel_engine_fontbits(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_fontbits$D_IN),
.ENQ(pixel_engine_fontbits$ENQ),
.DEQ(pixel_engine_fontbits$DEQ),
.CLR(pixel_engine_fontbits$CLR),
.D_OUT(pixel_engine_fontbits$D_OUT),
.FULL_N(pixel_engine_fontbits$FULL_N),
.EMPTY_N(pixel_engine_fontbits$EMPTY_N));
// submodule pixel_engine_fontrom_rom
VerilogAlteraROM #(.FILENAME("vgafontrom.mif"),
.ADDRESS_WIDTH(32'd12),
.DATA_WIDTH(32'd8)) pixel_engine_fontrom_rom(.clk(csi_clockreset_clk),
.v_addr(pixel_engine_fontrom_rom$v_addr),
.v_en(pixel_engine_fontrom_rom$v_en),
.v_data(pixel_engine_fontrom_rom$v_data));
// submodule pixel_engine_fontrom_seq_fifo
FIFO1 #(.width(32'd1),
.guarded(32'd1)) pixel_engine_fontrom_seq_fifo(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_fontrom_seq_fifo$D_IN),
.ENQ(pixel_engine_fontrom_seq_fifo$ENQ),
.DEQ(pixel_engine_fontrom_seq_fifo$DEQ),
.CLR(pixel_engine_fontrom_seq_fifo$CLR),
.D_OUT(),
.FULL_N(pixel_engine_fontrom_seq_fifo$FULL_N),
.EMPTY_N(pixel_engine_fontrom_seq_fifo$EMPTY_N));
// submodule pixel_engine_pixpos
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_pixpos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_pixpos$D_IN),
.ENQ(pixel_engine_pixpos$ENQ),
.DEQ(pixel_engine_pixpos$DEQ),
.CLR(pixel_engine_pixpos$CLR),
.D_OUT(pixel_engine_pixpos$D_OUT),
.FULL_N(pixel_engine_pixpos$FULL_N),
.EMPTY_N(pixel_engine_pixpos$EMPTY_N));
// submodule pixel_engine_req
FIFO2 #(.width(32'd62),
.guarded(32'd1)) pixel_engine_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_req$D_IN),
.ENQ(pixel_engine_req$ENQ),
.DEQ(pixel_engine_req$DEQ),
.CLR(pixel_engine_req$CLR),
.D_OUT(pixel_engine_req$D_OUT),
.FULL_N(pixel_engine_req$FULL_N),
.EMPTY_N(pixel_engine_req$EMPTY_N));
// submodule pixel_engine_ssram_req
FIFOL1 #(.width(32'd62)) pixel_engine_ssram_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_ssram_req$D_IN),
.ENQ(pixel_engine_ssram_req$ENQ),
.DEQ(pixel_engine_ssram_req$DEQ),
.CLR(pixel_engine_ssram_req$CLR),
.D_OUT(pixel_engine_ssram_req$D_OUT),
.FULL_N(pixel_engine_ssram_req$FULL_N),
.EMPTY_N(pixel_engine_ssram_req$EMPTY_N));
// submodule pixel_engine_ssram_resp
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_ssram_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_ssram_resp$D_IN),
.ENQ(pixel_engine_ssram_resp$ENQ),
.DEQ(pixel_engine_ssram_resp$DEQ),
.CLR(pixel_engine_ssram_resp$CLR),
.D_OUT(pixel_engine_ssram_resp$D_OUT),
.FULL_N(pixel_engine_ssram_resp$FULL_N),
.EMPTY_N(pixel_engine_ssram_resp$EMPTY_N));
// submodule pixel_engine_two_chars
FIFO2 #(.width(32'd32),
.guarded(32'd1)) pixel_engine_two_chars(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_two_chars$D_IN),
.ENQ(pixel_engine_two_chars$ENQ),
.DEQ(pixel_engine_two_chars$DEQ),
.CLR(pixel_engine_two_chars$CLR),
.D_OUT(pixel_engine_two_chars$D_OUT),
.FULL_N(pixel_engine_two_chars$FULL_N),
.EMPTY_N(pixel_engine_two_chars$EMPTY_N));
// submodule response_for_avalon
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) response_for_avalon(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(response_for_avalon$D_IN),
.ENQ(response_for_avalon$ENQ),
.DEQ(response_for_avalon$DEQ),
.CLR(response_for_avalon$CLR),
.D_OUT(response_for_avalon$D_OUT),
.FULL_N(response_for_avalon$FULL_N),
.EMPTY_N(response_for_avalon$EMPTY_N));
// submodule touch
FIFO2 #(.width(32'd48),
.guarded(32'd0)) touch(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(touch$D_IN),
.ENQ(touch$ENQ),
.DEQ(touch$DEQ),
.CLR(touch$CLR),
.D_OUT(touch$D_OUT),
.FULL_N(touch$FULL_N),
.EMPTY_N(touch$EMPTY_N));
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
pixel_engine_ssram_req$EMPTY_N && pixel_engine_req$FULL_N ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_return_control_register_response
assign CAN_FIRE_RL_return_control_register_response =
avalon_control_reg_resp$EMPTY_N && !avalon_mem_resp$EMPTY_N ;
assign WILL_FIRE_RL_return_control_register_response =
CAN_FIRE_RL_return_control_register_response ;
// rule RL_return_mem_response
assign CAN_FIRE_RL_return_mem_response = avalon_mem_resp$EMPTY_N ;
assign WILL_FIRE_RL_return_mem_response = avalon_mem_resp$EMPTY_N ;
// rule RL_receive_mem_responses
assign CAN_FIRE_RL_receive_mem_responses =
mem_resp$EMPTY_N &&
(!lower_16b_returned$EMPTY_N ||
response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529) ;
assign WILL_FIRE_RL_receive_mem_responses =
CAN_FIRE_RL_receive_mem_responses ;
// rule RL_avalon_slave_hanlde_bus_requests
assign CAN_FIRE_RL_avalon_slave_hanlde_bus_requests =
avalon_slave_outbuf$FULL_N && (avs_s0_read || avs_s0_write) &&
!avalon_slave_ignore_further_requests ;
assign WILL_FIRE_RL_avalon_slave_hanlde_bus_requests =
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests ;
// rule RL_avalon_slave_wire_up_avalonwait
assign CAN_FIRE_RL_avalon_slave_wire_up_avalonwait = 1'd1 ;
assign WILL_FIRE_RL_avalon_slave_wire_up_avalonwait = 1'd1 ;
// rule RL_avalon_slave_cancel_ingore_further_requests
assign CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests =
!avalon_slave_avalonwait$wget &&
avalon_slave_ignore_further_requests ;
assign WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests =
CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests ;
// rule RL_pixel_engine_request_char_values
assign CAN_FIRE_RL_pixel_engine_request_char_values =
pixel_engine_ssram_req$FULL_N &&
pixel_engine_font_y_pos$FULL_N &&
pixel_engine_char_pos$FULL_N &&
pixel_engine_chars_read$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_request_char_values =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// rule RL_pixel_engine_request_pixel_values
assign CAN_FIRE_RL_pixel_engine_request_pixel_values =
pixel_engine_ssram_req$FULL_N &&
pixel_engine_chars_read$FULL_N &&
pixel_engine_pixpos$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_request_pixel_values =
CAN_FIRE_RL_pixel_engine_request_pixel_values &&
!WILL_FIRE_RL_pixel_engine_request_char_values ;
// rule RL_pixel_engine_forward_pixel_values
assign CAN_FIRE_RL_pixel_engine_forward_pixel_values =
pixel_engine_chars_read$EMPTY_N && aso_stream_out_ready &&
pixel_engine_char_pixel$EMPTY_N &&
pixel_engine_ssram_resp$EMPTY_N &&
pixel_engine_pixpos$EMPTY_N &&
!pixel_engine_chars_read$D_OUT ;
assign WILL_FIRE_RL_pixel_engine_forward_pixel_values =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
// rule RL_pixel_engine_buffer_characters_read
assign CAN_FIRE_RL_pixel_engine_buffer_characters_read =
pixel_engine_chars_read$EMPTY_N &&
pixel_engine_ssram_resp$EMPTY_N &&
pixel_engine_two_chars$FULL_N &&
pixel_engine_chars_read$D_OUT ;
assign WILL_FIRE_RL_pixel_engine_buffer_characters_read =
CAN_FIRE_RL_pixel_engine_buffer_characters_read ;
// rule RL_pixel_engine_mkConnectionGetPut
assign CAN_FIRE_RL_pixel_engine_mkConnectionGetPut =
pixel_engine_fontrom_seq_fifo$EMPTY_N &&
pixel_engine_fontbits$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_mkConnectionGetPut =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
// rule RL_pixel_engine_demux_two_chars
assign CAN_FIRE_RL_pixel_engine_demux_two_chars =
pixel_engine_two_chars$EMPTY_N &&
pixel_engine_font_y_pos$EMPTY_N &&
pixel_engine_fontrom_seq_fifo$FULL_N &&
pixel_engine_char_colour$FULL_N &&
pixel_engine_char_pos$EMPTY_N ;
assign WILL_FIRE_RL_pixel_engine_demux_two_chars =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// rule RL_avalon_request_splitter
assign CAN_FIRE_RL_avalon_request_splitter =
avalon_slave_outbuf$EMPTY_N &&
((avalon_slave_outbuf$D_OUT[60:54] == 7'd4) ?
avalon_control_reg_resp$FULL_N :
avalon_req$FULL_N) ;
assign WILL_FIRE_RL_avalon_request_splitter =
CAN_FIRE_RL_avalon_request_splitter ;
// rule RL_pixel_engine_char_pixels
assign CAN_FIRE_RL_pixel_engine_char_pixels =
pixel_engine_char_pixel$FULL_N &&
pixel_engine_char_colour$EMPTY_N &&
pixel_engine_fontbits$EMPTY_N ;
assign WILL_FIRE_RL_pixel_engine_char_pixels =
CAN_FIRE_RL_pixel_engine_char_pixels ;
// rule RL_mem_pipe_stage_2
assign CAN_FIRE_RL_mem_pipe_stage_2 = mem_resp$FULL_N && mem_pipe2$EMPTY_N ;
assign WILL_FIRE_RL_mem_pipe_stage_2 = CAN_FIRE_RL_mem_pipe_stage_2 ;
// rule RL_mem_pipe_stage_1
assign CAN_FIRE_RL_mem_pipe_stage_1 =
mem_pipe1$EMPTY_N && mem_pipe2$FULL_N ;
assign WILL_FIRE_RL_mem_pipe_stage_1 = CAN_FIRE_RL_mem_pipe_stage_1 ;
// rule RL_mem_pipe_stage_0
assign CAN_FIRE_RL_mem_pipe_stage_0 =
mem_pipe1$FULL_N && mem_pipe0$EMPTY_N ;
assign WILL_FIRE_RL_mem_pipe_stage_0 = CAN_FIRE_RL_mem_pipe_stage_0 ;
// rule RL_mem_forward_requests_ssram
assign CAN_FIRE_RL_mem_forward_requests_ssram =
mem_req$EMPTY_N && mem_pipe0$FULL_N && !mem_req$D_OUT[41] ;
assign WILL_FIRE_RL_mem_forward_requests_ssram =
CAN_FIRE_RL_mem_forward_requests_ssram ;
// rule RL_mem_forward_requests_flash
assign CAN_FIRE_RL_mem_forward_requests_flash =
mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345 &&
mem_req$D_OUT[41] &&
!mem_ssram_ce_pw$whas ;
assign WILL_FIRE_RL_mem_forward_requests_flash =
CAN_FIRE_RL_mem_forward_requests_flash &&
!WILL_FIRE_RL_mem_pipe_stage_1 &&
!WILL_FIRE_RL_mem_pipe_stage_2 ;
// rule RL_arbitrate_requests
assign CAN_FIRE_RL_arbitrate_requests =
response_for_avalon$FULL_N && mem_req$FULL_N &&
!mem_upper_16b_request$EMPTY_N &&
(pixel_engine_req$EMPTY_N || avalon_req$EMPTY_N) ;
assign WILL_FIRE_RL_arbitrate_requests = CAN_FIRE_RL_arbitrate_requests ;
// rule RL_forward_upper_bytes
assign CAN_FIRE_RL_forward_upper_bytes =
mem_req$FULL_N && mem_upper_16b_request$EMPTY_N ;
assign WILL_FIRE_RL_forward_upper_bytes = CAN_FIRE_RL_forward_upper_bytes ;
// inputs to muxes for submodule ports
assign MUX_avalon_slave_datareturned$wset_1__SEL_1 =
avalon_mem_resp$EMPTY_N && avalon_mem_resp$D_OUT[32] ;
assign MUX_mem_fsm_a_w$wset_1__SEL_1 =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ;
assign MUX_mem_resp$enq_1__SEL_1 =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ;
assign MUX_mem_fsm_dout_dw$wset_1__VAL_2 =
mem_pipe1$D_OUT[16] ? mem_pipe1$D_OUT[15:0] : 16'hEEEE ;
assign MUX_mem_req$enq_1__VAL_1 =
{ IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668[1:0],
x__h13071,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669[15:0] } ;
assign MUX_mem_resp$enq_1__VAL_1 =
(mem_req$D_OUT[43:42] == 2'b0) ?
(mem_req$D_OUT[44] ? 17'd43690 : 17'd65536) :
{ !mem_req$D_OUT[44], coe_fsm_d_in } ;
assign MUX_mem_resp$enq_1__VAL_2 = { !mem_pipe2$D_OUT[16], coe_fsm_d_in } ;
assign MUX_pixel_engine_ssram_req$enq_1__VAL_1 =
{ 5'd15, pixel_engine_char_addr, 32'd0 } ;
assign MUX_pixel_engine_ssram_req$enq_1__VAL_2 =
{ 5'd15, pixel_engine_addr, 32'd0 } ;
// inlined wires
assign pixel_engine_lcd_stream_data_dw$wget =
{ 1'd1,
bitmap_col_chan_r__h3298,
bitmap_col_chan_g__h3299,
bitmap_col_chan_b__h3300 } ;
assign mem_fsm_a_w$whas =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign mem_fsm_dout_dw$wget =
MUX_mem_fsm_a_w$wset_1__SEL_1 ?
mem_req$D_OUT[15:0] :
MUX_mem_fsm_dout_dw$wset_1__VAL_2 ;
assign mem_fsm_dout_dw$whas =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ||
WILL_FIRE_RL_mem_pipe_stage_1 ;
assign mem_fsm_dout_req_dw$wget =
MUX_mem_fsm_a_w$wset_1__SEL_1 ?
mem_req$D_OUT[44] :
mem_pipe1$D_OUT[16] ;
assign mem_flash_ce_n_dw$wget =
mem_req$D_OUT[44] && mem_flash_timer == 4'd10 ;
assign mem_flash_we_n_dw$wget =
!mem_req$D_OUT[44] || mem_flash_timer == 4'd10 ||
mem_flash_timer == 4'd9 ;
assign avalon_slave_avalonwait_end_read$whas =
avalon_mem_resp$EMPTY_N && avalon_mem_resp$D_OUT[32] ||
WILL_FIRE_RL_return_control_register_response &&
avalon_control_reg_resp$D_OUT[32] ;
assign avalon_slave_avalonwait_end_write$whas =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests && avs_s0_write ;
assign mem_ssram_ce_pw$whas =
WILL_FIRE_RL_mem_pipe_stage_2 || WILL_FIRE_RL_mem_pipe_stage_1 ||
WILL_FIRE_RL_mem_pipe_stage_0 ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign avalon_slave_avalonwait$wget =
avs_s0_read && !avalon_slave_avalonwait_end_read$whas ||
avs_s0_write && !avalon_slave_avalonwait_end_write$whas ;
// register avalon_slave_ignore_further_requests
assign avalon_slave_ignore_further_requests$D_IN =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests && avs_s0_read ;
assign avalon_slave_ignore_further_requests$EN =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests ||
WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests ;
// register mem_flash_timer
assign mem_flash_timer$D_IN =
(mem_flash_timer == 4'd10) ? 4'd0 : mem_flash_timer + 4'd1 ;
assign mem_flash_timer$EN = MUX_mem_fsm_a_w$wset_1__SEL_1 ;
// register pixel_engine_addr
assign pixel_engine_addr$D_IN =
(pixel_engine_addr == 25'd383999) ? 25'd0 : next_addr__h3065 ;
assign pixel_engine_addr$EN =
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
// register pixel_engine_char_addr
assign pixel_engine_char_addr$D_IN =
x__h3050 +
IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55[24:0] ;
assign pixel_engine_char_addr$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_char_base
assign pixel_engine_char_base$D_IN = avalon_slave_outbuf$D_OUT[30:6] ;
assign pixel_engine_char_base$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_char_ctr
assign pixel_engine_char_ctr$D_IN = pixel_engine_char_ctr + 1'd1 ;
assign pixel_engine_char_ctr$EN = CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// register pixel_engine_char_end
assign pixel_engine_char_end$D_IN =
avalon_slave_outbuf$D_OUT[30:6] + 25'd6000 ;
assign pixel_engine_char_end$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_char_x_pos
assign pixel_engine_char_x_pos$D_IN = pixel_engine_char_x_pos + 3'd1 ;
assign pixel_engine_char_x_pos$EN = CAN_FIRE_RL_pixel_engine_char_pixels ;
// register pixel_engine_char_x_two_char
assign pixel_engine_char_x_two_char$D_IN = next_x_two_char_addr__h2901 ;
assign pixel_engine_char_x_two_char$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_char_y
assign pixel_engine_char_y$D_IN = next_char_y__h2903 ;
assign pixel_engine_char_y$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_cursor_pos
assign pixel_engine_cursor_pos$D_IN = avalon_slave_outbuf$D_OUT[19:4] ;
assign pixel_engine_cursor_pos$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd1 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_fb_blend
assign pixel_engine_fb_blend$D_IN = avalon_slave_outbuf$D_OUT[35:4] ;
assign pixel_engine_fb_blend$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd0 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_flash_col
assign pixel_engine_flash_col$D_IN = pixel_engine_flash_col + 6'd1 ;
assign pixel_engine_flash_col$EN =
WILL_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[0] ;
// register pixel_engine_font_y
assign pixel_engine_font_y$D_IN =
(pixel_engine_char_x_two_char == 6'd49) ?
((pixel_engine_font_y == 4'd11) ?
4'd0 :
next_font_y___2__h2969) :
pixel_engine_font_y ;
assign pixel_engine_font_y$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register prev_touch_info
assign prev_touch_info$D_IN =
{ coe_touch_x1,
coe_touch_y1,
coe_touch_x2,
coe_touch_y2,
coe_touch_count_gesture } ;
assign prev_touch_info$EN =
coe_touch_touch_valid &&
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 &&
touch$FULL_N ;
// submodule avalon_control_reg_resp
assign avalon_control_reg_resp$D_IN =
{ avalon_slave_outbuf$D_OUT[62:61] == 2'd0,
(avalon_slave_outbuf$D_OUT[53:36] == 18'd0 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
pixel_engine_fb_blend :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458 } ;
assign avalon_control_reg_resp$ENQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 ;
assign avalon_control_reg_resp$DEQ =
CAN_FIRE_RL_return_control_register_response ;
assign avalon_control_reg_resp$CLR = 1'b0 ;
// submodule avalon_mem_resp
assign avalon_mem_resp$D_IN =
{ mem_resp$D_OUT[16] && lower_16b_returned$D_OUT[16],
mem_resp$D_OUT[15:0],
lower_16b_returned$D_OUT[15:0] } ;
assign avalon_mem_resp$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N &&
response_for_avalon$D_OUT ;
assign avalon_mem_resp$DEQ = avalon_mem_resp$EMPTY_N ;
assign avalon_mem_resp$CLR = 1'b0 ;
// submodule avalon_req
assign avalon_req$D_IN =
{ avalon_slave_outbuf$D_OUT[62:61] == 2'd1,
avalon_slave_outbuf$D_OUT[3:0],
avalon_slave_outbuf$D_OUT[60:4] } ;
assign avalon_req$ENQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] != 7'd4 ;
assign avalon_req$DEQ =
WILL_FIRE_RL_arbitrate_requests && !pixel_engine_req$EMPTY_N ;
assign avalon_req$CLR = 1'b0 ;
// submodule avalon_slave_outbuf
assign avalon_slave_outbuf$D_IN =
{ avs_s0_read ? 2'd0 : 2'd1,
avs_s0_address,
avs_s0_writedata,
avs_s0_byteenable } ;
assign avalon_slave_outbuf$ENQ =
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests ;
assign avalon_slave_outbuf$DEQ = CAN_FIRE_RL_avalon_request_splitter ;
assign avalon_slave_outbuf$CLR = 1'b0 ;
// submodule lower_16b_returned
assign lower_16b_returned$D_IN = mem_resp$D_OUT ;
assign lower_16b_returned$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
!lower_16b_returned$EMPTY_N ;
assign lower_16b_returned$DEQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N ;
assign lower_16b_returned$CLR = 1'b0 ;
// submodule mem_pipe0
assign mem_pipe0$D_IN = { mem_req$D_OUT[44], mem_req$D_OUT[15:0] } ;
assign mem_pipe0$ENQ = CAN_FIRE_RL_mem_forward_requests_ssram ;
assign mem_pipe0$DEQ = CAN_FIRE_RL_mem_pipe_stage_0 ;
assign mem_pipe0$CLR = 1'b0 ;
// submodule mem_pipe1
assign mem_pipe1$D_IN = mem_pipe0$D_OUT ;
assign mem_pipe1$ENQ = CAN_FIRE_RL_mem_pipe_stage_0 ;
assign mem_pipe1$DEQ = CAN_FIRE_RL_mem_pipe_stage_1 ;
assign mem_pipe1$CLR = 1'b0 ;
// submodule mem_pipe2
assign mem_pipe2$D_IN = mem_pipe1$D_OUT ;
assign mem_pipe2$ENQ = CAN_FIRE_RL_mem_pipe_stage_1 ;
assign mem_pipe2$DEQ = CAN_FIRE_RL_mem_pipe_stage_2 ;
assign mem_pipe2$CLR = 1'b0 ;
// submodule mem_req
assign mem_req$D_IN =
WILL_FIRE_RL_arbitrate_requests ?
MUX_mem_req$enq_1__VAL_1 :
mem_upper_16b_request$D_OUT ;
assign mem_req$ENQ =
WILL_FIRE_RL_arbitrate_requests ||
WILL_FIRE_RL_forward_upper_bytes ;
assign mem_req$DEQ =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign mem_req$CLR = 1'b0 ;
// submodule mem_resp
assign mem_resp$D_IN =
MUX_mem_resp$enq_1__SEL_1 ?
MUX_mem_resp$enq_1__VAL_1 :
MUX_mem_resp$enq_1__VAL_2 ;
assign mem_resp$ENQ =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ||
WILL_FIRE_RL_mem_pipe_stage_2 ;
assign mem_resp$DEQ = CAN_FIRE_RL_receive_mem_responses ;
assign mem_resp$CLR = 1'b0 ;
// submodule mem_upper_16b_request
assign mem_upper_16b_request$D_IN =
{ IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668[3:2],
x_addr__h13123,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669[31:16] } ;
assign mem_upper_16b_request$ENQ = CAN_FIRE_RL_arbitrate_requests ;
assign mem_upper_16b_request$DEQ = CAN_FIRE_RL_forward_upper_bytes ;
assign mem_upper_16b_request$CLR = 1'b0 ;
// submodule pixel_engine_char_colour
assign pixel_engine_char_colour$D_IN =
{ x__h7183 == pixel_engine_cursor_pos[15:8] &&
pixel_engine_char_pos$D_OUT[7:0] ==
pixel_engine_cursor_pos[7:0],
pixel_engine_char_ctr ?
pixel_engine_two_chars$D_OUT[31:24] :
pixel_engine_two_chars$D_OUT[15:8],
1'd0 } ;
assign pixel_engine_char_colour$ENQ =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
assign pixel_engine_char_colour$DEQ =
WILL_FIRE_RL_pixel_engine_char_pixels &&
pixel_engine_char_x_pos == 3'd7 ;
assign pixel_engine_char_colour$CLR = 1'b0 ;
// submodule pixel_engine_char_pixel
assign pixel_engine_char_pixel$D_IN =
{ pixel_engine_char_colour$D_OUT[9:1], x__h7731 } ;
assign pixel_engine_char_pixel$ENQ = CAN_FIRE_RL_pixel_engine_char_pixels ;
assign pixel_engine_char_pixel$DEQ =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_char_pixel$CLR = 1'b0 ;
// submodule pixel_engine_char_pos
assign pixel_engine_char_pos$D_IN = { x__h2840, pixel_engine_char_y[7:0] } ;
assign pixel_engine_char_pos$ENQ =
CAN_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_char_pos$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_char_pos$CLR = 1'b0 ;
// submodule pixel_engine_chars_read
assign pixel_engine_chars_read$D_IN =
!WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_chars_read$ENQ =
WILL_FIRE_RL_pixel_engine_request_pixel_values ||
WILL_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_chars_read$DEQ =
WILL_FIRE_RL_pixel_engine_buffer_characters_read ||
WILL_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_chars_read$CLR = 1'b0 ;
// submodule pixel_engine_font_y_pos
assign pixel_engine_font_y_pos$D_IN = pixel_engine_font_y ;
assign pixel_engine_font_y_pos$ENQ =
CAN_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_font_y_pos$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_font_y_pos$CLR = 1'b0 ;
// submodule pixel_engine_fontbits
assign pixel_engine_fontbits$D_IN = pixel_engine_fontrom_rom$v_data ;
assign pixel_engine_fontbits$ENQ =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
assign pixel_engine_fontbits$DEQ =
WILL_FIRE_RL_pixel_engine_char_pixels &&
pixel_engine_char_x_pos == 3'd7 ;
assign pixel_engine_fontbits$CLR = 1'b0 ;
// submodule pixel_engine_fontrom_rom
assign pixel_engine_fontrom_rom$v_addr =
{ char__h6798, pixel_engine_font_y_pos$D_OUT } ;
assign pixel_engine_fontrom_rom$v_en =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// submodule pixel_engine_fontrom_seq_fifo
assign pixel_engine_fontrom_seq_fifo$D_IN = 1'd1 ;
assign pixel_engine_fontrom_seq_fifo$ENQ =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
assign pixel_engine_fontrom_seq_fifo$DEQ =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
assign pixel_engine_fontrom_seq_fifo$CLR = 1'b0 ;
// submodule pixel_engine_pixpos
assign pixel_engine_pixpos$D_IN =
{ pixel_engine_addr == 25'd0, pixel_engine_addr == 25'd383999 } ;
assign pixel_engine_pixpos$ENQ =
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_pixpos$DEQ =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_pixpos$CLR = 1'b0 ;
// submodule pixel_engine_req
assign pixel_engine_req$D_IN = pixel_engine_ssram_req$D_OUT ;
assign pixel_engine_req$ENQ = CAN_FIRE_RL_mkConnectionGetPut ;
assign pixel_engine_req$DEQ =
WILL_FIRE_RL_arbitrate_requests && pixel_engine_req$EMPTY_N ;
assign pixel_engine_req$CLR = 1'b0 ;
// submodule pixel_engine_ssram_req
assign pixel_engine_ssram_req$D_IN =
WILL_FIRE_RL_pixel_engine_request_char_values ?
MUX_pixel_engine_ssram_req$enq_1__VAL_1 :
MUX_pixel_engine_ssram_req$enq_1__VAL_2 ;
assign pixel_engine_ssram_req$ENQ =
WILL_FIRE_RL_pixel_engine_request_char_values ||
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_ssram_req$DEQ = CAN_FIRE_RL_mkConnectionGetPut ;
assign pixel_engine_ssram_req$CLR = 1'b0 ;
// submodule pixel_engine_ssram_resp
assign pixel_engine_ssram_resp$D_IN =
{ mem_resp$D_OUT[15:0], lower_16b_returned$D_OUT[15:0] } ;
assign pixel_engine_ssram_resp$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N &&
!response_for_avalon$D_OUT ;
assign pixel_engine_ssram_resp$DEQ =
WILL_FIRE_RL_pixel_engine_buffer_characters_read ||
WILL_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_ssram_resp$CLR = 1'b0 ;
// submodule pixel_engine_two_chars
assign pixel_engine_two_chars$D_IN = pixel_engine_ssram_resp$D_OUT ;
assign pixel_engine_two_chars$ENQ =
CAN_FIRE_RL_pixel_engine_buffer_characters_read ;
assign pixel_engine_two_chars$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_two_chars$CLR = 1'b0 ;
// submodule response_for_avalon
assign response_for_avalon$D_IN = !pixel_engine_req$EMPTY_N ;
assign response_for_avalon$ENQ = CAN_FIRE_RL_arbitrate_requests ;
assign response_for_avalon$DEQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N ;
assign response_for_avalon$CLR = 1'b0 ;
// submodule touch
assign touch$D_IN = prev_touch_info$D_IN ;
assign touch$ENQ =
coe_touch_touch_valid &&
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 &&
touch$FULL_N ;
assign touch$DEQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd7 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0 ;
assign touch$CLR = 1'b0 ;
// remaining internal signals
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd7 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ? { 22'd0, touch$D_OUT[9:0] } : 32'hFFFFFFFF) :
32'hFFFFFFFF ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd6 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 23'd0, touch$D_OUT[18:10] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd5 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 22'd0, touch$D_OUT[28:19] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd4 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 23'd0, touch$D_OUT[37:29] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd3 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 22'd0, touch$D_OUT[47:38] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd1 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
{ 16'd0, pixel_engine_cursor_pos } :
((avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
{ 7'd0, pixel_engine_char_base[22:0], 2'd0 } :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456) ;
assign IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710 =
CAN_FIRE_RL_mem_forward_requests_ssram ?
mem_req$D_OUT[43:42] :
2'b0 ;
assign IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55 =
next_char_y__h2903 * 25'd50 ;
assign IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645 =
(pixel_engine_font_y == 4'd11) ?
((pixel_engine_char_y == 25'd39) ?
25'd0 :
next_char_y___2__h3016) :
pixel_engine_char_y ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[61] :
avalon_req$D_OUT[61] ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[60:57] :
avalon_req$D_OUT[60:57] ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[31:0] :
avalon_req$D_OUT[31:0] ;
assign NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 =
coe_touch_x1 != prev_touch_info[47:38] ||
coe_touch_y1 != prev_touch_info[37:29] ||
coe_touch_x2 != prev_touch_info[28:19] ||
coe_touch_y2 != prev_touch_info[18:10] ||
coe_touch_count_gesture != prev_touch_info[9:0] ;
assign a__h3765 = minus__h3867[8] ? 8'd0 : minus__h3867[7:0] ;
assign a__h3866 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[23:16] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[23:16] ;
assign a__h5019 = minus__h5121[8] ? 8'd0 : minus__h5121[7:0] ;
assign a__h5120 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[15:8] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[15:8] ;
assign a__h5610 = minus__h5712[8] ? 8'd0 : minus__h5712[7:0] ;
assign a__h5711 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[7:0] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[7:0] ;
assign b__h14135 =
MUX_avalon_slave_datareturned$wset_1__SEL_1 ?
avalon_mem_resp$D_OUT[31:0] :
avalon_control_reg_resp$D_OUT[31:0] ;
assign b__h3310 = sum__h3767[8] ? 8'hFF : sum__h3767[7:0] ;
assign b__h3766 = minus__h4723[8] ? 8'd0 : minus__h4723[7:0] ;
assign b__h4865 = sum__h5021[8] ? 8'hFF : sum__h5021[7:0] ;
assign b__h5020 = minus__h5335[8] ? 8'd0 : minus__h5335[7:0] ;
assign b__h5456 = sum__h5612[8] ? 8'hFF : sum__h5612[7:0] ;
assign b__h5611 = minus__h5926[8] ? 8'd0 : minus__h5926[7:0] ;
assign bitmap_col_chan_b__h3300 = sum__h5457[8] ? 8'hFF : sum__h5457[7:0] ;
assign bitmap_col_chan_g__h3299 = sum__h4866[8] ? 8'hFF : sum__h4866[7:0] ;
assign bitmap_col_chan_r__h3298 = sum__h3311[8] ? 8'hFF : sum__h3311[7:0] ;
assign char__h6798 =
pixel_engine_char_ctr ?
pixel_engine_two_chars$D_OUT[23:16] :
pixel_engine_two_chars$D_OUT[7:0] ;
assign char_alpha__h3227 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
pixel_engine_fb_blend[7:0] :
pixel_engine_fb_blend[15:8] ;
assign mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345 =
mem_req$EMPTY_N &&
((mem_req$D_OUT[43:42] == 2'b0) ?
mem_resp$FULL_N :
mem_flash_timer != 4'd10 || mem_resp$FULL_N) ;
assign minus__h3867 =
{ 1'd0, a__h3866 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h4723 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[23:16] } -
{ 1'd0, char_alpha__h3227 } ;
assign minus__h5121 =
{ 1'd0, a__h5120 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h5335 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[15:8] } -
{ 1'd0, char_alpha__h3227 } ;
assign minus__h5712 =
{ 1'd0, a__h5711 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h5926 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[7:0] } -
{ 1'd0, char_alpha__h3227 } ;
assign next_addr__h3065 = pixel_engine_addr + 25'd1 ;
assign next_char_y___2__h3016 = pixel_engine_char_y + 25'd1 ;
assign next_char_y__h2903 =
(pixel_engine_char_x_two_char == 6'd49) ?
IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645 :
pixel_engine_char_y ;
assign next_font_y___2__h2969 = pixel_engine_font_y + 4'd1 ;
assign next_x_two_char_addr__h2897 = pixel_engine_char_x_two_char + 6'd1 ;
assign next_x_two_char_addr__h2901 =
(pixel_engine_char_x_two_char == 6'd49) ?
6'd0 :
next_x_two_char_addr__h2897 ;
assign pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 =
(pixel_engine_char_pixel$D_OUT[9] &&
pixel_engine_flash_col[5]) ==
(pixel_engine_char_pixel$D_OUT[0] &&
(!pixel_engine_char_pixel$D_OUT[8] ||
pixel_engine_flash_col[4])) ;
assign response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529 =
response_for_avalon$EMPTY_N &&
(response_for_avalon$D_OUT ?
avalon_mem_resp$FULL_N :
pixel_engine_ssram_resp$FULL_N) ;
assign sum__h3311 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[23:16] } +
{ 1'd0, b__h3310 } ;
assign sum__h3767 = { 1'd0, a__h3765 } + { 1'd0, b__h3766 } ;
assign sum__h4866 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[15:8] } +
{ 1'd0, b__h4865 } ;
assign sum__h5021 = { 1'd0, a__h5019 } + { 1'd0, b__h5020 } ;
assign sum__h5457 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[7:0] } +
{ 1'd0, b__h5456 } ;
assign sum__h5612 = { 1'd0, a__h5610 } + { 1'd0, b__h5611 } ;
assign x1_avValue_addr__h12990 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[56:32] :
avalon_req$D_OUT[56:32] ;
assign x__h13071 = { x1_avValue_addr__h12990, 1'b0 } ;
assign x__h2840 = { 1'd0, pixel_engine_char_x_two_char, 1'd0 } ;
assign x__h3050 = pixel_engine_char_base + y__h3053 ;
assign x__h7183 =
pixel_engine_char_pos$D_OUT[15:8] +
{ 7'd0, pixel_engine_char_ctr } ;
assign x__h7731 = pixel_engine_fontbits$D_OUT[x__h7767] ;
assign x__h7767 = 3'd7 - pixel_engine_char_x_pos ;
assign x_addr__h13123 = { x1_avValue_addr__h12990, 1'b1 } ;
assign y__h3053 = { 19'd0, next_x_two_char_addr__h2901 } ;
always@(pixel_engine_fb_blend)
begin
case (pixel_engine_fb_blend[27:24])
4'd0: IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 = 24'h0;
4'd1:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h0000AA;
4'd2:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h00AA00;
4'd3:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h00AAAA;
4'd4:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA0000;
4'd5:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA00AA;
4'd6:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA5500;
4'd7:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAAAAAA;
4'd8:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h555555;
4'd9:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h5555FF;
4'd10:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h55FF55;
4'd11:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h55FFFF;
4'd12:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFF5555;
4'd13:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFF55FF;
4'd14:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFFFF55;
4'd15:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFFFFFF;
endcase
end
always@(pixel_engine_char_pixel$D_OUT)
begin
case (pixel_engine_char_pixel$D_OUT[7:5])
3'd0: IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 = 24'h0;
3'd1:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h0000AA;
3'd2:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h00AA00;
3'd3:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h00AAAA;
3'd4:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA0000;
3'd5:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA00AA;
3'd6:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA5500;
3'd7:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAAAAAA;
endcase
end
always@(pixel_engine_char_pixel$D_OUT)
begin
case (pixel_engine_char_pixel$D_OUT[4:1])
4'd0: IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 = 24'h0;
4'd1:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h0000AA;
4'd2:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h00AA00;
4'd3:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h00AAAA;
4'd4:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA0000;
4'd5:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA00AA;
4'd6:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA5500;
4'd7:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAAAAAA;
4'd8:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h555555;
4'd9:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h5555FF;
4'd10:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h55FF55;
4'd11:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h55FFFF;
4'd12:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFF5555;
4'd13:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFF55FF;
4'd14:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFFFF55;
4'd15:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFFFFFF;
endcase
end
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
avalon_slave_ignore_further_requests <= `BSV_ASSIGNMENT_DELAY 1'd0;
mem_flash_timer <= `BSV_ASSIGNMENT_DELAY 4'd0;
pixel_engine_addr <= `BSV_ASSIGNMENT_DELAY 25'd0;
pixel_engine_char_addr <= `BSV_ASSIGNMENT_DELAY 25'd384000;
pixel_engine_char_base <= `BSV_ASSIGNMENT_DELAY 25'd384000;
pixel_engine_char_ctr <= `BSV_ASSIGNMENT_DELAY 1'd0;
pixel_engine_char_end <= `BSV_ASSIGNMENT_DELAY 25'd390000;
pixel_engine_char_x_pos <= `BSV_ASSIGNMENT_DELAY 3'd0;
pixel_engine_char_x_two_char <= `BSV_ASSIGNMENT_DELAY 6'd0;
pixel_engine_char_y <= `BSV_ASSIGNMENT_DELAY 25'd0;
pixel_engine_cursor_pos <= `BSV_ASSIGNMENT_DELAY 16'd65535;
pixel_engine_fb_blend <= `BSV_ASSIGNMENT_DELAY 32'd50331647;
pixel_engine_flash_col <= `BSV_ASSIGNMENT_DELAY 6'd0;
pixel_engine_font_y <= `BSV_ASSIGNMENT_DELAY 4'd0;
prev_touch_info <= `BSV_ASSIGNMENT_DELAY 48'hAAAAAAAAAAAA;
end
else
begin
if (avalon_slave_ignore_further_requests$EN)
avalon_slave_ignore_further_requests <= `BSV_ASSIGNMENT_DELAY
avalon_slave_ignore_further_requests$D_IN;
if (mem_flash_timer$EN)
mem_flash_timer <= `BSV_ASSIGNMENT_DELAY mem_flash_timer$D_IN;
if (pixel_engine_addr$EN)
pixel_engine_addr <= `BSV_ASSIGNMENT_DELAY pixel_engine_addr$D_IN;
if (pixel_engine_char_addr$EN)
pixel_engine_char_addr <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_addr$D_IN;
if (pixel_engine_char_base$EN)
pixel_engine_char_base <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_base$D_IN;
if (pixel_engine_char_ctr$EN)
pixel_engine_char_ctr <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_ctr$D_IN;
if (pixel_engine_char_end$EN)
pixel_engine_char_end <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_end$D_IN;
if (pixel_engine_char_x_pos$EN)
pixel_engine_char_x_pos <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_x_pos$D_IN;
if (pixel_engine_char_x_two_char$EN)
pixel_engine_char_x_two_char <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_x_two_char$D_IN;
if (pixel_engine_char_y$EN)
pixel_engine_char_y <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_y$D_IN;
if (pixel_engine_cursor_pos$EN)
pixel_engine_cursor_pos <= `BSV_ASSIGNMENT_DELAY
pixel_engine_cursor_pos$D_IN;
if (pixel_engine_fb_blend$EN)
pixel_engine_fb_blend <= `BSV_ASSIGNMENT_DELAY
pixel_engine_fb_blend$D_IN;
if (pixel_engine_flash_col$EN)
pixel_engine_flash_col <= `BSV_ASSIGNMENT_DELAY
pixel_engine_flash_col$D_IN;
if (pixel_engine_font_y$EN)
pixel_engine_font_y <= `BSV_ASSIGNMENT_DELAY
pixel_engine_font_y$D_IN;
if (prev_touch_info$EN)
prev_touch_info <= `BSV_ASSIGNMENT_DELAY prev_touch_info$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
avalon_slave_ignore_further_requests = 1'h0;
mem_flash_timer = 4'hA;
pixel_engine_addr = 25'h0AAAAAA;
pixel_engine_char_addr = 25'h0AAAAAA;
pixel_engine_char_base = 25'h0AAAAAA;
pixel_engine_char_ctr = 1'h0;
pixel_engine_char_end = 25'h0AAAAAA;
pixel_engine_char_x_pos = 3'h2;
pixel_engine_char_x_two_char = 6'h2A;
pixel_engine_char_y = 25'h0AAAAAA;
pixel_engine_cursor_pos = 16'hAAAA;
pixel_engine_fb_blend = 32'hAAAAAAAA;
pixel_engine_flash_col = 6'h2A;
pixel_engine_font_y = 4'hA;
prev_touch_info = 48'hAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkMTL_Framebuffer_Flash
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:45:36 BST 2012
//
// Method conflict info:
// Method: avm_m0
// Conflict-free: avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Conflicts: avm_m0
//
// Method: avm_irq
// Conflict-free: avm_m0,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Sequenced before (restricted): avm_irq
//
// Method: avm_writedata
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_address
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_read
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_write
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_byteenable
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: debugStreamSink_stream_in
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Conflicts: debugStreamSink_stream_in
//
// Method: debugStreamSink_stream_in_ready
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out_data
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Sequenced after (restricted): debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out_valid
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Sequenced after (restricted): debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready
// Sequenced before (restricted): debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Conflicts: debugStreamSource_stream_out
//
//
// Ports:
// Name I/O size props
// avm_writedata O 256 reg
// avm_address O 32
// avm_read O 1 reg
// avm_write O 1 reg
// avm_byteenable O 32 reg
// debugStreamSink_stream_in_ready O 1
// debugStreamSource_stream_out_data O 8
// debugStreamSource_stream_out_valid O 1
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// avm_readdata I 256
// avm_readdatavalid I 1
// avm_waitrequest I 1
// avm_irq_irqs I 5 reg
// debugStreamSink_stream_in_data I 8
// debugStreamSink_stream_in_valid I 1
// debugStreamSource_stream_out_ready I 1
//
// Combinational paths from inputs to outputs:
// debugStreamSource_stream_out_ready -> debugStreamSource_stream_out_data
// debugStreamSource_stream_out_ready -> debugStreamSource_stream_out_valid
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkTopAvalonPhy(csi_clockreset_clk,
csi_clockreset_reset_n,
avm_readdata,
avm_readdatavalid,
avm_waitrequest,
avm_irq_irqs,
avm_writedata,
avm_address,
avm_read,
avm_write,
avm_byteenable,
debugStreamSink_stream_in_data,
debugStreamSink_stream_in_valid,
debugStreamSink_stream_in_ready,
debugStreamSource_stream_out_data,
debugStreamSource_stream_out_valid,
debugStreamSource_stream_out_ready);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method avm_m0
input [255 : 0] avm_readdata;
input avm_readdatavalid;
input avm_waitrequest;
// action method avm_irq
input [4 : 0] avm_irq_irqs;
// value method avm_writedata
output [255 : 0] avm_writedata;
// value method avm_address
output [31 : 0] avm_address;
// value method avm_read
output avm_read;
// value method avm_write
output avm_write;
// value method avm_byteenable
output [31 : 0] avm_byteenable;
// action method debugStreamSink_stream_in
input [7 : 0] debugStreamSink_stream_in_data;
input debugStreamSink_stream_in_valid;
// value method debugStreamSink_stream_in_ready
output debugStreamSink_stream_in_ready;
// value method debugStreamSource_stream_out_data
output [7 : 0] debugStreamSource_stream_out_data;
// value method debugStreamSource_stream_out_valid
output debugStreamSource_stream_out_valid;
// action method debugStreamSource_stream_out
input debugStreamSource_stream_out_ready;
// signals for module outputs
wire [255 : 0] avm_writedata;
wire [31 : 0] avm_address, avm_byteenable;
wire [7 : 0] debugStreamSource_stream_out_data;
wire avm_read,
avm_write,
debugStreamSink_stream_in_ready,
debugStreamSource_stream_out_valid;
// inlined wires
wire [256 : 0] datareturnbuf_rw_enq$wget;
wire [8 : 0] streamIn_d_dw$wget, streamOut_data_dw$wget;
wire signal_read$whas, signal_write$whas, streamOut_data_dw$whas;
// register address_r
reg [26 : 0] address_r;
wire [26 : 0] address_r$D_IN;
wire address_r$EN;
// register byteenable_r
reg [31 : 0] byteenable_r;
wire [31 : 0] byteenable_r$D_IN;
wire byteenable_r$EN;
// register count
reg [15 : 0] count;
wire [15 : 0] count$D_IN;
wire count$EN;
// register datareturnbuf_taggedReg
reg [257 : 0] datareturnbuf_taggedReg;
wire [257 : 0] datareturnbuf_taggedReg$D_IN;
wire datareturnbuf_taggedReg$EN;
// register interrupts
reg [4 : 0] interrupts;
wire [4 : 0] interrupts$D_IN;
wire interrupts$EN;
// register read_r
reg read_r;
wire read_r$D_IN, read_r$EN;
// register write_r
reg write_r;
wire write_r$D_IN, write_r$EN;
// register writedata_r
reg [255 : 0] writedata_r;
wire [255 : 0] writedata_r$D_IN;
wire writedata_r$EN;
// ports of submodule beri
wire [316 : 0] beri$memory_request_get;
wire [255 : 0] beri$memory_response_put;
wire [7 : 0] beri$debugStream_request_put, beri$debugStream_response_get;
wire [4 : 0] beri$putIrqs_interruptLines;
wire beri$EN_debugStream_request_put,
beri$EN_debugStream_response_get,
beri$EN_memory_request_get,
beri$EN_memory_response_put,
beri$EN_putIrqs,
beri$RDY_debugStream_request_put,
beri$RDY_debugStream_response_get,
beri$RDY_memory_request_get,
beri$RDY_memory_response_put;
// ports of submodule pending_acks
wire pending_acks$CLR,
pending_acks$DEQ,
pending_acks$D_IN,
pending_acks$EMPTY_N,
pending_acks$ENQ,
pending_acks$FULL_N;
// ports of submodule perif_reads
wire [2 : 0] perif_reads$D_IN, perif_reads$D_OUT;
wire perif_reads$CLR, perif_reads$DEQ, perif_reads$EMPTY_N, perif_reads$ENQ;
// ports of submodule streamIn_f
wire [7 : 0] streamIn_f$D_IN, streamIn_f$D_OUT;
wire streamIn_f$CLR,
streamIn_f$DEQ,
streamIn_f$EMPTY_N,
streamIn_f$ENQ,
streamIn_f$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_buffer_data_read,
WILL_FIRE_RL_datareturnbuf_rule_enq,
WILL_FIRE_RL_getRequest;
// inputs to muxes for submodule ports
wire [257 : 0] MUX_datareturnbuf_taggedReg$write_1__VAL_1;
wire MUX_datareturnbuf_taggedReg$write_1__SEL_2;
// remaining internal signals
wire [255 : 0] v__h1794, v__h1820;
// value method avm_writedata
assign avm_writedata = writedata_r ;
// value method avm_address
assign avm_address = { address_r, 5'b0 } ;
// value method avm_read
assign avm_read = read_r ;
// value method avm_write
assign avm_write = write_r ;
// value method avm_byteenable
assign avm_byteenable = byteenable_r ;
// value method debugStreamSink_stream_in_ready
assign debugStreamSink_stream_in_ready = streamIn_f$FULL_N ;
// value method debugStreamSource_stream_out_data
assign debugStreamSource_stream_out_data = streamOut_data_dw$wget[7:0] ;
// value method debugStreamSource_stream_out_valid
assign debugStreamSource_stream_out_valid =
streamOut_data_dw$whas && streamOut_data_dw$wget[8] ;
// submodule beri
mkMIPSTop beri(.csi_c0_clk(csi_clockreset_clk),
.csi_c0_reset_n(csi_clockreset_reset_n),
.debugStream_request_put(beri$debugStream_request_put),
.memory_response_put(beri$memory_response_put),
.putIrqs_interruptLines(beri$putIrqs_interruptLines),
.EN_memory_request_get(beri$EN_memory_request_get),
.EN_memory_response_put(beri$EN_memory_response_put),
.EN_putIrqs(beri$EN_putIrqs),
.EN_debugStream_request_put(beri$EN_debugStream_request_put),
.EN_debugStream_response_get(beri$EN_debugStream_response_get),
.memory_request_get(beri$memory_request_get),
.RDY_memory_request_get(beri$RDY_memory_request_get),
.RDY_memory_response_put(beri$RDY_memory_response_put),
.RDY_putIrqs(),
.RDY_debugStream_request_put(beri$RDY_debugStream_request_put),
.debugStream_response_get(beri$debugStream_response_get),
.RDY_debugStream_response_get(beri$RDY_debugStream_response_get));
// submodule pending_acks
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) pending_acks(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pending_acks$D_IN),
.ENQ(pending_acks$ENQ),
.DEQ(pending_acks$DEQ),
.CLR(pending_acks$CLR),
.D_OUT(),
.FULL_N(pending_acks$FULL_N),
.EMPTY_N(pending_acks$EMPTY_N));
// submodule perif_reads
FIFO2 #(.width(32'd3),
.guarded(32'd0)) perif_reads(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(perif_reads$D_IN),
.ENQ(perif_reads$ENQ),
.DEQ(perif_reads$DEQ),
.CLR(perif_reads$CLR),
.D_OUT(perif_reads$D_OUT),
.FULL_N(),
.EMPTY_N(perif_reads$EMPTY_N));
// submodule streamIn_f
FIFOL1 #(.width(32'd8)) streamIn_f(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(streamIn_f$D_IN),
.ENQ(streamIn_f$ENQ),
.DEQ(streamIn_f$DEQ),
.CLR(streamIn_f$CLR),
.D_OUT(streamIn_f$D_OUT),
.FULL_N(streamIn_f$FULL_N),
.EMPTY_N(streamIn_f$EMPTY_N));
// rule RL_buffer_data_read
assign WILL_FIRE_RL_buffer_data_read =
!datareturnbuf_taggedReg[257] && avm_readdatavalid ;
// rule RL_getRequest
assign WILL_FIRE_RL_getRequest =
beri$RDY_memory_request_get && pending_acks$FULL_N &&
(!avm_waitrequest || !read_r && !write_r) ;
// rule RL_datareturnbuf_rule_enq
assign WILL_FIRE_RL_datareturnbuf_rule_enq =
WILL_FIRE_RL_buffer_data_read &&
!MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_datareturnbuf_taggedReg$write_1__SEL_2 =
beri$RDY_memory_response_put &&
(datareturnbuf_taggedReg[257] ||
WILL_FIRE_RL_buffer_data_read) &&
pending_acks$EMPTY_N ;
assign MUX_datareturnbuf_taggedReg$write_1__VAL_1 =
{ 1'd1, datareturnbuf_rw_enq$wget } ;
// inlined wires
assign datareturnbuf_rw_enq$wget =
{ 1'd1, perif_reads$EMPTY_N ? v__h1794 : avm_readdata } ;
assign streamIn_d_dw$wget = { 1'd1, debugStreamSink_stream_in_data } ;
assign streamOut_data_dw$wget = { 1'd1, beri$debugStream_response_get } ;
assign streamOut_data_dw$whas =
beri$RDY_debugStream_response_get &&
debugStreamSource_stream_out_ready ;
assign signal_read$whas =
WILL_FIRE_RL_getRequest && !beri$memory_request_get[316] ;
assign signal_write$whas =
WILL_FIRE_RL_getRequest && beri$memory_request_get[316] ;
// register address_r
assign address_r$D_IN = beri$memory_request_get[315:289] ;
assign address_r$EN = WILL_FIRE_RL_getRequest ;
// register byteenable_r
assign byteenable_r$D_IN = beri$memory_request_get[32:1] ;
assign byteenable_r$EN = WILL_FIRE_RL_getRequest ;
// register count
assign count$D_IN = count + 16'd1 ;
assign count$EN =
WILL_FIRE_RL_buffer_data_read && perif_reads$EMPTY_N &&
perif_reads$D_OUT == 3'd2 ;
// register datareturnbuf_taggedReg
assign datareturnbuf_taggedReg$D_IN =
WILL_FIRE_RL_datareturnbuf_rule_enq ?
MUX_datareturnbuf_taggedReg$write_1__VAL_1 :
258'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign datareturnbuf_taggedReg$EN =
WILL_FIRE_RL_datareturnbuf_rule_enq ||
beri$RDY_memory_response_put &&
(datareturnbuf_taggedReg[257] ||
WILL_FIRE_RL_buffer_data_read) &&
pending_acks$EMPTY_N ;
// register interrupts
assign interrupts$D_IN = avm_irq_irqs ;
assign interrupts$EN = 1'd1 ;
// register read_r
assign read_r$D_IN = signal_read$whas ;
assign read_r$EN = signal_read$whas || !avm_waitrequest ;
// register write_r
assign write_r$D_IN = signal_write$whas ;
assign write_r$EN = signal_write$whas || !avm_waitrequest ;
// register writedata_r
assign writedata_r$D_IN = beri$memory_request_get[288:33] ;
assign writedata_r$EN = WILL_FIRE_RL_getRequest ;
// submodule beri
assign beri$debugStream_request_put = streamIn_f$D_OUT ;
assign beri$memory_response_put =
(WILL_FIRE_RL_buffer_data_read ?
!datareturnbuf_rw_enq$wget[256] :
datareturnbuf_taggedReg[257] &&
!datareturnbuf_taggedReg[256]) ?
256'b0 :
(WILL_FIRE_RL_buffer_data_read ?
datareturnbuf_rw_enq$wget[255:0] :
datareturnbuf_taggedReg[255:0]) ;
assign beri$putIrqs_interruptLines = interrupts ;
assign beri$EN_memory_request_get = WILL_FIRE_RL_getRequest ;
assign beri$EN_memory_response_put =
MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
assign beri$EN_putIrqs = 1'd1 ;
assign beri$EN_debugStream_request_put =
beri$RDY_debugStream_request_put && streamIn_f$EMPTY_N ;
assign beri$EN_debugStream_response_get =
beri$RDY_debugStream_response_get &&
debugStreamSource_stream_out_ready ;
// submodule pending_acks
assign pending_acks$D_IN = 1'd0 ;
assign pending_acks$ENQ = signal_read$whas ;
assign pending_acks$DEQ = MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
assign pending_acks$CLR = 1'b0 ;
// submodule perif_reads
assign perif_reads$D_IN =
(beri$memory_request_get[315:289] == 27'h3F80200) ? 3'd2 : 3'd5 ;
assign perif_reads$ENQ = signal_read$whas ;
assign perif_reads$DEQ =
WILL_FIRE_RL_buffer_data_read && perif_reads$EMPTY_N ;
assign perif_reads$CLR = 1'b0 ;
// submodule streamIn_f
assign streamIn_f$D_IN = streamIn_d_dw$wget[7:0] ;
assign streamIn_f$ENQ =
streamIn_f$FULL_N && debugStreamSink_stream_in_valid &&
streamIn_d_dw$wget[8] ;
assign streamIn_f$DEQ =
beri$RDY_debugStream_request_put && streamIn_f$EMPTY_N ;
assign streamIn_f$CLR = 1'b0 ;
// remaining internal signals
assign v__h1794 = (perif_reads$D_OUT == 3'd2) ? v__h1820 : avm_readdata ;
assign v__h1820 = { avm_readdata[255:16], count } ;
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
address_r <= `BSV_ASSIGNMENT_DELAY 27'd0;
byteenable_r <= `BSV_ASSIGNMENT_DELAY 32'hAAAAAAAA;
count <= `BSV_ASSIGNMENT_DELAY 16'd0;
datareturnbuf_taggedReg <= `BSV_ASSIGNMENT_DELAY
258'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
interrupts <= `BSV_ASSIGNMENT_DELAY 5'b0;
read_r <= `BSV_ASSIGNMENT_DELAY 1'd0;
write_r <= `BSV_ASSIGNMENT_DELAY 1'd0;
writedata_r <= `BSV_ASSIGNMENT_DELAY 256'd0;
end
else
begin
if (address_r$EN) address_r <= `BSV_ASSIGNMENT_DELAY address_r$D_IN;
if (byteenable_r$EN)
byteenable_r <= `BSV_ASSIGNMENT_DELAY byteenable_r$D_IN;
if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (datareturnbuf_taggedReg$EN)
datareturnbuf_taggedReg <= `BSV_ASSIGNMENT_DELAY
datareturnbuf_taggedReg$D_IN;
if (interrupts$EN)
interrupts <= `BSV_ASSIGNMENT_DELAY interrupts$D_IN;
if (read_r$EN) read_r <= `BSV_ASSIGNMENT_DELAY read_r$D_IN;
if (write_r$EN) write_r <= `BSV_ASSIGNMENT_DELAY write_r$D_IN;
if (writedata_r$EN)
writedata_r <= `BSV_ASSIGNMENT_DELAY writedata_r$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
address_r = 27'h2AAAAAA;
byteenable_r = 32'hAAAAAAAA;
count = 16'hAAAA;
datareturnbuf_taggedReg =
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
interrupts = 5'h0A;
read_r = 1'h0;
write_r = 1'h0;
writedata_r =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkTopAvalonPhy
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_ac_ROM_no_ifdef_params (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter ROM_INIT_FILE_NAME = "AC_ROM.hex";
input clock;
input [31:0] data;
input [5:0] rdaddress;
input [5:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b0),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "AC_ROM.rif"
`else
altsyncram_component.init_file = ROM_INIT_FILE_NAME
`endif
,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 40,
altsyncram_component.numwords_b = 40,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ac_ROM_reg(
rdaddress,
clock,
wraddress,
data,
wren,
q);
parameter AC_ROM_DATA_WIDTH = "";
parameter AC_ROM_ADDRESS_WIDTH = "";
input [(AC_ROM_ADDRESS_WIDTH-1):0] rdaddress;
input clock;
input [(AC_ROM_ADDRESS_WIDTH-1):0] wraddress;
input [(AC_ROM_DATA_WIDTH-1):0] data;
input wren;
output reg [(AC_ROM_DATA_WIDTH-1):0] q;
reg [(AC_ROM_DATA_WIDTH-1):0] ac_mem[(2**AC_ROM_ADDRESS_WIDTH-1):0];
always @(posedge clock)
begin
if(wren)
ac_mem[wraddress] <= data;
q <= ac_mem[rdaddress];
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_bitcheck(
ck,
reset_n,
clear,
enable,
read_data,
reference_data,
mask,
error_word
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input clear;
input enable;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input [DATA_BUS_SIZE - 1 : 0] reference_data;
input [NUMBER_OF_WORDS - 1 : 0] mask;
output [DATA_WIDTH - 1 : 0] error_word;
reg [DATA_BUS_SIZE - 1 : 0] read_data_r;
reg [DATA_WIDTH - 1 : 0] error_word;
reg enable_r;
wire [DATA_WIDTH - 1 : 0] error_compute;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
error_word <= {DATA_WIDTH{1'b0}};
read_data_r <= {DATA_BUS_SIZE{1'b0}};
enable_r <= 1'b0;
end
else begin
if(clear) begin
error_word <= {DATA_WIDTH{1'b0}};
end
else if(enable_r) begin
error_word <= error_word | error_compute;
end
read_data_r <= read_data;
enable_r <= enable;
end
end
genvar b;
generate
for(b = 0; b < DATA_WIDTH; b = b + 1)
begin : bit_loop
if (AFI_RATIO == 4) begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2]) |
((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]) |
((read_data_r[b + 4 * DATA_WIDTH] ^ reference_data[b + 4 * DATA_WIDTH]) & ~mask[4]) |
((read_data_r[b + 5 * DATA_WIDTH] ^ reference_data[b + 5 * DATA_WIDTH]) & ~mask[5]) |
((read_data_r[b + 6 * DATA_WIDTH] ^ reference_data[b + 6 * DATA_WIDTH]) & ~mask[6]) |
((read_data_r[b + 7 * DATA_WIDTH] ^ reference_data[b + 7 * DATA_WIDTH]) & ~mask[7]);
end
else if (AFI_RATIO == 2) begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2])|
((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]);
end
else begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]);
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_datamux(datain, sel, dataout);
parameter DATA_WIDTH = 8;
parameter SELECT_WIDTH = 1;
parameter NUMBER_OF_CHANNELS = 2;
input [NUMBER_OF_CHANNELS * DATA_WIDTH - 1 : 0] datain;
input [SELECT_WIDTH - 1 : 0] sel;
output [DATA_WIDTH - 1 : 0] dataout;
wire [DATA_WIDTH - 1 : 0] vectorized_data [0 : NUMBER_OF_CHANNELS - 1];
assign dataout = vectorized_data[sel];
genvar c;
generate
for(c = 0 ; c < NUMBER_OF_CHANNELS ; c = c + 1)
begin : channel_iterator
assign vectorized_data[c] = datain[(c + 1) * DATA_WIDTH - 1 : c * DATA_WIDTH];
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@datain NUMBER_OF_CHANNELS == 2**SELECT_WIDTH) else
$error("%t, [DATAMUX ASSERT] NUMBER_OF_CHANNELS PARAMETER is incorrect, NUMBER_OF_CHANNELS = %d, 2**SELECT_WIDTH = %d", $time, NUMBER_OF_CHANNELS, 2**SELECT_WIDTH);
`endif
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_broadcast(
dq_data_in,
dm_data_in,
dq_data_out,
dm_data_out
);
parameter NUMBER_OF_DQS_GROUPS = "";
parameter NUMBER_OF_DQ_PER_DQS = "";
parameter AFI_RATIO = "";
parameter MEM_DM_WIDTH = "";
localparam NUMBER_OF_DQ_BITS = NUMBER_OF_DQS_GROUPS * NUMBER_OF_DQ_PER_DQS;
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
input [NUMBER_OF_DQ_PER_DQS * NUMBER_OF_WORDS - 1 : 0] dq_data_in;
input [NUMBER_OF_WORDS - 1 : 0] dm_data_in;
output [NUMBER_OF_DQ_BITS * NUMBER_OF_WORDS - 1 : 0] dq_data_out;
output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1 : 0] dm_data_out;
genvar gr, wr, dmbit;
generate
for(wr = 0; wr < NUMBER_OF_WORDS; wr = wr + 1)
begin : word
for(gr = 0; gr < NUMBER_OF_DQS_GROUPS; gr = gr + 1)
begin : group
assign dq_data_out[wr * NUMBER_OF_DQ_BITS + (gr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_BITS + gr * NUMBER_OF_DQ_PER_DQS] =
dq_data_in[(wr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_PER_DQS];
end
for(dmbit = 0; dmbit < MEM_DM_WIDTH; dmbit = dmbit + 1)
begin : data_mask_bit
assign dm_data_out[wr * MEM_DM_WIDTH + dmbit] = dm_data_in[wr];
end
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@dm_data_in NUMBER_OF_DQS_GROUPS == MEM_DM_WIDTH) else
$error("%t, [DATA BROADCAST ASSERT] NUMBER_OF_DQS_GROUPS and MEM_DM_WIDTH mismatch, NUMBER_OF_DQS_GROUPS = %d, MEM_DM_WIDTH = %d", $time, NUMBER_OF_DQS_GROUPS, MEM_DM_WIDTH);
`endif
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_decoder(
ck,
reset_n,
code,
pattern
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
input ck;
input reset_n;
input [3:0] code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] pattern;
reg [3:0] code_R;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
code_R <= 4'b0000;
end
else begin
code_R <= code;
end
end
genvar j;
generate
for(j = 0; j < DATA_WIDTH; j = j + 1)
begin : bit_pattern
if(j % 2 == 0) begin
assign pattern[j] = code_R[3];
assign pattern[j + DATA_WIDTH] = code_R[2];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end
end
else begin
assign pattern[j] = code_R[3] ^ code_R[0];
assign pattern[j + DATA_WIDTH] = code_R[2] ^ code_R[0];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3] ^ code_R[0];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2] ^ code_R[0];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module rw_manager_ddr2 (
avl_clk,
avl_reset_n,
avl_address,
avl_write,
avl_writedata,
avl_read,
avl_readdata,
avl_waitrequest,
afi_clk,
afi_reset_n,
afi_addr,
afi_ba,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
csr_clk,
csr_ena,
csr_dout_phy,
csr_dout
);
parameter AVL_DATA_WIDTH = 32;
parameter AVL_ADDR_WIDTH = 16;
parameter MEM_ADDRESS_WIDTH = 19;
parameter MEM_CONTROL_WIDTH = 4;
parameter MEM_DQ_WIDTH = 36;
parameter MEM_DM_WIDTH = 4;
parameter MEM_NUMBER_OF_RANKS = 1;
parameter MEM_CLK_EN_WIDTH = 1;
parameter MEM_BANK_WIDTH = 2;
parameter MEM_ODT_WIDTH = 1;
parameter MEM_CHIP_SELECT_WIDTH = 1;
parameter MEM_READ_DQS_WIDTH = 4;
parameter MEM_WRITE_DQS_WIDTH = 4;
parameter AFI_RATIO = 2;
parameter RATE = "Half";
parameter HCX_COMPAT_MODE = 0;
parameter DEVICE_FAMILY = "STRATIXIV";
parameter AC_ROM_INIT_FILE_NAME = "AC_ROM.hex";
parameter INST_ROM_INIT_FILE_NAME = "inst_ROM.hex";
localparam ZERO_EXTEND_WIDTH = (MEM_ADDRESS_WIDTH > 13) ? MEM_ADDRESS_WIDTH - 13 : 0;
input avl_clk;
input avl_reset_n;
input [AVL_ADDR_WIDTH-1:0] avl_address;
input avl_write;
input [AVL_DATA_WIDTH-1:0] avl_writedata;
input avl_read;
output [AVL_DATA_WIDTH-1:0] avl_readdata;
output avl_waitrequest;
input afi_clk;
input afi_reset_n;
output [MEM_ADDRESS_WIDTH * AFI_RATIO - 1:0] afi_addr;
output [MEM_BANK_WIDTH * AFI_RATIO - 1:0] afi_ba;
output [MEM_CHIP_SELECT_WIDTH * AFI_RATIO - 1:0] afi_cs_n;
output [MEM_CLK_EN_WIDTH * AFI_RATIO - 1:0] afi_cke;
output [MEM_ODT_WIDTH * AFI_RATIO - 1:0] afi_odt;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_ras_n;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_cas_n;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_we_n;
output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_dqs_burst;
output [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_wdata;
output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_wdata_valid;
output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1:0] afi_dm;
output [AFI_RATIO-1:0] afi_rdata_en;
output [AFI_RATIO-1:0] afi_rdata_en_full;
input [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_rdata;
input [AFI_RATIO-1:0] afi_rdata_valid;
input csr_clk;
input csr_ena;
input csr_dout_phy;
output csr_dout;
parameter AC_BUS_WIDTH = 30;
wire [AC_BUS_WIDTH - 1:0] ac_bus;
rw_manager_generic rw_mgr_inst (
.avl_clk(avl_clk),
.avl_reset_n(avl_reset_n),
.avl_address(avl_address),
.avl_write(avl_write),
.avl_writedata(avl_writedata),
.avl_read(avl_read),
.avl_readdata(avl_readdata),
.avl_waitrequest(avl_waitrequest),
.afi_clk(afi_clk),
.afi_reset_n(afi_reset_n),
.ac_masked_bus (afi_cs_n),
.ac_bus (ac_bus),
.afi_wdata(afi_wdata),
.afi_dm(afi_dm),
.afi_odt(afi_odt),
.afi_rdata(afi_rdata),
.afi_rdata_valid(afi_rdata_valid),
.csr_clk(csr_clk),
.csr_ena(csr_ena),
.csr_dout_phy(csr_dout_phy),
.csr_dout(csr_dout)
);
defparam rw_mgr_inst.AVL_DATA_WIDTH = AVL_DATA_WIDTH;
defparam rw_mgr_inst.AVL_ADDRESS_WIDTH = AVL_ADDR_WIDTH;
defparam rw_mgr_inst.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam rw_mgr_inst.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam rw_mgr_inst.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam rw_mgr_inst.AC_BUS_WIDTH = AC_BUS_WIDTH;
defparam rw_mgr_inst.AC_MASKED_BUS_WIDTH = MEM_CHIP_SELECT_WIDTH * AFI_RATIO;
defparam rw_mgr_inst.MASK_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam rw_mgr_inst.AFI_RATIO = AFI_RATIO;
defparam rw_mgr_inst.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam rw_mgr_inst.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam rw_mgr_inst.RATE = RATE;
defparam rw_mgr_inst.HCX_COMPAT_MODE = HCX_COMPAT_MODE;
defparam rw_mgr_inst.DEVICE_FAMILY = DEVICE_FAMILY;
defparam rw_mgr_inst.DEBUG_READ_DI_WIDTH = 32;
defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = 0;
defparam rw_mgr_inst.AC_ROM_INIT_FILE_NAME = AC_ROM_INIT_FILE_NAME;
defparam rw_mgr_inst.INST_ROM_INIT_FILE_NAME = INST_ROM_INIT_FILE_NAME;
defparam rw_mgr_inst.AC_ODT_BIT =
(AFI_RATIO == 2) ? 24 :
23;
generate
begin
if (AFI_RATIO == 2) begin
wire [MEM_ADDRESS_WIDTH-1:0] afi_address_half;
assign afi_address_half = ac_bus[12:0];
assign afi_addr = {AFI_RATIO{afi_address_half}};
assign afi_ba = {AFI_RATIO{ac_bus[MEM_BANK_WIDTH - 1 + 13:13]}};
assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
assign afi_dqs_burst = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[20]}}, {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[19]}}};
assign afi_rdata_en_full[0] = ac_bus[21];
assign afi_rdata_en[0] = ac_bus[22];
assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[23]}};
assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[25]}};
end else begin
wire [MEM_ADDRESS_WIDTH-1:0] afi_address_half;
assign afi_address_half = ac_bus[12:0];
assign afi_addr = {AFI_RATIO{afi_address_half}};
assign afi_ba = {AFI_RATIO{ac_bus[MEM_BANK_WIDTH - 1 + 13:13]}};
assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
assign afi_dqs_burst = {(MEM_WRITE_DQS_WIDTH * AFI_RATIO){ac_bus[19]}};
assign afi_rdata_en_full[0] = ac_bus[20];
assign afi_rdata_en[0] = ac_bus[21];
assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[22]}};
assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[24]}};
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_di_buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [35:0] data;
input [1:0] rdaddress;
input [1:0] wraddress;
input wren;
output [35:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [35:0] sub_wire0;
wire [35:0] q = sub_wire0[35:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({36{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 4,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 2,
altsyncram_component.width_a = 36,
altsyncram_component.width_b = 36,
altsyncram_component.width_byteena_a = 1;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_di_buffer_wrap(
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter DATA_WIDTH = 18;
parameter READ_DATA_SIZE = 9;
parameter WRITE_TO_READ_RATIO_2_EXPONENT = 2;
localparam WRITE_TO_READ_RATIO = 2 ** WRITE_TO_READ_RATIO_2_EXPONENT;
input clock;
input [DATA_WIDTH-1:0] data;
input [WRITE_TO_READ_RATIO_2_EXPONENT + 1 : 0] rdaddress;
input [1:0] wraddress;
input wren;
output [READ_DATA_SIZE - 1 : 0] q;
wire [DATA_WIDTH-1:0] q_wire;
rw_manager_di_buffer rw_manager_di_buffer_i(
.clock(clock),
.data(data),
.rdaddress(rdaddress[WRITE_TO_READ_RATIO_2_EXPONENT + 1 : WRITE_TO_READ_RATIO_2_EXPONENT]),
.wraddress(wraddress),
.wren(wren),
.q(q_wire));
generate
if(WRITE_TO_READ_RATIO_2_EXPONENT > 0) begin
rw_manager_datamux rw_manager_datamux_i(
.datain(q_wire),
.sel(rdaddress[WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0]),
.dataout(q)
);
defparam rw_manager_datamux_i.DATA_WIDTH = READ_DATA_SIZE;
defparam rw_manager_datamux_i.SELECT_WIDTH = WRITE_TO_READ_RATIO_2_EXPONENT;
defparam rw_manager_datamux_i.NUMBER_OF_CHANNELS = WRITE_TO_READ_RATIO;
end
else begin
assign q = q_wire;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_dm_decoder(ck, reset_n, code, pattern);
parameter AFI_RATIO = "";
input ck;
input reset_n;
input [2:0] code;
output [2 * AFI_RATIO - 1 : 0] pattern;
reg [2:0] code_R;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
code_R <= 3'b000;
end
else begin
code_R <= code;
end
end
assign pattern[0] = code_R[2];
assign pattern[1] = code_R[1];
generate
if (AFI_RATIO == 2) begin
assign pattern[2] = code_R[2] ^ code_R[0];
assign pattern[3] = code_R[1] ^ code_R[0];
end else if (AFI_RATIO == 4) begin
assign pattern[2] = code_R[2] ^ code_R[0];
assign pattern[3] = code_R[1] ^ code_R[0];
assign pattern[4] = code_R[2];
assign pattern[5] = code_R[1];
assign pattern[6] = code_R[2] ^ code_R[0];
assign pattern[7] = code_R[1] ^ code_R[0];
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_inst_ROM_no_ifdef_params (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter ROM_INIT_FILE_NAME = "inst_ROM.hex";
input clock;
input [19:0] data;
input [6:0] rdaddress;
input [6:0] wraddress;
input wren;
output [19:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [19:0] sub_wire0;
wire [19:0] q = sub_wire0[19:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (rdaddress),
.wren_a (1'b0),
.data_a ({20{1'b1}}),
.q_a (sub_wire0),
.address_b ({7{1'b0}}),
.q_b (),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({20{1'b1}}),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "inst_ROM.rif",
`else
altsyncram_component.init_file = ROM_INIT_FILE_NAME,
`endif
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.operation_mode = "ROM",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 20,
altsyncram_component.width_b = 20,
altsyncram_component.width_byteena_a = 1;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_inst_ROM_reg(
rdaddress,
clock,
data,
wraddress,
wren,
q);
parameter INST_ROM_DATA_WIDTH = "";
parameter INST_ROM_ADDRESS_WIDTH = "";
input [(INST_ROM_ADDRESS_WIDTH-1):0] rdaddress;
input clock;
input [(INST_ROM_ADDRESS_WIDTH-1):0] wraddress;
input [(INST_ROM_DATA_WIDTH-1):0] data;
input wren;
output reg [(INST_ROM_DATA_WIDTH-1):0] q;
reg [(INST_ROM_DATA_WIDTH-1):0] inst_mem[(2**INST_ROM_ADDRESS_WIDTH-1):0];
always @(posedge clock)
begin
if (wren)
inst_mem[wraddress]<= data;
q <= inst_mem[rdaddress];
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_jumplogic(
ck,
reset_n,
cntr_value,
cntr_load,
reg_select,
reg_load_select,
jump_value,
jump_load,
jump_check,
jump_taken,
jump_address,
cntr_3
);
parameter DATA_WIDTH = 8;
input ck;
input reset_n;
input [DATA_WIDTH-1:0] cntr_value;
input cntr_load;
input [1:0] reg_select;
input [1:0] reg_load_select;
input [DATA_WIDTH-1:0] jump_value;
input jump_load;
input jump_check;
output jump_taken;
output [DATA_WIDTH-1:0] jump_address;
output [DATA_WIDTH-1:0] cntr_3;
reg [7:0] cntr [0:3];
reg [7:0] cntr_shadow [0:3];
reg [7:0] jump_pointers [0:3];
wire [3:0] comparisons;
assign jump_address = jump_pointers[reg_select];
assign jump_taken = (jump_check & ~comparisons[reg_select]);
assign cntr_3 = cntr[3];
genvar c;
generate
for(c = 0; c < 4; c = c + 1)
begin : jumpcounter
assign comparisons[c] = (cntr[c] == 8'b00000000);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
cntr[c] <= {DATA_WIDTH{1'b0}};
end
else if (cntr_load && reg_load_select == c) begin
cntr[c] <= cntr_value;
end
else if (jump_check && reg_select == c) begin
cntr[c] <= (comparisons[c]) ? cntr_shadow[c] : cntr[c] - 1'b1;
end
end
end
endgenerate
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
jump_pointers[0] <= {DATA_WIDTH{1'b0}};
jump_pointers[1] <= {DATA_WIDTH{1'b0}};
jump_pointers[2] <= {DATA_WIDTH{1'b0}};
jump_pointers[3] <= {DATA_WIDTH{1'b0}};
cntr_shadow[0] <= {DATA_WIDTH{1'b0}};
cntr_shadow[1] <= {DATA_WIDTH{1'b0}};
cntr_shadow[2] <= {DATA_WIDTH{1'b0}};
cntr_shadow[3] <= {DATA_WIDTH{1'b0}};
end
else begin
if(jump_load) begin
jump_pointers[0] <= (reg_load_select == 2'b00)? jump_value : jump_pointers[0];
jump_pointers[1] <= (reg_load_select == 2'b01)? jump_value : jump_pointers[1];
jump_pointers[2] <= (reg_load_select == 2'b10)? jump_value : jump_pointers[2];
jump_pointers[3] <= (reg_load_select == 2'b11)? jump_value : jump_pointers[3];
end
if(cntr_load) begin
cntr_shadow[0] <= (reg_load_select == 2'b00)? cntr_value : cntr_shadow[0];
cntr_shadow[1] <= (reg_load_select == 2'b01)? cntr_value : cntr_shadow[1];
cntr_shadow[2] <= (reg_load_select == 2'b10)? cntr_value : cntr_shadow[2];
cntr_shadow[3] <= (reg_load_select == 2'b11)? cntr_value : cntr_shadow[3];
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr12(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [11:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 12'b101001101011;
end
else if(ena) begin
word[11] <= word[0];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6] ^ word[0];
word[4] <= word[5];
word[3] <= word[4] ^ word[0];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1] ^ word[0];
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr36(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [35:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 36'hF0F0AA55;
end
else if(ena) begin
word[35] <= word[0];
word[34] <= word[35];
word[33] <= word[34];
word[32] <= word[33];
word[31] <= word[32];
word[30] <= word[31];
word[29] <= word[30];
word[28] <= word[29];
word[27] <= word[28];
word[26] <= word[27];
word[25] <= word[26];
word[24] <= word[25] ^ word[0];
word[23] <= word[24];
word[22] <= word[23];
word[21] <= word[22];
word[20] <= word[21];
word[19] <= word[20];
word[18] <= word[19];
word[17] <= word[18];
word[16] <= word[17];
word[15] <= word[16];
word[14] <= word[15];
word[13] <= word[14];
word[12] <= word[13];
word[11] <= word[12];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6];
word[4] <= word[5];
word[3] <= word[4];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1];
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr72(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [71:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 72'hAAF0F0AA55F0F0AA55;
end
else if(ena) begin
word[71] <= word[0];
word[70:66] <= word[71:67];
word[65] <= word[66] ^ word[0];
word[64:25] <= word[65:26];
word[24] <= word[25] ^ word[0];
word[23:19] <= word[24:20];
word[18] <= word[19] ^ word[0];
word[17:0] <= word[18:1];
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_pattern_fifo (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [8:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
output [8:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({9{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 9,
altsyncram_component.width_b = 9,
altsyncram_component.width_byteena_a = 1;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram
(
data,
rdaddress,
wraddress,
wren, clock,
q
);
parameter DATA_WIDTH=36;
parameter ADDR_WIDTH=8;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] rdaddress, wraddress;
input wren, clock;
output reg [(DATA_WIDTH-1):0] q;
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clock)
begin
if (wren)
ram[wraddress] <= data[DATA_WIDTH-1:0];
q <= ram[rdaddress];
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram_csr #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 2,
parameter NUM_WORDS = 4
) (
input csr_clk,
input csr_ena,
input csr_din,
input ram_clk,
input wren,
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] wraddress,
input [(ADDR_WIDTH-1):0] rdaddress,
output reg [(DATA_WIDTH-1):0] q,
output reg csr_dout
);
localparam integer DATA_COUNT = DATA_WIDTH*NUM_WORDS;
reg [DATA_COUNT-1:0] all_data;
wire [DATA_COUNT-1:0] load_data;
wire [DATA_WIDTH-1:0] row_data [NUM_WORDS-1:0];
wire int_clk;
assign int_clk = (~csr_ena)? csr_clk : ram_clk;
always @(posedge int_clk)
begin
if (~csr_ena)
all_data <= {all_data[DATA_COUNT-2:0], csr_din};
else if (wren)
all_data <= load_data;
else
all_data <= all_data;
q <= row_data[rdaddress];
end
always @(negedge csr_clk)
begin
csr_dout <= all_data[DATA_COUNT-1];
end
generate
genvar i;
for (i = 0; i < (NUM_WORDS); i = i + 1)
begin: row_assign
assign row_data[i] = all_data[(DATA_WIDTH*(i+1)-1) : (DATA_WIDTH*i)];
end
endgenerate
generate
genvar j,k;
for (j = 0; j < (NUM_WORDS); j = j + 1)
begin: row
for (k = 0; k < (DATA_WIDTH); k = k + 1)
begin: column
assign load_data[(DATA_WIDTH*j)+k] = (wraddress == j)? data[k] : all_data[(DATA_WIDTH*j)+k];
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_read_datapath(
ck,
reset_n,
check_do,
check_dm,
check_do_lfsr,
check_dm_lfsr,
check_pattern_push,
clear_error,
read_data,
read_data_valid,
error_word
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input [3:0] check_do;
input [2:0] check_dm;
input check_do_lfsr;
input check_dm_lfsr;
input check_pattern_push;
input clear_error;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input read_data_valid;
output [DATA_WIDTH - 1 : 0] error_word;
reg [4:0] pattern_radd;
reg [4:0] pattern_wadd;
wire [4:0] pattern_radd_next;
wire [8:0] check_word_write = { check_do, check_dm, check_do_lfsr, check_dm_lfsr };
wire [8:0] check_word_read;
wire [3:0] check_do_read = check_word_read[8:5];
wire [2:0] check_dm_read = check_word_read[4:2];
wire check_do_lfsr_read = check_word_read[1];
wire check_dm_lfsr_read = check_word_read[0];
wire [DATA_BUS_SIZE - 1 : 0] do_data;
wire [NUMBER_OF_WORDS - 1 : 0] dm_data;
wire do_lfsr_step = check_do_lfsr_read & read_data_valid;
wire dm_lfsr_step = check_dm_lfsr_read & read_data_valid;
rw_manager_bitcheck bitcheck_i(
.ck(ck),
.reset_n(reset_n),
.clear(clear_error),
.enable(read_data_valid),
.read_data(read_data),
.reference_data(do_data),
.mask(dm_data),
.error_word(error_word)
);
defparam bitcheck_i.DATA_WIDTH = DATA_WIDTH;
defparam bitcheck_i.AFI_RATIO = AFI_RATIO;
rw_manager_write_decoder write_decoder_i(
.ck(ck),
.reset_n(reset_n),
.do_lfsr(check_do_lfsr_read),
.dm_lfsr(check_dm_lfsr_read),
.do_lfsr_step(do_lfsr_step),
.dm_lfsr_step(dm_lfsr_step),
.do_code(check_do_read),
.dm_code(check_dm_read),
.do_data(do_data),
.dm_data(dm_data)
);
defparam write_decoder_i.DATA_WIDTH = DATA_WIDTH;
defparam write_decoder_i.AFI_RATIO = AFI_RATIO;
rw_manager_pattern_fifo pattern_fifo_i(
.clock(ck),
.data(check_word_write),
.rdaddress(pattern_radd_next),
.wraddress(pattern_wadd),
.wren(check_pattern_push),
.q(check_word_read)
);
assign pattern_radd_next = pattern_radd + (read_data_valid ? 1'b1 : 1'b0);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end
else begin
if (clear_error) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end else begin
if(read_data_valid) begin
pattern_radd <= pattern_radd + 1'b1;
end
if(check_pattern_push) begin
pattern_wadd <= pattern_wadd + 1'b1;
end
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_write_decoder(
ck,
reset_n,
do_lfsr,
dm_lfsr,
do_lfsr_step,
dm_lfsr_step,
do_code,
dm_code,
do_data,
dm_data
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DO_LFSR_WIDTH = ((AFI_RATIO == 4) ? 72 : 36);
input ck;
input reset_n;
input do_lfsr;
input dm_lfsr;
input do_lfsr_step;
input dm_lfsr_step;
input [3:0] do_code;
input [2:0] dm_code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_data;
output [NUMBER_OF_WORDS-1:0] dm_data;
reg do_lfsr_r;
reg dm_lfsr_r;
wire [DO_LFSR_WIDTH-1:0] do_lfsr_word;
wire [11:0] dm_lfsr_word;
wire [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_word;
wire [NUMBER_OF_WORDS -1 : 0] dm_word;
rw_manager_data_decoder DO_decoder(
.ck(ck),
.reset_n(reset_n),
.code(do_code),
.pattern(do_word)
);
defparam DO_decoder.DATA_WIDTH = DATA_WIDTH;
defparam DO_decoder.AFI_RATIO = AFI_RATIO;
rw_manager_dm_decoder DM_decoder_i(
.ck(ck),
.reset_n(reset_n),
.code(dm_code),
.pattern(dm_word)
);
defparam DM_decoder_i.AFI_RATIO = AFI_RATIO;
generate
begin
if (AFI_RATIO == 4) begin
rw_manager_lfsr72 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end else begin
rw_manager_lfsr36 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end
end
endgenerate
rw_manager_lfsr12 dm_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(dm_lfsr_step),
.word(dm_lfsr_word)
);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
do_lfsr_r <= 1'b0;
dm_lfsr_r <= 1'b0;
end
else begin
do_lfsr_r <= do_lfsr;
dm_lfsr_r <= dm_lfsr;
end
end
assign do_data = (do_lfsr_r) ? do_lfsr_word[2 * DATA_WIDTH * AFI_RATIO - 1 : 0] : do_word;
assign dm_data = (dm_lfsr_r) ? dm_lfsr_word[NUMBER_OF_WORDS+1: 2] : dm_word;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module sequencer_scc_acv_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 8
)
(
avl_writedata,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
// Arria V and Cyclone V only have dqse_phase control
// phase decoding.
output [3:0] dqse_phase;
reg [3:0] dqse_phase;
always @ (*) begin
// DQSE = 270
dqse_phase = 4'b0110;
case (avl_writedata[2:0])
3'b000: // DQSE = 90
begin
dqse_phase = 4'b0010;
end
3'b001: // DQSE = 135
begin
dqse_phase = 4'b0011;
end
3'b010: // DQSE = 180
begin
dqse_phase = 4'b0100;
end
3'b011: // DQSE = 225
begin
dqse_phase = 4'b0101;
end
3'b100: // DQSE = 270
begin
dqse_phase = 4'b0110;
end
3'b101: // DQSE = 315
begin
dqse_phase = 4'b1111;
end
3'b110: // DQSE = 360
begin
dqse_phase = 4'b1000;
end
3'b111: // DQSE = 405
begin
dqse_phase = 4'b1001;
end
default : begin end
endcase
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sequencer_scc_reg_file (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter WIDTH = "";
parameter DEPTH = "";
input clock;
input [WIDTH-1:0] data;
input [DEPTH-1:0] rdaddress;
input [DEPTH-1:0] wraddress;
input wren;
output [WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [WIDTH-1:0] sub_wire0;
wire [WIDTH-1:0] q = sub_wire0[WIDTH-1:0];
altdpram altdpram_component (
.data (data),
.outclock (clock),
.rdaddress (rdaddress),
.wren (wren),
.inclock (clock),
.wraddress (wraddress),
.q (sub_wire0),
.aclr (1'b0),
.byteena (1'b1),
.inclocken (1'b1),
.outclocken (1'b1),
.rdaddressstall (1'b0),
.rden (1'b1),
.wraddressstall (1'b0));
defparam
altdpram_component.indata_aclr = "OFF",
altdpram_component.indata_reg = "INCLOCK",
altdpram_component.intended_device_family = "Stratix IV",
altdpram_component.lpm_type = "altdpram",
altdpram_component.outdata_aclr = "OFF",
altdpram_component.outdata_reg = "UNREGISTERED",
altdpram_component.ram_block_type = "MLAB",
altdpram_component.rdaddress_aclr = "OFF",
altdpram_component.rdaddress_reg = "UNREGISTERED",
altdpram_component.rdcontrol_aclr = "OFF",
altdpram_component.rdcontrol_reg = "UNREGISTERED",
altdpram_component.width = WIDTH,
altdpram_component.widthad = DEPTH,
altdpram_component.width_byteena = 1,
altdpram_component.wraddress_aclr = "OFF",
altdpram_component.wraddress_reg = "INCLOCK",
altdpram_component.wrcontrol_aclr = "OFF",
altdpram_component.wrcontrol_reg = "INCLOCK";
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module sequencer_scc_siii_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 6
)
(
avl_writedata,
dqsi_phase,
dqs_phase,
dq_phase,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
output [2:0] dqsi_phase;
output [6:0] dqs_phase;
output [6:0] dq_phase;
output [5:0] dqse_phase;
// phase decoding.
reg [2:0] dqsi_phase;
reg [6:0] dqs_phase;
reg [6:0] dq_phase;
reg [5:0] dqse_phase;
// decode phases
always @ (*) begin
dqsi_phase = 0;
dqs_phase = 0;
dq_phase = 0;
dqse_phase = 0;
case (DLL_DELAY_CHAIN_LENGTH)
6: begin
// DQSin = 60, DQS = 180, DQ = 120, DQSE = 120
dqsi_phase = 3'b000;
dqs_phase = 7'b0010100;
dq_phase = 7'b0001100;
dqse_phase = 6'b001000;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 120, DQSE = 120
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0001100;
dqse_phase = 6'b001000;
end
5'b00001: // DQS = 240, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0010100;
dqse_phase = 6'b001100;
end
5'b00010: // DQS = 300, DQ = 240, DQSE = 240
begin
dqs_phase = 7'b0100110;
dq_phase = 7'b0011100;
dqse_phase = 6'b000110;
end
5'b00011: // DQS = 360, DQ = 300, DQSE = 300
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0001010;
dqse_phase = 6'b001011;
end
5'b00100: // DQS = 420, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0010010;
dqse_phase = 6'b001111;
end
5'b00101: // DQS = 480, DQ = 420, DQSE = 420
begin
dqs_phase = 7'b0100001;
dq_phase = 7'b0011010;
dqse_phase = 6'b000101;
end
5'b00110: // DQS = 540, DQ = 480
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0001101;
end
5'b00111: // DQS = 600, DQ = 540
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0010101;
end
5'b01000: // DQS = 660, DQ = 600
begin
dqs_phase = 7'b0100111;
dq_phase = 7'b0011101;
end
5'b01001: // DQS = 720, DQ = 660
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0001011;
end
5'b01010: // DQS = 780, DQ = 720
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0010011;
end
default : begin end
endcase
end
8: begin
// DQSin = 90, DQS = 180, DQ = 90, DQSE = 90
dqsi_phase = 3'b001;
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001000;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 90, DQSE = 90
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001000;
end
5'b00001: // DQS = 225, DQ = 135, DQSE = 135
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0001100;
dqse_phase = 6'b001100;
end
5'b00010: // DQS = 270, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b0100100;
dq_phase = 7'b0010100;
dqse_phase = 6'b010000;
end
5'b00011: // DQS = 315, DQ = 225, DQSE = 225
begin
dqs_phase = 7'b0101110;
dq_phase = 7'b0011100;
dqse_phase = 6'b000110;
end
5'b00100: // DQS = 360, DQ = 270, DQSE = 270
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0000000;
dqse_phase = 6'b001010;
end
5'b00101: // DQS = 405, DQ = 315, DQSE = 315
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0001010;
dqse_phase = 6'b001111;
end
5'b00110: // DQS = 450, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b0100010;
dq_phase = 7'b0010010;
dqse_phase = 6'b010011;
end
5'b00111: // DQS = 495, DQ = 405, DQSE = 405
begin
dqs_phase = 7'b0101001;
dq_phase = 7'b0011010;
dqse_phase = 6'b000101;
end
5'b01000: // DQS = 540, DQ = 450
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0000110;
end
5'b01001: // DQS = 585, DQ = 495
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0001101;
end
5'b01010: // DQS = 630, DQ = 540
begin
dqs_phase = 7'b0100101;
dq_phase = 7'b0010101;
end
5'b01011: // DQS = 675, DQ = 585
begin
dqs_phase = 7'b0101111;
dq_phase = 7'b0011101;
end
5'b01100: // DQS = 720, DQ = 630
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0000001;
end
5'b01101: // DQS = 765, DQ = 675
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0001011;
end
5'b01110: // DQS = 810, DQ = 720
begin
dqs_phase = 7'b0100011;
dq_phase = 7'b0010011;
end
default : begin end
endcase
end
10: begin
// DQSin = 72, DQS = 180, DQ = 108, DQSE = 108
dqsi_phase = 3'b001;
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 108, DQSE = 108
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
end
5'b00001: // DQS = 216, DQ = 144, DQSE = 144
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0001100;
dqse_phase = 6'b010000;
end
5'b00010: // DQS = 252, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b0100100;
dq_phase = 7'b0010100;
dqse_phase = 6'b010100;
end
5'b00011: // DQS = 288, DQ = 216, DQSE = 216
begin
dqs_phase = 7'b0101110;
dq_phase = 7'b0011100;
dqse_phase = 6'b000110;
end
5'b00100: // DQS = 324, DQ = 252, DQSE = 252
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b0100100;
dqse_phase = 6'b001010;
end
5'b00101: // DQS = 360, DQ = 288, DQSE = 288
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0000010;
dqse_phase = 6'b001111;
end
5'b00110: // DQS = 396, DQ = 324, DQSE = 324
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0001010;
dqse_phase = 6'b010011;
end
5'b00111: // DQS = 432, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b0100010;
dq_phase = 7'b0010010;
dqse_phase = 6'b010111;
end
5'b01000: // DQS = 468, DQ = 396, DQSE = 396
begin
dqs_phase = 7'b0101001;
dq_phase = 7'b0011010;
dqse_phase = 6'b000101;
end
5'b01001: // DQS = 504, DQ = 432, DQSE = 432
begin
dqs_phase = 7'b0110001;
dq_phase = 7'b0100010;
dqse_phase = 6'b001001;
end
5'b01010: // DQS = 540, DQ = 468
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0000101;
end
5'b01011: // DQS = 576, DQ = 504
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0001101;
end
5'b01100: // DQS = 612, DQ = 540
begin
dqs_phase = 7'b0100101;
dq_phase = 7'b0010101;
end
5'b01101: // DQS = 648, DQ = 576
begin
dqs_phase = 7'b0101111;
dq_phase = 7'b0011101;
end
5'b01110: // DQS = 684, DQ = 612
begin
dqs_phase = 7'b0110111;
dq_phase = 7'b0100101;
end
5'b01111: // DQS = 720, DQ = 648
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0000011;
end
5'b10000: // DQS = 756, DQ = 684
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0001011;
end
5'b10001: // DQS = 792, DQ = 720
begin
dqs_phase = 7'b0100011;
dq_phase = 7'b0010011;
end
default : begin end
endcase
end
12: begin
// DQSin = 60, DQS = 180, DQ = 120, DQSE = 90
dqsi_phase = 3'b001;
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 120, DQSE = 90
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
end
5'b00001: // DQS = 210, DQ = 150, DQSE = 120
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0001100;
dqse_phase = 6'b010000;
end
5'b00010: // DQS = 240, DQ = 180, DQSE = 150
begin
dqs_phase = 7'b0100100;
dq_phase = 7'b0010100;
dqse_phase = 6'b010100;
end
5'b00011: // DQS = 270, DQ = 210, DQSE = 180
begin
dqs_phase = 7'b0101100;
dq_phase = 7'b0011100;
dqse_phase = 6'b011000;
end
5'b00100: // DQS = 300, DQ = 240, DQSE = 210
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b0100100;
dqse_phase = 6'b000110;
end
5'b00101: // DQS = 330, DQ = 270, DQSE = 240
begin
dqs_phase = 7'b0111110;
dq_phase = 7'b0101100;
dqse_phase = 6'b001010;
end
5'b00110: // DQS = 360, DQ = 300, DQSE = 270
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0000010;
dqse_phase = 6'b001110;
end
5'b00111: // DQS = 390, DQ = 330, DQSE = 300
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0001010;
dqse_phase = 6'b010011;
end
5'b01000: // DQS = 420, DQ = 360, DQSE = 330
begin
dqs_phase = 7'b0100010;
dq_phase = 7'b0010010;
dqse_phase = 6'b010111;
end
5'b01001: // DQS = 450, DQ = 390, DQSE = 360
begin
dqs_phase = 7'b0101010;
dq_phase = 7'b0011010;
dqse_phase = 6'b011011;
end
5'b01010: // DQS = 480, DQ = 420, DQSE = 390
begin
dqs_phase = 7'b0110001;
dq_phase = 7'b0100010;
dqse_phase = 6'b000101;
end
5'b01011: // DQS = 510, DQ = 450, DQSE = 420
begin
dqs_phase = 7'b0111001;
dq_phase = 7'b0101010;
dqse_phase = 6'b001001;
end
5'b01100: // DQS = 540, DQ = 480
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0000101;
end
5'b01101: // DQS = 570, DQ = 510
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0001101;
end
5'b01110: // DQS = 600, DQ = 540
begin
dqs_phase = 7'b0100101;
dq_phase = 7'b0010101;
end
5'b01111: // DQS = 630, DQ = 570
begin
dqs_phase = 7'b0101101;
dq_phase = 7'b0011101;
end
5'b10000: // DQS = 660, DQ = 600
begin
dqs_phase = 7'b0110111;
dq_phase = 7'b0100101;
end
5'b10001: // DQS = 690, DQ = 630
begin
dqs_phase = 7'b0111111;
dq_phase = 7'b0101101;
end
5'b10010: // DQS = 720, DQ = 660
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0000011;
end
5'b10011: // DQS = 750, DQ = 690
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0001011;
end
5'b10100: // DQS = 780, DQ = 720
begin
dqs_phase = 7'b0100011;
dq_phase = 7'b0010011;
end
5'b10101: // DQS = 810, DQ = 750
begin
dqs_phase = 7'b0101011;
dq_phase = 7'b0011011;
end
default : begin end
endcase
end
default : begin end
endcase
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module sequencer_scc_sv_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 6
)
(
avl_writedata,
dqsi_phase,
dqs_phase,
dq_phase,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
output [2:0] dqsi_phase;
output [6:0] dqs_phase;
output [6:0] dq_phase;
output [5:0] dqse_phase;
reg [2:0] dqsi_phase;
reg [6:0] dqs_phase;
reg [6:0] dq_phase;
reg [5:0] dqse_phase;
always @ (*) begin
dqsi_phase = 3'b010;
dqs_phase = 7'b1110110;
dq_phase = 7'b0110100;
dqse_phase = 6'b000110;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 90, DQSE = 90
begin
dqs_phase = 7'b0010110;
dq_phase = 7'b1000110;
dqse_phase = 6'b000010;
end
5'b00001: // DQS = 225, DQ = 135, DQSE = 135
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b1100110;
dqse_phase = 6'b000011;
end
5'b00010: // DQS = 270, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b1010110;
dq_phase = 7'b0010110;
dqse_phase = 6'b000100;
end
5'b00011: // DQS = 315, DQ = 225, DQSE = 225
begin
dqs_phase = 7'b1110111;
dq_phase = 7'b0110110;
dqse_phase = 6'b000101;
end
5'b00100: // DQS = 360, DQ = 270, DQSE = 270
begin
dqs_phase = 7'b0000111;
dq_phase = 7'b1010110;
dqse_phase = 6'b000110;
end
5'b00101: // DQS = 405, DQ = 315, DQSE = 315
begin
dqs_phase = 7'b0100111;
dq_phase = 7'b1110111;
dqse_phase = 6'b001111;
end
5'b00110: // DQS = 450, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b1001000;
dq_phase = 7'b0000111;
dqse_phase = 6'b001000;
end
5'b00111: // DQS = 495, DQ = 405, DQSE = 405
begin
dqs_phase = 7'b1101000;
dq_phase = 7'b0100111;
dqse_phase = 6'b001001;
end
5'b01000: // DQS = 540, DQ = 450
begin
dqs_phase = 7'b0011000;
dq_phase = 7'b1001000;
end
5'b01001:
begin
dqs_phase = 7'b0111000;
dq_phase = 7'b1101000;
end
5'b01010:
begin
dqs_phase = 7'b1011000;
dq_phase = 7'b0011000;
end
5'b01011:
begin
dqs_phase = 7'b1111001;
dq_phase = 7'b0111000;
end
5'b01100:
begin
dqs_phase = 7'b0001001;
dq_phase = 7'b1011000;
end
5'b01101:
begin
dqs_phase = 7'b0101001;
dq_phase = 7'b1111001;
end
5'b01110:
begin
dqs_phase = 7'b1001010;
dq_phase = 7'b0001001;
end
5'b01111:
begin
dqs_phase = 7'b1101010;
dq_phase = 7'b0101001;
end
5'b10000:
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b1001010;
end
5'b10001:
begin
dqs_phase = 7'b0111010;
dq_phase = 7'b1101010;
end
5'b10010:
begin
dqs_phase = 7'b1011010;
dq_phase = 7'b0011010;
end
5'b10011:
begin
dqs_phase = 7'b1111011;
dq_phase = 7'b0111010;
end
default : begin end
endcase
end
endmodule
|
Subsets and Splits