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// megafunction wizard: %ALTCLKCTRL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclkctrl
// ============================================================
// File Name: AltClkCtl.v
// Megafunction Name(s):
// altclkctrl
//
// Simulation Library Files(s):
// stratixiv
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Periphery clock" DEVICE_FAMILY="Stratix IV" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
//VERSION_BEGIN 11.1 cbx_altclkbuf 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module AltClkCtl_altclkctrl_2re
(
ena,
inclk,
outclk) ;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_outclk;
wire [1:0] clkselect;
stratixiv_clkena sd1
(
.ena(ena),
.enaout(),
.inclk(inclk[0]),
.outclk(wire_sd1_outclk)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
sd1.clock_type = "Auto",
sd1.ena_register_mode = "falling edge",
sd1.lpm_type = "stratixiv_clkena";
assign
clkselect = {2{1'b0}},
outclk = wire_sd1_outclk;
endmodule //AltClkCtl_altclkctrl_2re
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module AltClkCtl (
inclk,
outclk);
input inclk;
output outclk;
wire sub_wire0;
wire sub_wire1 = 1'h1;
wire [2:0] sub_wire4 = 3'h0;
wire outclk = sub_wire0;
wire sub_wire2 = inclk;
wire [3:0] sub_wire3 = {sub_wire4, sub_wire2};
AltClkCtl_altclkctrl_2re AltClkCtl_altclkctrl_2re_component (
.ena (sub_wire1),
.inclk (sub_wire3),
.outclk (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
// Retrieval info: CONSTANT: clock_type STRING "Periphery clock"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl_bb.v TRUE
// Retrieval info: LIB_FILE: stratixiv
|
// megafunction wizard: %ALTCLKCTRL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclkctrl
// ============================================================
// File Name: AltClkCtl.v
// Megafunction Name(s):
// altclkctrl
//
// Simulation Library Files(s):
// stratixiv
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module AltClkCtl (
inclk,
outclk)/* synthesis synthesis_clearbox = 1 */;
input inclk;
output outclk;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
// Retrieval info: CONSTANT: clock_type STRING "Periphery clock"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL AltClkCtl_bb.v TRUE
// Retrieval info: LIB_FILE: stratixiv
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
// synopsys template
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [ADDR_WIDTH-1:0] ADDRA_R;
reg [ADDR_WIDTH-1:0] ADDRB_R;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
wire [DATA_WIDTH-1:0] DOA_noreg;
wire [DATA_WIDTH-1:0] DOB_noreg;
wire [ADDR_WIDTH-1:0] ADDRA_muxed;
wire [ADDR_WIDTH-1:0] ADDRB_muxed;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDRA_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
ADDRB_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
ADDRA_R <= `BSV_ASSIGNMENT_DELAY ADDRA_muxed;
if (ENA) begin
if (WEA)
RAM[ADDRA_muxed] <= `BSV_ASSIGNMENT_DELAY DIA;
end
end
always @(posedge CLKB) begin
ADDRB_R <= `BSV_ASSIGNMENT_DELAY ADDRB_muxed;
if (ENB) begin
if (WEB)
RAM[ADDRB_muxed] <= `BSV_ASSIGNMENT_DELAY DIB;
end
end
// ENA workaround for Synplify
assign ADDRA_muxed = (ENA) ? ADDRA : ADDRA_R;
assign ADDRB_muxed = (ENB) ? ADDRB : ADDRB_R;
// Memory read
assign DOA_noreg = RAM[ADDRA_R];
assign DOB_noreg = RAM[ADDRB_R];
// Pipeline
always @(posedge CLKA)
DOA_R <= DOA_noreg;
always @(posedge CLKB)
DOB_R <= DOB_noreg;
// Output drivers
assign DOA = (PIPELINED) ? DOA_R : DOA_noreg;
assign DOB = (PIPELINED) ? DOB_R : DOB_noreg;
endmodule // BRAM2
|
// ============================================================================
// Copyright (c) 2010 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
// Major Functions/Design Description:
//
// Please refer to DE4_UserManual.pdf in DE4 system CD.
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |Richard |10/06/30 |
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
//`define USE_DDR2_DIMM2
module DE4_DDR2(
//////// CLOCK //////////
GCLKIN,
GCLKOUT_FPGA,
MAX_CONF_D,
MAX_PLL_D,
OSC_50_Bank2,
OSC_50_Bank3,
OSC_50_Bank4,
OSC_50_Bank5,
OSC_50_Bank6,
OSC_50_Bank7,
PLL_CLKIN_p,
//////// LED x 8 //////////
LED,
//////// BUTTON x 4 //////////
BUTTON,
CPU_RESET_n,
EXT_IO,
//////// Ethernet x 4 //////////
ETH_INT_n,
ETH_MDC,
ETH_MDIO,
ETH_RST_n,
ETH_RX_p,
ETH_TX_p,
//////// SDCARD //////////
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_n,
`ifndef USE_DDR2_DIMM2
//////// DDR2 SODIMM //////////
// M1_DDR2_addr,
// M1_DDR2_ba,
// M1_DDR2_cas_n,
// M1_DDR2_cke,
// M1_DDR2_clk,
// M1_DDR2_clk_n,
// M1_DDR2_cs_n,
// M1_DDR2_dm,
// M1_DDR2_dq,
// M1_DDR2_dqs,
// M1_DDR2_dqsn,
// M1_DDR2_odt,
// M1_DDR2_ras_n,
// M1_DDR2_SA,
// M1_DDR2_SCL,
// M1_DDR2_SDA,
// M1_DDR2_we_n,
`else
//////// DDR2 SODIMM //////////
M2_DDR2_addr,
M2_DDR2_ba,
M2_DDR2_cas_n,
M2_DDR2_cke,
M2_DDR2_clk,
M2_DDR2_clk_n,
M2_DDR2_cs_n,
M2_DDR2_dm,
M2_DDR2_dq,
M2_DDR2_dqs,
M2_DDR2_dqsn,
M2_DDR2_odt,
M2_DDR2_ras_n,
M2_DDR2_SA,
M2_DDR2_SCL,
M2_DDR2_SDA,
M2_DDR2_we_n,
`endif //USE_DDR2_DIMM2
termination_blk0_rup_pad,
termination_blk0_rdn_pad,
//////////// DIP SWITCH x 8 //////////
SW,
//////////// SLIDE SWITCH x 4 //////////
SLIDE_SW,
//////////// SEG7 //////////
SEG0_D,
SEG0_DP,
SEG1_D,
SEG1_DP,
//////////// Temperature //////////
TEMP_INT_n,
TEMP_SMCLK,
TEMP_SMDAT,
//////////// Current //////////
CSENSE_ADC_FO,
CSENSE_CS_n,
CSENSE_SCK,
CSENSE_SDI,
CSENSE_SDO,
//////////// Fan //////////
FAN_CTRL,
//////////// Flash and SRAM Address/Data Share Bus //////////
FSM_A,
FSM_D,
//////////// Flash Control //////////
FLASH_ADV_n,
FLASH_CE_n,
FLASH_CLK,
FLASH_OE_n,
FLASH_RESET_n,
FLASH_RYBY_n,
FLASH_WE_n,
//////////// SSRAM Control //////////
SSRAM_ADV,
SSRAM_BWA_n,
SSRAM_BWB_n,
SSRAM_CE_n,
SSRAM_CKE_n,
SSRAM_CLK,
SSRAM_OE_n,
SSRAM_WE_n,
//////////// GPIO_0, GPIO_0 connect to LTM - 4.3" LCD and Touch //////////
lcdtouchLTM_ADC_BUSY,
lcdtouchLTM_ADC_DCLK,
lcdtouchLTM_ADC_DIN,
lcdtouchLTM_ADC_DOUT,
lcdtouchLTM_ADC_PENIRQ_n,
lcdtouchLTM_B,
lcdtouchLTM_DEN,
lcdtouchLTM_G,
lcdtouchLTM_GREST,
lcdtouchLTM_HD,
lcdtouchLTM_NCLK,
lcdtouchLTM_R,
lcdtouchLTM_SCEN,
lcdtouchLTM_SDA,
lcdtouchLTM_VD,
//////////// GPIO_1 connect to MTL capacitive touch screen
mtl_dclk,
mtl_r,
mtl_g,
mtl_b,
mtl_hsd,
mtl_vsd,
mtl_touch_i2cscl,
mtl_touch_i2csda,
mtl_touch_int
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input GCLKIN;
output GCLKOUT_FPGA;
inout [2:0] MAX_CONF_D;
output [2:0] MAX_PLL_D;
input OSC_50_Bank2;
input OSC_50_Bank3;
input OSC_50_Bank4;
input OSC_50_Bank5;
input OSC_50_Bank6;
input OSC_50_Bank7;
input PLL_CLKIN_p;
//////////// Ethernet x 4 //////////
input [3:0] ETH_INT_n;
output [3:0] ETH_MDC;
inout [3:0] ETH_MDIO;
output ETH_RST_n;
//input [3:0] ETH_RX_p;
//output [3:0] ETH_TX_p;
//////////// SDCARD //////////
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_n;
//////////// LED x 8 //////////
output [7:0] LED;
//////////// BUTTON x 4 //////////
input [3:0] BUTTON;
input CPU_RESET_n;
inout EXT_IO;
//////////// DDR2 SODIMM //////////
//output [15:0] M1_DDR2_addr;
//output [2:0] M1_DDR2_ba;
//output M1_DDR2_cas_n;
//output [1:0] M1_DDR2_cke;
//inout [1:0] M1_DDR2_clk;
//inout [1:0] M1_DDR2_clk_n;
//output [1:0] M1_DDR2_cs_n;
//output [7:0] M1_DDR2_dm;
//inout [63:0] M1_DDR2_dq;
//inout [7:0] M1_DDR2_dqs;
//inout [7:0] M1_DDR2_dqsn;
//output [1:0] M1_DDR2_odt;
//output M1_DDR2_ras_n;
//output [1:0] M1_DDR2_SA;
//output M1_DDR2_SCL;
//inout M1_DDR2_SDA;
//output M1_DDR2_we_n;
input termination_blk0_rup_pad;
input termination_blk0_rdn_pad;
//////////// DIP SWITCH x 8 //////////
input [7:0] SW;
//////////// SLIDE SWITCH x 4 //////////
input [3:0] SLIDE_SW;
//////////// SEG7 //////////
output [6:0] SEG0_D;
output SEG0_DP;
output [6:0] SEG1_D;
output SEG1_DP;
//////////// Temperature //////////
input TEMP_INT_n;
output TEMP_SMCLK;
inout TEMP_SMDAT;
//////////// Current //////////
output CSENSE_ADC_FO;
output [1:0] CSENSE_CS_n;
output CSENSE_SCK;
output CSENSE_SDI;
input CSENSE_SDO;
//////////// Fan //////////
output FAN_CTRL;
//////////// Flash and SRAM Address/Data Share Bus //////////
output [25:1] FSM_A;
inout [15:0] FSM_D;
//////////// Flash Control //////////
output FLASH_ADV_n;
output FLASH_CE_n;
output FLASH_CLK;
output FLASH_OE_n;
output FLASH_RESET_n;
input FLASH_RYBY_n;
output FLASH_WE_n;
//////////// SSRAM Control //////////
output SSRAM_ADV;
output SSRAM_BWA_n;
output SSRAM_BWB_n;
output SSRAM_CE_n;
output SSRAM_CKE_n;
output SSRAM_CLK;
output SSRAM_OE_n;
output SSRAM_WE_n;
//////////// GPIO_0, GPIO_0 connect to LTM - 4.3" LCD and Touch //////////
input lcdtouchLTM_ADC_BUSY;
output lcdtouchLTM_ADC_DCLK;
output lcdtouchLTM_ADC_DIN;
input lcdtouchLTM_ADC_DOUT;
input lcdtouchLTM_ADC_PENIRQ_n;
output [7:0] lcdtouchLTM_B;
output lcdtouchLTM_DEN;
output [7:0] lcdtouchLTM_G;
output lcdtouchLTM_GREST;
output lcdtouchLTM_HD;
output lcdtouchLTM_NCLK;
output [7:0] lcdtouchLTM_R;
output lcdtouchLTM_SCEN;
inout lcdtouchLTM_SDA;
output lcdtouchLTM_VD;
/////////// GPIO_1 connected to the capacitive multitouch screen
output mtl_dclk;
output [7:0] mtl_r;
output [7:0] mtl_g;
output [7:0] mtl_b;
output mtl_hsd;
output mtl_vsd;
output mtl_touch_i2cscl;
inout mtl_touch_i2csda;
input mtl_touch_int;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire global_reset_n;
wire enet_reset_n;
//// Ethernet
wire enet_mdc;
wire enet_mdio_in;
wire enet_mdio_oen;
wire enet_mdio_out;
wire enet_refclk_125MHz;
wire lvds_rxp;
wire lvds_txp;
//=======================================================
// Structural coding
//=======================================================
// Assign outputs that are not used to 0
assign MAX_PLL_D = 3'b0;
assign ETH_MDC[3:1] = 3'b0;
assign M1_DDR2_SA = 1'b0;
assign CSENSE_CS_n = 1'b0;
assign CSENSE_ADC_FO = 1'b0;
assign CSENSE_SCK = 1'b0;
assign CSENSE_SDI = 1'b0;
assign GCLKOUT_FPGA = 1'b0;
assign M1_DDR2_SCL = 1'b0;
//// Ethernet
assign ETH_RST_n = enet_reset_n;
input [0:0] ETH_RX_p;
output [0:0] ETH_TX_p;
assign lvds_rxp = ETH_RX_p[0];
assign ETH_TX_p[0] = lvds_txp;
assign enet_mdio_in = ETH_MDIO[0];
assign ETH_MDIO[0] = !enet_mdio_oen ? enet_mdio_out : 1'bz;
assign ETH_MDC[0] = enet_mdc;
wire mipsClk;
wire clk25;
wire [7:0] LED_n;
//wire ddr_sysClk;
//assign SSRAM_CLK = ddr_sysClk;
assign LED = ~LED_n;
// === Ethernet clock PLL
pll_125 pll_125_ins (
.inclk0(OSC_50_Bank4),
.c0(enet_refclk_125MHz),
//.c1(SSRAM_CLK)
);
wire sramClk;
assign SSRAM_CLK=sramClk;
/*
AltClkCtl clkCtl (
.inclk(sramClk),
.outclk(SSRAM_CLK)
);
*/
/****************************************************************************
From Simon's Project
*****************************************************************************/
// synchronize reset signal
reg rstn, rstn_metastable;
always @(posedge OSC_50_Bank2)
begin
rstn_metastable <= CPU_RESET_n;
rstn <= rstn_metastable;
end
// clocks generated by the mail PLL
// KM: removed so prevent errors caused
// by this wierd circuitry in VPR
// instead hook-up to an unused PLL
// input
//(* keep = 1 *) wire clk33;
//(* noprune *) reg rstn33;
wire clk33;
assign clk33 = PLL_CLKIN_p;
reg rstn33;
reg rstn33sample;
always @(posedge clk33)
begin
rstn33sample <= rstn;
rstn33 <= rstn33sample;
end
reg [7:0] SW_P;
always @(posedge OSC_50_Bank2)
SW_P <= ~SW; // positive version of DIP switches
wire [15:0] hexleds;
assign SEG1_DP = ~1'b0;
assign SEG1_D = ~hexleds[14:8];
assign SEG0_DP = ~1'b0;
assign SEG0_D = ~hexleds[6:0];
reg [3:0] slide_sw_metastable, slide_sw_sync;
always @(posedge OSC_50_Bank2)
begin
slide_sw_metastable <= SLIDE_SW;
slide_sw_sync <= slide_sw_metastable;
end
// assign PCIE_WAKE_n = 1'b0;
// assign PCIE_SMBDATA = 1'bz;
// signals for the old Terasic resistive touch screen (currently unused)
wire [7:0] vga_R, vga_G, vga_B;
wire vga_DEN, vga_HD, vga_VD;
assign vga_DEN = 1'b0;
assign vga_HD = 1'b0;
assign vga_VD = 1'b0;
assign vga_R = 8'd0;
assign vga_G = 8'd0;
assign vga_B = 8'd0;
assign lcdtouchLTM_R = vga_R;
assign lcdtouchLTM_G = vga_G;
assign lcdtouchLTM_B = vga_B;
assign lcdtouchLTM_DEN = vga_DEN;
assign lcdtouchLTM_HD = vga_HD;
assign lcdtouchLTM_VD = vga_VD;
assign lcdtouchLTM_GREST = rstn33;
assign lcdtouchLTM_NCLK = clk33;
assign lcdtouchLTM_SCEN = 1'b1;
assign lcdtouchLTM_ADC_DCLK = 1'b1;
assign lcdtouchLTM_ADC_DIN = 1'b1;
// temperature reading and fan control
wire [7:0] temp_val;
reg [7:0] temp_dec_r;
temperature_fan_control fan_speed(
.clk50(OSC_50_Bank2),
.rstn(rstn),
.temperatureDegC(temp_val),
.fanOn(FAN_CTRL));
// display the temperature
always @(posedge OSC_50_Bank2)
begin
temp_dec_r[3:0] <= temp_val % 8'd10;
temp_dec_r[7:4] <= temp_val / 8'd10;
end
hex2leds digit0(.hexval(temp_dec_r[3:0]), .ledcode(hexleds[6:0]));
hex2leds digit1(.hexval(temp_dec_r[7:4]), .ledcode(hexleds[14:8]));
// clock for multitouch screen
assign mtl_dclk = clk33;
(* keep = 1 *) wire ssram_data_outen;
(* keep = 1 *) wire [15:0] ssram_data_out;
// instantiate the touch screen controller provided by Terasic (encrypted block)
wire touch_ready;
wire [9:0] touch_x1, touch_x2;
wire [8:0] touch_y1, touch_y2;
wire [1:0] touch_count;
wire [7:0] touch_gesture;
(* noprune *) reg rstn50;
reg rstn50sample;
always @(posedge OSC_50_Bank2)
begin
rstn50sample <= rstn;
rstn50 <= rstn50sample;
end
/*i2c_touch_config touch(
.iCLK(OSC_50_Bank2),
.iRSTN(rstn50),
.iTRIG(!mtl_touch_int), // note that this signal is inverted
.oREADY(touch_ready),
.oREG_X1(touch_x1),
.oREG_Y1(touch_y1),
.oREG_X2(touch_x2),
.oREG_Y2(touch_y2),
.oREG_TOUCH_COUNT(touch_count),
.oREG_GESTURE(touch_gesture),
.I2C_SCLK(mtl_touch_i2cscl),
.I2C_SDAT(mtl_touch_i2csda));*/
/****************************************************************************
End
*****************************************************************************/
DE4_SOPC DE4_SOPC_inst(
// 1) global signals:
.clk_50(OSC_50_Bank4),
.reset_reset_n(rstn),
.leds_external_connection_export(LED_n),
// the_ddr2
.ddr2_global_reset_reset_n(),
// .memory_mem_cke (M1_DDR2_cke), // ddr2.cke
// .memory_mem_ck_n (M1_DDR2_clk_n), // .ck_n
// .memory_mem_cas_n (M1_DDR2_cas_n), // .cas_n
// .memory_mem_dq (M1_DDR2_dq), // .dq
// .memory_mem_dqs (M1_DDR2_dqs), // .dqs
// .memory_mem_odt (M1_DDR2_odt), // .odt
// .memory_mem_cs_n (M1_DDR2_cs_n), // .cs_n
// .memory_mem_ba (M1_DDR2_ba), // .ba
// .memory_mem_dm (M1_DDR2_dm), // .dm
// .memory_mem_we_n (M1_DDR2_we_n), // .we_n
// .memory_mem_dqs_n (M1_DDR2_dqsn), // .dqs_n
// .memory_mem_ras_n (M1_DDR2_ras_n), // .ras_n
// .memory_mem_ck (M1_DDR2_clk), // .ck
// .memory_mem_a (M1_DDR2_addr), // .a
// .oct_rup (termination_blk0_rup_pad), // .oct_rup
// .oct_rdn (termination_blk0_rdn_pad), // .oct_rdn
// ddr2 psd i2c
// .out_port_from_the_ddr2_i2c_scl(M1_DDR2_SCL),
// .out_port_from_the_ddr2_i2c_sa(M1_DDR2_SA),
// .bidir_port_to_and_from_the_ddr2_i2c_sda(M1_DDR2_SDA)
/*
output wire ddr2_aux_full_rate_clk_out, // ddr2_auxfull.clk
output wire ddr2_aux_half_rate_clk_out, // ddr2_auxhalf.clk
output wire local_init_done_from_the_ddr2, // .local_init_done
input wire mipsClk, // mipsClk_clk_in.clk
output wire ddr2_phy_clk_out, // sysclk_out_clk.clk
*/
// the_tse_mac
//.mac_mdio_out (enet_mdio_out), // mac.mdio_out
//.mac_mdio_oen (enet_mdio_oen), // .mdio_oen
//.mac_mdio_in (enet_mdio_in), // .mdio_in
//.mac_mdc (enet_mdc), // .mdc
//.mac_led_an (led_an_from_the_tse_mac), // mac.led_an
//.mac_led_char_err (led_char_err_from_the_tse_mac), // .led_char_err
// led_col_from_the_tse_mac?
// led_crs_from_the_tse_mac?
//.mac_led_link (led_link_from_the_tse_mac), // .led_link
//.mac_led_disp_err (led_disp_err_from_the_tse_mac), // .led_disp_err
//.mac_txp (lvds_txp), // .txp
//.mac_rxp (lvds_rxp), // .rxp
//.mac_ref_clk (enet_refclk_125MHz), // .ref_clk
.sd_b_SD_cmd (SD_CMD), // sd.b_SD_cmd
.sd_b_SD_dat (SD_DAT[0]), // .b_SD_dat
.sd_b_SD_dat3 (SD_DAT[3]), // .b_SD_dat3
.sd_o_SD_clock (SD_CLK), // .o_SD_clock
.mem_ssram_adv (SSRAM_ADV), // fbssram_1.ssram_adv
.mem_ssram_bwa_n (SSRAM_BWA_n), // .ssram_bwa_n
.mem_ssram_bwb_n (SSRAM_BWB_n), // .ssram_bwb_n
.mem_ssram_ce_n (SSRAM_CE_n), // .ssram_ce_n
.mem_ssram_cke_n (SSRAM_CKE_n), // .ssram_cke_n
.mem_ssram_oe_n (SSRAM_OE_n), // .ssram_oe_n
.mem_ssram_we_n (SSRAM_WE_n), // .ssram_we_n
.mem_fsm_a (FSM_A), // .fsm_a
.mem_fsm_d_out (ssram_data_out), // .fsm_d_out
.mem_fsm_d_in (FSM_D), // .fsm_d_in
.mem_fsm_dout_req (ssram_data_outen), // .fsm_dout_req
.mem_flash_adv_n (FLASH_ADV_n),
.mem_flash_ce_n (FLASH_CE_n),
.mem_flash_clk (FLASH_CLK),
.mem_flash_oe_n (FLASH_OE_n),
.mem_flash_we_n (FLASH_WE_n),
.touch_x1 (touch_x1), // .touch_x1
.touch_y1 (touch_y1), // .touch_y1
.touch_x2 (touch_x2), // .touch_x2
.touch_y2 (touch_y2), // .touch_y2
.touch_count_gesture ({touch_count,touch_gesture}), // .touch_count_gesture
.touch_touch_valid (touch_ready), // .touch_touch_valid
.mtl_lcd_r (mtl_r), // mtl_1.r
.mtl_lcd_g (mtl_g), // .g
.mtl_lcd_b (mtl_b), // .b
.mtl_lcd_hsd (mtl_hsd), // .hsd
.mtl_lcd_vsd (mtl_vsd), // .vsd
.sram_clk_clk (sramClk), // sram_clk.clk
// .sram_clk_clk (SSRAM_CLK)
// .display_clk_clk (clk33),
.switches_export ({SLIDE_SW[3:0], BUTTON[3:0], SW_P[7:0]})
);
// handle unused flash reset signal
assign FLASH_RESET_n = rstn;
// handle tristate ssram data bus
assign FSM_D = ssram_data_outen ? ssram_data_out : 16'bzzzzzzzzzzzzzzzz;
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST_N,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
// synopsys template
parameter width = 1;
parameter guarded = 1;
input CLK;
input RST_N;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK /* or negedge RST_N */ )
begin
if (!RST_N)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST_N == 0)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
always@(posedge CLK /* or negedge RST_N */)
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (!RST_N)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( RST_N )
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if ( RST_N )
end
// synopsys translate_on
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Depth 2 FIFO
module FIFO2(CLK,
RST_N,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
// synopsys template
parameter width = 1;
parameter guarded = 1;
input CLK ;
input RST_N ;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg full_reg;
reg empty_reg;
reg [width - 1 : 0] data0_reg;
reg [width - 1 : 0] data1_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
assign D_OUT = data0_reg ;
// Optimize the loading logic since state encoding is not power of 2!
wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
wire d0d1 = DEQ && ! full_reg ;
wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
wire d1di = ENQ & empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
data0_reg = {((width + 1)/2) {2'b10}} ;
data1_reg = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0;
full_reg = 1'b1;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK /* or negedge RST_N */)
begin
if (!RST_N)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST_N == 0)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (CLR)
else if ( ENQ && ! DEQ ) // just enq
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
end
else if ( DEQ && ! ENQ )
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if ( DEQ && ! ENQ )
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
always@(posedge CLK /* or negedge RST_N */ )
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (!RST_N)
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY
{width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
data1_reg <= `BSV_ASSIGNMENT_DELAY
d1di ? D_IN : data1_reg ;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( RST_N )
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1;
$display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1;
$display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ;
end
end
end // always@ (posedge CLK)
// synopsys translate_on
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Depth 1 FIFO
// Allows simultaneous ENQ and DEQ (at the expense of potentially
// causing combinational loops).
module FIFOL1(CLK,
RST_N,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
// synopsys template
parameter width = 1;
input CLK;
input RST_N;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg empty_reg ;
reg [width - 1 : 0] D_OUT;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ;
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg || DEQ;
assign EMPTY_N = empty_reg ;
always@(posedge CLK /* or negedge RST_N */ )
begin
if (!RST_N)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
always@(posedge CLK /* or negedge RST_N */ )
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (!RST_N)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && ! DEQ)
begin
enqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ;
end
end
// synopsys translate_on
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: MIPSPLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MIPSPLL (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 2,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=MIPSPLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "MIPSPLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: MIPSPLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module MIPSPLL (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "MIPSPLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MIPSPLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Thu Aug 16 11:48:36 BST 2012
//
// Method conflict info:
// Method: asi_stream_in
// Conflict-free: asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
// Conflicts: asi_stream_in
//
// Method: asi_stream_in_ready
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_r
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_g
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_b
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_hsd
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_vsd
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
//
// Ports:
// Name I/O size props
// asi_stream_in_ready O 1
// coe_tpadlcd_mtl_r O 8 reg
// coe_tpadlcd_mtl_g O 8 reg
// coe_tpadlcd_mtl_b O 8 reg
// coe_tpadlcd_mtl_hsd O 1 reg
// coe_tpadlcd_mtl_vsd O 1 reg
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// asi_stream_in_data I 24
// asi_stream_in_valid I 1
// asi_stream_in_startofpacket I 1
// asi_stream_in_endofpacket I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkAvalonStream2MTL_LCD24bit(csi_clockreset_clk,
csi_clockreset_reset_n,
asi_stream_in_data,
asi_stream_in_valid,
asi_stream_in_startofpacket,
asi_stream_in_endofpacket,
asi_stream_in_ready,
coe_tpadlcd_mtl_r,
coe_tpadlcd_mtl_g,
coe_tpadlcd_mtl_b,
coe_tpadlcd_mtl_hsd,
coe_tpadlcd_mtl_vsd);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method asi_stream_in
input [23 : 0] asi_stream_in_data;
input asi_stream_in_valid;
input asi_stream_in_startofpacket;
input asi_stream_in_endofpacket;
// value method asi_stream_in_ready
output asi_stream_in_ready;
// value method coe_tpadlcd_mtl_r
output [7 : 0] coe_tpadlcd_mtl_r;
// value method coe_tpadlcd_mtl_g
output [7 : 0] coe_tpadlcd_mtl_g;
// value method coe_tpadlcd_mtl_b
output [7 : 0] coe_tpadlcd_mtl_b;
// value method coe_tpadlcd_mtl_hsd
output coe_tpadlcd_mtl_hsd;
// value method coe_tpadlcd_mtl_vsd
output coe_tpadlcd_mtl_vsd;
// signals for module outputs
wire [7 : 0] coe_tpadlcd_mtl_b, coe_tpadlcd_mtl_g, coe_tpadlcd_mtl_r;
wire asi_stream_in_ready, coe_tpadlcd_mtl_hsd, coe_tpadlcd_mtl_vsd;
// inlined wires
wire [26 : 0] streamIn_d_dw$wget;
// register lcdtiming_hsd
reg lcdtiming_hsd;
wire lcdtiming_hsd$D_IN, lcdtiming_hsd$EN;
// register lcdtiming_pixel_out
reg [24 : 0] lcdtiming_pixel_out;
wire [24 : 0] lcdtiming_pixel_out$D_IN;
wire lcdtiming_pixel_out$EN;
// register lcdtiming_vsd
reg lcdtiming_vsd;
wire lcdtiming_vsd$D_IN, lcdtiming_vsd$EN;
// register lcdtiming_x
reg [11 : 0] lcdtiming_x;
wire [11 : 0] lcdtiming_x$D_IN;
wire lcdtiming_x$EN;
// register lcdtiming_y
reg [11 : 0] lcdtiming_y;
wire [11 : 0] lcdtiming_y$D_IN;
wire lcdtiming_y$EN;
// ports of submodule lcdtiming_pixel_buf
wire [24 : 0] lcdtiming_pixel_buf$D_IN, lcdtiming_pixel_buf$D_OUT;
wire lcdtiming_pixel_buf$CLR,
lcdtiming_pixel_buf$DEQ,
lcdtiming_pixel_buf$EMPTY_N,
lcdtiming_pixel_buf$ENQ,
lcdtiming_pixel_buf$FULL_N;
// ports of submodule streamIn_f
wire [25 : 0] streamIn_f$D_IN, streamIn_f$D_OUT;
wire streamIn_f$CLR,
streamIn_f$DEQ,
streamIn_f$EMPTY_N,
streamIn_f$ENQ,
streamIn_f$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_connect_stream_to_lcd_interface,
CAN_FIRE_RL_lcdtiming_every_clock_cycle,
CAN_FIRE_RL_streamIn_push_data_into_fifo,
CAN_FIRE_asi_stream_in,
WILL_FIRE_RL_connect_stream_to_lcd_interface,
WILL_FIRE_RL_lcdtiming_every_clock_cycle,
WILL_FIRE_RL_streamIn_push_data_into_fifo,
WILL_FIRE_asi_stream_in;
// remaining internal signals
wire [7 : 0] IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40;
wire NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59,
lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65,
lcdtiming_x_SLT_1009___d66;
// action method asi_stream_in
assign CAN_FIRE_asi_stream_in = 1'd1 ;
assign WILL_FIRE_asi_stream_in = 1'd1 ;
// value method asi_stream_in_ready
assign asi_stream_in_ready = streamIn_f$FULL_N ;
// value method coe_tpadlcd_mtl_r
assign coe_tpadlcd_mtl_r = lcdtiming_pixel_out[24:17] ;
// value method coe_tpadlcd_mtl_g
assign coe_tpadlcd_mtl_g = lcdtiming_pixel_out[16:9] ;
// value method coe_tpadlcd_mtl_b
assign coe_tpadlcd_mtl_b = lcdtiming_pixel_out[8:1] ;
// value method coe_tpadlcd_mtl_hsd
assign coe_tpadlcd_mtl_hsd = lcdtiming_hsd ;
// value method coe_tpadlcd_mtl_vsd
assign coe_tpadlcd_mtl_vsd = lcdtiming_vsd ;
// submodule lcdtiming_pixel_buf
FIFO2 #(.width(32'd25),
.guarded(32'd1)) lcdtiming_pixel_buf(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(lcdtiming_pixel_buf$D_IN),
.ENQ(lcdtiming_pixel_buf$ENQ),
.DEQ(lcdtiming_pixel_buf$DEQ),
.CLR(lcdtiming_pixel_buf$CLR),
.D_OUT(lcdtiming_pixel_buf$D_OUT),
.FULL_N(lcdtiming_pixel_buf$FULL_N),
.EMPTY_N(lcdtiming_pixel_buf$EMPTY_N));
// submodule streamIn_f
FIFOL1 #(.width(32'd26)) streamIn_f(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(streamIn_f$D_IN),
.ENQ(streamIn_f$ENQ),
.DEQ(streamIn_f$DEQ),
.CLR(streamIn_f$CLR),
.D_OUT(streamIn_f$D_OUT),
.FULL_N(streamIn_f$FULL_N),
.EMPTY_N(streamIn_f$EMPTY_N));
// rule RL_connect_stream_to_lcd_interface
assign CAN_FIRE_RL_connect_stream_to_lcd_interface =
streamIn_f$EMPTY_N && lcdtiming_pixel_buf$FULL_N ;
assign WILL_FIRE_RL_connect_stream_to_lcd_interface =
CAN_FIRE_RL_connect_stream_to_lcd_interface ;
// rule RL_lcdtiming_every_clock_cycle
assign CAN_FIRE_RL_lcdtiming_every_clock_cycle = 1'd1 ;
assign WILL_FIRE_RL_lcdtiming_every_clock_cycle = 1'd1 ;
// rule RL_streamIn_push_data_into_fifo
assign CAN_FIRE_RL_streamIn_push_data_into_fifo =
streamIn_f$FULL_N && asi_stream_in_valid &&
streamIn_d_dw$wget[26] ;
assign WILL_FIRE_RL_streamIn_push_data_into_fifo =
CAN_FIRE_RL_streamIn_push_data_into_fifo ;
// inlined wires
assign streamIn_d_dw$wget =
{ 1'd1,
asi_stream_in_data,
asi_stream_in_startofpacket,
asi_stream_in_endofpacket } ;
// register lcdtiming_hsd
assign lcdtiming_hsd$D_IN = (lcdtiming_x ^ 12'h800) >= 12'd2032 ;
assign lcdtiming_hsd$EN = 1'd1 ;
// register lcdtiming_pixel_out
assign lcdtiming_pixel_out$D_IN =
{ IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40,
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 } ;
assign lcdtiming_pixel_out$EN = 1'd1 ;
// register lcdtiming_vsd
assign lcdtiming_vsd$D_IN = (lcdtiming_y ^ 12'h800) >= 12'd2038 ;
assign lcdtiming_vsd$EN = 1'd1 ;
// register lcdtiming_x
assign lcdtiming_x$D_IN =
lcdtiming_x_SLT_1009___d66 ? lcdtiming_x + 12'd1 : 12'd4050 ;
assign lcdtiming_x$EN = 1'd1 ;
// register lcdtiming_y
assign lcdtiming_y$D_IN =
((lcdtiming_y ^ 12'h800) < 12'd2549) ?
lcdtiming_y + 12'd1 :
12'd4073 ;
assign lcdtiming_y$EN = !lcdtiming_x_SLT_1009___d66 ;
// submodule lcdtiming_pixel_buf
assign lcdtiming_pixel_buf$D_IN = streamIn_f$D_OUT[25:1] ;
assign lcdtiming_pixel_buf$ENQ =
CAN_FIRE_RL_connect_stream_to_lcd_interface ;
assign lcdtiming_pixel_buf$DEQ =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 &&
lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ;
assign lcdtiming_pixel_buf$CLR = 1'b0 ;
// submodule streamIn_f
assign streamIn_f$D_IN = streamIn_d_dw$wget[25:0] ;
assign streamIn_f$ENQ = CAN_FIRE_RL_streamIn_push_data_into_fifo ;
assign streamIn_f$DEQ = CAN_FIRE_RL_connect_stream_to_lcd_interface ;
assign streamIn_f$CLR = 1'b0 ;
// remaining internal signals
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[24:17] :
8'd255) :
8'd0 ;
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[16:9] :
8'd0) :
8'd0 ;
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[8:1] :
8'd0) :
8'd0 ;
assign NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 =
!lcdtiming_y[11] && (lcdtiming_y ^ 12'h800) < 12'd2528 &&
!lcdtiming_x[11] &&
(lcdtiming_x ^ 12'h800) < 12'd2848 ;
assign lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 =
lcdtiming_pixel_buf$EMPTY_N &&
lcdtiming_pixel_buf$D_OUT[0] ==
(lcdtiming_x == 12'd0 && lcdtiming_y == 12'd0) ;
assign lcdtiming_x_SLT_1009___d66 = (lcdtiming_x ^ 12'h800) < 12'd3057 ;
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
lcdtiming_x <= `BSV_ASSIGNMENT_DELAY 12'd4050;
lcdtiming_y <= `BSV_ASSIGNMENT_DELAY 12'd4073;
end
else
begin
if (lcdtiming_x$EN)
lcdtiming_x <= `BSV_ASSIGNMENT_DELAY lcdtiming_x$D_IN;
if (lcdtiming_y$EN)
lcdtiming_y <= `BSV_ASSIGNMENT_DELAY lcdtiming_y$D_IN;
end
if (lcdtiming_hsd$EN)
lcdtiming_hsd <= `BSV_ASSIGNMENT_DELAY lcdtiming_hsd$D_IN;
if (lcdtiming_pixel_out$EN)
lcdtiming_pixel_out <= `BSV_ASSIGNMENT_DELAY lcdtiming_pixel_out$D_IN;
if (lcdtiming_vsd$EN)
lcdtiming_vsd <= `BSV_ASSIGNMENT_DELAY lcdtiming_vsd$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
lcdtiming_hsd = 1'h0;
lcdtiming_pixel_out = 25'h0AAAAAA;
lcdtiming_vsd = 1'h0;
lcdtiming_x = 12'hAAA;
lcdtiming_y = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkAvalonStream2MTL_LCD24bit
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:44:20 BST 2012
//
// Method conflict info:
// Method: getPc
// Conflict-free: putRegisterTarget, getEpoch
// Sequenced before: putTarget, pcWriteback
// Conflicts: getPc
//
// Method: putTarget
// Conflict-free: pcWriteback, getEpoch
// Sequenced after: getPc
// Sequenced after (restricted): putRegisterTarget
// Conflicts: putTarget
//
// Method: putRegisterTarget
// Conflict-free: getPc, pcWriteback, getEpoch
// Sequenced before (restricted): putTarget
// Conflicts: putRegisterTarget
//
// Method: pcWriteback
// Conflict-free: putTarget, putRegisterTarget
// Sequenced after: getPc, getEpoch
// Conflicts: pcWriteback
//
// Method: getEpoch
// Conflict-free: getPc, putTarget, putRegisterTarget, getEpoch
// Sequenced before: pcWriteback
//
//
// Ports:
// Name I/O size props
// getPc O 67
// RDY_getPc O 1
// RDY_putTarget O 1
// RDY_putRegisterTarget O 1
// RDY_pcWriteback O 1
// getEpoch O 3 reg
// RDY_getEpoch O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// getPc_id I 4 unused
// getPc_fromDebug I 1
// putTarget_branchType I 2
// putTarget_target I 64
// putTarget_instEpoch I 3
// putTarget_id I 4
// putTarget_fromDebug I 1
// putRegisterTarget_target I 64
// putRegisterTarget_instEpoch I 3
// putRegisterTarget_id I 4
// putRegisterTarget_fromDebug I 1
// pcWriteback_truePc I 65
// pcWriteback_exception I 1
// pcWriteback_fromDebug I 1
// EN_putTarget I 1
// EN_putRegisterTarget I 1
// EN_pcWriteback I 1
// EN_getPc I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkBranch(CLK,
RST_N,
getPc_id,
getPc_fromDebug,
EN_getPc,
getPc,
RDY_getPc,
putTarget_branchType,
putTarget_target,
putTarget_instEpoch,
putTarget_id,
putTarget_fromDebug,
EN_putTarget,
RDY_putTarget,
putRegisterTarget_target,
putRegisterTarget_instEpoch,
putRegisterTarget_id,
putRegisterTarget_fromDebug,
EN_putRegisterTarget,
RDY_putRegisterTarget,
pcWriteback_truePc,
pcWriteback_exception,
pcWriteback_fromDebug,
EN_pcWriteback,
RDY_pcWriteback,
getEpoch,
RDY_getEpoch);
input CLK;
input RST_N;
// actionvalue method getPc
input [3 : 0] getPc_id;
input getPc_fromDebug;
input EN_getPc;
output [66 : 0] getPc;
output RDY_getPc;
// action method putTarget
input [1 : 0] putTarget_branchType;
input [63 : 0] putTarget_target;
input [2 : 0] putTarget_instEpoch;
input [3 : 0] putTarget_id;
input putTarget_fromDebug;
input EN_putTarget;
output RDY_putTarget;
// action method putRegisterTarget
input [63 : 0] putRegisterTarget_target;
input [2 : 0] putRegisterTarget_instEpoch;
input [3 : 0] putRegisterTarget_id;
input putRegisterTarget_fromDebug;
input EN_putRegisterTarget;
output RDY_putRegisterTarget;
// action method pcWriteback
input [64 : 0] pcWriteback_truePc;
input pcWriteback_exception;
input pcWriteback_fromDebug;
input EN_pcWriteback;
output RDY_pcWriteback;
// value method getEpoch
output [2 : 0] getEpoch;
output RDY_getEpoch;
// signals for module outputs
wire [66 : 0] getPc;
wire [2 : 0] getEpoch;
wire RDY_getEpoch,
RDY_getPc,
RDY_pcWriteback,
RDY_putRegisterTarget,
RDY_putTarget;
// inlined wires
wire [71 : 0] registerTarget_rw_enq$wget;
wire [1 : 0] branchHistory_serverAdapterA_outData_outData$wget;
wire branchHistory_serverAdapterA_outData_enqData$whas,
branchHistory_serverAdapterA_outData_outData$whas,
branchHistory_serverAdapterB_outData_enqData$whas,
branchHistory_serverAdapterB_writeWithResp$whas,
jumpTargets_serverAdapterA_outData_enqData$whas,
jumpTargets_serverAdapterA_outData_outData$whas,
jumpTargets_serverAdapterB_outData_enqData$whas,
jumpTargets_serverAdapterB_writeWithResp$whas,
registerTarget_rw_enq$whas;
// register branchHist
reg [5 : 0] branchHist;
wire [5 : 0] branchHist$D_IN;
wire branchHist$EN;
// register branchHistory_serverAdapterA_cnt
reg [2 : 0] branchHistory_serverAdapterA_cnt;
wire [2 : 0] branchHistory_serverAdapterA_cnt$D_IN;
wire branchHistory_serverAdapterA_cnt$EN;
// register branchHistory_serverAdapterA_s1
reg [1 : 0] branchHistory_serverAdapterA_s1;
wire [1 : 0] branchHistory_serverAdapterA_s1$D_IN;
wire branchHistory_serverAdapterA_s1$EN;
// register branchHistory_serverAdapterB_cnt
reg [2 : 0] branchHistory_serverAdapterB_cnt;
wire [2 : 0] branchHistory_serverAdapterB_cnt$D_IN;
wire branchHistory_serverAdapterB_cnt$EN;
// register branchHistory_serverAdapterB_s1
reg [1 : 0] branchHistory_serverAdapterB_s1;
wire [1 : 0] branchHistory_serverAdapterB_s1$D_IN;
wire branchHistory_serverAdapterB_s1$EN;
// register countIn
reg [4 : 0] countIn;
wire [4 : 0] countIn$D_IN;
wire countIn$EN;
// register countOut
reg [4 : 0] countOut;
wire [4 : 0] countOut$D_IN;
wire countOut$EN;
// register epoch
reg [2 : 0] epoch;
wire [2 : 0] epoch$D_IN;
wire epoch$EN;
// register flushCount
reg [3 : 0] flushCount;
wire [3 : 0] flushCount$D_IN;
wire flushCount$EN;
// register issueEpoch
reg [2 : 0] issueEpoch;
wire [2 : 0] issueEpoch$D_IN;
wire issueEpoch$EN;
// register jumpTargets_serverAdapterA_cnt
reg [2 : 0] jumpTargets_serverAdapterA_cnt;
wire [2 : 0] jumpTargets_serverAdapterA_cnt$D_IN;
wire jumpTargets_serverAdapterA_cnt$EN;
// register jumpTargets_serverAdapterA_s1
reg [1 : 0] jumpTargets_serverAdapterA_s1;
wire [1 : 0] jumpTargets_serverAdapterA_s1$D_IN;
wire jumpTargets_serverAdapterA_s1$EN;
// register jumpTargets_serverAdapterB_cnt
reg [2 : 0] jumpTargets_serverAdapterB_cnt;
wire [2 : 0] jumpTargets_serverAdapterB_cnt$D_IN;
wire jumpTargets_serverAdapterB_cnt$EN;
// register jumpTargets_serverAdapterB_s1
reg [1 : 0] jumpTargets_serverAdapterB_s1;
wire [1 : 0] jumpTargets_serverAdapterB_s1$D_IN;
wire jumpTargets_serverAdapterB_s1$EN;
// register pc
reg [63 : 0] pc;
wire [63 : 0] pc$D_IN;
wire pc$EN;
// register registerTarget_taggedReg
reg [72 : 0] registerTarget_taggedReg;
wire [72 : 0] registerTarget_taggedReg$D_IN;
wire registerTarget_taggedReg$EN;
// register specPc
reg [63 : 0] specPc;
wire [63 : 0] specPc$D_IN;
wire specPc$EN;
// register state
reg state;
wire state$D_IN, state$EN;
// register waitRegTarget
reg waitRegTarget;
wire waitRegTarget$D_IN, waitRegTarget$EN;
// register waitRegTargetHist
reg [1 : 0] waitRegTargetHist;
wire [1 : 0] waitRegTargetHist$D_IN;
wire waitRegTargetHist$EN;
// ports of submodule branchHistory_memory
wire [11 : 0] branchHistory_memory$ADDRA, branchHistory_memory$ADDRB;
wire [1 : 0] branchHistory_memory$DIA,
branchHistory_memory$DIB,
branchHistory_memory$DOA,
branchHistory_memory$DOB;
wire branchHistory_memory$ENA,
branchHistory_memory$ENB,
branchHistory_memory$WEA,
branchHistory_memory$WEB;
// ports of submodule branchHistory_serverAdapterA_outDataCore
wire [1 : 0] branchHistory_serverAdapterA_outDataCore$D_IN,
branchHistory_serverAdapterA_outDataCore$D_OUT;
wire branchHistory_serverAdapterA_outDataCore$CLR,
branchHistory_serverAdapterA_outDataCore$DEQ,
branchHistory_serverAdapterA_outDataCore$EMPTY_N,
branchHistory_serverAdapterA_outDataCore$ENQ,
branchHistory_serverAdapterA_outDataCore$FULL_N;
// ports of submodule branchHistory_serverAdapterB_outDataCore
wire [1 : 0] branchHistory_serverAdapterB_outDataCore$D_IN;
wire branchHistory_serverAdapterB_outDataCore$CLR,
branchHistory_serverAdapterB_outDataCore$DEQ,
branchHistory_serverAdapterB_outDataCore$ENQ,
branchHistory_serverAdapterB_outDataCore$FULL_N;
// ports of submodule flushFifo
wire flushFifo$CLR,
flushFifo$DEQ,
flushFifo$D_IN,
flushFifo$EMPTY_N,
flushFifo$ENQ;
// ports of submodule jumpTargets_memory
wire [31 : 0] jumpTargets_memory$DIA,
jumpTargets_memory$DIB,
jumpTargets_memory$DOA,
jumpTargets_memory$DOB;
wire [7 : 0] jumpTargets_memory$ADDRA, jumpTargets_memory$ADDRB;
wire jumpTargets_memory$ENA,
jumpTargets_memory$ENB,
jumpTargets_memory$WEA,
jumpTargets_memory$WEB;
// ports of submodule jumpTargets_serverAdapterA_outDataCore
wire [31 : 0] jumpTargets_serverAdapterA_outDataCore$D_IN,
jumpTargets_serverAdapterA_outDataCore$D_OUT;
wire jumpTargets_serverAdapterA_outDataCore$CLR,
jumpTargets_serverAdapterA_outDataCore$DEQ,
jumpTargets_serverAdapterA_outDataCore$EMPTY_N,
jumpTargets_serverAdapterA_outDataCore$ENQ,
jumpTargets_serverAdapterA_outDataCore$FULL_N;
// ports of submodule jumpTargets_serverAdapterB_outDataCore
wire [31 : 0] jumpTargets_serverAdapterB_outDataCore$D_IN;
wire jumpTargets_serverAdapterB_outDataCore$CLR,
jumpTargets_serverAdapterB_outDataCore$DEQ,
jumpTargets_serverAdapterB_outDataCore$ENQ,
jumpTargets_serverAdapterB_outDataCore$FULL_N;
// ports of submodule keys
wire [21 : 0] keys$D_IN, keys$D_OUT;
wire keys$CLR, keys$DEQ, keys$EMPTY_N, keys$ENQ, keys$FULL_N;
// ports of submodule newEpoch
wire [2 : 0] newEpoch$D_IN, newEpoch$D_OUT;
wire newEpoch$CLR, newEpoch$DEQ, newEpoch$EMPTY_N, newEpoch$ENQ;
// ports of submodule predictionCheck
wire [89 : 0] predictionCheck$D_IN, predictionCheck$D_OUT;
wire predictionCheck$CLR,
predictionCheck$DEQ,
predictionCheck$EMPTY_N,
predictionCheck$ENQ,
predictionCheck$FULL_N;
// ports of submodule predictions
reg [71 : 0] predictions$D_IN;
wire [71 : 0] predictions$D_OUT;
wire predictions$CLR,
predictions$DEQ,
predictions$EMPTY_N,
predictions$ENQ,
predictions$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_branchHistory_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_branchHistory_serverAdapterA_outData_setFirstEnq,
WILL_FIRE_RL_dumpRegisterTarget,
WILL_FIRE_RL_flushDelay,
WILL_FIRE_RL_jumpTargets_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_primeFifoRule,
WILL_FIRE_RL_registerTarget_rule_enq,
WILL_FIRE_RL_reportRegisterTarget;
// inputs to muxes for submodule ports
wire [89 : 0] MUX_predictionCheck$enq_1__VAL_1,
MUX_predictionCheck$enq_1__VAL_2;
wire [72 : 0] MUX_registerTarget_taggedReg$write_1__VAL_1;
wire [71 : 0] MUX_predictions$enq_1__VAL_1,
MUX_predictions$enq_1__VAL_2,
MUX_predictions$enq_1__VAL_3;
wire [3 : 0] MUX_flushCount$write_1__VAL_1, MUX_flushCount$write_1__VAL_2;
wire MUX_predictionCheck$enq_1__SEL_1,
MUX_predictions$enq_1__SEL_1,
MUX_registerTarget_taggedReg$write_1__SEL_2,
MUX_waitRegTarget$write_1__SEL_1;
// remaining internal signals
reg [63 : 0] IF_putTarget_branchType_EQ_1_24_OR_putTarget_b_ETC___d547;
wire [63 : 0] IF_registerTarget_rw_enq_whas_THEN_registerTar_ETC___d431,
_theResult_____2__h8248,
nextPc___1__h8384,
pcWriteback_truePc_BITS_63_TO_0__q4,
x__h8310;
wire [31 : 0] v__h9023;
wire [2 : 0] IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q2,
IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q3,
IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d465,
IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d466,
SEXT_predictionCheck_first__77_BITS_25_TO_24_97___d463,
SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d462,
SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d464,
branchHistory_serverAdapterA_cnt_8_PLUS_IF_bra_ETC___d44,
jumpTargets_serverAdapterA_cnt_52_PLUS_IF_jump_ETC___d158;
wire [1 : 0] predictionCheckD_OUT_BITS_25_TO_24__q1;
wire IF_predictionCheck_first__77_BITS_23_TO_22_78__ETC___d508,
IF_putTarget_branchType_EQ_1_24_THEN_branchHis_ETC___d546,
branchHistory_serverAdapterA_outData_outData_w_ETC___d367,
predictionCheck_first__77_BITS_89_TO_26_89_EQ__ETC___d495,
registerTarget_taggedReg_48_BIT_72_49_OR_regis_ETC___d256;
// actionvalue method getPc
assign getPc = { _theResult_____2__h8248, issueEpoch } ;
assign RDY_getPc =
!flushFifo$EMPTY_N && predictions$EMPTY_N &&
(branchHistory_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
(jumpTargets_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
keys$FULL_N ;
// action method putTarget
assign RDY_putTarget =
state && !waitRegTarget &&
(branchHistory_serverAdapterA_outDataCore$EMPTY_N ||
branchHistory_serverAdapterA_outData_enqData$whas) &&
branchHistory_serverAdapterA_outData_outData_w_ETC___d367 ;
// action method putRegisterTarget
assign RDY_putRegisterTarget = state && !registerTarget_taggedReg[72] ;
// action method pcWriteback
assign RDY_pcWriteback =
predictionCheck$EMPTY_N &&
(jumpTargets_serverAdapterB_cnt ^ 3'h4) < 3'd7 &&
(branchHistory_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
// value method getEpoch
assign getEpoch = epoch ;
assign RDY_getEpoch = 1'd1 ;
// submodule branchHistory_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd12),
.DATA_WIDTH(32'd2),
.MEMSIZE(13'd4096)) branchHistory_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(branchHistory_memory$ADDRA),
.ADDRB(branchHistory_memory$ADDRB),
.DIA(branchHistory_memory$DIA),
.DIB(branchHistory_memory$DIB),
.WEA(branchHistory_memory$WEA),
.WEB(branchHistory_memory$WEB),
.ENA(branchHistory_memory$ENA),
.ENB(branchHistory_memory$ENB),
.DOA(branchHistory_memory$DOA),
.DOB(branchHistory_memory$DOB));
// submodule branchHistory_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) branchHistory_serverAdapterA_outDataCore(.RST_N(RST_N),
.CLK(CLK),
.D_IN(branchHistory_serverAdapterA_outDataCore$D_IN),
.ENQ(branchHistory_serverAdapterA_outDataCore$ENQ),
.DEQ(branchHistory_serverAdapterA_outDataCore$DEQ),
.CLR(branchHistory_serverAdapterA_outDataCore$CLR),
.D_OUT(branchHistory_serverAdapterA_outDataCore$D_OUT),
.FULL_N(branchHistory_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(branchHistory_serverAdapterA_outDataCore$EMPTY_N));
// submodule branchHistory_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) branchHistory_serverAdapterB_outDataCore(.RST_N(RST_N),
.CLK(CLK),
.D_IN(branchHistory_serverAdapterB_outDataCore$D_IN),
.ENQ(branchHistory_serverAdapterB_outDataCore$ENQ),
.DEQ(branchHistory_serverAdapterB_outDataCore$DEQ),
.CLR(branchHistory_serverAdapterB_outDataCore$CLR),
.D_OUT(),
.FULL_N(branchHistory_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N());
// submodule flushFifo
FIFO1 #(.width(32'd1), .guarded(32'd0)) flushFifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(flushFifo$D_IN),
.ENQ(flushFifo$ENQ),
.DEQ(flushFifo$DEQ),
.CLR(flushFifo$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(flushFifo$EMPTY_N));
// submodule jumpTargets_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd8),
.DATA_WIDTH(32'd32),
.MEMSIZE(9'd256)) jumpTargets_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(jumpTargets_memory$ADDRA),
.ADDRB(jumpTargets_memory$ADDRB),
.DIA(jumpTargets_memory$DIA),
.DIB(jumpTargets_memory$DIB),
.WEA(jumpTargets_memory$WEA),
.WEB(jumpTargets_memory$WEB),
.ENA(jumpTargets_memory$ENA),
.ENB(jumpTargets_memory$ENB),
.DOA(jumpTargets_memory$DOA),
.DOB(jumpTargets_memory$DOB));
// submodule jumpTargets_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) jumpTargets_serverAdapterA_outDataCore(.RST_N(RST_N),
.CLK(CLK),
.D_IN(jumpTargets_serverAdapterA_outDataCore$D_IN),
.ENQ(jumpTargets_serverAdapterA_outDataCore$ENQ),
.DEQ(jumpTargets_serverAdapterA_outDataCore$DEQ),
.CLR(jumpTargets_serverAdapterA_outDataCore$CLR),
.D_OUT(jumpTargets_serverAdapterA_outDataCore$D_OUT),
.FULL_N(jumpTargets_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(jumpTargets_serverAdapterA_outDataCore$EMPTY_N));
// submodule jumpTargets_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) jumpTargets_serverAdapterB_outDataCore(.RST_N(RST_N),
.CLK(CLK),
.D_IN(jumpTargets_serverAdapterB_outDataCore$D_IN),
.ENQ(jumpTargets_serverAdapterB_outDataCore$ENQ),
.DEQ(jumpTargets_serverAdapterB_outDataCore$DEQ),
.CLR(jumpTargets_serverAdapterB_outDataCore$CLR),
.D_OUT(),
.FULL_N(jumpTargets_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N());
// submodule keys
FIFO2 #(.width(32'd22), .guarded(32'd1)) keys(.RST_N(RST_N),
.CLK(CLK),
.D_IN(keys$D_IN),
.ENQ(keys$ENQ),
.DEQ(keys$DEQ),
.CLR(keys$CLR),
.D_OUT(keys$D_OUT),
.FULL_N(keys$FULL_N),
.EMPTY_N(keys$EMPTY_N));
// submodule newEpoch
FIFO2 #(.width(32'd3), .guarded(32'd0)) newEpoch(.RST_N(RST_N),
.CLK(CLK),
.D_IN(newEpoch$D_IN),
.ENQ(newEpoch$ENQ),
.DEQ(newEpoch$DEQ),
.CLR(newEpoch$CLR),
.D_OUT(newEpoch$D_OUT),
.FULL_N(),
.EMPTY_N(newEpoch$EMPTY_N));
// submodule predictionCheck
SizedFIFO #(.p1width(32'd90),
.p2depth(32'd10),
.p3cntr_width(32'd4),
.guarded(32'd1)) predictionCheck(.RST_N(RST_N),
.CLK(CLK),
.D_IN(predictionCheck$D_IN),
.ENQ(predictionCheck$ENQ),
.DEQ(predictionCheck$DEQ),
.CLR(predictionCheck$CLR),
.D_OUT(predictionCheck$D_OUT),
.FULL_N(predictionCheck$FULL_N),
.EMPTY_N(predictionCheck$EMPTY_N));
// submodule predictions
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) predictions(.RST_N(RST_N),
.CLK(CLK),
.D_IN(predictions$D_IN),
.ENQ(predictions$ENQ),
.DEQ(predictions$DEQ),
.CLR(predictions$CLR),
.D_OUT(predictions$D_OUT),
.FULL_N(predictions$FULL_N),
.EMPTY_N(predictions$EMPTY_N));
// rule RL_flushDelay
assign WILL_FIRE_RL_flushDelay = state && flushFifo$EMPTY_N ;
// rule RL_reportRegisterTarget
assign WILL_FIRE_RL_reportRegisterTarget =
registerTarget_taggedReg_48_BIT_72_49_OR_regis_ETC___d256 &&
state &&
waitRegTarget ;
// rule RL_dumpRegisterTarget
assign WILL_FIRE_RL_dumpRegisterTarget =
(registerTarget_taggedReg[72] || registerTarget_rw_enq$whas) &&
state &&
!waitRegTarget ;
// rule RL_primeFifoRule
assign WILL_FIRE_RL_primeFifoRule = predictions$FULL_N && !state ;
// rule RL_registerTarget_rule_enq
assign WILL_FIRE_RL_registerTarget_rule_enq =
registerTarget_rw_enq$whas &&
!MUX_registerTarget_taggedReg$write_1__SEL_2 ;
// rule RL_branchHistory_serverAdapterA_outData_setFirstEnq
assign WILL_FIRE_RL_branchHistory_serverAdapterA_outData_setFirstEnq =
!branchHistory_serverAdapterA_outDataCore$EMPTY_N &&
branchHistory_serverAdapterA_outData_enqData$whas ;
// rule RL_branchHistory_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_branchHistory_serverAdapterA_outData_enqAndDeq =
branchHistory_serverAdapterA_outDataCore$EMPTY_N &&
branchHistory_serverAdapterA_outDataCore$FULL_N &&
EN_putTarget &&
branchHistory_serverAdapterA_outData_enqData$whas ;
// rule RL_jumpTargets_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_jumpTargets_serverAdapterA_outData_enqAndDeq =
jumpTargets_serverAdapterA_outDataCore$EMPTY_N &&
jumpTargets_serverAdapterA_outDataCore$FULL_N &&
EN_putTarget &&
jumpTargets_serverAdapterA_outData_enqData$whas ;
// inputs to muxes for submodule ports
assign MUX_predictionCheck$enq_1__SEL_1 =
EN_putTarget &&
(putTarget_branchType != 2'd3 ||
branchHistory_serverAdapterA_outData_outData$wget[1] ||
putTarget_fromDebug) ;
assign MUX_predictions$enq_1__SEL_1 =
EN_putTarget &&
(putTarget_branchType != 2'd3 ||
branchHistory_serverAdapterA_outData_outData$wget[1]) &&
!putTarget_fromDebug ;
assign MUX_registerTarget_taggedReg$write_1__SEL_2 =
WILL_FIRE_RL_dumpRegisterTarget ||
WILL_FIRE_RL_reportRegisterTarget ;
assign MUX_waitRegTarget$write_1__SEL_1 =
EN_putTarget && putTarget_branchType == 2'd3 &&
IF_putTarget_branchType_EQ_1_24_THEN_branchHis_ETC___d546 &&
!putTarget_fromDebug ;
assign MUX_flushCount$write_1__VAL_1 =
(flushCount == 4'd4) ? 4'd0 : flushCount + 4'd1 ;
assign MUX_flushCount$write_1__VAL_2 = flushCount + 4'd1 ;
assign MUX_predictionCheck$enq_1__VAL_1 =
{ IF_putTarget_branchType_EQ_1_24_OR_putTarget_b_ETC___d547,
branchHistory_serverAdapterA_outData_outData$wget,
putTarget_branchType,
keys$D_OUT } ;
assign MUX_predictionCheck$enq_1__VAL_2 =
{ IF_registerTarget_rw_enq_whas_THEN_registerTar_ETC___d431,
waitRegTargetHist,
2'd3,
keys$D_OUT } ;
assign MUX_predictions$enq_1__VAL_1 =
{ (putTarget_branchType == 2'd1) ?
!branchHistory_serverAdapterA_outData_outData$wget[1] :
putTarget_branchType == 2'd2 ||
putTarget_branchType == 2'd3 &&
branchHistory_serverAdapterA_outData_outData$wget[1],
IF_putTarget_branchType_EQ_1_24_OR_putTarget_b_ETC___d547,
putTarget_instEpoch,
putTarget_id } ;
assign MUX_predictions$enq_1__VAL_2 =
{ registerTarget_rw_enq$whas ?
registerTarget_rw_enq$wget[71] :
!registerTarget_taggedReg[72] ||
registerTarget_taggedReg[71],
IF_registerTarget_rw_enq_whas_THEN_registerTar_ETC___d431,
registerTarget_rw_enq$whas ?
registerTarget_rw_enq$wget[6:0] :
registerTarget_taggedReg[6:0] } ;
assign MUX_predictions$enq_1__VAL_3 =
{ 1'd1, (flushCount == 4'd0) ? pc : pc + 64'd4, epoch, 4'hA } ;
assign MUX_registerTarget_taggedReg$write_1__VAL_1 =
{ 1'd1, registerTarget_rw_enq$wget } ;
// inlined wires
assign registerTarget_rw_enq$wget =
{ 1'd1,
putRegisterTarget_target,
putRegisterTarget_instEpoch,
putRegisterTarget_id } ;
assign registerTarget_rw_enq$whas =
EN_putRegisterTarget && !putRegisterTarget_fromDebug ;
assign branchHistory_serverAdapterA_outData_enqData$whas =
branchHistory_serverAdapterA_outDataCore$FULL_N &&
branchHistory_serverAdapterA_s1[1] &&
branchHistory_serverAdapterA_s1[0] ;
assign branchHistory_serverAdapterA_outData_outData$wget =
WILL_FIRE_RL_branchHistory_serverAdapterA_outData_setFirstEnq ?
branchHistory_memory$DOA :
branchHistory_serverAdapterA_outDataCore$D_OUT ;
assign branchHistory_serverAdapterA_outData_outData$whas =
WILL_FIRE_RL_branchHistory_serverAdapterA_outData_setFirstEnq ||
branchHistory_serverAdapterA_outDataCore$EMPTY_N ;
assign branchHistory_serverAdapterB_outData_enqData$whas =
branchHistory_serverAdapterB_outDataCore$FULL_N &&
branchHistory_serverAdapterB_s1[1] &&
branchHistory_serverAdapterB_s1[0] ;
assign branchHistory_serverAdapterB_writeWithResp$whas =
EN_pcWriteback && pcWriteback_truePc[64] &&
!pcWriteback_fromDebug &&
(predictionCheck$D_OUT[23:22] == 2'd1 ||
predictionCheck$D_OUT[23:22] == 2'd3) ;
assign jumpTargets_serverAdapterA_outData_enqData$whas =
jumpTargets_serverAdapterA_outDataCore$FULL_N &&
jumpTargets_serverAdapterA_s1[1] &&
jumpTargets_serverAdapterA_s1[0] ;
assign jumpTargets_serverAdapterA_outData_outData$whas =
jumpTargets_serverAdapterA_outDataCore$EMPTY_N ||
!jumpTargets_serverAdapterA_outDataCore$EMPTY_N &&
jumpTargets_serverAdapterA_outData_enqData$whas ;
assign jumpTargets_serverAdapterB_outData_enqData$whas =
jumpTargets_serverAdapterB_outDataCore$FULL_N &&
jumpTargets_serverAdapterB_s1[1] &&
jumpTargets_serverAdapterB_s1[0] ;
assign jumpTargets_serverAdapterB_writeWithResp$whas =
EN_pcWriteback && pcWriteback_truePc[64] &&
!pcWriteback_fromDebug &&
predictionCheck$D_OUT[23:22] == 2'd3 ;
// register branchHist
assign branchHist$D_IN =
{ branchHist[4:0],
!branchHistory_serverAdapterA_outData_outData$wget[1] } ;
assign branchHist$EN = EN_putTarget && putTarget_branchType == 2'd1 ;
// register branchHistory_serverAdapterA_cnt
assign branchHistory_serverAdapterA_cnt$D_IN =
branchHistory_serverAdapterA_cnt_8_PLUS_IF_bra_ETC___d44 ;
assign branchHistory_serverAdapterA_cnt$EN = EN_getPc || EN_putTarget ;
// register branchHistory_serverAdapterA_s1
assign branchHistory_serverAdapterA_s1$D_IN = { EN_getPc, 1'b1 } ;
assign branchHistory_serverAdapterA_s1$EN = 1'd1 ;
// register branchHistory_serverAdapterB_cnt
assign branchHistory_serverAdapterB_cnt$D_IN =
branchHistory_serverAdapterB_cnt + 3'd0 + 3'd0 ;
assign branchHistory_serverAdapterB_cnt$EN = 1'b0 ;
// register branchHistory_serverAdapterB_s1
assign branchHistory_serverAdapterB_s1$D_IN =
{ branchHistory_serverAdapterB_writeWithResp$whas, 1'b0 } ;
assign branchHistory_serverAdapterB_s1$EN = 1'd1 ;
// register countIn
assign countIn$D_IN = countIn + 5'd1 ;
assign countIn$EN = EN_getPc ;
// register countOut
assign countOut$D_IN = countOut + 5'd1 ;
assign countOut$EN = EN_pcWriteback ;
// register epoch
assign epoch$D_IN =
(pcWriteback_truePc[64] && pcWriteback_exception) ?
(newEpoch$EMPTY_N ? epoch + 3'd2 : epoch + 3'd1) :
newEpoch$D_OUT ;
assign epoch$EN =
EN_pcWriteback &&
(pcWriteback_truePc[64] && pcWriteback_exception ||
newEpoch$EMPTY_N) ;
// register flushCount
assign flushCount$D_IN =
WILL_FIRE_RL_flushDelay ?
MUX_flushCount$write_1__VAL_1 :
MUX_flushCount$write_1__VAL_2 ;
assign flushCount$EN =
WILL_FIRE_RL_flushDelay || WILL_FIRE_RL_primeFifoRule ;
// register issueEpoch
assign issueEpoch$D_IN = epoch ;
assign issueEpoch$EN = EN_getPc ;
// register jumpTargets_serverAdapterA_cnt
assign jumpTargets_serverAdapterA_cnt$D_IN =
jumpTargets_serverAdapterA_cnt_52_PLUS_IF_jump_ETC___d158 ;
assign jumpTargets_serverAdapterA_cnt$EN = EN_getPc || EN_putTarget ;
// register jumpTargets_serverAdapterA_s1
assign jumpTargets_serverAdapterA_s1$D_IN = { EN_getPc, 1'b1 } ;
assign jumpTargets_serverAdapterA_s1$EN = 1'd1 ;
// register jumpTargets_serverAdapterB_cnt
assign jumpTargets_serverAdapterB_cnt$D_IN =
jumpTargets_serverAdapterB_cnt + 3'd0 + 3'd0 ;
assign jumpTargets_serverAdapterB_cnt$EN = 1'b0 ;
// register jumpTargets_serverAdapterB_s1
assign jumpTargets_serverAdapterB_s1$D_IN =
{ jumpTargets_serverAdapterB_writeWithResp$whas, 1'b0 } ;
assign jumpTargets_serverAdapterB_s1$EN = 1'd1 ;
// register pc
assign pc$D_IN = pcWriteback_truePc[63:0] ;
assign pc$EN = EN_pcWriteback && pcWriteback_truePc[64] ;
// register registerTarget_taggedReg
assign registerTarget_taggedReg$D_IN =
WILL_FIRE_RL_registerTarget_rule_enq ?
MUX_registerTarget_taggedReg$write_1__VAL_1 :
73'h0AAAAAAAAAAAAAAAAAA ;
assign registerTarget_taggedReg$EN =
WILL_FIRE_RL_registerTarget_rule_enq ||
WILL_FIRE_RL_dumpRegisterTarget ||
WILL_FIRE_RL_reportRegisterTarget ;
// register specPc
assign specPc$D_IN = (issueEpoch == epoch) ? x__h8310 : pc ;
assign specPc$EN = EN_getPc && !getPc_fromDebug ;
// register state
assign state$D_IN = 1'd1 ;
assign state$EN = WILL_FIRE_RL_primeFifoRule && flushCount == 4'd1 ;
// register waitRegTarget
assign waitRegTarget$D_IN = MUX_waitRegTarget$write_1__SEL_1 ;
assign waitRegTarget$EN =
EN_putTarget && putTarget_branchType == 2'd3 &&
IF_putTarget_branchType_EQ_1_24_THEN_branchHis_ETC___d546 &&
!putTarget_fromDebug ||
WILL_FIRE_RL_reportRegisterTarget ;
// register waitRegTargetHist
assign waitRegTargetHist$D_IN =
branchHistory_serverAdapterA_outData_outData$wget ;
assign waitRegTargetHist$EN = MUX_waitRegTarget$write_1__SEL_1 ;
// submodule branchHistory_memory
assign branchHistory_memory$ADDRA = _theResult_____2__h8248[13:2] ;
assign branchHistory_memory$ADDRB = predictionCheck$D_OUT[11:0] ;
assign branchHistory_memory$DIA = 2'b10 /* unspecified value */ ;
assign branchHistory_memory$DIB =
IF_predictionCheck_first__77_BITS_23_TO_22_78__ETC___d508 ?
(predictionCheck$D_OUT[25] ?
IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q2[1:0] :
IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q3[1:0]) :
(predictionCheck$D_OUT[25] ?
IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q3[1:0] :
IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q2[1:0]) ;
assign branchHistory_memory$WEA = 1'd0 ;
assign branchHistory_memory$WEB = 1'd1 ;
assign branchHistory_memory$ENA = EN_getPc ;
assign branchHistory_memory$ENB =
branchHistory_serverAdapterB_writeWithResp$whas ;
// submodule branchHistory_serverAdapterA_outDataCore
assign branchHistory_serverAdapterA_outDataCore$D_IN =
branchHistory_memory$DOA ;
assign branchHistory_serverAdapterA_outDataCore$ENQ =
WILL_FIRE_RL_branchHistory_serverAdapterA_outData_enqAndDeq ||
branchHistory_serverAdapterA_outDataCore$FULL_N &&
!EN_putTarget &&
branchHistory_serverAdapterA_outData_enqData$whas ;
assign branchHistory_serverAdapterA_outDataCore$DEQ =
WILL_FIRE_RL_branchHistory_serverAdapterA_outData_enqAndDeq ||
branchHistory_serverAdapterA_outDataCore$EMPTY_N &&
EN_putTarget &&
!branchHistory_serverAdapterA_outData_enqData$whas ;
assign branchHistory_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule branchHistory_serverAdapterB_outDataCore
assign branchHistory_serverAdapterB_outDataCore$D_IN =
branchHistory_memory$DOB ;
assign branchHistory_serverAdapterB_outDataCore$ENQ =
branchHistory_serverAdapterB_outDataCore$FULL_N &&
branchHistory_serverAdapterB_outData_enqData$whas ;
assign branchHistory_serverAdapterB_outDataCore$DEQ = 1'b0 ;
assign branchHistory_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule flushFifo
assign flushFifo$D_IN = 1'd1 ;
assign flushFifo$ENQ =
EN_pcWriteback && pcWriteback_truePc[64] &&
pcWriteback_exception &&
!flushFifo$EMPTY_N ;
assign flushFifo$DEQ = WILL_FIRE_RL_flushDelay && flushCount == 4'd4 ;
assign flushFifo$CLR = 1'b0 ;
// submodule jumpTargets_memory
assign jumpTargets_memory$ADDRA = _theResult_____2__h8248[9:2] ;
assign jumpTargets_memory$ADDRB = predictionCheck$D_OUT[7:0] ;
assign jumpTargets_memory$DIA = 32'hAAAAAAAA /* unspecified value */ ;
assign jumpTargets_memory$DIB = pcWriteback_truePc_BITS_63_TO_0__q4[31:0] ;
assign jumpTargets_memory$WEA = 1'd0 ;
assign jumpTargets_memory$WEB = 1'd1 ;
assign jumpTargets_memory$ENA = EN_getPc ;
assign jumpTargets_memory$ENB =
jumpTargets_serverAdapterB_writeWithResp$whas ;
// submodule jumpTargets_serverAdapterA_outDataCore
assign jumpTargets_serverAdapterA_outDataCore$D_IN =
jumpTargets_memory$DOA ;
assign jumpTargets_serverAdapterA_outDataCore$ENQ =
WILL_FIRE_RL_jumpTargets_serverAdapterA_outData_enqAndDeq ||
jumpTargets_serverAdapterA_outDataCore$FULL_N && !EN_putTarget &&
jumpTargets_serverAdapterA_outData_enqData$whas ;
assign jumpTargets_serverAdapterA_outDataCore$DEQ =
WILL_FIRE_RL_jumpTargets_serverAdapterA_outData_enqAndDeq ||
jumpTargets_serverAdapterA_outDataCore$EMPTY_N && EN_putTarget &&
!jumpTargets_serverAdapterA_outData_enqData$whas ;
assign jumpTargets_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule jumpTargets_serverAdapterB_outDataCore
assign jumpTargets_serverAdapterB_outDataCore$D_IN =
jumpTargets_memory$DOB ;
assign jumpTargets_serverAdapterB_outDataCore$ENQ =
jumpTargets_serverAdapterB_outDataCore$FULL_N &&
jumpTargets_serverAdapterB_outData_enqData$whas ;
assign jumpTargets_serverAdapterB_outDataCore$DEQ = 1'b0 ;
assign jumpTargets_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule keys
assign keys$D_IN = { branchHist, _theResult_____2__h8248[17:2] } ;
assign keys$ENQ = EN_getPc ;
assign keys$DEQ =
EN_putTarget &&
(putTarget_branchType != 2'd3 ||
branchHistory_serverAdapterA_outData_outData$wget[1] ||
putTarget_fromDebug) ||
WILL_FIRE_RL_reportRegisterTarget ;
assign keys$CLR = 1'b0 ;
// submodule newEpoch
assign newEpoch$D_IN = epoch + 3'd1 ;
assign newEpoch$ENQ =
EN_pcWriteback && pcWriteback_truePc[64] &&
!pcWriteback_fromDebug &&
IF_predictionCheck_first__77_BITS_23_TO_22_78__ETC___d508 &&
!pcWriteback_exception ;
assign newEpoch$DEQ = EN_pcWriteback && newEpoch$EMPTY_N ;
assign newEpoch$CLR = 1'b0 ;
// submodule predictionCheck
assign predictionCheck$D_IN =
MUX_predictionCheck$enq_1__SEL_1 ?
MUX_predictionCheck$enq_1__VAL_1 :
MUX_predictionCheck$enq_1__VAL_2 ;
assign predictionCheck$ENQ =
EN_putTarget &&
(putTarget_branchType != 2'd3 ||
branchHistory_serverAdapterA_outData_outData$wget[1] ||
putTarget_fromDebug) ||
WILL_FIRE_RL_reportRegisterTarget ;
assign predictionCheck$DEQ = EN_pcWriteback ;
assign predictionCheck$CLR = 1'b0 ;
// submodule predictions
always@(MUX_predictions$enq_1__SEL_1 or
MUX_predictions$enq_1__VAL_1 or
WILL_FIRE_RL_reportRegisterTarget or
MUX_predictions$enq_1__VAL_2 or
WILL_FIRE_RL_primeFifoRule or MUX_predictions$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_predictions$enq_1__SEL_1:
predictions$D_IN = MUX_predictions$enq_1__VAL_1;
WILL_FIRE_RL_reportRegisterTarget:
predictions$D_IN = MUX_predictions$enq_1__VAL_2;
WILL_FIRE_RL_primeFifoRule:
predictions$D_IN = MUX_predictions$enq_1__VAL_3;
default: predictions$D_IN =
72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign predictions$ENQ =
EN_putTarget &&
(putTarget_branchType != 2'd3 ||
branchHistory_serverAdapterA_outData_outData$wget[1]) &&
!putTarget_fromDebug ||
WILL_FIRE_RL_reportRegisterTarget ||
WILL_FIRE_RL_primeFifoRule ;
assign predictions$DEQ = EN_getPc && !getPc_fromDebug ;
assign predictions$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q2 =
((IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d466 ^
3'h4) <
3'd2) ?
3'd6 :
IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d466 ;
assign IF_IF_SEXT_predictionCheck_first__77_BITS_25_T_ETC__q3 =
((IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d465 ^
3'h4) <
3'd2) ?
3'd6 :
IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d465 ;
assign IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d465 =
((SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d464 ^
3'h4) <=
3'd5) ?
SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d464 :
3'd1 ;
assign IF_SEXT_predictionCheck_first__77_BITS_25_TO_2_ETC___d466 =
((SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d462 ^
3'h4) <=
3'd5) ?
SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d462 :
3'd1 ;
assign IF_predictionCheck_first__77_BITS_23_TO_22_78__ETC___d508 =
(predictionCheck$D_OUT[23:22] == 2'd1) ?
!(predictionCheck_first__77_BITS_89_TO_26_89_EQ__ETC___d495 ^
predictionCheck$D_OUT[25]) :
predictionCheck$D_OUT[23:22] == 2'd3 &&
!predictionCheck_first__77_BITS_89_TO_26_89_EQ__ETC___d495 ;
assign IF_putTarget_branchType_EQ_1_24_THEN_branchHis_ETC___d546 =
(putTarget_branchType == 2'd1) ?
branchHistory_serverAdapterA_outData_outData$wget[1] :
putTarget_branchType != 2'd2 &&
(putTarget_branchType != 2'd3 ||
!branchHistory_serverAdapterA_outData_outData$wget[1]) ;
assign IF_registerTarget_rw_enq_whas_THEN_registerTar_ETC___d431 =
registerTarget_rw_enq$whas ?
registerTarget_rw_enq$wget[70:7] :
registerTarget_taggedReg[70:7] ;
assign SEXT_predictionCheck_first__77_BITS_25_TO_24_97___d463 =
{ predictionCheckD_OUT_BITS_25_TO_24__q1[1],
predictionCheckD_OUT_BITS_25_TO_24__q1 } ;
assign SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d462 =
SEXT_predictionCheck_first__77_BITS_25_TO_24_97___d463 + 3'd1 ;
assign SEXT_predictionCheck_first__77_BITS_25_TO_24_9_ETC___d464 =
SEXT_predictionCheck_first__77_BITS_25_TO_24_97___d463 + 3'd7 ;
assign _theResult_____2__h8248 =
(issueEpoch == predictions$D_OUT[6:4] && predictions$D_OUT[71]) ?
nextPc___1__h8384 :
specPc ;
assign branchHistory_serverAdapterA_cnt_8_PLUS_IF_bra_ETC___d44 =
branchHistory_serverAdapterA_cnt + (EN_getPc ? 3'd1 : 3'd0) +
(EN_putTarget ? 3'd7 : 3'd0) ;
assign branchHistory_serverAdapterA_outData_outData_w_ETC___d367 =
branchHistory_serverAdapterA_outData_outData$whas &&
(jumpTargets_serverAdapterA_outDataCore$EMPTY_N ||
jumpTargets_serverAdapterA_outData_enqData$whas) &&
predictionCheck$FULL_N &&
keys$EMPTY_N &&
predictions$FULL_N &&
jumpTargets_serverAdapterA_outData_outData$whas ;
assign jumpTargets_serverAdapterA_cnt_52_PLUS_IF_jump_ETC___d158 =
jumpTargets_serverAdapterA_cnt + (EN_getPc ? 3'd1 : 3'd0) +
(EN_putTarget ? 3'd7 : 3'd0) ;
assign nextPc___1__h8384 =
predictions$D_OUT[71] ? predictions$D_OUT[70:7] : specPc ;
assign pcWriteback_truePc_BITS_63_TO_0__q4 = pcWriteback_truePc[63:0] ;
assign predictionCheckD_OUT_BITS_25_TO_24__q1 =
predictionCheck$D_OUT[25:24] ;
assign predictionCheck_first__77_BITS_89_TO_26_89_EQ__ETC___d495 =
predictionCheck$D_OUT[89:26] == pcWriteback_truePc[63:0] ;
assign registerTarget_taggedReg_48_BIT_72_49_OR_regis_ETC___d256 =
(registerTarget_taggedReg[72] || registerTarget_rw_enq$whas) &&
predictions$FULL_N &&
predictionCheck$FULL_N &&
keys$EMPTY_N ;
assign v__h9023 =
jumpTargets_serverAdapterA_outDataCore$EMPTY_N ?
jumpTargets_serverAdapterA_outDataCore$D_OUT :
jumpTargets_memory$DOA ;
assign x__h8310 = _theResult_____2__h8248 + 64'd4 ;
always@(putTarget_branchType or putTarget_target or v__h9023)
begin
case (putTarget_branchType)
2'd1, 2'd2:
IF_putTarget_branchType_EQ_1_24_OR_putTarget_b_ETC___d547 =
putTarget_target;
default: IF_putTarget_branchType_EQ_1_24_OR_putTarget_b_ETC___d547 =
{ putTarget_target[63:32], v__h9023 };
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
branchHist <= `BSV_ASSIGNMENT_DELAY 6'd0;
branchHistory_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
branchHistory_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
branchHistory_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
branchHistory_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
countIn <= `BSV_ASSIGNMENT_DELAY 5'd0;
countOut <= `BSV_ASSIGNMENT_DELAY 5'd0;
epoch <= `BSV_ASSIGNMENT_DELAY 3'd0;
flushCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
issueEpoch <= `BSV_ASSIGNMENT_DELAY 3'd0;
jumpTargets_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
jumpTargets_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
jumpTargets_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
jumpTargets_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
pc <= `BSV_ASSIGNMENT_DELAY 64'h9000000040000000;
registerTarget_taggedReg <= `BSV_ASSIGNMENT_DELAY
73'h0AAAAAAAAAAAAAAAAAA;
specPc <= `BSV_ASSIGNMENT_DELAY 64'd0;
state <= `BSV_ASSIGNMENT_DELAY 1'd0;
waitRegTarget <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (branchHist$EN)
branchHist <= `BSV_ASSIGNMENT_DELAY branchHist$D_IN;
if (branchHistory_serverAdapterA_cnt$EN)
branchHistory_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
branchHistory_serverAdapterA_cnt$D_IN;
if (branchHistory_serverAdapterA_s1$EN)
branchHistory_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
branchHistory_serverAdapterA_s1$D_IN;
if (branchHistory_serverAdapterB_cnt$EN)
branchHistory_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
branchHistory_serverAdapterB_cnt$D_IN;
if (branchHistory_serverAdapterB_s1$EN)
branchHistory_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
branchHistory_serverAdapterB_s1$D_IN;
if (countIn$EN) countIn <= `BSV_ASSIGNMENT_DELAY countIn$D_IN;
if (countOut$EN) countOut <= `BSV_ASSIGNMENT_DELAY countOut$D_IN;
if (epoch$EN) epoch <= `BSV_ASSIGNMENT_DELAY epoch$D_IN;
if (flushCount$EN)
flushCount <= `BSV_ASSIGNMENT_DELAY flushCount$D_IN;
if (issueEpoch$EN)
issueEpoch <= `BSV_ASSIGNMENT_DELAY issueEpoch$D_IN;
if (jumpTargets_serverAdapterA_cnt$EN)
jumpTargets_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
jumpTargets_serverAdapterA_cnt$D_IN;
if (jumpTargets_serverAdapterA_s1$EN)
jumpTargets_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
jumpTargets_serverAdapterA_s1$D_IN;
if (jumpTargets_serverAdapterB_cnt$EN)
jumpTargets_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
jumpTargets_serverAdapterB_cnt$D_IN;
if (jumpTargets_serverAdapterB_s1$EN)
jumpTargets_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
jumpTargets_serverAdapterB_s1$D_IN;
if (pc$EN) pc <= `BSV_ASSIGNMENT_DELAY pc$D_IN;
if (registerTarget_taggedReg$EN)
registerTarget_taggedReg <= `BSV_ASSIGNMENT_DELAY
registerTarget_taggedReg$D_IN;
if (specPc$EN) specPc <= `BSV_ASSIGNMENT_DELAY specPc$D_IN;
if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN;
if (waitRegTarget$EN)
waitRegTarget <= `BSV_ASSIGNMENT_DELAY waitRegTarget$D_IN;
end
if (waitRegTargetHist$EN)
waitRegTargetHist <= `BSV_ASSIGNMENT_DELAY waitRegTargetHist$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
branchHist = 6'h2A;
branchHistory_serverAdapterA_cnt = 3'h2;
branchHistory_serverAdapterA_s1 = 2'h2;
branchHistory_serverAdapterB_cnt = 3'h2;
branchHistory_serverAdapterB_s1 = 2'h2;
countIn = 5'h0A;
countOut = 5'h0A;
epoch = 3'h2;
flushCount = 4'hA;
issueEpoch = 3'h2;
jumpTargets_serverAdapterA_cnt = 3'h2;
jumpTargets_serverAdapterA_s1 = 2'h2;
jumpTargets_serverAdapterB_cnt = 3'h2;
jumpTargets_serverAdapterB_s1 = 2'h2;
pc = 64'hAAAAAAAAAAAAAAAA;
registerTarget_taggedReg = 73'h0AAAAAAAAAAAAAAAAAA;
specPc = 64'hAAAAAAAAAAAAAAAA;
state = 1'h0;
waitRegTarget = 1'h0;
waitRegTargetHist = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (branchHistory_serverAdapterA_s1[1] &&
!branchHistory_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N)
if (branchHistory_serverAdapterB_s1[1] &&
!branchHistory_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N)
if (jumpTargets_serverAdapterA_s1[1] &&
!jumpTargets_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N)
if (jumpTargets_serverAdapterB_s1[1] &&
!jumpTargets_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
end
// synopsys translate_on
endmodule // mkBranch
|
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Thu Jun 21 15:25:16 BST 2012
//
// Method conflict info:
// Method: capMem_request_get
// Conflict-free: capMem_response_put,
// iGet,
// putCapInst,
// getCapResponse,
// hadException,
// commitWriteback
// Conflicts: capMem_request_get
//
// Method: capMem_response_put
// Conflict-free: capMem_request_get,
// iGet,
// putCapInst,
// getCapResponse,
// hadException,
// commitWriteback
// Conflicts: capMem_response_put
//
// Method: iGet
// Conflict-free: capMem_request_get,
// capMem_response_put,
// putCapInst,
// commitWriteback
// Sequenced before: getCapResponse, hadException
// Conflicts: iGet
//
// Method: putCapInst
// Conflict-free: capMem_request_get,
// capMem_response_put,
// iGet,
// getCapResponse,
// hadException,
// commitWriteback
// Conflicts: putCapInst
//
// Method: getCapResponse
// Conflict-free: capMem_request_get,
// capMem_response_put,
// putCapInst,
// hadException,
// commitWriteback
// Sequenced after: iGet
// Conflicts: getCapResponse
//
// Method: hadException
// Conflict-free: capMem_request_get,
// capMem_response_put,
// putCapInst,
// getCapResponse,
// commitWriteback
// Sequenced after: iGet
// Conflicts: hadException
//
// Method: commitWriteback
// Conflict-free: capMem_request_get,
// capMem_response_put,
// iGet,
// putCapInst,
// getCapResponse,
// hadException
// Conflicts: commitWriteback
//
//
// Ports:
// Name I/O size props
// capMem_request_get O 322 reg
// RDY_capMem_request_get O 1 reg
// RDY_capMem_response_put O 1
// iGet O 65
// RDY_iGet O 1
// RDY_putCapInst O 1
// getCapResponse O 65
// RDY_getCapResponse O 1
// RDY_hadException O 1 reg
// RDY_commitWriteback O 1
// CLK I 1 clock
// RST_N I 1 reset
// capMem_response_put I 256
// iGet_capReq I 75
// putCapInst_capInst I 87
// getCapResponse_capReq I 75
// hadException_expEvent I 1 reg
// commitWriteback_wbReq I 5
// EN_capMem_response_put I 1
// EN_putCapInst I 1
// EN_hadException I 1
// EN_commitWriteback I 1
// EN_capMem_request_get I 1
// EN_iGet I 1
// EN_getCapResponse I 1
//
// Combinational paths from inputs to outputs:
// iGet_capReq -> iGet
// getCapResponse_capReq -> getCapResponse
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkCapCop(CLK,
RST_N,
EN_capMem_request_get,
capMem_request_get,
RDY_capMem_request_get,
capMem_response_put,
EN_capMem_response_put,
RDY_capMem_response_put,
iGet_capReq,
EN_iGet,
iGet,
RDY_iGet,
putCapInst_capInst,
EN_putCapInst,
RDY_putCapInst,
getCapResponse_capReq,
EN_getCapResponse,
getCapResponse,
RDY_getCapResponse,
hadException_expEvent,
EN_hadException,
RDY_hadException,
commitWriteback_wbReq,
EN_commitWriteback,
RDY_commitWriteback);
input CLK;
input RST_N;
// actionvalue method capMem_request_get
input EN_capMem_request_get;
output [321 : 0] capMem_request_get;
output RDY_capMem_request_get;
// action method capMem_response_put
input [255 : 0] capMem_response_put;
input EN_capMem_response_put;
output RDY_capMem_response_put;
// actionvalue method iGet
input [74 : 0] iGet_capReq;
input EN_iGet;
output [64 : 0] iGet;
output RDY_iGet;
// action method putCapInst
input [86 : 0] putCapInst_capInst;
input EN_putCapInst;
output RDY_putCapInst;
// actionvalue method getCapResponse
input [74 : 0] getCapResponse_capReq;
input EN_getCapResponse;
output [64 : 0] getCapResponse;
output RDY_getCapResponse;
// action method hadException
input hadException_expEvent;
input EN_hadException;
output RDY_hadException;
// action method commitWriteback
input [4 : 0] commitWriteback_wbReq;
input EN_commitWriteback;
output RDY_commitWriteback;
// signals for module outputs
wire [321 : 0] capMem_request_get;
wire [64 : 0] getCapResponse, iGet;
wire RDY_capMem_request_get,
RDY_capMem_response_put,
RDY_commitWriteback,
RDY_getCapResponse,
RDY_hadException,
RDY_iGet,
RDY_putCapInst;
// inlined wires
wire commitWritebackFifo_rw_enq$whas;
// register capState
reg [2 : 0] capState;
reg [2 : 0] capState$D_IN;
wire capState$EN;
// register capWriteback
reg [265 : 0] capWriteback;
wire [265 : 0] capWriteback$D_IN;
wire capWriteback$EN;
// register commitWritebackFifo_taggedReg
reg [1 : 0] commitWritebackFifo_taggedReg;
wire [1 : 0] commitWritebackFifo_taggedReg$D_IN;
wire commitWritebackFifo_taggedReg$EN;
// register count
reg [4 : 0] count;
wire [4 : 0] count$D_IN;
wire count$EN;
// register pcc
reg [255 : 0] pcc;
wire [255 : 0] pcc$D_IN;
wire pcc$EN;
// register pipeEmpty
reg pipeEmpty;
wire pipeEmpty$D_IN, pipeEmpty$EN;
// register writesCalculated
reg [4 : 0] writesCalculated;
wire [4 : 0] writesCalculated$D_IN;
wire writesCalculated$EN;
// register writesDone
reg [4 : 0] writesDone;
wire [4 : 0] writesDone$D_IN;
wire writesDone$EN;
// register writesIn
reg [4 : 0] writesIn;
wire [4 : 0] writesIn$D_IN;
wire writesIn$EN;
// ports of submodule baseRegs
reg [63 : 0] baseRegs$D_IN;
reg [4 : 0] baseRegs$ADDR_IN;
wire [63 : 0] baseRegs$D_OUT_1, baseRegs$D_OUT_2;
wire [4 : 0] baseRegs$ADDR_1,
baseRegs$ADDR_2,
baseRegs$ADDR_3,
baseRegs$ADDR_4,
baseRegs$ADDR_5;
wire baseRegs$WE;
// ports of submodule capInsts
wire [96 : 0] capInsts$D_IN, capInsts$D_OUT;
wire capInsts$CLR,
capInsts$DEQ,
capInsts$EMPTY_N,
capInsts$ENQ,
capInsts$FULL_N;
// ports of submodule capMemInsts
wire [334 : 0] capMemInsts$D_IN, capMemInsts$D_OUT;
wire capMemInsts$CLR,
capMemInsts$DEQ,
capMemInsts$EMPTY_N,
capMemInsts$ENQ,
capMemInsts$FULL_N;
// ports of submodule capWritebackTags
wire [9 : 0] capWritebackTags$D_IN, capWritebackTags$D_OUT;
wire capWritebackTags$CLR,
capWritebackTags$DEQ,
capWritebackTags$EMPTY_N,
capWritebackTags$ENQ,
capWritebackTags$FULL_N;
// ports of submodule commitStore
wire commitStore$CLR,
commitStore$DEQ,
commitStore$D_IN,
commitStore$D_OUT,
commitStore$EMPTY_N,
commitStore$ENQ,
commitStore$FULL_N;
// ports of submodule exception
wire exception$CLR,
exception$DEQ,
exception$D_IN,
exception$D_OUT,
exception$EMPTY_N,
exception$ENQ,
exception$FULL_N;
// ports of submodule fetchFifoA
wire [4 : 0] fetchFifoA$D_IN, fetchFifoA$D_OUT;
wire fetchFifoA$CLR,
fetchFifoA$DEQ,
fetchFifoA$EMPTY_N,
fetchFifoA$ENQ,
fetchFifoA$FULL_N;
// ports of submodule fetchFifoB
wire [4 : 0] fetchFifoB$D_IN, fetchFifoB$D_OUT;
wire fetchFifoB$CLR,
fetchFifoB$DEQ,
fetchFifoB$EMPTY_N,
fetchFifoB$ENQ,
fetchFifoB$FULL_N;
// ports of submodule insts
wire insts$CLR,
insts$DEQ,
insts$D_IN,
insts$EMPTY_N,
insts$ENQ,
insts$FULL_N;
// ports of submodule lengthRegs
reg [63 : 0] lengthRegs$D_IN;
reg [4 : 0] lengthRegs$ADDR_IN;
wire [63 : 0] lengthRegs$D_OUT_1, lengthRegs$D_OUT_2;
wire [4 : 0] lengthRegs$ADDR_1,
lengthRegs$ADDR_2,
lengthRegs$ADDR_3,
lengthRegs$ADDR_4,
lengthRegs$ADDR_5;
wire lengthRegs$WE;
// ports of submodule memAccesses
wire [321 : 0] memAccesses$D_IN, memAccesses$D_OUT;
wire memAccesses$CLR,
memAccesses$DEQ,
memAccesses$EMPTY_N,
memAccesses$ENQ,
memAccesses$FULL_N;
// ports of submodule memResponse
wire [255 : 0] memResponse$D_IN;
wire memResponse$CLR, memResponse$DEQ, memResponse$ENQ, memResponse$FULL_N;
// ports of submodule nextCapState
wire [2 : 0] nextCapState$D_IN, nextCapState$D_OUT;
wire nextCapState$CLR,
nextCapState$DEQ,
nextCapState$EMPTY_N,
nextCapState$ENQ;
// ports of submodule nextWillWriteback
wire nextWillWriteback$CLR,
nextWillWriteback$DEQ,
nextWillWriteback$D_IN,
nextWillWriteback$D_OUT,
nextWillWriteback$EMPTY_N,
nextWillWriteback$ENQ,
nextWillWriteback$FULL_N;
// ports of submodule oTypeRegs
reg [63 : 0] oTypeRegs$D_IN;
reg [4 : 0] oTypeRegs$ADDR_IN;
wire [63 : 0] oTypeRegs$D_OUT_1;
wire [4 : 0] oTypeRegs$ADDR_1,
oTypeRegs$ADDR_2,
oTypeRegs$ADDR_3,
oTypeRegs$ADDR_4,
oTypeRegs$ADDR_5;
wire oTypeRegs$WE;
// ports of submodule permRegs
reg [63 : 0] permRegs$D_IN;
reg [4 : 0] permRegs$ADDR_IN;
wire [63 : 0] permRegs$D_OUT_1;
wire [4 : 0] permRegs$ADDR_1,
permRegs$ADDR_2,
permRegs$ADDR_3,
permRegs$ADDR_4,
permRegs$ADDR_5;
wire permRegs$WE;
// ports of submodule startExp
wire startExp$CLR,
startExp$DEQ,
startExp$D_IN,
startExp$EMPTY_N,
startExp$ENQ,
startExp$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_capMemoryLoad,
WILL_FIRE_RL_capMemoryStore,
WILL_FIRE_RL_commitWritebackFifo_rule_enq,
WILL_FIRE_RL_finishException,
WILL_FIRE_RL_startException,
WILL_FIRE_RL_writeBack;
// inputs to muxes for submodule ports
wire [321 : 0] MUX_memAccesses$enq_1__VAL_1, MUX_memAccesses$enq_1__VAL_2;
wire [265 : 0] MUX_capWriteback$write_1__VAL_1,
MUX_capWriteback$write_1__VAL_2;
wire [255 : 0] MUX_pcc$write_1__VAL_2;
wire [9 : 0] MUX_capWritebackTags$enq_1__VAL_1,
MUX_capWritebackTags$enq_1__VAL_2;
wire [4 : 0] MUX_fetchFifoA$enq_1__VAL_1,
MUX_fetchFifoA$enq_1__VAL_2,
MUX_writesCalculated$write_1__VAL_1;
wire [2 : 0] MUX_capState$write_1__VAL_2;
wire MUX_baseRegs$upd_1__SEL_1,
MUX_capState$write_1__SEL_1,
MUX_capState$write_1__SEL_2,
MUX_capState$write_1__SEL_4,
MUX_capWriteback$write_1__SEL_1,
MUX_capWritebackTags$enq_1__SEL_1,
MUX_memAccesses$enq_1__SEL_1,
MUX_pcc$write_1__SEL_1,
MUX_writesCalculated$write_1__SEL_1;
// remaining internal signals
reg [127 : 0] CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q6;
reg [63 : 0] CASE_capInstsD_OUT_BITS_96_TO_92_IF_NOT_capIn_ETC__q4,
IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d895,
_theResult_____8_fst_oType_eaddr__h13470;
reg [14 : 0] CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q5;
reg [5 : 0] x__h6671;
reg [4 : 0] CASE_capInstsD_OUT_BITS_96_TO_92_31_0_capInst_ETC__q7,
CASE_capMemInstsD_OUT_BITS_334_TO_330_31_0_ca_ETC__q8,
CASE_putCapInst_capInst_BITS_86_TO_82_0_1_putC_ETC__q3,
CASE_putCapInst_capInst_BITS_86_TO_82_31_0_put_ETC__q9,
x__h13350;
reg CASE_capInstsD_OUT_BITS_17_TO_15_NOT_capInsts_ETC__q2,
CASE_capInstsD_OUT_BITS_96_TO_92_NOT_capInsts_ETC__q1,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d819,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d634;
wire [255 : 0] IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d960;
wire [254 : 0] IF_capInsts_first__28_BITS_96_TO_92_29_EQ_0_32_ETC___d679,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d680,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1152;
wire [127 : 0] IF_IF_capInsts_first__28_BITS_9_TO_5_02_EQ_cap_ETC___d669,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1150,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d664;
wire [73 : 0] getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d558;
wire [63 : 0] IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d940,
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1109,
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d542,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968,
_theResult_____8_fst_oType_eaddr__h13460,
writeback___1_base__h13507,
x1_avValue_base__h9411,
x1_avValue_oType_eaddr__h9410;
wire [47 : 0] x1_avValue_reserved__h9409;
wire [39 : 0] IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1133;
wire [23 : 0] IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1110;
wire [15 : 0] x__h14462;
wire [14 : 0] IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1149;
wire [5 : 0] x__h12726;
wire [4 : 0] IF_putCapInst_capInst_BITS_86_TO_82_11_EQ_0_12_ETC___d939,
x__h8745,
x__h8753;
wire IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d820,
IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d823,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d635,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d825,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1030,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d565,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d626,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d629,
NOT_capInsts_first__28_BITS_96_TO_92_29_EQ_0_3_ETC___d569,
capInsts_first__28_BITS_96_TO_92_29_EQ_16_34_O_ETC___d817,
capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_OR_ETC___d589,
capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_OR_ETC___d730,
capState_read_EQ_5_9_OR_capState_read_EQ_1_6_0_ETC___d906,
commitWriteback_wbReq_BITS_3_TO_0_15_EQ_capWri_ETC___d918,
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_0_C_ETC___d1135,
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d971,
getCapResponse_capReq_BITS_69_TO_6_54_ULT_IF_c_ETC___d972,
pcc_7_BIT_244_46_OR_NOT_IF_capInsts_first__28__ETC___d822;
// actionvalue method capMem_request_get
assign capMem_request_get = memAccesses$D_OUT ;
assign RDY_capMem_request_get = memAccesses$EMPTY_N ;
// action method capMem_response_put
assign RDY_capMem_response_put =
memResponse$FULL_N && capMemInsts$EMPTY_N && capState == 3'd2 &&
capWritebackTags$FULL_N ;
// actionvalue method iGet
assign iGet =
{ iGet_capReq[45:6] + { 34'd0, x__h6671 } <= pcc[39:0],
pcc[127:104] + iGet_capReq[69:46],
pcc[103:64] + iGet_capReq[45:6] } ;
assign RDY_iGet = !exception$EMPTY_N && insts$FULL_N ;
// action method putCapInst
assign RDY_putCapInst =
capState == 3'd5 && writesIn - writesDone <= 5'd2 &&
fetchFifoA$FULL_N &&
fetchFifoB$FULL_N &&
capInsts$FULL_N &&
nextWillWriteback$FULL_N ;
// actionvalue method getCapResponse
assign getCapResponse =
{ IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d825,
IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d940 } ;
assign RDY_getCapResponse =
nextWillWriteback$EMPTY_N &&
capState_read_EQ_5_9_OR_capState_read_EQ_1_6_0_ETC___d906 &&
fetchFifoA$EMPTY_N &&
capInsts$EMPTY_N &&
fetchFifoB$EMPTY_N &&
capMemInsts$FULL_N &&
capWritebackTags$FULL_N ;
// action method hadException
assign RDY_hadException = exception$FULL_N ;
// action method commitWriteback
assign RDY_commitWriteback =
capState != 3'd0 && capState != 3'd3 &&
capWritebackTags$EMPTY_N &&
insts$EMPTY_N &&
!commitWritebackFifo_taggedReg[1] &&
commitStore$FULL_N ;
// submodule baseRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) baseRegs(.CLK(CLK),
.ADDR_1(baseRegs$ADDR_1),
.ADDR_2(baseRegs$ADDR_2),
.ADDR_3(baseRegs$ADDR_3),
.ADDR_4(baseRegs$ADDR_4),
.ADDR_5(baseRegs$ADDR_5),
.ADDR_IN(baseRegs$ADDR_IN),
.D_IN(baseRegs$D_IN),
.WE(baseRegs$WE),
.D_OUT_1(baseRegs$D_OUT_1),
.D_OUT_2(baseRegs$D_OUT_2),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule capInsts
SizedFIFO #(.p1width(32'd97),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) capInsts(.RST_N(RST_N),
.CLK(CLK),
.D_IN(capInsts$D_IN),
.ENQ(capInsts$ENQ),
.DEQ(capInsts$DEQ),
.CLR(capInsts$CLR),
.D_OUT(capInsts$D_OUT),
.FULL_N(capInsts$FULL_N),
.EMPTY_N(capInsts$EMPTY_N));
// submodule capMemInsts
FIFO1 #(.width(32'd335), .guarded(32'd1)) capMemInsts(.RST_N(RST_N),
.CLK(CLK),
.D_IN(capMemInsts$D_IN),
.ENQ(capMemInsts$ENQ),
.DEQ(capMemInsts$DEQ),
.CLR(capMemInsts$CLR),
.D_OUT(capMemInsts$D_OUT),
.FULL_N(capMemInsts$FULL_N),
.EMPTY_N(capMemInsts$EMPTY_N));
// submodule capWritebackTags
FIFO2 #(.width(32'd10), .guarded(32'd1)) capWritebackTags(.RST_N(RST_N),
.CLK(CLK),
.D_IN(capWritebackTags$D_IN),
.ENQ(capWritebackTags$ENQ),
.DEQ(capWritebackTags$DEQ),
.CLR(capWritebackTags$CLR),
.D_OUT(capWritebackTags$D_OUT),
.FULL_N(capWritebackTags$FULL_N),
.EMPTY_N(capWritebackTags$EMPTY_N));
// submodule commitStore
FIFO2 #(.width(32'd1), .guarded(32'd1)) commitStore(.RST_N(RST_N),
.CLK(CLK),
.D_IN(commitStore$D_IN),
.ENQ(commitStore$ENQ),
.DEQ(commitStore$DEQ),
.CLR(commitStore$CLR),
.D_OUT(commitStore$D_OUT),
.FULL_N(commitStore$FULL_N),
.EMPTY_N(commitStore$EMPTY_N));
// submodule exception
FIFO1 #(.width(32'd1), .guarded(32'd1)) exception(.RST_N(RST_N),
.CLK(CLK),
.D_IN(exception$D_IN),
.ENQ(exception$ENQ),
.DEQ(exception$DEQ),
.CLR(exception$CLR),
.D_OUT(exception$D_OUT),
.FULL_N(exception$FULL_N),
.EMPTY_N(exception$EMPTY_N));
// submodule fetchFifoA
SizedFIFO #(.p1width(32'd5),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) fetchFifoA(.RST_N(RST_N),
.CLK(CLK),
.D_IN(fetchFifoA$D_IN),
.ENQ(fetchFifoA$ENQ),
.DEQ(fetchFifoA$DEQ),
.CLR(fetchFifoA$CLR),
.D_OUT(fetchFifoA$D_OUT),
.FULL_N(fetchFifoA$FULL_N),
.EMPTY_N(fetchFifoA$EMPTY_N));
// submodule fetchFifoB
SizedFIFO #(.p1width(32'd5),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) fetchFifoB(.RST_N(RST_N),
.CLK(CLK),
.D_IN(fetchFifoB$D_IN),
.ENQ(fetchFifoB$ENQ),
.DEQ(fetchFifoB$DEQ),
.CLR(fetchFifoB$CLR),
.D_OUT(fetchFifoB$D_OUT),
.FULL_N(fetchFifoB$FULL_N),
.EMPTY_N(fetchFifoB$EMPTY_N));
// submodule insts
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) insts(.RST_N(RST_N),
.CLK(CLK),
.D_IN(insts$D_IN),
.ENQ(insts$ENQ),
.DEQ(insts$DEQ),
.CLR(insts$CLR),
.D_OUT(),
.FULL_N(insts$FULL_N),
.EMPTY_N(insts$EMPTY_N));
// submodule lengthRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) lengthRegs(.CLK(CLK),
.ADDR_1(lengthRegs$ADDR_1),
.ADDR_2(lengthRegs$ADDR_2),
.ADDR_3(lengthRegs$ADDR_3),
.ADDR_4(lengthRegs$ADDR_4),
.ADDR_5(lengthRegs$ADDR_5),
.ADDR_IN(lengthRegs$ADDR_IN),
.D_IN(lengthRegs$D_IN),
.WE(lengthRegs$WE),
.D_OUT_1(lengthRegs$D_OUT_1),
.D_OUT_2(lengthRegs$D_OUT_2),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule memAccesses
FIFO1 #(.width(32'd322), .guarded(32'd1)) memAccesses(.RST_N(RST_N),
.CLK(CLK),
.D_IN(memAccesses$D_IN),
.ENQ(memAccesses$ENQ),
.DEQ(memAccesses$DEQ),
.CLR(memAccesses$CLR),
.D_OUT(memAccesses$D_OUT),
.FULL_N(memAccesses$FULL_N),
.EMPTY_N(memAccesses$EMPTY_N));
// submodule memResponse
FIFO2 #(.width(32'd256), .guarded(32'd0)) memResponse(.RST_N(RST_N),
.CLK(CLK),
.D_IN(memResponse$D_IN),
.ENQ(memResponse$ENQ),
.DEQ(memResponse$DEQ),
.CLR(memResponse$CLR),
.D_OUT(),
.FULL_N(memResponse$FULL_N),
.EMPTY_N());
// submodule nextCapState
FIFO2 #(.width(32'd3), .guarded(32'd0)) nextCapState(.RST_N(RST_N),
.CLK(CLK),
.D_IN(nextCapState$D_IN),
.ENQ(nextCapState$ENQ),
.DEQ(nextCapState$DEQ),
.CLR(nextCapState$CLR),
.D_OUT(nextCapState$D_OUT),
.FULL_N(),
.EMPTY_N(nextCapState$EMPTY_N));
// submodule nextWillWriteback
FIFO2 #(.width(32'd1), .guarded(32'd1)) nextWillWriteback(.RST_N(RST_N),
.CLK(CLK),
.D_IN(nextWillWriteback$D_IN),
.ENQ(nextWillWriteback$ENQ),
.DEQ(nextWillWriteback$DEQ),
.CLR(nextWillWriteback$CLR),
.D_OUT(nextWillWriteback$D_OUT),
.FULL_N(nextWillWriteback$FULL_N),
.EMPTY_N(nextWillWriteback$EMPTY_N));
// submodule oTypeRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) oTypeRegs(.CLK(CLK),
.ADDR_1(oTypeRegs$ADDR_1),
.ADDR_2(oTypeRegs$ADDR_2),
.ADDR_3(oTypeRegs$ADDR_3),
.ADDR_4(oTypeRegs$ADDR_4),
.ADDR_5(oTypeRegs$ADDR_5),
.ADDR_IN(oTypeRegs$ADDR_IN),
.D_IN(oTypeRegs$D_IN),
.WE(oTypeRegs$WE),
.D_OUT_1(oTypeRegs$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule permRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) permRegs(.CLK(CLK),
.ADDR_1(permRegs$ADDR_1),
.ADDR_2(permRegs$ADDR_2),
.ADDR_3(permRegs$ADDR_3),
.ADDR_4(permRegs$ADDR_4),
.ADDR_5(permRegs$ADDR_5),
.ADDR_IN(permRegs$ADDR_IN),
.D_IN(permRegs$D_IN),
.WE(permRegs$WE),
.D_OUT_1(permRegs$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule startExp
FIFO1 #(.width(32'd1), .guarded(32'd1)) startExp(.RST_N(RST_N),
.CLK(CLK),
.D_IN(startExp$D_IN),
.ENQ(startExp$ENQ),
.DEQ(startExp$DEQ),
.CLR(startExp$CLR),
.D_OUT(),
.FULL_N(startExp$FULL_N),
.EMPTY_N(startExp$EMPTY_N));
// rule RL_capMemoryLoad
assign WILL_FIRE_RL_capMemoryLoad =
capMemInsts$EMPTY_N && memAccesses$FULL_N && capState == 3'd1 &&
capMemInsts$D_OUT[334:330] == 5'd10 ;
// rule RL_capMemoryStore
assign WILL_FIRE_RL_capMemoryStore =
capMemInsts$EMPTY_N && commitStore$EMPTY_N &&
memAccesses$FULL_N &&
(capState == 3'd5 || capState == 3'd1) &&
capMemInsts$D_OUT[334:330] == 5'd9 ;
// rule RL_startException
assign WILL_FIRE_RL_startException =
exception$EMPTY_N && fetchFifoA$FULL_N && startExp$FULL_N &&
capState == 3'd3 ;
// rule RL_finishException
assign WILL_FIRE_RL_finishException =
exception$EMPTY_N && fetchFifoA$EMPTY_N && startExp$EMPTY_N &&
capState == 3'd3 &&
!WILL_FIRE_RL_startException ;
// rule RL_writeBack
assign WILL_FIRE_RL_writeBack =
(commitWritebackFifo_taggedReg[1] ||
commitWritebackFifo_rw_enq$whas) &&
capState != 3'd0 &&
capState != 3'd3 ;
// rule RL_commitWritebackFifo_rule_enq
assign WILL_FIRE_RL_commitWritebackFifo_rule_enq =
commitWritebackFifo_rw_enq$whas && !WILL_FIRE_RL_writeBack ;
// inputs to muxes for submodule ports
assign MUX_baseRegs$upd_1__SEL_1 =
WILL_FIRE_RL_startException && !exception$D_OUT ;
assign MUX_capState$write_1__SEL_1 = capState == 3'd0 && count == 5'd31 ;
assign MUX_capState$write_1__SEL_2 =
capState == 3'd5 &&
(exception$EMPTY_N && pipeEmpty || nextCapState$EMPTY_N) ;
assign MUX_capState$write_1__SEL_4 =
WILL_FIRE_RL_finishException || EN_capMem_response_put ;
assign MUX_capWriteback$write_1__SEL_1 =
EN_getCapResponse &&
capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_OR_ETC___d589 ;
assign MUX_capWritebackTags$enq_1__SEL_1 =
EN_getCapResponse && capInsts$D_OUT[96:92] != 5'd10 ;
assign MUX_memAccesses$enq_1__SEL_1 =
WILL_FIRE_RL_capMemoryStore && capMemInsts$D_OUT[73] &&
commitStore$D_OUT ;
assign MUX_pcc$write_1__SEL_1 =
EN_getCapResponse &&
(capInsts$D_OUT[96:92] == 5'd7 ||
capInsts$D_OUT[96:92] == 5'd8) ;
assign MUX_writesCalculated$write_1__SEL_1 =
EN_getCapResponse &&
(capInsts$D_OUT[96:92] == 5'd4 ||
NOT_capInsts_first__28_BITS_96_TO_92_29_EQ_0_3_ETC___d569) ;
assign MUX_capState$write_1__VAL_2 =
(exception$EMPTY_N && pipeEmpty) ? 3'd3 : nextCapState$D_OUT ;
assign MUX_capWriteback$write_1__VAL_1 =
{ 1'd1,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d635,
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d680,
x__h13350,
capInsts$D_OUT[13:10] } ;
assign MUX_capWriteback$write_1__VAL_2 =
{ (pcc[244] || capMemInsts$D_OUT[8:4] != 5'd28) &&
(pcc[243] || capMemInsts$D_OUT[8:4] != 5'd29) &&
(pcc[242] || capMemInsts$D_OUT[8:4] != 5'd30) &&
(pcc[241] || capMemInsts$D_OUT[8:4] != 5'd31),
capMem_response_put,
capMemInsts$D_OUT[8:0] } ;
assign MUX_capWritebackTags$enq_1__VAL_1 =
{ CASE_capInstsD_OUT_BITS_96_TO_92_31_0_capInst_ETC__q7,
capInsts$D_OUT[13:10],
capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_OR_ETC___d730 } ;
assign MUX_capWritebackTags$enq_1__VAL_2 =
{ CASE_capMemInstsD_OUT_BITS_334_TO_330_31_0_ca_ETC__q8,
capMemInsts$D_OUT[3:0],
(pcc[244] || capMemInsts$D_OUT[8:4] != 5'd28) &&
(pcc[243] || capMemInsts$D_OUT[8:4] != 5'd29) &&
(pcc[242] || capMemInsts$D_OUT[8:4] != 5'd30) &&
(pcc[241] || capMemInsts$D_OUT[8:4] != 5'd31) } ;
assign MUX_fetchFifoA$enq_1__VAL_1 = exception$D_OUT ? 5'd31 : 5'd29 ;
assign MUX_fetchFifoA$enq_1__VAL_2 =
(putCapInst_capInst[86:82] == 5'd2 ||
putCapInst_capInst[86:82] == 5'd3 ||
putCapInst_capInst[86:82] == 5'd5 ||
putCapInst_capInst[86:82] == 5'd6) ?
5'd0 :
IF_putCapInst_capInst_BITS_86_TO_82_11_EQ_0_12_ETC___d939 ;
assign MUX_memAccesses$enq_1__VAL_1 =
{ 2'd1, capMemInsts$D_OUT[72:9], capMemInsts$D_OUT[329:74] } ;
assign MUX_memAccesses$enq_1__VAL_2 =
{ 2'd0,
capMemInsts$D_OUT[72:9],
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_pcc$write_1__VAL_2 =
{ permRegs$D_OUT_1,
oTypeRegs$D_OUT_1,
baseRegs$D_OUT_2,
lengthRegs$D_OUT_2 } ;
assign MUX_writesCalculated$write_1__VAL_1 = writesCalculated + 5'd1 ;
// inlined wires
assign commitWritebackFifo_rw_enq$whas =
EN_commitWriteback &&
commitWriteback_wbReq_BITS_3_TO_0_15_EQ_capWri_ETC___d918 &&
capWritebackTags$D_OUT[0] &&
capWritebackTags$D_OUT[4:1] == capWriteback[3:0] &&
commitWriteback_wbReq[4] ;
// register capState
always@(MUX_capState$write_1__SEL_2 or
MUX_capState$write_1__VAL_2 or
WILL_FIRE_RL_capMemoryLoad or
MUX_capState$write_1__SEL_1 or MUX_capState$write_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_capState$write_1__SEL_2:
capState$D_IN = MUX_capState$write_1__VAL_2;
WILL_FIRE_RL_capMemoryLoad: capState$D_IN = 3'd2;
MUX_capState$write_1__SEL_1 || MUX_capState$write_1__SEL_4:
capState$D_IN = 3'd5;
default: capState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign capState$EN =
capState == 3'd0 && count == 5'd31 ||
MUX_capState$write_1__SEL_2 ||
WILL_FIRE_RL_capMemoryLoad ||
WILL_FIRE_RL_finishException ||
EN_capMem_response_put ;
// register capWriteback
assign capWriteback$D_IN =
MUX_capWriteback$write_1__SEL_1 ?
MUX_capWriteback$write_1__VAL_1 :
MUX_capWriteback$write_1__VAL_2 ;
assign capWriteback$EN =
EN_getCapResponse &&
capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_OR_ETC___d589 ||
EN_capMem_response_put ;
// register commitWritebackFifo_taggedReg
assign commitWritebackFifo_taggedReg$D_IN =
WILL_FIRE_RL_commitWritebackFifo_rule_enq ? 2'd3 : 2'd0 ;
assign commitWritebackFifo_taggedReg$EN =
WILL_FIRE_RL_commitWritebackFifo_rule_enq ||
(commitWritebackFifo_taggedReg[1] ||
commitWritebackFifo_rw_enq$whas) &&
capState != 3'd0 &&
capState != 3'd3 ;
// register count
assign count$D_IN = count + 5'd1 ;
assign count$EN = capState == 3'd0 ;
// register pcc
assign pcc$D_IN =
MUX_pcc$write_1__SEL_1 ?
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d960 :
MUX_pcc$write_1__VAL_2 ;
assign pcc$EN =
EN_getCapResponse &&
(capInsts$D_OUT[96:92] == 5'd7 ||
capInsts$D_OUT[96:92] == 5'd8) ||
WILL_FIRE_RL_finishException ;
// register pipeEmpty
assign pipeEmpty$D_IN = !insts$EMPTY_N ;
assign pipeEmpty$EN = 1'd1 ;
// register writesCalculated
assign writesCalculated$D_IN =
MUX_writesCalculated$write_1__SEL_1 ?
MUX_writesCalculated$write_1__VAL_1 :
MUX_writesCalculated$write_1__VAL_1 ;
assign writesCalculated$EN =
EN_getCapResponse &&
(capInsts$D_OUT[96:92] == 5'd4 ||
NOT_capInsts_first__28_BITS_96_TO_92_29_EQ_0_3_ETC___d569) ||
EN_capMem_response_put ;
// register writesDone
assign writesDone$D_IN = writesDone + 5'd1 ;
assign writesDone$EN =
EN_commitWriteback &&
commitWriteback_wbReq_BITS_3_TO_0_15_EQ_capWri_ETC___d918 &&
capWritebackTags$D_OUT[0] &&
capWritebackTags$D_OUT[4:1] == capWriteback[3:0] ;
// register writesIn
assign writesIn$D_IN = writesIn + 5'd1 ;
assign writesIn$EN =
EN_putCapInst &&
(putCapInst_capInst[86:82] == 5'd4 ||
putCapInst_capInst[86:82] == 5'd7 ||
putCapInst_capInst[86:82] == 5'd1 ||
putCapInst_capInst[86:82] == 5'd10) ;
// submodule baseRegs
assign baseRegs$ADDR_1 = fetchFifoB$D_OUT ;
assign baseRegs$ADDR_2 = fetchFifoA$D_OUT ;
assign baseRegs$ADDR_3 = 5'h0 ;
assign baseRegs$ADDR_4 = 5'h0 ;
assign baseRegs$ADDR_5 = 5'h0 ;
always@(MUX_baseRegs$upd_1__SEL_1 or
WILL_FIRE_RL_writeBack or capWriteback or capState or count)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: baseRegs$ADDR_IN = 5'd31;
WILL_FIRE_RL_writeBack: baseRegs$ADDR_IN = capWriteback[8:4];
capState == 3'd0: baseRegs$ADDR_IN = count;
default: baseRegs$ADDR_IN = 5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_baseRegs$upd_1__SEL_1 or
pcc or WILL_FIRE_RL_writeBack or capWriteback or capState)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: baseRegs$D_IN = pcc[127:64];
WILL_FIRE_RL_writeBack: baseRegs$D_IN = capWriteback[136:73];
capState == 3'd0: baseRegs$D_IN = 64'b0;
default: baseRegs$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign baseRegs$WE =
WILL_FIRE_RL_startException && !exception$D_OUT ||
WILL_FIRE_RL_writeBack ||
capState == 3'd0 ;
// submodule capInsts
assign capInsts$D_IN =
{ CASE_putCapInst_capInst_BITS_86_TO_82_31_0_put_ETC__q9,
putCapInst_capInst[81:0],
x__h8745,
x__h8753 } ;
assign capInsts$ENQ = EN_putCapInst ;
assign capInsts$DEQ = EN_getCapResponse ;
assign capInsts$CLR = 1'b0 ;
// submodule capMemInsts
assign capMemInsts$D_IN =
{ (capInsts$D_OUT[96:92] == 5'd10) ?
capInsts$D_OUT[96:92] :
5'd9,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d960,
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d558 } ;
assign capMemInsts$ENQ =
EN_getCapResponse &&
(capInsts$D_OUT[96:92] == 5'd10 ||
capInsts$D_OUT[96:92] == 5'd9) ;
assign capMemInsts$DEQ =
WILL_FIRE_RL_capMemoryStore || EN_capMem_response_put ;
assign capMemInsts$CLR = 1'b0 ;
// submodule capWritebackTags
assign capWritebackTags$D_IN =
MUX_capWritebackTags$enq_1__SEL_1 ?
MUX_capWritebackTags$enq_1__VAL_1 :
MUX_capWritebackTags$enq_1__VAL_2 ;
assign capWritebackTags$ENQ =
EN_getCapResponse && capInsts$D_OUT[96:92] != 5'd10 ||
EN_capMem_response_put ;
assign capWritebackTags$DEQ =
EN_commitWriteback &&
commitWriteback_wbReq_BITS_3_TO_0_15_EQ_capWri_ETC___d918 ;
assign capWritebackTags$CLR = 1'b0 ;
// submodule commitStore
assign commitStore$D_IN = commitWriteback_wbReq[4] ;
assign commitStore$ENQ =
EN_commitWriteback &&
commitWriteback_wbReq_BITS_3_TO_0_15_EQ_capWri_ETC___d918 &&
capWritebackTags$D_OUT[9:5] == 5'd9 ;
assign commitStore$DEQ = WILL_FIRE_RL_capMemoryStore ;
assign commitStore$CLR = 1'b0 ;
// submodule exception
assign exception$D_IN = hadException_expEvent ;
assign exception$ENQ = EN_hadException ;
assign exception$DEQ = WILL_FIRE_RL_finishException ;
assign exception$CLR = 1'b0 ;
// submodule fetchFifoA
assign fetchFifoA$D_IN =
WILL_FIRE_RL_startException ?
MUX_fetchFifoA$enq_1__VAL_1 :
MUX_fetchFifoA$enq_1__VAL_2 ;
assign fetchFifoA$ENQ = WILL_FIRE_RL_startException || EN_putCapInst ;
assign fetchFifoA$DEQ = WILL_FIRE_RL_finishException || EN_getCapResponse ;
assign fetchFifoA$CLR = 1'b0 ;
// submodule fetchFifoB
assign fetchFifoB$D_IN =
(putCapInst_capInst[86:82] != 5'd9 &&
putCapInst_capInst[86:82] != 5'd10) ?
5'd0 :
putCapInst_capInst[76:72] ;
assign fetchFifoB$ENQ = EN_putCapInst ;
assign fetchFifoB$DEQ = EN_getCapResponse ;
assign fetchFifoB$CLR = 1'b0 ;
// submodule insts
assign insts$D_IN = 1'd1 ;
assign insts$ENQ = EN_iGet ;
assign insts$DEQ = EN_commitWriteback ;
assign insts$CLR = 1'b0 ;
// submodule lengthRegs
assign lengthRegs$ADDR_1 = fetchFifoB$D_OUT ;
assign lengthRegs$ADDR_2 = fetchFifoA$D_OUT ;
assign lengthRegs$ADDR_3 = 5'h0 ;
assign lengthRegs$ADDR_4 = 5'h0 ;
assign lengthRegs$ADDR_5 = 5'h0 ;
always@(MUX_baseRegs$upd_1__SEL_1 or
WILL_FIRE_RL_writeBack or capWriteback or capState or count)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: lengthRegs$ADDR_IN = 5'd31;
WILL_FIRE_RL_writeBack: lengthRegs$ADDR_IN = capWriteback[8:4];
capState == 3'd0: lengthRegs$ADDR_IN = count;
default: lengthRegs$ADDR_IN = 5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_baseRegs$upd_1__SEL_1 or
pcc or WILL_FIRE_RL_writeBack or capWriteback or capState)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: lengthRegs$D_IN = pcc[63:0];
WILL_FIRE_RL_writeBack: lengthRegs$D_IN = capWriteback[72:9];
capState == 3'd0: lengthRegs$D_IN = 64'hFFFFFFFFFFFFFFFF;
default: lengthRegs$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign lengthRegs$WE =
WILL_FIRE_RL_startException && !exception$D_OUT ||
WILL_FIRE_RL_writeBack ||
capState == 3'd0 ;
// submodule memAccesses
assign memAccesses$D_IN =
MUX_memAccesses$enq_1__SEL_1 ?
MUX_memAccesses$enq_1__VAL_1 :
MUX_memAccesses$enq_1__VAL_2 ;
assign memAccesses$ENQ =
WILL_FIRE_RL_capMemoryStore && capMemInsts$D_OUT[73] &&
commitStore$D_OUT ||
WILL_FIRE_RL_capMemoryLoad && capMemInsts$D_OUT[73] ;
assign memAccesses$DEQ = EN_capMem_request_get ;
assign memAccesses$CLR = 1'b0 ;
// submodule memResponse
assign memResponse$D_IN = 256'h0 ;
assign memResponse$ENQ = 1'b0 ;
assign memResponse$DEQ = 1'b0 ;
assign memResponse$CLR = 1'b0 ;
// submodule nextCapState
assign nextCapState$D_IN =
(putCapInst_capInst[86:82] != 5'd2 &&
putCapInst_capInst[86:82] != 5'd3 &&
putCapInst_capInst[86:82] != 5'd5 &&
putCapInst_capInst[86:82] != 5'd6 &&
putCapInst_capInst[86:82] != 5'd10 &&
putCapInst_capInst[86:82] != 5'd11) ?
3'd5 :
((putCapInst_capInst[86:82] == 5'd10) ? 3'd1 : 3'd5) ;
assign nextCapState$ENQ = EN_putCapInst ;
assign nextCapState$DEQ =
capState == 3'd5 && (!exception$EMPTY_N || !pipeEmpty) &&
nextCapState$EMPTY_N ;
assign nextCapState$CLR = 1'b0 ;
// submodule nextWillWriteback
assign nextWillWriteback$D_IN =
putCapInst_capInst[86:82] == 5'd4 ||
putCapInst_capInst[86:82] == 5'd7 ||
putCapInst_capInst[86:82] == 5'd1 ||
putCapInst_capInst[86:82] == 5'd10 ;
assign nextWillWriteback$ENQ = EN_putCapInst ;
assign nextWillWriteback$DEQ = EN_getCapResponse ;
assign nextWillWriteback$CLR = 1'b0 ;
// submodule oTypeRegs
assign oTypeRegs$ADDR_1 = fetchFifoA$D_OUT ;
assign oTypeRegs$ADDR_2 = 5'h0 ;
assign oTypeRegs$ADDR_3 = 5'h0 ;
assign oTypeRegs$ADDR_4 = 5'h0 ;
assign oTypeRegs$ADDR_5 = 5'h0 ;
always@(MUX_baseRegs$upd_1__SEL_1 or
WILL_FIRE_RL_writeBack or capWriteback or capState or count)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: oTypeRegs$ADDR_IN = 5'd31;
WILL_FIRE_RL_writeBack: oTypeRegs$ADDR_IN = capWriteback[8:4];
capState == 3'd0: oTypeRegs$ADDR_IN = count;
default: oTypeRegs$ADDR_IN = 5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_baseRegs$upd_1__SEL_1 or
pcc or WILL_FIRE_RL_writeBack or capWriteback or capState)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: oTypeRegs$D_IN = pcc[191:128];
WILL_FIRE_RL_writeBack: oTypeRegs$D_IN = capWriteback[200:137];
capState == 3'd0: oTypeRegs$D_IN = 64'b0;
default: oTypeRegs$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign oTypeRegs$WE =
WILL_FIRE_RL_startException && !exception$D_OUT ||
WILL_FIRE_RL_writeBack ||
capState == 3'd0 ;
// submodule permRegs
assign permRegs$ADDR_1 = fetchFifoA$D_OUT ;
assign permRegs$ADDR_2 = 5'h0 ;
assign permRegs$ADDR_3 = 5'h0 ;
assign permRegs$ADDR_4 = 5'h0 ;
assign permRegs$ADDR_5 = 5'h0 ;
always@(MUX_baseRegs$upd_1__SEL_1 or
WILL_FIRE_RL_writeBack or capWriteback or capState or count)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: permRegs$ADDR_IN = 5'd31;
WILL_FIRE_RL_writeBack: permRegs$ADDR_IN = capWriteback[8:4];
capState == 3'd0: permRegs$ADDR_IN = count;
default: permRegs$ADDR_IN = 5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_baseRegs$upd_1__SEL_1 or
pcc or WILL_FIRE_RL_writeBack or capWriteback or capState)
begin
case (1'b1) // synopsys parallel_case
MUX_baseRegs$upd_1__SEL_1: permRegs$D_IN = pcc[255:192];
WILL_FIRE_RL_writeBack: permRegs$D_IN = capWriteback[264:201];
capState == 3'd0: permRegs$D_IN = 64'hFFFF000000000000;
default: permRegs$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign permRegs$WE =
WILL_FIRE_RL_startException && !exception$D_OUT ||
WILL_FIRE_RL_writeBack ||
capState == 3'd0 ;
// submodule startExp
assign startExp$D_IN = 1'd1 ;
assign startExp$ENQ = WILL_FIRE_RL_startException ;
assign startExp$DEQ = WILL_FIRE_RL_finishException ;
assign startExp$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_capInsts_first__28_BITS_9_TO_5_02_EQ_cap_ETC___d669 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1030 ?
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1150 :
{ writeback___1_base__h13507,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968 -
getCapResponse_capReq[69:6] } ;
assign IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d820 =
(capInsts$D_OUT[96:92] != 5'd4 &&
capInsts$D_OUT[96:92] != 5'd0 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd1 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6) ?
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_0_C_ETC___d1135 :
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d819 ;
assign IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d823 =
(capInsts$D_OUT[96:92] != 5'd0 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd1 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6) ?
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_0_C_ETC___d1135 :
((capInsts$D_OUT[96:92] == 5'd0) ?
capInsts$D_OUT[17:15] != 3'd3 &&
capInsts$D_OUT[17:15] != 3'd5 :
capInsts_first__28_BITS_96_TO_92_29_EQ_16_34_O_ETC___d817) ;
assign IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d940 =
(capInsts$D_OUT[96:92] != 5'd4 &&
capInsts$D_OUT[96:92] != 5'd0 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd1 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6) ?
{ x1_avValue_base__h9411[63:40] + getCapResponse_capReq[69:46],
x1_avValue_base__h9411[39:0] +
getCapResponse_capReq[45:6] } :
CASE_capInstsD_OUT_BITS_96_TO_92_IF_NOT_capIn_ETC__q4 ;
assign IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1109 =
(capInsts$D_OUT[4:0] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[136:73] :
baseRegs$D_OUT_1 ;
assign IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1110 =
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1109[63:40] +
getCapResponse_capReq[69:46] ;
assign IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1133 =
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1109[39:0] +
getCapResponse_capReq[45:6] ;
assign IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d542 =
(capInsts$D_OUT[4:0] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[72:9] :
lengthRegs$D_OUT_1 ;
assign IF_capInsts_first__28_BITS_96_TO_92_29_EQ_0_32_ETC___d679 =
(capInsts$D_OUT[96:92] != 5'd1 &&
capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd11) ?
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1152 :
((capInsts$D_OUT[96:92] == 5'd7) ?
pcc[254:0] :
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1152) ;
assign IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d635 =
(capInsts$D_OUT[96:92] != 5'd1 &&
capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd11) ?
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073 :
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d634 ;
assign IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d680 =
(capInsts$D_OUT[96:92] == 5'd4) ?
{ CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q5,
x1_avValue_reserved__h9409,
_theResult_____8_fst_oType_eaddr__h13470,
CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q6 } :
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_0_32_ETC___d679 ;
assign IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d825 =
(capInsts$D_OUT[96:92] == 5'd4 ||
NOT_capInsts_first__28_BITS_96_TO_92_29_EQ_0_3_ETC___d569) ?
pcc_7_BIT_244_46_OR_NOT_IF_capInsts_first__28__ETC___d822 :
!capInsts$D_OUT[14] &&
IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d823 ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1030 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968 <=
getCapResponse_capReq[69:6] ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[264] :
permRegs$D_OUT_1[63] ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1149 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[263:249] :
permRegs$D_OUT_1[62:48] ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1150 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[136:9] :
{ baseRegs$D_OUT_2, lengthRegs$D_OUT_2 } ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1152 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[263:9] :
{ permRegs$D_OUT_1[62:48],
48'b0,
oTypeRegs$D_OUT_1,
baseRegs$D_OUT_2,
lengthRegs$D_OUT_2 } ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d565 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[263] :
permRegs$D_OUT_1[62] ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d626 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
!capWriteback[264] :
!permRegs$D_OUT_1[63] ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d629 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
!capWriteback[263] :
!permRegs$D_OUT_1[62] ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d664 =
{ x1_avValue_base__h9411,
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1030 ?
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968 :
getCapResponse_capReq[69:6] } ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d960 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[264:9] :
{ permRegs$D_OUT_1[63:48],
48'b0,
oTypeRegs$D_OUT_1,
baseRegs$D_OUT_2,
lengthRegs$D_OUT_2 } ;
assign IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[72:9] :
lengthRegs$D_OUT_2 ;
assign IF_putCapInst_capInst_BITS_86_TO_82_11_EQ_0_12_ETC___d939 =
(putCapInst_capInst[86:82] != 5'd1 &&
putCapInst_capInst[86:82] != 5'd2 &&
putCapInst_capInst[86:82] != 5'd3 &&
putCapInst_capInst[86:82] != 5'd5 &&
putCapInst_capInst[86:82] != 5'd6 &&
putCapInst_capInst[86:82] != 5'd9 &&
putCapInst_capInst[86:82] != 5'd10 &&
putCapInst_capInst[86:82] != 5'd11) ?
putCapInst_capInst[76:72] :
CASE_putCapInst_capInst_BITS_86_TO_82_0_1_putC_ETC__q3 ;
assign NOT_capInsts_first__28_BITS_96_TO_92_29_EQ_0_3_ETC___d569 =
capInsts$D_OUT[96:92] == 5'd7 ||
capInsts$D_OUT[96:92] == 5'd1 &&
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073 &&
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d565 ;
assign _theResult_____8_fst_oType_eaddr__h13460 =
getCapResponse_capReq_BITS_69_TO_6_54_ULT_IF_c_ETC___d972 ?
writeback___1_base__h13507 :
x1_avValue_oType_eaddr__h9410 ;
assign capInsts_first__28_BITS_96_TO_92_29_EQ_16_34_O_ETC___d817 =
capInsts$D_OUT[96:92] != 5'd1 && capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd11 ||
((capInsts$D_OUT[96:92] == 5'd7) ?
getCapResponse_capReq[45:6] + 40'd4 <= pcc[39:0] :
capInsts$D_OUT[96:92] == 5'd8 ||
CASE_capInstsD_OUT_BITS_96_TO_92_NOT_capInsts_ETC__q1) ;
assign capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_OR_ETC___d589 =
(capInsts$D_OUT[96:92] == 5'd4 ||
NOT_capInsts_first__28_BITS_96_TO_92_29_EQ_0_3_ETC___d569) &&
(pcc[244] || x__h13350 != 5'd28) &&
(pcc[243] || x__h13350 != 5'd29) &&
(pcc[242] || x__h13350 != 5'd30) &&
(pcc[241] || x__h13350 != 5'd31) ;
assign capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_OR_ETC___d730 =
(capInsts$D_OUT[96:92] == 5'd4 ||
NOT_capInsts_first__28_BITS_96_TO_92_29_EQ_0_3_ETC___d569) &&
(pcc[244] || x__h13350 != 5'd28) &&
(pcc[243] || x__h13350 != 5'd29) &&
(pcc[242] || x__h13350 != 5'd30) &&
(pcc[241] || x__h13350 != 5'd31) ;
assign capState_read_EQ_5_9_OR_capState_read_EQ_1_6_0_ETC___d906 =
(capState == 3'd5 || capState == 3'd1) &&
(!nextWillWriteback$D_OUT || writesCalculated == writesDone) ;
assign commitWriteback_wbReq_BITS_3_TO_0_15_EQ_capWri_ETC___d918 =
commitWriteback_wbReq[3:0] == capWritebackTags$D_OUT[4:1] ;
assign getCapResponse_capReq_BITS_45_TO_6_35_PLUS_0_C_ETC___d1135 =
getCapResponse_capReq[45:6] + { 34'd0, x__h12726 } <=
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968[39:0] ;
assign getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d558 =
{ getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d971,
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1110,
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1133,
(capInsts$D_OUT[96:92] == 5'd10) ?
capInsts$D_OUT[91:87] :
5'd0,
capInsts$D_OUT[13:10] } ;
assign getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d971 =
getCapResponse_capReq[45:6] + 40'd32 <=
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d542[39:0] ;
assign getCapResponse_capReq_BITS_69_TO_6_54_ULT_IF_c_ETC___d972 =
getCapResponse_capReq[69:6] <
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968 ;
assign pcc_7_BIT_244_46_OR_NOT_IF_capInsts_first__28__ETC___d822 =
(pcc[244] || x__h13350 != 5'd28) &&
(pcc[243] || x__h13350 != 5'd29) &&
(pcc[242] || x__h13350 != 5'd30) &&
(pcc[241] || x__h13350 != 5'd31) &&
!capInsts$D_OUT[14] &&
IF_NOT_capInsts_first__28_BITS_96_TO_92_29_EQ__ETC___d820 ;
assign writeback___1_base__h13507 =
x1_avValue_base__h9411 + getCapResponse_capReq[69:6] ;
assign x1_avValue_base__h9411 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[136:73] :
baseRegs$D_OUT_2 ;
assign x1_avValue_oType_eaddr__h9410 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[200:137] :
oTypeRegs$D_OUT_1 ;
assign x1_avValue_reserved__h9409 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[248:201] :
48'b0 ;
assign x__h12726 =
(capInsts$D_OUT[96:92] == 5'd10 ||
capInsts$D_OUT[96:92] == 5'd9) ?
6'd32 :
((capInsts$D_OUT[96:92] != 5'd4 &&
capInsts$D_OUT[96:92] != 5'd0 &&
capInsts$D_OUT[96:92] != 5'd16 &&
capInsts$D_OUT[96:92] != 5'd20 &&
capInsts$D_OUT[96:92] != 5'd17 &&
capInsts$D_OUT[96:92] != 5'd21 &&
capInsts$D_OUT[96:92] != 5'd18 &&
capInsts$D_OUT[96:92] != 5'd22 &&
capInsts$D_OUT[96:92] != 5'd24 &&
capInsts$D_OUT[96:92] != 5'd28 &&
capInsts$D_OUT[96:92] != 5'd25 &&
capInsts$D_OUT[96:92] != 5'd29 &&
capInsts$D_OUT[96:92] != 5'd26 &&
capInsts$D_OUT[96:92] != 5'd30 &&
capInsts$D_OUT[96:92] != 5'd1 &&
capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd11) ?
6'd8 :
((capInsts$D_OUT[96:92] == 5'd4 ||
capInsts$D_OUT[96:92] == 5'd0 ||
capInsts$D_OUT[96:92] == 5'd18 ||
capInsts$D_OUT[96:92] == 5'd22 ||
capInsts$D_OUT[96:92] == 5'd26 ||
capInsts$D_OUT[96:92] == 5'd30 ||
(capInsts$D_OUT[96:92] == 5'd1 ||
capInsts$D_OUT[96:92] == 5'd2 ||
capInsts$D_OUT[96:92] == 5'd3 ||
capInsts$D_OUT[96:92] == 5'd5 ||
capInsts$D_OUT[96:92] == 5'd6 ||
capInsts$D_OUT[96:92] == 5'd7 ||
capInsts$D_OUT[96:92] == 5'd8 ||
capInsts$D_OUT[96:92] == 5'd9 ||
capInsts$D_OUT[96:92] == 5'd10 ||
capInsts$D_OUT[96:92] == 5'd11) &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd9) ?
6'd4 :
((capInsts$D_OUT[96:92] == 5'd17 ||
capInsts$D_OUT[96:92] == 5'd21 ||
capInsts$D_OUT[96:92] == 5'd25 ||
capInsts$D_OUT[96:92] == 5'd29) ?
6'd2 :
((capInsts$D_OUT[96:92] == 5'd16 ||
capInsts$D_OUT[96:92] == 5'd20 ||
capInsts$D_OUT[96:92] == 5'd24 ||
capInsts$D_OUT[96:92] == 5'd28) ?
6'd1 :
6'd32)))) ;
assign x__h14462 =
(capInsts$D_OUT[9:5] == capWriteback[8:4] && capWriteback[265]) ?
capWriteback[264:249] :
permRegs$D_OUT_1[63:48] ;
assign x__h8745 =
(putCapInst_capInst[86:82] != 5'd2 &&
putCapInst_capInst[86:82] != 5'd3 &&
putCapInst_capInst[86:82] != 5'd5 &&
putCapInst_capInst[86:82] != 5'd6) ?
IF_putCapInst_capInst_BITS_86_TO_82_11_EQ_0_12_ETC___d939 :
5'd0 ;
assign x__h8753 =
(putCapInst_capInst[86:82] == 5'd9 ||
putCapInst_capInst[86:82] == 5'd10) ?
putCapInst_capInst[76:72] :
5'd0 ;
always@(capInsts$D_OUT)
begin
case (capInsts$D_OUT[96:92])
5'd4: x__h13350 = capInsts$D_OUT[91:87];
5'd7: x__h13350 = 5'd27;
default: x__h13350 = capInsts$D_OUT[86:82];
endcase
end
always@(iGet_capReq)
begin
case (iGet_capReq[5:2])
4'd0: x__h6671 = 6'd32;
4'd1, 4'd2, 4'd3: x__h6671 = 6'd8;
4'd4, 4'd5, 4'd6: x__h6671 = 6'd4;
4'd7: x__h6671 = 6'd2;
4'd8: x__h6671 = 6'd1;
default: x__h6671 = 6'd32;
endcase
end
always@(capInsts$D_OUT or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968 or
x1_avValue_base__h9411 or
x1_avValue_oType_eaddr__h9410 or x__h14462)
begin
case (capInsts$D_OUT[17:15])
3'd0:
IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d968;
3'd1:
IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889 =
x1_avValue_base__h9411;
3'd2:
IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889 =
x1_avValue_oType_eaddr__h9410;
3'd4: IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889 = 64'd0;
3'd6:
IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889 =
{ 48'd0, x__h14462 };
default: IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889 =
64'h0;
endcase
end
always@(capInsts$D_OUT or
x1_avValue_oType_eaddr__h9410 or
_theResult_____8_fst_oType_eaddr__h13460)
begin
case (capInsts$D_OUT[17:15])
3'd0, 3'd1:
_theResult_____8_fst_oType_eaddr__h13470 =
x1_avValue_oType_eaddr__h9410;
3'd2:
_theResult_____8_fst_oType_eaddr__h13470 =
_theResult_____8_fst_oType_eaddr__h13460;
default: _theResult_____8_fst_oType_eaddr__h13470 =
x1_avValue_oType_eaddr__h9410;
endcase
end
always@(capInsts$D_OUT or
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d971 or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073 or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d565)
begin
case (capInsts$D_OUT[96:92])
5'd1:
CASE_capInstsD_OUT_BITS_96_TO_92_NOT_capInsts_ETC__q1 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073 &&
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d565;
5'd10:
CASE_capInstsD_OUT_BITS_96_TO_92_NOT_capInsts_ETC__q1 =
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d971;
default: CASE_capInstsD_OUT_BITS_96_TO_92_NOT_capInsts_ETC__q1 =
capInsts$D_OUT[96:92] != 5'd9 ||
getCapResponse_capReq_BITS_45_TO_6_35_PLUS_32__ETC___d971;
endcase
end
always@(capInsts$D_OUT or
getCapResponse_capReq_BITS_69_TO_6_54_ULT_IF_c_ETC___d972 or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1030)
begin
case (capInsts$D_OUT[17:15])
3'd0, 3'd1:
CASE_capInstsD_OUT_BITS_17_TO_15_NOT_capInsts_ETC__q2 =
!IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1030;
default: CASE_capInstsD_OUT_BITS_17_TO_15_NOT_capInsts_ETC__q2 =
capInsts$D_OUT[17:15] != 3'd2 ||
getCapResponse_capReq_BITS_69_TO_6_54_ULT_IF_c_ETC___d972;
endcase
end
always@(capInsts$D_OUT or
capInsts_first__28_BITS_96_TO_92_29_EQ_16_34_O_ETC___d817 or
CASE_capInstsD_OUT_BITS_17_TO_15_NOT_capInsts_ETC__q2)
begin
case (capInsts$D_OUT[96:92])
5'd0:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d819 =
capInsts$D_OUT[17:15] != 3'd3 && capInsts$D_OUT[17:15] != 3'd5;
5'd4:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d819 =
CASE_capInstsD_OUT_BITS_17_TO_15_NOT_capInsts_ETC__q2;
default: IF_capInsts_first__28_BITS_96_TO_92_29_EQ_4_30_ETC___d819 =
capInsts_first__28_BITS_96_TO_92_29_EQ_16_34_O_ETC___d817;
endcase
end
always@(capInsts$D_OUT or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073 or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d626 or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d629 or pcc)
begin
case (capInsts$D_OUT[96:92])
5'd1:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d634 =
(IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d626 ||
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d629) &&
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073;
5'd7:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d634 =
pcc[255];
5'd8:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d634 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073;
default: IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d634 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1073;
endcase
end
always@(putCapInst_capInst)
begin
case (putCapInst_capInst[86:82])
5'd1, 5'd9, 5'd10:
CASE_putCapInst_capInst_BITS_86_TO_82_0_1_putC_ETC__q3 =
putCapInst_capInst[81:77];
default: CASE_putCapInst_capInst_BITS_86_TO_82_0_1_putC_ETC__q3 = 5'd0;
endcase
end
always@(capInsts$D_OUT or
pcc or
getCapResponse_capReq or
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1110 or
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1133)
begin
case (capInsts$D_OUT[96:92])
5'd1, 5'd8:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d895 = 64'b0;
5'd7:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d895 =
{ pcc[127:104] + getCapResponse_capReq[69:46],
pcc[103:64] + getCapResponse_capReq[45:6] };
5'd9, 5'd10:
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d895 =
{ IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1110,
IF_capInsts_first__28_BITS_4_TO_0_37_EQ_capWri_ETC___d1133 };
default: IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d895 =
64'h0;
endcase
end
always@(capInsts$D_OUT or
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d895 or
IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889)
begin
case (capInsts$D_OUT[96:92])
5'd0:
CASE_capInstsD_OUT_BITS_96_TO_92_IF_NOT_capIn_ETC__q4 =
IF_capInsts_first__28_BITS_17_TO_15_36_EQ_0_37_ETC___d889;
5'd4: CASE_capInstsD_OUT_BITS_96_TO_92_IF_NOT_capIn_ETC__q4 = 64'h0;
default: CASE_capInstsD_OUT_BITS_96_TO_92_IF_NOT_capIn_ETC__q4 =
(capInsts$D_OUT[96:92] != 5'd1 &&
capInsts$D_OUT[96:92] != 5'd2 &&
capInsts$D_OUT[96:92] != 5'd3 &&
capInsts$D_OUT[96:92] != 5'd5 &&
capInsts$D_OUT[96:92] != 5'd6 &&
capInsts$D_OUT[96:92] != 5'd7 &&
capInsts$D_OUT[96:92] != 5'd8 &&
capInsts$D_OUT[96:92] != 5'd9 &&
capInsts$D_OUT[96:92] != 5'd10 &&
capInsts$D_OUT[96:92] != 5'd11) ?
64'h0 :
IF_capInsts_first__28_BITS_96_TO_92_29_EQ_7_76_ETC___d895;
endcase
end
always@(capInsts$D_OUT or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1149 or
getCapResponse_capReq)
begin
case (capInsts$D_OUT[17:15])
3'd0, 3'd1, 3'd2:
CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q5 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1149;
3'd6:
CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q5 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1149 &
getCapResponse_capReq[20:6];
default: CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q5 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1149;
endcase
end
always@(capInsts$D_OUT or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1150 or
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d664 or
IF_IF_capInsts_first__28_BITS_9_TO_5_02_EQ_cap_ETC___d669)
begin
case (capInsts$D_OUT[17:15])
3'd0:
CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q6 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d664;
3'd1:
CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q6 =
IF_IF_capInsts_first__28_BITS_9_TO_5_02_EQ_cap_ETC___d669;
default: CASE_capInstsD_OUT_BITS_17_TO_15_IF_capInsts__ETC__q6 =
IF_capInsts_first__28_BITS_9_TO_5_02_EQ_capWri_ETC___d1150;
endcase
end
always@(capInsts$D_OUT)
begin
case (capInsts$D_OUT[96:92])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd11,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30:
CASE_capInstsD_OUT_BITS_96_TO_92_31_0_capInst_ETC__q7 =
capInsts$D_OUT[96:92];
default: CASE_capInstsD_OUT_BITS_96_TO_92_31_0_capInst_ETC__q7 = 5'd31;
endcase
end
always@(capMemInsts$D_OUT)
begin
case (capMemInsts$D_OUT[334:330])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30:
CASE_capMemInstsD_OUT_BITS_334_TO_330_31_0_ca_ETC__q8 =
capMemInsts$D_OUT[334:330];
default: CASE_capMemInstsD_OUT_BITS_334_TO_330_31_0_ca_ETC__q8 = 5'd31;
endcase
end
always@(putCapInst_capInst)
begin
case (putCapInst_capInst[86:82])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30:
CASE_putCapInst_capInst_BITS_86_TO_82_31_0_put_ETC__q9 =
putCapInst_capInst[86:82];
default: CASE_putCapInst_capInst_BITS_86_TO_82_31_0_put_ETC__q9 = 5'd31;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
capState <= `BSV_ASSIGNMENT_DELAY 3'd0;
capWriteback <= `BSV_ASSIGNMENT_DELAY
266'h15555555555555555555555555555555555555555555555555555555555555555F0;
commitWritebackFifo_taggedReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
count <= `BSV_ASSIGNMENT_DELAY 5'd0;
pcc <= `BSV_ASSIGNMENT_DELAY
256'hFFFF00000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF;
pipeEmpty <= `BSV_ASSIGNMENT_DELAY 1'd0;
writesCalculated <= `BSV_ASSIGNMENT_DELAY 5'd0;
writesDone <= `BSV_ASSIGNMENT_DELAY 5'd0;
writesIn <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (capState$EN) capState <= `BSV_ASSIGNMENT_DELAY capState$D_IN;
if (capWriteback$EN)
capWriteback <= `BSV_ASSIGNMENT_DELAY capWriteback$D_IN;
if (commitWritebackFifo_taggedReg$EN)
commitWritebackFifo_taggedReg <= `BSV_ASSIGNMENT_DELAY
commitWritebackFifo_taggedReg$D_IN;
if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (pcc$EN) pcc <= `BSV_ASSIGNMENT_DELAY pcc$D_IN;
if (pipeEmpty$EN) pipeEmpty <= `BSV_ASSIGNMENT_DELAY pipeEmpty$D_IN;
if (writesCalculated$EN)
writesCalculated <= `BSV_ASSIGNMENT_DELAY writesCalculated$D_IN;
if (writesDone$EN)
writesDone <= `BSV_ASSIGNMENT_DELAY writesDone$D_IN;
if (writesIn$EN) writesIn <= `BSV_ASSIGNMENT_DELAY writesIn$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
capState = 3'h2;
capWriteback =
266'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitWritebackFifo_taggedReg = 2'h2;
count = 5'h0A;
pcc =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
pipeEmpty = 1'h0;
writesCalculated = 5'h0A;
writesDone = 5'h0A;
writesIn = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCapCop
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:44:29 BST 2012
//
// Method conflict info:
// Method: readReq
// Conflict-free: writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced after (restricted): readGet
// Conflicts: readReq
//
// Method: readGet
// Conflict-free: writeReg,
// getException,
// putException,
// getLlScReg,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced before (restricted): readReq, interrupts
// Conflicts: readGet
//
// Method: writeReg
// Conflict-free: readReq,
// readGet,
// getException,
// putException,
// getLlScReg,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced before (restricted): interrupts
// Conflicts: writeReg
//
// Method: getException
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced before (restricted): interrupts
//
// Method: putException
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// getLlScReg,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced before (restricted): interrupts
// Conflicts: putException
//
// Method: getLlScReg
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
//
// Method: interrupts
// Conflict-free: readReq,
// getLlScReg,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupData_request_put,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced before (restricted): interrupts
// Sequenced after (restricted): readGet,
// writeReg,
// getException,
// putException,
// tlbLookupInstruction_response_get,
// tlbLookupData_response_get
//
// Method: getExceptionReturn
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Conflicts: getExceptionReturn
//
// Method: getCoprocessorEnables
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
//
// Method: tlbLookupInstruction_request_put
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Conflicts: tlbLookupInstruction_request_put
//
// Method: tlbLookupInstruction_response_get
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced before (restricted): interrupts
// Conflicts: tlbLookupInstruction_response_get
//
// Method: tlbLookupData_request_put
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Conflicts: tlbLookupData_request_put
//
// Method: tlbLookupData_response_get
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupCoprocessors_0_request_put,
// tlbLookupCoprocessors_0_response_get
// Sequenced before (restricted): interrupts
// Conflicts: tlbLookupData_response_get
//
// Method: tlbLookupCoprocessors_0_request_put
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_response_get
// Conflicts: tlbLookupCoprocessors_0_request_put
//
// Method: tlbLookupCoprocessors_0_response_get
// Conflict-free: readReq,
// readGet,
// writeReg,
// getException,
// putException,
// getLlScReg,
// interrupts,
// getExceptionReturn,
// getCoprocessorEnables,
// tlbLookupInstruction_request_put,
// tlbLookupInstruction_response_get,
// tlbLookupData_request_put,
// tlbLookupData_response_get,
// tlbLookupCoprocessors_0_request_put
// Conflicts: tlbLookupCoprocessors_0_response_get
//
//
// Ports:
// Name I/O size props
// RDY_readReq O 1
// readGet O 64
// RDY_readGet O 1
// RDY_writeReg O 1
// getException O 7
// RDY_getException O 1 const
// RDY_putException O 1 const
// getLlScReg O 1
// RDY_getLlScReg O 1 const
// RDY_interrupts O 1 const
// RDY_getExceptionReturn O 1 reg
// getCoprocessorEnables O 4
// RDY_getCoprocessorEnables O 1 const
// RDY_tlbLookupInstruction_request_put O 1
// tlbLookupInstruction_response_get O 50
// RDY_tlbLookupInstruction_response_get O 1
// RDY_tlbLookupData_request_put O 1
// tlbLookupData_response_get O 50
// RDY_tlbLookupData_response_get O 1
// RDY_tlbLookupCoprocessors_0_request_put O 1
// tlbLookupCoprocessors_0_response_get O 50
// RDY_tlbLookupCoprocessors_0_response_get O 1
// CLK I 1 clock
// RST_N I 1 reset
// readReq_rn I 5 reg
// readReq_sel I 3 reg
// readGet_goingToWrite I 1
// writeReg_rn I 5 reg
// writeReg_data I 64 reg
// writeReg_forceKernelMode I 1 reg
// writeReg_writeBack I 1
// putException_exp I 139
// getLlScReg_matchAddress I 64
// interrupts_interruptLines I 5 reg
// tlbLookupInstruction_request_put I 75
// tlbLookupData_request_put I 75
// tlbLookupCoprocessors_0_request_put I 75
// EN_readReq I 1
// EN_writeReg I 1
// EN_putException I 1
// EN_interrupts I 1
// EN_getExceptionReturn I 1
// EN_tlbLookupInstruction_request_put I 1
// EN_tlbLookupData_request_put I 1
// EN_tlbLookupCoprocessors_0_request_put I 1
// EN_readGet I 1
// EN_getException I 1 unused
// EN_tlbLookupInstruction_response_get I 1
// EN_tlbLookupData_response_get I 1
// EN_tlbLookupCoprocessors_0_response_get I 1
//
// Combinational paths from inputs to outputs:
// getLlScReg_matchAddress -> getLlScReg
// EN_readGet -> RDY_readReq
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkCP0(CLK,
RST_N,
readReq_rn,
readReq_sel,
EN_readReq,
RDY_readReq,
readGet_goingToWrite,
EN_readGet,
readGet,
RDY_readGet,
writeReg_rn,
writeReg_data,
writeReg_forceKernelMode,
writeReg_writeBack,
EN_writeReg,
RDY_writeReg,
EN_getException,
getException,
RDY_getException,
putException_exp,
EN_putException,
RDY_putException,
getLlScReg_matchAddress,
getLlScReg,
RDY_getLlScReg,
interrupts_interruptLines,
EN_interrupts,
RDY_interrupts,
EN_getExceptionReturn,
RDY_getExceptionReturn,
getCoprocessorEnables,
RDY_getCoprocessorEnables,
tlbLookupInstruction_request_put,
EN_tlbLookupInstruction_request_put,
RDY_tlbLookupInstruction_request_put,
EN_tlbLookupInstruction_response_get,
tlbLookupInstruction_response_get,
RDY_tlbLookupInstruction_response_get,
tlbLookupData_request_put,
EN_tlbLookupData_request_put,
RDY_tlbLookupData_request_put,
EN_tlbLookupData_response_get,
tlbLookupData_response_get,
RDY_tlbLookupData_response_get,
tlbLookupCoprocessors_0_request_put,
EN_tlbLookupCoprocessors_0_request_put,
RDY_tlbLookupCoprocessors_0_request_put,
EN_tlbLookupCoprocessors_0_response_get,
tlbLookupCoprocessors_0_response_get,
RDY_tlbLookupCoprocessors_0_response_get);
input CLK;
input RST_N;
// action method readReq
input [4 : 0] readReq_rn;
input [2 : 0] readReq_sel;
input EN_readReq;
output RDY_readReq;
// actionvalue method readGet
input readGet_goingToWrite;
input EN_readGet;
output [63 : 0] readGet;
output RDY_readGet;
// action method writeReg
input [4 : 0] writeReg_rn;
input [63 : 0] writeReg_data;
input writeReg_forceKernelMode;
input writeReg_writeBack;
input EN_writeReg;
output RDY_writeReg;
// actionvalue method getException
input EN_getException;
output [6 : 0] getException;
output RDY_getException;
// action method putException
input [138 : 0] putException_exp;
input EN_putException;
output RDY_putException;
// value method getLlScReg
input [63 : 0] getLlScReg_matchAddress;
output getLlScReg;
output RDY_getLlScReg;
// action method interrupts
input [4 : 0] interrupts_interruptLines;
input EN_interrupts;
output RDY_interrupts;
// action method getExceptionReturn
input EN_getExceptionReturn;
output RDY_getExceptionReturn;
// value method getCoprocessorEnables
output [3 : 0] getCoprocessorEnables;
output RDY_getCoprocessorEnables;
// action method tlbLookupInstruction_request_put
input [74 : 0] tlbLookupInstruction_request_put;
input EN_tlbLookupInstruction_request_put;
output RDY_tlbLookupInstruction_request_put;
// actionvalue method tlbLookupInstruction_response_get
input EN_tlbLookupInstruction_response_get;
output [49 : 0] tlbLookupInstruction_response_get;
output RDY_tlbLookupInstruction_response_get;
// action method tlbLookupData_request_put
input [74 : 0] tlbLookupData_request_put;
input EN_tlbLookupData_request_put;
output RDY_tlbLookupData_request_put;
// actionvalue method tlbLookupData_response_get
input EN_tlbLookupData_response_get;
output [49 : 0] tlbLookupData_response_get;
output RDY_tlbLookupData_response_get;
// action method tlbLookupCoprocessors_0_request_put
input [74 : 0] tlbLookupCoprocessors_0_request_put;
input EN_tlbLookupCoprocessors_0_request_put;
output RDY_tlbLookupCoprocessors_0_request_put;
// actionvalue method tlbLookupCoprocessors_0_response_get
input EN_tlbLookupCoprocessors_0_response_get;
output [49 : 0] tlbLookupCoprocessors_0_response_get;
output RDY_tlbLookupCoprocessors_0_response_get;
// signals for module outputs
reg [63 : 0] readGet;
wire [49 : 0] tlbLookupCoprocessors_0_response_get,
tlbLookupData_response_get,
tlbLookupInstruction_response_get;
wire [6 : 0] getException;
wire [3 : 0] getCoprocessorEnables;
wire RDY_getCoprocessorEnables,
RDY_getException,
RDY_getExceptionReturn,
RDY_getLlScReg,
RDY_interrupts,
RDY_putException,
RDY_readGet,
RDY_readReq,
RDY_tlbLookupCoprocessors_0_request_put,
RDY_tlbLookupCoprocessors_0_response_get,
RDY_tlbLookupData_request_put,
RDY_tlbLookupData_response_get,
RDY_tlbLookupInstruction_request_put,
RDY_tlbLookupInstruction_response_get,
RDY_writeReg,
getLlScReg;
// register badVAddr
reg [63 : 0] badVAddr;
wire [63 : 0] badVAddr$D_IN;
wire badVAddr$EN;
// register cause
reg [31 : 0] cause;
wire [31 : 0] cause$D_IN;
wire cause$EN;
// register compare
reg [31 : 0] compare;
wire [31 : 0] compare$D_IN;
wire compare$EN;
// register configReg0
reg [31 : 0] configReg0;
wire [31 : 0] configReg0$D_IN;
wire configReg0$EN;
// register configReg1
reg [31 : 0] configReg1;
wire [31 : 0] configReg1$D_IN;
wire configReg1$EN;
// register configReg2
reg [31 : 0] configReg2;
wire [31 : 0] configReg2$D_IN;
wire configReg2$EN;
// register configReg3
reg [30 : 0] configReg3;
wire [30 : 0] configReg3$D_IN;
wire configReg3$EN;
// register count
reg [31 : 0] count;
wire [31 : 0] count$D_IN;
wire count$EN;
// register epc
reg [63 : 0] epc;
wire [63 : 0] epc$D_IN;
wire epc$EN;
// register errorEPC
reg [63 : 0] errorEPC;
wire [63 : 0] errorEPC$D_IN;
wire errorEPC$EN;
// register exInterrupts
reg [4 : 0] exInterrupts;
wire [4 : 0] exInterrupts$D_IN;
wire exInterrupts$EN;
// register llScReg
reg [64 : 0] llScReg;
wire [64 : 0] llScReg$D_IN;
wire llScReg$EN;
// register procid
reg [31 : 0] procid;
wire [31 : 0] procid$D_IN;
wire procid$EN;
// register sr
reg [31 : 0] sr;
wire [31 : 0] sr$D_IN;
wire sr$EN;
// register tlbContext
reg [63 : 0] tlbContext;
wire [63 : 0] tlbContext$D_IN;
wire tlbContext$EN;
// register tlbEntryHi
reg [63 : 0] tlbEntryHi;
reg [63 : 0] tlbEntryHi$D_IN;
wire tlbEntryHi$EN;
// register tlbEntryLo0
reg [31 : 0] tlbEntryLo0;
wire [31 : 0] tlbEntryLo0$D_IN;
wire tlbEntryLo0$EN;
// register tlbEntryLo1
reg [31 : 0] tlbEntryLo1;
wire [31 : 0] tlbEntryLo1$D_IN;
wire tlbEntryLo1$EN;
// register tlbIndex
reg [6 : 0] tlbIndex;
wire [6 : 0] tlbIndex$D_IN;
wire tlbIndex$EN;
// register tlbPageMask
reg [11 : 0] tlbPageMask;
wire [11 : 0] tlbPageMask$D_IN;
wire tlbPageMask$EN;
// register tlbWired
reg [2 : 0] tlbWired;
wire [2 : 0] tlbWired$D_IN;
wire tlbWired$EN;
// register tlbXContext
reg [63 : 0] tlbXContext;
wire [63 : 0] tlbXContext$D_IN;
wire tlbXContext$EN;
// register tlb_asid
reg [7 : 0] tlb_asid;
wire [7 : 0] tlb_asid$D_IN;
wire tlb_asid$EN;
// register tlb_count
reg [4 : 0] tlb_count;
wire [4 : 0] tlb_count$D_IN;
wire tlb_count$EN;
// register tlb_entryLo0Reg
reg [31 : 0] tlb_entryLo0Reg;
wire [31 : 0] tlb_entryLo0Reg$D_IN;
wire tlb_entryLo0Reg$EN;
// register tlb_entryLo1Reg
reg [31 : 0] tlb_entryLo1Reg;
wire [31 : 0] tlb_entryLo1Reg$D_IN;
wire tlb_entryLo1Reg$EN;
// register tlb_entrySrch
reg [77 : 0] tlb_entrySrch;
wire [77 : 0] tlb_entrySrch$D_IN;
wire tlb_entrySrch$EN;
// register tlb_entrySrch_1
reg [77 : 0] tlb_entrySrch_1;
wire [77 : 0] tlb_entrySrch_1$D_IN;
wire tlb_entrySrch_1$EN;
// register tlb_entrySrch_2
reg [77 : 0] tlb_entrySrch_2;
wire [77 : 0] tlb_entrySrch_2$D_IN;
wire tlb_entrySrch_2$EN;
// register tlb_entrySrch_3
reg [77 : 0] tlb_entrySrch_3;
wire [77 : 0] tlb_entrySrch_3$D_IN;
wire tlb_entrySrch_3$EN;
// register tlb_entrySrch_4
reg [77 : 0] tlb_entrySrch_4;
wire [77 : 0] tlb_entrySrch_4$D_IN;
wire tlb_entrySrch_4$EN;
// register tlb_entrySrch_5
reg [77 : 0] tlb_entrySrch_5;
wire [77 : 0] tlb_entrySrch_5$D_IN;
wire tlb_entrySrch_5$EN;
// register tlb_entrySrch_6
reg [77 : 0] tlb_entrySrch_6;
wire [77 : 0] tlb_entrySrch_6$D_IN;
wire tlb_entrySrch_6$EN;
// register tlb_entrySrch_7
reg [77 : 0] tlb_entrySrch_7;
wire [77 : 0] tlb_entrySrch_7$D_IN;
wire tlb_entrySrch_7$EN;
// register tlb_last_hit
reg [98 : 0] tlb_last_hit;
wire [98 : 0] tlb_last_hit$D_IN;
wire tlb_last_hit$EN;
// register tlb_last_hit_1
reg [98 : 0] tlb_last_hit_1;
wire [98 : 0] tlb_last_hit_1$D_IN;
wire tlb_last_hit_1$EN;
// register tlb_last_hit_2
reg [98 : 0] tlb_last_hit_2;
wire [98 : 0] tlb_last_hit_2$D_IN;
wire tlb_last_hit_2$EN;
// register tlb_last_hit_3
reg [98 : 0] tlb_last_hit_3;
wire [98 : 0] tlb_last_hit_3$D_IN;
wire tlb_last_hit_3$EN;
// register tlb_randomIndex
reg [2 : 0] tlb_randomIndex;
wire [2 : 0] tlb_randomIndex$D_IN;
wire tlb_randomIndex$EN;
// register tlb_tlbState
reg [2 : 0] tlb_tlbState;
reg [2 : 0] tlb_tlbState$D_IN;
wire tlb_tlbState$EN;
// register watchHi
reg [3 : 0] watchHi;
wire [3 : 0] watchHi$D_IN;
wire watchHi$EN;
// register watchLo
reg [31 : 0] watchLo;
wire [31 : 0] watchLo$D_IN;
wire watchLo$EN;
// ports of submodule avaddrs
wire [67 : 0] avaddrs$D_IN, avaddrs$D_OUT;
wire avaddrs$CLR, avaddrs$DEQ, avaddrs$EMPTY_N, avaddrs$ENQ, avaddrs$FULL_N;
// ports of submodule causeUpdate0
wire [31 : 0] causeUpdate0$D_IN, causeUpdate0$D_OUT;
wire causeUpdate0$CLR,
causeUpdate0$DEQ,
causeUpdate0$EMPTY_N,
causeUpdate0$ENQ;
// ports of submodule causeUpdate1
wire [31 : 0] causeUpdate1$D_IN, causeUpdate1$D_OUT;
wire causeUpdate1$CLR,
causeUpdate1$DEQ,
causeUpdate1$EMPTY_N,
causeUpdate1$ENQ;
// ports of submodule causeUpdate2
wire [7 : 0] causeUpdate2$D_IN, causeUpdate2$D_OUT;
wire causeUpdate2$CLR,
causeUpdate2$DEQ,
causeUpdate2$EMPTY_N,
causeUpdate2$ENQ;
// ports of submodule causeUpdate3
wire [7 : 0] causeUpdate3$D_IN, causeUpdate3$D_OUT;
wire causeUpdate3$CLR,
causeUpdate3$DEQ,
causeUpdate3$EMPTY_N,
causeUpdate3$ENQ,
causeUpdate3$FULL_N;
// ports of submodule contxtUpdate
wire [40 : 0] contxtUpdate$D_IN, contxtUpdate$D_OUT;
wire contxtUpdate$CLR,
contxtUpdate$DEQ,
contxtUpdate$EMPTY_N,
contxtUpdate$ENQ;
// ports of submodule counterInt
wire [4 : 0] counterInt$D_IN;
wire counterInt$CLR, counterInt$DEQ, counterInt$ENQ;
// ports of submodule dataUpdate
wire [63 : 0] dataUpdate$D_IN, dataUpdate$D_OUT;
wire dataUpdate$CLR,
dataUpdate$DEQ,
dataUpdate$EMPTY_N,
dataUpdate$ENQ,
dataUpdate$FULL_N;
// ports of submodule dvaddrs
wire [67 : 0] dvaddrs$D_IN, dvaddrs$D_OUT;
wire dvaddrs$CLR, dvaddrs$DEQ, dvaddrs$EMPTY_N, dvaddrs$ENQ;
// ports of submodule eretHappened
wire eretHappened$CLR,
eretHappened$DEQ,
eretHappened$D_IN,
eretHappened$EMPTY_N,
eretHappened$ENQ;
// ports of submodule eretReport
wire eretReport$CLR,
eretReport$DEQ,
eretReport$D_IN,
eretReport$EMPTY_N,
eretReport$ENQ,
eretReport$FULL_N;
// ports of submodule expectWrites
wire expectWrites$CLR,
expectWrites$DEQ,
expectWrites$D_IN,
expectWrites$EMPTY_N,
expectWrites$ENQ;
// ports of submodule forceUpdate
wire forceUpdate$CLR,
forceUpdate$DEQ,
forceUpdate$D_IN,
forceUpdate$D_OUT,
forceUpdate$EMPTY_N,
forceUpdate$ENQ,
forceUpdate$FULL_N;
// ports of submodule ivaddrs
wire [67 : 0] ivaddrs$D_IN, ivaddrs$D_OUT;
wire ivaddrs$CLR, ivaddrs$DEQ, ivaddrs$EMPTY_N, ivaddrs$ENQ;
// ports of submodule readReqs
wire [7 : 0] readReqs$D_IN, readReqs$D_OUT;
wire readReqs$CLR,
readReqs$DEQ,
readReqs$EMPTY_N,
readReqs$ENQ,
readReqs$FULL_N;
// ports of submodule resetRandom
wire resetRandom$CLR,
resetRandom$DEQ,
resetRandom$D_IN,
resetRandom$ENQ,
resetRandom$FULL_N;
// ports of submodule rnUpdate
wire [4 : 0] rnUpdate$D_IN, rnUpdate$D_OUT;
wire rnUpdate$CLR,
rnUpdate$DEQ,
rnUpdate$EMPTY_N,
rnUpdate$ENQ,
rnUpdate$FULL_N;
// ports of submodule tlbProbeResponses
wire tlbProbeResponses$CLR,
tlbProbeResponses$DEQ,
tlbProbeResponses$D_IN,
tlbProbeResponses$EMPTY_N,
tlbProbeResponses$ENQ;
// ports of submodule tlbProbes
wire [63 : 0] tlbProbes$D_IN, tlbProbes$D_OUT;
wire tlbProbes$CLR,
tlbProbes$DEQ,
tlbProbes$EMPTY_N,
tlbProbes$ENQ,
tlbProbes$FULL_N;
// ports of submodule tlbReads
wire tlbReads$CLR,
tlbReads$DEQ,
tlbReads$D_IN,
tlbReads$EMPTY_N,
tlbReads$ENQ,
tlbReads$FULL_N;
// ports of submodule tlb_entryHiHash
wire [77 : 0] tlb_entryHiHash$DIA, tlb_entryHiHash$DIB, tlb_entryHiHash$DOA;
wire [4 : 0] tlb_entryHiHash$ADDRA, tlb_entryHiHash$ADDRB;
wire tlb_entryHiHash$ENA,
tlb_entryHiHash$ENB,
tlb_entryHiHash$WEA,
tlb_entryHiHash$WEB;
// ports of submodule tlb_entryLo0
wire [31 : 0] tlb_entryLo0$DIA, tlb_entryLo0$DIB, tlb_entryLo0$DOA;
wire [5 : 0] tlb_entryLo0$ADDRA, tlb_entryLo0$ADDRB;
wire tlb_entryLo0$ENA, tlb_entryLo0$ENB, tlb_entryLo0$WEA, tlb_entryLo0$WEB;
// ports of submodule tlb_entryLo1
wire [31 : 0] tlb_entryLo1$DIA, tlb_entryLo1$DIB, tlb_entryLo1$DOA;
wire [5 : 0] tlb_entryLo1$ADDRA, tlb_entryLo1$ADDRB;
wire tlb_entryLo1$ENA, tlb_entryLo1$ENB, tlb_entryLo1$WEA, tlb_entryLo1$WEB;
// ports of submodule tlb_readOut_fifo
wire [5 : 0] tlb_readOut_fifo$D_IN, tlb_readOut_fifo$D_OUT;
wire tlb_readOut_fifo$CLR,
tlb_readOut_fifo$DEQ,
tlb_readOut_fifo$EMPTY_N,
tlb_readOut_fifo$ENQ,
tlb_readOut_fifo$FULL_N;
// ports of submodule tlb_readWrite_fifo
wire [149 : 0] tlb_readWrite_fifo$D_IN, tlb_readWrite_fifo$D_OUT;
wire tlb_readWrite_fifo$CLR,
tlb_readWrite_fifo$DEQ,
tlb_readWrite_fifo$EMPTY_N,
tlb_readWrite_fifo$ENQ;
// ports of submodule tlb_read_fifo
wire [84 : 0] tlb_read_fifo$D_IN, tlb_read_fifo$D_OUT;
wire tlb_read_fifo$CLR,
tlb_read_fifo$DEQ,
tlb_read_fifo$EMPTY_N,
tlb_read_fifo$ENQ,
tlb_read_fifo$FULL_N;
// ports of submodule tlb_req_fifos
wire [74 : 0] tlb_req_fifos$D_IN, tlb_req_fifos$D_OUT;
wire tlb_req_fifos$CLR,
tlb_req_fifos$DEQ,
tlb_req_fifos$EMPTY_N,
tlb_req_fifos$ENQ;
// ports of submodule tlb_req_fifos_1
wire [74 : 0] tlb_req_fifos_1$D_IN, tlb_req_fifos_1$D_OUT;
wire tlb_req_fifos_1$CLR,
tlb_req_fifos_1$DEQ,
tlb_req_fifos_1$EMPTY_N,
tlb_req_fifos_1$ENQ;
// ports of submodule tlb_req_fifos_2
wire [74 : 0] tlb_req_fifos_2$D_IN, tlb_req_fifos_2$D_OUT;
wire tlb_req_fifos_2$CLR,
tlb_req_fifos_2$DEQ,
tlb_req_fifos_2$EMPTY_N,
tlb_req_fifos_2$ENQ;
// ports of submodule tlb_req_fifos_3
wire [74 : 0] tlb_req_fifos_3$D_IN, tlb_req_fifos_3$D_OUT;
wire tlb_req_fifos_3$CLR,
tlb_req_fifos_3$DEQ,
tlb_req_fifos_3$EMPTY_N,
tlb_req_fifos_3$ENQ;
// ports of submodule tlb_rsp_fifos
wire [49 : 0] tlb_rsp_fifos$D_IN, tlb_rsp_fifos$D_OUT;
wire tlb_rsp_fifos$CLR,
tlb_rsp_fifos$DEQ,
tlb_rsp_fifos$EMPTY_N,
tlb_rsp_fifos$ENQ;
// ports of submodule tlb_rsp_fifos_1
wire [49 : 0] tlb_rsp_fifos_1$D_IN, tlb_rsp_fifos_1$D_OUT;
wire tlb_rsp_fifos_1$CLR,
tlb_rsp_fifos_1$DEQ,
tlb_rsp_fifos_1$EMPTY_N,
tlb_rsp_fifos_1$ENQ;
// ports of submodule tlb_rsp_fifos_2
wire [49 : 0] tlb_rsp_fifos_2$D_IN, tlb_rsp_fifos_2$D_OUT;
wire tlb_rsp_fifos_2$CLR,
tlb_rsp_fifos_2$DEQ,
tlb_rsp_fifos_2$EMPTY_N,
tlb_rsp_fifos_2$ENQ;
// ports of submodule tlb_rsp_fifos_3
wire [49 : 0] tlb_rsp_fifos_3$D_IN, tlb_rsp_fifos_3$D_OUT;
wire tlb_rsp_fifos_3$CLR,
tlb_rsp_fifos_3$DEQ,
tlb_rsp_fifos_3$EMPTY_N,
tlb_rsp_fifos_3$ENQ;
// ports of submodule tlb_smt_fifos
wire [49 : 0] tlb_smt_fifos$D_IN;
wire tlb_smt_fifos$CLR, tlb_smt_fifos$DEQ, tlb_smt_fifos$ENQ;
// ports of submodule tlb_smt_fifos_1
wire [49 : 0] tlb_smt_fifos_1$D_IN, tlb_smt_fifos_1$D_OUT;
wire tlb_smt_fifos_1$CLR,
tlb_smt_fifos_1$DEQ,
tlb_smt_fifos_1$EMPTY_N,
tlb_smt_fifos_1$ENQ,
tlb_smt_fifos_1$FULL_N;
// ports of submodule tlb_smt_fifos_2
wire [49 : 0] tlb_smt_fifos_2$D_IN, tlb_smt_fifos_2$D_OUT;
wire tlb_smt_fifos_2$CLR,
tlb_smt_fifos_2$DEQ,
tlb_smt_fifos_2$EMPTY_N,
tlb_smt_fifos_2$ENQ,
tlb_smt_fifos_2$FULL_N;
// ports of submodule tlb_smt_fifos_3
wire [49 : 0] tlb_smt_fifos_3$D_IN, tlb_smt_fifos_3$D_OUT;
wire tlb_smt_fifos_3$CLR,
tlb_smt_fifos_3$DEQ,
tlb_smt_fifos_3$EMPTY_N,
tlb_smt_fifos_3$ENQ,
tlb_smt_fifos_3$FULL_N;
// ports of submodule xcntxtUpdate
wire [30 : 0] xcntxtUpdate$D_IN, xcntxtUpdate$D_OUT;
wire xcntxtUpdate$CLR,
xcntxtUpdate$DEQ,
xcntxtUpdate$EMPTY_N,
xcntxtUpdate$ENQ;
// rule scheduling signals
wire WILL_FIRE_RL_readTlb,
WILL_FIRE_RL_tlb_doRead,
WILL_FIRE_RL_tlb_readTLB,
WILL_FIRE_RL_tlb_startTLB,
WILL_FIRE_RL_updateCP0Registers;
// inputs to muxes for submodule ports
wire [149 : 0] MUX_tlb_readWrite_fifo$enq_1__VAL_1,
MUX_tlb_readWrite_fifo$enq_1__VAL_2;
wire [98 : 0] MUX_tlb_last_hit$write_1__VAL_1,
MUX_tlb_last_hit$write_1__VAL_2,
MUX_tlb_last_hit_1$write_1__VAL_2,
MUX_tlb_last_hit_2$write_1__VAL_2,
MUX_tlb_last_hit_3$write_1__VAL_2;
wire [63 : 0] MUX_tlbEntryHi$write_1__VAL_2, MUX_tlbEntryHi$write_1__VAL_3;
wire [31 : 0] MUX_count$write_1__VAL_1,
MUX_sr$write_1__VAL_1,
MUX_sr$write_1__VAL_2,
MUX_tlbEntryLo0$write_1__VAL_1,
MUX_tlbEntryLo0$write_1__VAL_2,
MUX_tlbEntryLo1$write_1__VAL_2,
MUX_tlb_entryLo0$a_put_3__VAL_2,
MUX_tlb_entryLo1$a_put_3__VAL_2;
wire [11 : 0] MUX_tlbPageMask$write_1__VAL_2;
wire [6 : 0] MUX_tlbIndex$write_1__VAL_1, MUX_tlbIndex$write_1__VAL_2;
wire [5 : 0] MUX_tlb_entryLo0$a_put_2__VAL_1,
MUX_tlb_entryLo0$a_put_2__VAL_2,
MUX_tlb_entryLo0$b_put_2__VAL_1,
MUX_tlb_entryLo0$b_put_2__VAL_2;
wire [2 : 0] MUX_tlb_tlbState$write_1__VAL_2,
MUX_tlb_tlbState$write_1__VAL_3,
MUX_tlb_tlbState$write_1__VAL_4;
wire MUX_count$write_1__SEL_1,
MUX_epc$write_1__SEL_1,
MUX_epc$write_1__SEL_2,
MUX_sr$write_1__SEL_1,
MUX_tlbEntryHi$write_1__SEL_1,
MUX_tlbEntryHi$write_1__SEL_3,
MUX_tlbEntryLo0$write_1__SEL_1,
MUX_tlbEntryLo1$write_1__SEL_1,
MUX_tlbPageMask$write_1__SEL_1,
MUX_tlb_entryHiHash$a_put_1__SEL_1,
MUX_tlb_entryHiHash$a_put_1__SEL_2,
MUX_tlb_entryHiHash$b_put_1__SEL_1,
MUX_tlb_entrySrch$write_1__SEL_2,
MUX_tlb_entrySrch$write_1__SEL_3,
MUX_tlb_entrySrch_1$write_1__SEL_2,
MUX_tlb_entrySrch_1$write_1__SEL_3,
MUX_tlb_entrySrch_2$write_1__SEL_2,
MUX_tlb_entrySrch_2$write_1__SEL_3,
MUX_tlb_entrySrch_3$write_1__SEL_2,
MUX_tlb_entrySrch_3$write_1__SEL_3,
MUX_tlb_entrySrch_4$write_1__SEL_2,
MUX_tlb_entrySrch_4$write_1__SEL_3,
MUX_tlb_entrySrch_5$write_1__SEL_2,
MUX_tlb_entrySrch_5$write_1__SEL_3,
MUX_tlb_entrySrch_6$write_1__SEL_2,
MUX_tlb_entrySrch_6$write_1__SEL_3,
MUX_tlb_entrySrch_7$write_1__SEL_2,
MUX_tlb_entrySrch_7$write_1__SEL_3,
MUX_tlb_last_hit$write_1__SEL_1,
MUX_tlb_last_hit_1$write_1__SEL_1,
MUX_tlb_last_hit_2$write_1__SEL_1,
MUX_tlb_last_hit_3$write_1__SEL_1,
MUX_tlb_readWrite_fifo$enq_1__SEL_1,
MUX_tlb_tlbState$write_1__SEL_1,
MUX_tlb_tlbState$write_1__SEL_2,
MUX_tlb_tlbState$write_1__SEL_5;
// remaining internal signals
reg [74 : 0] CASE_requestSource___11175_tlb_req_fifos_3D_O_ETC__q19;
reg [63 : 0] CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5,
IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131,
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140,
v__h24572,
v__h24691,
v__h24929;
reg [11 : 0] IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534;
reg [5 : 0] CASE_dataUpdateD_OUT_BITS_5_TO_0_te_tlbAddr30_ETC__q16;
reg [4 : 0] CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4,
CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3,
CASE_cause_BITS_6_TO_2_31_0_cause_BITS_6_TO_2__ETC__q2,
CASE_dataUpdateD_OUT_BITS_6_TO_2_31_0_dataUpd_ETC__q17,
CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18,
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087;
reg [2 : 0] CASE_configReg0_BITS_2_TO_0_4_0_configReg0_BIT_ETC__q1,
CASE_dataUpdateD_OUT_BITS_5_TO_3_4_0_dataUpda_ETC__q7,
CASE_tlb_entryLo0DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q6,
CASE_tlb_entryLo1DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q8,
CASE_tlb_last_hit_1_BITS_5_TO_3_4_0_tlb_last_h_ETC__q12,
CASE_tlb_last_hit_2_BITS_5_TO_3_4_0_tlb_last_h_ETC__q13,
CASE_tlb_last_hit_3_BITS_5_TO_3_4_0_tlb_last_h_ETC__q14,
CASE_tlb_last_hit_BITS_5_TO_3_4_0_tlb_last_hit_ETC__q11,
CASE_tlb_readWrite_fifoD_OUT_BITS_37_TO_35_4__ETC__q9,
CASE_tlb_readWrite_fifoD_OUT_BITS_5_TO_3_4_0__ETC__q10,
IF_tlbEntryLo0_read__000_BITS_5_TO_3_007_EQ_0__ETC___d2143,
IF_tlbEntryLo1_read__002_BITS_5_TO_3_017_EQ_0__ETC___d2145;
reg [1 : 0] CASE_dataUpdateD_OUT_BITS_5_TO_0_3_1_0_2_2__q15;
reg IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079,
TASK_testplusargs___d1294,
TASK_testplusargs___d1393,
TASK_testplusargs___d1535,
TASK_testplusargs___d1708,
TASK_testplusargs___d492,
TASK_testplusargs___d500,
TASK_testplusargs___d779;
wire [141 : 0] IF_dataUpdate_first__21_BITS_5_TO_0_22_EQ_1_80_ETC___d1031;
wire [96 : 0] IF_tlb_read_fifo_first__52_BIT_84_55_THEN_IF_t_ETC___d487;
wire [63 : 0] IF_tlb_entryHiHash_a_read__5_BIT_13_6_AND_tlb__ETC___d473,
IF_tlb_req_fifos_1_i_notEmpty__69_AND_NOT_tlb__ETC___d1766,
IF_tlb_req_fifos_2_i_notEmpty__70_AND_NOT_tlb__ETC___d1776,
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759,
rv__h23510,
rv__h23551,
rv__h23577,
rv__h23612,
rv__h23621,
rv__h23634,
rv__h23650,
rv__h23658,
rv__h23688,
rv__h23771,
rv__h23813,
rv__h23926,
rv__h24032,
rv__h24107,
rv__h24236,
rv__h24245,
v__h24510,
v__h24520,
v__h24653,
v__h24663,
v__h24795,
v__h24890;
wire [40 : 0] v__h19352;
wire [35 : 0] IF_tlbLookupCoprocessors_0_request_put_BITS_74_ETC___d1659,
IF_tlbLookupData_request_put_BITS_74_TO_43_459_ETC___d1486,
IF_tlbLookupInstruction_request_put_BITS_74_TO_ETC___d1345,
IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d1761,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1760,
_theResult_____5__h15306,
addr__h26547,
addr__h28269,
addr__h30356,
response___1__h15677,
response__h15158,
x_addr__h27037,
x_addr__h28759,
x_addr__h30846;
wire [31 : 0] x__h23513, x__h23691, x__h23816;
wire [30 : 0] tlbIndexBase__h23491, v__h19480;
wire [29 : 0] cause_79_BITS_29_TO_28_90_CONCAT_IF_causeUpdat_ETC___d759;
wire [26 : 0] cause_79_BITS_26_TO_24_95_CONCAT_IF_causeUpdat_ETC___d758;
wire [23 : 0] _theResult___pfn__h15802;
wire [22 : 0] IF_causeUpdate0_i_notEmpty__66_THEN_causeUpdat_ETC___d757;
wire [15 : 0] IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d756;
wire [8 : 0] tlb_read_fifo_first__52_BITS_13_TO_12_16_CONCA_ETC___d427;
wire [7 : 0] IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d2124,
x1_avValue_ip__h18475,
x1_avValue_ip__h18496,
x1_avValue_ip__h18517,
x__h20699,
x__h21478,
x_ip__h18557,
y_avValue_ip__h18238;
wire [5 : 0] IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d485,
foundIndex___1__h15741,
te_tlbAddr__h23031,
x2__h14355,
x2__h14503,
x2__h8105,
x2__h9311,
x__h14519,
x__h15680,
x__h23535,
x__h8136,
x__h9327,
y_avValue_snd_fst__h15681;
wire [4 : 0] IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845,
IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_ETC___d2015,
IF_IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_ETC___d1436,
IF_IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_ETC___d1588,
IF_IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_ETC___d1862,
IF_IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_ETC___d1745,
IF_IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_ETC___d1749,
IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2064,
IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2070,
IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_AN_ETC___d2014,
IF_causeUpdate0_i_notEmpty__66_THEN_IF_cause_7_ETC___d2048,
IF_causeUpdate1_i_notEmpty__68_THEN_IF_causeUp_ETC___d708,
IF_tlbLookupCoprocessors_0_request_put_BITS_8__ETC___d2072,
IF_tlbLookupData_request_put_BITS_8_TO_4_455_E_ETC___d2066,
IF_tlbLookupInstruction_request_put_BITS_8_TO__ETC___d2060,
IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2099,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2102,
IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2103,
_theResult____h7635,
hashKey___1__h7990,
hashKey__h14215,
hashKey__h15193,
hashKey__h20299,
hashKey__h7634;
wire [2 : 0] IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d481,
IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d482,
IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d483,
IF_tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entryS_ETC___d1769,
IF_tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entryS_ETC___d1770,
IF_tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entryS_ETC___d1771,
IF_tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entryS_ETC___d1772,
IF_tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entryS_ETC___d1773,
IF_tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entryS_ETC___d1774,
IF_tlb_req_fifos_2_i_notEmpty__70_AND_NOT_tlb__ETC___d1767,
key__h14213,
requestSource___1__h11175,
x__h17372;
wire [1 : 0] IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2063,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2069,
IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2075,
_theResult___zeros__h15801;
wire IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_ETC___d414,
IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_AN_ETC___d403,
IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d584,
IF_tlb_entryHiHash_a_read__5_BIT_13_6_AND_tlb__ETC___d449,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_NOT_tl_ETC___d2125,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1576,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1931,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1972,
NOT_causeUpdate1_i_notEmpty__68_70_AND_IF_caus_ETC___d588,
NOT_llScReg_read__133_BIT_64_134_554_OR_NOT_0__ETC___d1595,
NOT_tlbLookupCoprocessors_0_request_put_BITS_7_ETC___d1706,
NOT_tlbLookupCoprocessors_0_request_put_BITS_7_ETC___d1720,
NOT_tlbLookupData_request_put_BITS_74_TO_43_45_ETC___d1533,
NOT_tlbLookupData_request_put_BITS_74_TO_43_45_ETC___d1547,
NOT_tlbLookupInstruction_request_put_BITS_74_T_ETC___d1391,
NOT_tlbLookupInstruction_request_put_BITS_74_T_ETC___d1405,
NOT_tlb_read_fifo_first__52_BIT_84_55_80_AND_N_ETC___d388,
avaddrs_first__198_BITS_3_TO_0_199_EQ_putExcep_ETC___d2058,
dataUpdate_i_notEmpty__91_AND_forceUpdate_i_no_ETC___d801,
dvaddrs_first__193_BITS_3_TO_0_194_EQ_putExcep_ETC___d2057,
ivaddrs_first__187_BITS_3_TO_0_188_EQ_putExcep_ETC___d2054,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d1045,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d1046,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d820,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d825,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d837,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d842,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d850,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d877,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d900,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d967,
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d989,
tlbLookupCoprocessors_0_request_put_BITS_74_TO_ETC___d1651,
tlbLookupData_request_put_BITS_74_TO_43_459_EQ_ETC___d1478,
tlbLookupInstruction_request_put_BITS_74_TO_43_ETC___d1337,
tlb_entryHiHash_a_read__5_BITS_21_TO_14_61_EQ__ETC___d2122,
tlb_entryHiHash_a_read__5_BITS_77_TO_27_57_EQ__ETC___d2121,
tlb_entrySrch_13_BIT_13_14_AND_tlb_entrySrch_1_ETC___d1907,
tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entrySrch_ETC___d1909,
tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entrySrch_ETC___d1911,
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1913,
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1944,
tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entrySrch_ETC___d1915,
tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entrySrch_ETC___d1917,
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1919,
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1950,
tlb_entrySrch_7_02_BIT_13_03_AND_tlb_entrySrch_ETC___d1921,
tlb_last_hit_1_17_BITS_39_TO_32_332_EQ_tlbEntr_ETC___d1333,
tlb_last_hit_1_17_BITS_95_TO_45_326_CONCAT_tlb_ETC___d1330,
tlb_last_hit_2_29_BITS_39_TO_32_473_EQ_tlbEntr_ETC___d1474,
tlb_last_hit_2_29_BITS_95_TO_45_467_CONCAT_tlb_ETC___d1471,
tlb_last_hit_3_41_BITS_39_TO_32_646_EQ_tlbEntr_ETC___d1647,
tlb_last_hit_3_41_BITS_95_TO_45_640_CONCAT_tlb_ETC___d1644,
tlb_readOut_fifo_first__09_ULT_8___d1869,
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867,
tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb_req_ETC___d1756,
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154;
// action method readReq
assign RDY_readReq = readReqs$FULL_N ;
// actionvalue method readGet
always@(readReqs$D_OUT or
rv__h23510 or
rv__h23551 or
rv__h23577 or
tlbContext or
rv__h23612 or
rv__h23621 or
badVAddr or
rv__h23634 or
tlbEntryHi or
rv__h23650 or
rv__h23658 or
rv__h23688 or
epc or
rv__h23771 or
IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131 or
llScReg or rv__h24236 or rv__h24245 or tlbXContext or errorEPC)
begin
case (readReqs$D_OUT[7:3])
5'd0: readGet = rv__h23510;
5'd2: readGet = rv__h23551;
5'd3: readGet = rv__h23577;
5'd4: readGet = tlbContext;
5'd5: readGet = rv__h23612;
5'd6: readGet = rv__h23621;
5'd8: readGet = badVAddr;
5'd9: readGet = rv__h23634;
5'd10: readGet = tlbEntryHi;
5'd11: readGet = rv__h23650;
5'd12: readGet = rv__h23658;
5'd13: readGet = rv__h23688;
5'd14: readGet = epc;
5'd15: readGet = rv__h23771;
5'd16:
readGet =
IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131;
5'd17: readGet = llScReg[63:0];
5'd18: readGet = rv__h24236;
5'd19: readGet = rv__h24245;
5'd20: readGet = tlbXContext;
5'd30: readGet = errorEPC;
default: readGet = 64'b0;
endcase
end
assign RDY_readGet =
!tlbProbeResponses$EMPTY_N && !expectWrites$EMPTY_N &&
readReqs$EMPTY_N ;
// action method writeReg
assign RDY_writeReg =
rnUpdate$FULL_N && dataUpdate$FULL_N && forceUpdate$FULL_N ;
// actionvalue method getException
assign getException =
{ sr[22],
sr[1],
((cause[15:8] & sr[15:8]) != 8'd0 && sr[0] && !sr[1]) ?
5'd0 :
5'd25 } ;
assign RDY_getException = 1'd1 ;
// action method putException
assign RDY_putException = 1'd1 ;
// value method getLlScReg
assign getLlScReg =
llScReg[64] && llScReg[11:0] == getLlScReg_matchAddress[11:0] &&
!eretHappened$EMPTY_N ;
assign RDY_getLlScReg = 1'd1 ;
// action method interrupts
assign RDY_interrupts = 1'd1 ;
// action method getExceptionReturn
assign RDY_getExceptionReturn = eretReport$EMPTY_N ;
// value method getCoprocessorEnables
assign getCoprocessorEnables =
{ sr[31:29], sr[4:3] == 2'd0 || sr[1] || sr[28] } ;
assign RDY_getCoprocessorEnables = 1'd1 ;
// action method tlbLookupInstruction_request_put
assign RDY_tlbLookupInstruction_request_put =
tlb_tlbState == 3'd1 && !tlb_req_fifos_1$EMPTY_N &&
tlb_smt_fifos_1$FULL_N ;
// actionvalue method tlbLookupInstruction_response_get
assign tlbLookupInstruction_response_get =
{ IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d1761,
(IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d1761 ==
{ watchHi, watchLo[31:3], 3'b0 } &&
watchLo[1]) ?
((IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2064 ==
5'd25) ?
5'd23 :
IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2064) :
IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2064,
tlb_smt_fifos_1$EMPTY_N ?
tlb_smt_fifos_1$D_OUT[8:0] :
tlb_rsp_fifos_1$D_OUT[8:0] } ;
assign RDY_tlbLookupInstruction_response_get =
tlb_smt_fifos_1$EMPTY_N || tlb_rsp_fifos_1$EMPTY_N ;
// action method tlbLookupData_request_put
assign RDY_tlbLookupData_request_put =
tlb_tlbState == 3'd1 && !tlb_req_fifos_2$EMPTY_N &&
tlb_smt_fifos_2$FULL_N ;
// actionvalue method tlbLookupData_response_get
assign tlbLookupData_response_get =
{ IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1760,
IF_IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_ETC___d1862,
tlb_smt_fifos_2$EMPTY_N ?
tlb_smt_fifos_2$D_OUT[8:0] :
tlb_rsp_fifos_2$D_OUT[8:0] } ;
assign RDY_tlbLookupData_response_get =
tlb_smt_fifos_2$EMPTY_N || tlb_rsp_fifos_2$EMPTY_N ;
// action method tlbLookupCoprocessors_0_request_put
assign RDY_tlbLookupCoprocessors_0_request_put =
tlb_tlbState == 3'd1 && !tlb_req_fifos_3$EMPTY_N &&
tlb_smt_fifos_3$FULL_N &&
avaddrs$FULL_N ;
// actionvalue method tlbLookupCoprocessors_0_response_get
assign tlbLookupCoprocessors_0_response_get =
{ tlb_smt_fifos_3$EMPTY_N ?
tlb_smt_fifos_3$D_OUT[49:14] :
tlb_rsp_fifos_3$D_OUT[49:14],
(sr[4:3] != 2'd0 && !sr[1]) ?
IF_IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_ETC___d1749 :
IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2103,
tlb_smt_fifos_3$EMPTY_N ?
tlb_smt_fifos_3$D_OUT[8:0] :
tlb_rsp_fifos_3$D_OUT[8:0] } ;
assign RDY_tlbLookupCoprocessors_0_response_get =
tlb_smt_fifos_3$EMPTY_N || tlb_rsp_fifos_3$EMPTY_N ;
// submodule avaddrs
FIFO2 #(.width(32'd68), .guarded(32'd0)) avaddrs(.RST_N(RST_N),
.CLK(CLK),
.D_IN(avaddrs$D_IN),
.ENQ(avaddrs$ENQ),
.DEQ(avaddrs$DEQ),
.CLR(avaddrs$CLR),
.D_OUT(avaddrs$D_OUT),
.FULL_N(avaddrs$FULL_N),
.EMPTY_N(avaddrs$EMPTY_N));
// submodule causeUpdate0
FIFO1 #(.width(32'd32), .guarded(32'd0)) causeUpdate0(.RST_N(RST_N),
.CLK(CLK),
.D_IN(causeUpdate0$D_IN),
.ENQ(causeUpdate0$ENQ),
.DEQ(causeUpdate0$DEQ),
.CLR(causeUpdate0$CLR),
.D_OUT(causeUpdate0$D_OUT),
.FULL_N(),
.EMPTY_N(causeUpdate0$EMPTY_N));
// submodule causeUpdate1
FIFO1 #(.width(32'd32), .guarded(32'd0)) causeUpdate1(.RST_N(RST_N),
.CLK(CLK),
.D_IN(causeUpdate1$D_IN),
.ENQ(causeUpdate1$ENQ),
.DEQ(causeUpdate1$DEQ),
.CLR(causeUpdate1$CLR),
.D_OUT(causeUpdate1$D_OUT),
.FULL_N(),
.EMPTY_N(causeUpdate1$EMPTY_N));
// submodule causeUpdate2
FIFO1 #(.width(32'd8), .guarded(32'd0)) causeUpdate2(.RST_N(RST_N),
.CLK(CLK),
.D_IN(causeUpdate2$D_IN),
.ENQ(causeUpdate2$ENQ),
.DEQ(causeUpdate2$DEQ),
.CLR(causeUpdate2$CLR),
.D_OUT(causeUpdate2$D_OUT),
.FULL_N(),
.EMPTY_N(causeUpdate2$EMPTY_N));
// submodule causeUpdate3
FIFO1 #(.width(32'd8), .guarded(32'd0)) causeUpdate3(.RST_N(RST_N),
.CLK(CLK),
.D_IN(causeUpdate3$D_IN),
.ENQ(causeUpdate3$ENQ),
.DEQ(causeUpdate3$DEQ),
.CLR(causeUpdate3$CLR),
.D_OUT(causeUpdate3$D_OUT),
.FULL_N(causeUpdate3$FULL_N),
.EMPTY_N(causeUpdate3$EMPTY_N));
// submodule contxtUpdate
FIFO1 #(.width(32'd41), .guarded(32'd0)) contxtUpdate(.RST_N(RST_N),
.CLK(CLK),
.D_IN(contxtUpdate$D_IN),
.ENQ(contxtUpdate$ENQ),
.DEQ(contxtUpdate$DEQ),
.CLR(contxtUpdate$CLR),
.D_OUT(contxtUpdate$D_OUT),
.FULL_N(),
.EMPTY_N(contxtUpdate$EMPTY_N));
// submodule counterInt
FIFO2 #(.width(32'd5), .guarded(32'd0)) counterInt(.RST_N(RST_N),
.CLK(CLK),
.D_IN(counterInt$D_IN),
.ENQ(counterInt$ENQ),
.DEQ(counterInt$DEQ),
.CLR(counterInt$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule dataUpdate
FIFO2 #(.width(32'd64), .guarded(32'd1)) dataUpdate(.RST_N(RST_N),
.CLK(CLK),
.D_IN(dataUpdate$D_IN),
.ENQ(dataUpdate$ENQ),
.DEQ(dataUpdate$DEQ),
.CLR(dataUpdate$CLR),
.D_OUT(dataUpdate$D_OUT),
.FULL_N(dataUpdate$FULL_N),
.EMPTY_N(dataUpdate$EMPTY_N));
// submodule dvaddrs
FIFO2 #(.width(32'd68), .guarded(32'd0)) dvaddrs(.RST_N(RST_N),
.CLK(CLK),
.D_IN(dvaddrs$D_IN),
.ENQ(dvaddrs$ENQ),
.DEQ(dvaddrs$DEQ),
.CLR(dvaddrs$CLR),
.D_OUT(dvaddrs$D_OUT),
.FULL_N(),
.EMPTY_N(dvaddrs$EMPTY_N));
// submodule eretHappened
FIFO1 #(.width(32'd1), .guarded(32'd0)) eretHappened(.RST_N(RST_N),
.CLK(CLK),
.D_IN(eretHappened$D_IN),
.ENQ(eretHappened$ENQ),
.DEQ(eretHappened$DEQ),
.CLR(eretHappened$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(eretHappened$EMPTY_N));
// submodule eretReport
FIFO1 #(.width(32'd1), .guarded(32'd1)) eretReport(.RST_N(RST_N),
.CLK(CLK),
.D_IN(eretReport$D_IN),
.ENQ(eretReport$ENQ),
.DEQ(eretReport$DEQ),
.CLR(eretReport$CLR),
.D_OUT(),
.FULL_N(eretReport$FULL_N),
.EMPTY_N(eretReport$EMPTY_N));
// submodule expectWrites
FIFO2 #(.width(32'd1), .guarded(32'd0)) expectWrites(.RST_N(RST_N),
.CLK(CLK),
.D_IN(expectWrites$D_IN),
.ENQ(expectWrites$ENQ),
.DEQ(expectWrites$DEQ),
.CLR(expectWrites$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(expectWrites$EMPTY_N));
// submodule forceUpdate
FIFO2 #(.width(32'd1), .guarded(32'd1)) forceUpdate(.RST_N(RST_N),
.CLK(CLK),
.D_IN(forceUpdate$D_IN),
.ENQ(forceUpdate$ENQ),
.DEQ(forceUpdate$DEQ),
.CLR(forceUpdate$CLR),
.D_OUT(forceUpdate$D_OUT),
.FULL_N(forceUpdate$FULL_N),
.EMPTY_N(forceUpdate$EMPTY_N));
// submodule ivaddrs
SizedFIFO #(.p1width(32'd68),
.p2depth(32'd7),
.p3cntr_width(32'd3),
.guarded(32'd0)) ivaddrs(.RST_N(RST_N),
.CLK(CLK),
.D_IN(ivaddrs$D_IN),
.ENQ(ivaddrs$ENQ),
.DEQ(ivaddrs$DEQ),
.CLR(ivaddrs$CLR),
.D_OUT(ivaddrs$D_OUT),
.FULL_N(),
.EMPTY_N(ivaddrs$EMPTY_N));
// submodule readReqs
FIFOL1 #(.width(32'd8)) readReqs(.RST_N(RST_N),
.CLK(CLK),
.D_IN(readReqs$D_IN),
.ENQ(readReqs$ENQ),
.DEQ(readReqs$DEQ),
.CLR(readReqs$CLR),
.D_OUT(readReqs$D_OUT),
.FULL_N(readReqs$FULL_N),
.EMPTY_N(readReqs$EMPTY_N));
// submodule resetRandom
FIFO2 #(.width(32'd1), .guarded(32'd0)) resetRandom(.RST_N(RST_N),
.CLK(CLK),
.D_IN(resetRandom$D_IN),
.ENQ(resetRandom$ENQ),
.DEQ(resetRandom$DEQ),
.CLR(resetRandom$CLR),
.D_OUT(),
.FULL_N(resetRandom$FULL_N),
.EMPTY_N());
// submodule rnUpdate
FIFO2 #(.width(32'd5), .guarded(32'd1)) rnUpdate(.RST_N(RST_N),
.CLK(CLK),
.D_IN(rnUpdate$D_IN),
.ENQ(rnUpdate$ENQ),
.DEQ(rnUpdate$DEQ),
.CLR(rnUpdate$CLR),
.D_OUT(rnUpdate$D_OUT),
.FULL_N(rnUpdate$FULL_N),
.EMPTY_N(rnUpdate$EMPTY_N));
// submodule tlbProbeResponses
FIFO2 #(.width(32'd1), .guarded(32'd0)) tlbProbeResponses(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlbProbeResponses$D_IN),
.ENQ(tlbProbeResponses$ENQ),
.DEQ(tlbProbeResponses$DEQ),
.CLR(tlbProbeResponses$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(tlbProbeResponses$EMPTY_N));
// submodule tlbProbes
FIFO1 #(.width(32'd64), .guarded(32'd1)) tlbProbes(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlbProbes$D_IN),
.ENQ(tlbProbes$ENQ),
.DEQ(tlbProbes$DEQ),
.CLR(tlbProbes$CLR),
.D_OUT(tlbProbes$D_OUT),
.FULL_N(tlbProbes$FULL_N),
.EMPTY_N(tlbProbes$EMPTY_N));
// submodule tlbReads
FIFO2 #(.width(32'd1), .guarded(32'd1)) tlbReads(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlbReads$D_IN),
.ENQ(tlbReads$ENQ),
.DEQ(tlbReads$DEQ),
.CLR(tlbReads$CLR),
.D_OUT(),
.FULL_N(tlbReads$FULL_N),
.EMPTY_N(tlbReads$EMPTY_N));
// submodule tlb_entryHiHash
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd5),
.DATA_WIDTH(32'd78),
.MEMSIZE(6'd32)) tlb_entryHiHash(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb_entryHiHash$ADDRA),
.ADDRB(tlb_entryHiHash$ADDRB),
.DIA(tlb_entryHiHash$DIA),
.DIB(tlb_entryHiHash$DIB),
.WEA(tlb_entryHiHash$WEA),
.WEB(tlb_entryHiHash$WEB),
.ENA(tlb_entryHiHash$ENA),
.ENB(tlb_entryHiHash$ENB),
.DOA(tlb_entryHiHash$DOA),
.DOB());
// submodule tlb_entryLo0
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd6),
.DATA_WIDTH(32'd32),
.MEMSIZE(7'd40)) tlb_entryLo0(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb_entryLo0$ADDRA),
.ADDRB(tlb_entryLo0$ADDRB),
.DIA(tlb_entryLo0$DIA),
.DIB(tlb_entryLo0$DIB),
.WEA(tlb_entryLo0$WEA),
.WEB(tlb_entryLo0$WEB),
.ENA(tlb_entryLo0$ENA),
.ENB(tlb_entryLo0$ENB),
.DOA(tlb_entryLo0$DOA),
.DOB());
// submodule tlb_entryLo1
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd6),
.DATA_WIDTH(32'd32),
.MEMSIZE(7'd40)) tlb_entryLo1(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb_entryLo1$ADDRA),
.ADDRB(tlb_entryLo1$ADDRB),
.DIA(tlb_entryLo1$DIA),
.DIB(tlb_entryLo1$DIB),
.WEA(tlb_entryLo1$WEA),
.WEB(tlb_entryLo1$WEB),
.ENA(tlb_entryLo1$ENA),
.ENB(tlb_entryLo1$ENB),
.DOA(tlb_entryLo1$DOA),
.DOB());
// submodule tlb_readOut_fifo
FIFO2 #(.width(32'd6), .guarded(32'd1)) tlb_readOut_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_readOut_fifo$D_IN),
.ENQ(tlb_readOut_fifo$ENQ),
.DEQ(tlb_readOut_fifo$DEQ),
.CLR(tlb_readOut_fifo$CLR),
.D_OUT(tlb_readOut_fifo$D_OUT),
.FULL_N(tlb_readOut_fifo$FULL_N),
.EMPTY_N(tlb_readOut_fifo$EMPTY_N));
// submodule tlb_readWrite_fifo
FIFO2 #(.width(32'd150), .guarded(32'd0)) tlb_readWrite_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_readWrite_fifo$D_IN),
.ENQ(tlb_readWrite_fifo$ENQ),
.DEQ(tlb_readWrite_fifo$DEQ),
.CLR(tlb_readWrite_fifo$CLR),
.D_OUT(tlb_readWrite_fifo$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_readWrite_fifo$EMPTY_N));
// submodule tlb_read_fifo
FIFO2 #(.width(32'd85), .guarded(32'd1)) tlb_read_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_read_fifo$D_IN),
.ENQ(tlb_read_fifo$ENQ),
.DEQ(tlb_read_fifo$DEQ),
.CLR(tlb_read_fifo$CLR),
.D_OUT(tlb_read_fifo$D_OUT),
.FULL_N(tlb_read_fifo$FULL_N),
.EMPTY_N(tlb_read_fifo$EMPTY_N));
// submodule tlb_req_fifos
FIFO2 #(.width(32'd75), .guarded(32'd0)) tlb_req_fifos(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_req_fifos$D_IN),
.ENQ(tlb_req_fifos$ENQ),
.DEQ(tlb_req_fifos$DEQ),
.CLR(tlb_req_fifos$CLR),
.D_OUT(tlb_req_fifos$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_req_fifos$EMPTY_N));
// submodule tlb_req_fifos_1
FIFO2 #(.width(32'd75), .guarded(32'd0)) tlb_req_fifos_1(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_req_fifos_1$D_IN),
.ENQ(tlb_req_fifos_1$ENQ),
.DEQ(tlb_req_fifos_1$DEQ),
.CLR(tlb_req_fifos_1$CLR),
.D_OUT(tlb_req_fifos_1$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_req_fifos_1$EMPTY_N));
// submodule tlb_req_fifos_2
FIFO2 #(.width(32'd75), .guarded(32'd0)) tlb_req_fifos_2(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_req_fifos_2$D_IN),
.ENQ(tlb_req_fifos_2$ENQ),
.DEQ(tlb_req_fifos_2$DEQ),
.CLR(tlb_req_fifos_2$CLR),
.D_OUT(tlb_req_fifos_2$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_req_fifos_2$EMPTY_N));
// submodule tlb_req_fifos_3
FIFO2 #(.width(32'd75), .guarded(32'd0)) tlb_req_fifos_3(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_req_fifos_3$D_IN),
.ENQ(tlb_req_fifos_3$ENQ),
.DEQ(tlb_req_fifos_3$DEQ),
.CLR(tlb_req_fifos_3$CLR),
.D_OUT(tlb_req_fifos_3$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_req_fifos_3$EMPTY_N));
// submodule tlb_rsp_fifos
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_rsp_fifos(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_rsp_fifos$D_IN),
.ENQ(tlb_rsp_fifos$ENQ),
.DEQ(tlb_rsp_fifos$DEQ),
.CLR(tlb_rsp_fifos$CLR),
.D_OUT(tlb_rsp_fifos$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_rsp_fifos$EMPTY_N));
// submodule tlb_rsp_fifos_1
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_rsp_fifos_1(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_rsp_fifos_1$D_IN),
.ENQ(tlb_rsp_fifos_1$ENQ),
.DEQ(tlb_rsp_fifos_1$DEQ),
.CLR(tlb_rsp_fifos_1$CLR),
.D_OUT(tlb_rsp_fifos_1$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_rsp_fifos_1$EMPTY_N));
// submodule tlb_rsp_fifos_2
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_rsp_fifos_2(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_rsp_fifos_2$D_IN),
.ENQ(tlb_rsp_fifos_2$ENQ),
.DEQ(tlb_rsp_fifos_2$DEQ),
.CLR(tlb_rsp_fifos_2$CLR),
.D_OUT(tlb_rsp_fifos_2$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_rsp_fifos_2$EMPTY_N));
// submodule tlb_rsp_fifos_3
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_rsp_fifos_3(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_rsp_fifos_3$D_IN),
.ENQ(tlb_rsp_fifos_3$ENQ),
.DEQ(tlb_rsp_fifos_3$DEQ),
.CLR(tlb_rsp_fifos_3$CLR),
.D_OUT(tlb_rsp_fifos_3$D_OUT),
.FULL_N(),
.EMPTY_N(tlb_rsp_fifos_3$EMPTY_N));
// submodule tlb_smt_fifos
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_smt_fifos(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_smt_fifos$D_IN),
.ENQ(tlb_smt_fifos$ENQ),
.DEQ(tlb_smt_fifos$DEQ),
.CLR(tlb_smt_fifos$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule tlb_smt_fifos_1
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_smt_fifos_1(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_smt_fifos_1$D_IN),
.ENQ(tlb_smt_fifos_1$ENQ),
.DEQ(tlb_smt_fifos_1$DEQ),
.CLR(tlb_smt_fifos_1$CLR),
.D_OUT(tlb_smt_fifos_1$D_OUT),
.FULL_N(tlb_smt_fifos_1$FULL_N),
.EMPTY_N(tlb_smt_fifos_1$EMPTY_N));
// submodule tlb_smt_fifos_2
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_smt_fifos_2(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_smt_fifos_2$D_IN),
.ENQ(tlb_smt_fifos_2$ENQ),
.DEQ(tlb_smt_fifos_2$DEQ),
.CLR(tlb_smt_fifos_2$CLR),
.D_OUT(tlb_smt_fifos_2$D_OUT),
.FULL_N(tlb_smt_fifos_2$FULL_N),
.EMPTY_N(tlb_smt_fifos_2$EMPTY_N));
// submodule tlb_smt_fifos_3
FIFO2 #(.width(32'd50), .guarded(32'd0)) tlb_smt_fifos_3(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tlb_smt_fifos_3$D_IN),
.ENQ(tlb_smt_fifos_3$ENQ),
.DEQ(tlb_smt_fifos_3$DEQ),
.CLR(tlb_smt_fifos_3$CLR),
.D_OUT(tlb_smt_fifos_3$D_OUT),
.FULL_N(tlb_smt_fifos_3$FULL_N),
.EMPTY_N(tlb_smt_fifos_3$EMPTY_N));
// submodule xcntxtUpdate
FIFO1 #(.width(32'd31), .guarded(32'd0)) xcntxtUpdate(.RST_N(RST_N),
.CLK(CLK),
.D_IN(xcntxtUpdate$D_IN),
.ENQ(xcntxtUpdate$ENQ),
.DEQ(xcntxtUpdate$DEQ),
.CLR(xcntxtUpdate$CLR),
.D_OUT(xcntxtUpdate$D_OUT),
.FULL_N(),
.EMPTY_N(xcntxtUpdate$EMPTY_N));
// rule RL_readTlb
assign WILL_FIRE_RL_readTlb =
tlb_tlbState == 3'd6 && !tlb_readWrite_fifo$EMPTY_N &&
tlb_readOut_fifo$EMPTY_N &&
tlbReads$EMPTY_N ;
// rule RL_updateCP0Registers
assign WILL_FIRE_RL_updateCP0Registers =
rnUpdate$EMPTY_N &&
dataUpdate_i_notEmpty__91_AND_forceUpdate_i_no_ETC___d801 &&
!tlbReads$EMPTY_N &&
!tlbProbeResponses$EMPTY_N ;
// rule RL_tlb_doRead
assign WILL_FIRE_RL_tlb_doRead =
tlb_readOut_fifo$FULL_N && tlb_tlbState == 3'd3 ;
// rule RL_tlb_startTLB
assign WILL_FIRE_RL_tlb_startTLB =
tlb_read_fifo$FULL_N && tlb_tlbState == 3'd1 ;
// rule RL_tlb_readTLB
assign WILL_FIRE_RL_tlb_readTLB =
tlb_read_fifo$EMPTY_N && tlb_tlbState == 3'd2 ;
// inputs to muxes for submodule ports
assign MUX_count$write_1__SEL_1 = !cause[27] && !TASK_testplusargs___d779 ;
assign MUX_epc$write_1__SEL_1 =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d967 ;
assign MUX_epc$write_1__SEL_2 =
EN_putException && putException_exp[138:134] != 5'd25 &&
!putException_exp[0] ;
assign MUX_sr$write_1__SEL_1 =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d900 ;
assign MUX_tlbEntryHi$write_1__SEL_1 =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d850 ;
assign MUX_tlbEntryHi$write_1__SEL_3 =
EN_putException && !putException_exp[0] &&
(putException_exp[138:134] == 5'd2 ||
putException_exp[138:134] == 5'd3 ||
putException_exp[138:134] == 5'd4 ||
putException_exp[138:134] == 5'd5 ||
putException_exp[138:134] == 5'd6 ||
putException_exp[138:134] == 5'd7 ||
putException_exp[138:134] == 5'd1 ||
putException_exp[138:134] == 5'd8 ||
putException_exp[138:134] == 5'd9 ||
putException_exp[138:134] == 5'd10) ;
assign MUX_tlbEntryLo0$write_1__SEL_1 =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d825 ;
assign MUX_tlbEntryLo1$write_1__SEL_1 =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d837 ;
assign MUX_tlbPageMask$write_1__SEL_1 =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d842 ;
assign MUX_tlb_entryHiHash$a_put_1__SEL_1 =
WILL_FIRE_RL_tlb_doRead &&
!tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 ;
assign MUX_tlb_entryHiHash$a_put_1__SEL_2 =
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 ;
assign MUX_tlb_entryHiHash$b_put_1__SEL_1 =
tlb_tlbState == 3'd4 &&
!tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 ;
assign MUX_tlb_entrySrch$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd0 ;
assign MUX_tlb_entrySrch$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd0 ;
assign MUX_tlb_entrySrch_1$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd1 ;
assign MUX_tlb_entrySrch_1$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd1 ;
assign MUX_tlb_entrySrch_2$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd2 ;
assign MUX_tlb_entrySrch_2$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd2 ;
assign MUX_tlb_entrySrch_3$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd3 ;
assign MUX_tlb_entrySrch_3$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd3 ;
assign MUX_tlb_entrySrch_4$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd4 ;
assign MUX_tlb_entrySrch_4$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd4 ;
assign MUX_tlb_entrySrch_5$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd5 ;
assign MUX_tlb_entrySrch_5$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd5 ;
assign MUX_tlb_entrySrch_6$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd6 ;
assign MUX_tlb_entrySrch_6$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd6 ;
assign MUX_tlb_entrySrch_7$write_1__SEL_2 =
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd7 ;
assign MUX_tlb_entrySrch_7$write_1__SEL_3 =
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd7 ;
assign MUX_tlb_last_hit$write_1__SEL_1 =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd0 ;
assign MUX_tlb_last_hit_1$write_1__SEL_1 =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd1 ;
assign MUX_tlb_last_hit_2$write_1__SEL_1 =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd2 ;
assign MUX_tlb_last_hit_3$write_1__SEL_1 =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd3 ;
assign MUX_tlb_readWrite_fifo$enq_1__SEL_1 =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d989 ;
assign MUX_tlb_tlbState$write_1__SEL_1 =
tlb_tlbState == 3'd0 && tlb_count == 5'd31 ;
assign MUX_tlb_tlbState$write_1__SEL_2 =
WILL_FIRE_RL_tlb_startTLB &&
(tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 ||
tlb_readWrite_fifo$EMPTY_N) ;
assign MUX_tlb_tlbState$write_1__SEL_5 =
WILL_FIRE_RL_readTlb || WILL_FIRE_RL_tlb_readTLB ||
tlb_tlbState == 3'd5 ;
assign MUX_count$write_1__VAL_1 = count + 32'd1 ;
assign MUX_sr$write_1__VAL_1 =
(rnUpdate$D_OUT == 5'd12) ?
{ dataUpdate$D_OUT[31:28],
sr[27:23],
dataUpdate$D_OUT[22],
sr[21:16],
dataUpdate$D_OUT[15:8],
sr[7:5],
dataUpdate$D_OUT[4:3],
sr[2],
dataUpdate$D_OUT[1:0] } :
{ sr[31:2], 1'd0, sr[0] } ;
assign MUX_sr$write_1__VAL_2 = { sr[31:2], 1'd1, sr[0] } ;
assign MUX_tlbEntryHi$write_1__VAL_2 =
tlb_readOut_fifo_first__09_ULT_8___d1869 ?
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 :
tlb_entryHiHash$DOA[77:14] ;
assign MUX_tlbEntryHi$write_1__VAL_3 =
{ v__h24795[63:13], 5'd0, tlbEntryHi[7:0] } ;
assign MUX_tlbEntryLo0$write_1__VAL_1 =
{ dataUpdate$D_OUT[31:6],
CASE_dataUpdateD_OUT_BITS_5_TO_3_4_0_dataUpda_ETC__q7,
dataUpdate$D_OUT[2:0] } ;
assign MUX_tlbEntryLo0$write_1__VAL_2 =
{ tlb_entryLo0$DOA[31:6],
CASE_tlb_entryLo0DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q6,
tlb_entryLo0$DOA[2:0] } ;
assign MUX_tlbEntryLo1$write_1__VAL_2 =
{ tlb_entryLo1$DOA[31:6],
CASE_tlb_entryLo1DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q8,
tlb_entryLo1$DOA[2:0] } ;
assign MUX_tlbIndex$write_1__VAL_1 =
{ tlb_rsp_fifos$D_OUT[13:9] != 5'd4 &&
tlb_rsp_fifos$D_OUT[13:9] != 5'd5,
tlb_rsp_fifos$D_OUT[19:14] } ;
assign MUX_tlbIndex$write_1__VAL_2 = { 1'd1, dataUpdate$D_OUT[5:0] } ;
assign MUX_tlbPageMask$write_1__VAL_2 =
tlb_readOut_fifo_first__09_ULT_8___d1869 ?
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 :
tlb_entryHiHash$DOA[12:1] ;
assign MUX_tlb_entryLo0$a_put_2__VAL_1 =
(tlb_entrySrch_7_02_BIT_13_03_AND_tlb_entrySrch_ETC___d1921 ||
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1950) ?
x2__h14355 :
x2__h14503 ;
assign MUX_tlb_entryLo0$a_put_2__VAL_2 =
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 ?
tlb_readWrite_fifo$D_OUT[147:142] :
x2__h8105 ;
assign MUX_tlb_entryLo0$a_put_3__VAL_2 =
{ tlb_readWrite_fifo$D_OUT[63:38],
CASE_tlb_readWrite_fifoD_OUT_BITS_37_TO_35_4__ETC__q9,
tlb_readWrite_fifo$D_OUT[34:32] } ;
assign MUX_tlb_entryLo0$b_put_2__VAL_1 = { 3'd0, tlb_randomIndex } ;
assign MUX_tlb_entryLo0$b_put_2__VAL_2 =
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 ?
tlb_readWrite_fifo$D_OUT[147:142] :
x2__h9311 ;
assign MUX_tlb_entryLo1$a_put_3__VAL_2 =
{ tlb_readWrite_fifo$D_OUT[31:6],
CASE_tlb_readWrite_fifoD_OUT_BITS_5_TO_3_4_0__ETC__q10,
tlb_readWrite_fifo$D_OUT[2:0] } ;
assign MUX_tlb_last_hit$write_1__VAL_1 =
{ 1'd1,
tlb_read_fifo$D_OUT[26],
IF_tlb_read_fifo_first__52_BIT_84_55_THEN_IF_t_ETC___d487 } ;
assign MUX_tlb_last_hit$write_1__VAL_2 =
{ 1'd0,
tlb_last_hit[97:6],
CASE_tlb_last_hit_BITS_5_TO_3_4_0_tlb_last_hit_ETC__q11,
tlb_last_hit[2:0] } ;
assign MUX_tlb_last_hit_1$write_1__VAL_2 =
{ 1'd0,
tlb_last_hit_1[97:6],
CASE_tlb_last_hit_1_BITS_5_TO_3_4_0_tlb_last_h_ETC__q12,
tlb_last_hit_1[2:0] } ;
assign MUX_tlb_last_hit_2$write_1__VAL_2 =
{ 1'd0,
tlb_last_hit_2[97:6],
CASE_tlb_last_hit_2_BITS_5_TO_3_4_0_tlb_last_h_ETC__q13,
tlb_last_hit_2[2:0] } ;
assign MUX_tlb_last_hit_3$write_1__VAL_2 =
{ 1'd0,
tlb_last_hit_3[97:6],
CASE_tlb_last_hit_3_BITS_5_TO_3_4_0_tlb_last_h_ETC__q14,
tlb_last_hit_3[2:0] } ;
assign MUX_tlb_readWrite_fifo$enq_1__VAL_1 =
{ CASE_dataUpdateD_OUT_BITS_5_TO_0_3_1_0_2_2__q15,
CASE_dataUpdateD_OUT_BITS_5_TO_0_te_tlbAddr30_ETC__q16,
IF_dataUpdate_first__21_BITS_5_TO_0_22_EQ_1_80_ETC___d1031 } ;
assign MUX_tlb_readWrite_fifo$enq_1__VAL_2 =
{ 8'h2A,
tlb_entryHiHash$DOA,
tlb_entryLo0$DOA[31:6],
CASE_tlb_entryLo0DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q6,
tlb_entryLo0$DOA[2:0],
tlb_entryLo1$DOA[31:6],
CASE_tlb_entryLo1DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q8,
tlb_entryLo1$DOA[2:0] } ;
assign MUX_tlb_tlbState$write_1__VAL_2 =
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 ?
3'd2 :
3'd3 ;
assign MUX_tlb_tlbState$write_1__VAL_3 =
tlb_readWrite_fifo$D_OUT[149] ? 3'd4 : 3'd6 ;
assign MUX_tlb_tlbState$write_1__VAL_4 =
(!tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_entryHiHash$DOA[13] &&
tlb_readWrite_fifo$D_OUT[148]) ?
3'd5 :
3'd1 ;
// register badVAddr
assign badVAddr$D_IN = v__h24795 ;
assign badVAddr$EN = MUX_tlbEntryHi$write_1__SEL_3 ;
// register cause
assign cause$D_IN =
{ IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d584,
causeUpdate0$EMPTY_N ?
cause[30] :
NOT_causeUpdate1_i_notEmpty__68_70_AND_IF_caus_ETC___d588,
cause_79_BITS_29_TO_28_90_CONCAT_IF_causeUpdat_ETC___d759 } ;
assign cause$EN = 1'd1 ;
// register compare
assign compare$D_IN = dataUpdate$D_OUT[31:0] ;
assign compare$EN =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd11 ;
// register configReg0
assign configReg0$D_IN = 32'h0 ;
assign configReg0$EN = 1'b0 ;
// register configReg1
assign configReg1$D_IN = 32'h0 ;
assign configReg1$EN = 1'b0 ;
// register configReg2
assign configReg2$D_IN = 32'h0 ;
assign configReg2$EN = 1'b0 ;
// register configReg3
assign configReg3$D_IN = 31'h0 ;
assign configReg3$EN = 1'b0 ;
// register count
assign count$D_IN =
MUX_count$write_1__SEL_1 ?
MUX_count$write_1__VAL_1 :
MUX_count$write_1__VAL_1 ;
assign count$EN =
!cause[27] && !TASK_testplusargs___d779 ||
EN_putException && putException_exp[138:134] == 5'd25 &&
!putException_exp[0] &&
!cause[27] &&
TASK_testplusargs___d1294 ;
// register epc
assign epc$D_IN =
MUX_epc$write_1__SEL_1 ?
dataUpdate$D_OUT :
putException_exp[133:70] ;
assign epc$EN =
EN_putException && putException_exp[138:134] != 5'd25 &&
!putException_exp[0] ||
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d967 ;
// register errorEPC
assign errorEPC$D_IN = 64'h0 ;
assign errorEPC$EN = 1'b0 ;
// register exInterrupts
assign exInterrupts$D_IN = interrupts_interruptLines ;
assign exInterrupts$EN = EN_interrupts ;
// register llScReg
assign llScReg$D_IN =
{ NOT_llScReg_read__133_BIT_64_134_554_OR_NOT_0__ETC___d1595 &&
!eretHappened$EMPTY_N &&
(IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1972 ||
llScReg[64]),
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1972 ?
{ 28'd0,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1760 } :
llScReg[63:0] } ;
assign llScReg$EN = EN_tlbLookupData_response_get ;
// register procid
assign procid$D_IN = 32'h0 ;
assign procid$EN = 1'b0 ;
// register sr
assign sr$D_IN =
MUX_sr$write_1__SEL_1 ?
MUX_sr$write_1__VAL_1 :
MUX_sr$write_1__VAL_2 ;
assign sr$EN =
EN_putException && putException_exp[138:134] != 5'd25 &&
!putException_exp[0] ||
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d900 ;
// register tlbContext
assign tlbContext$D_IN = { v__h19352, badVAddr[31:13], 4'b0 } ;
assign tlbContext$EN = 1'd1 ;
// register tlbEntryHi
always@(MUX_tlbEntryHi$write_1__SEL_1 or
dataUpdate$D_OUT or
WILL_FIRE_RL_readTlb or
MUX_tlbEntryHi$write_1__VAL_2 or
MUX_tlbEntryHi$write_1__SEL_3 or MUX_tlbEntryHi$write_1__VAL_3)
case (1'b1)
MUX_tlbEntryHi$write_1__SEL_1: tlbEntryHi$D_IN = dataUpdate$D_OUT;
WILL_FIRE_RL_readTlb: tlbEntryHi$D_IN = MUX_tlbEntryHi$write_1__VAL_2;
MUX_tlbEntryHi$write_1__SEL_3:
tlbEntryHi$D_IN = MUX_tlbEntryHi$write_1__VAL_3;
default: tlbEntryHi$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign tlbEntryHi$EN =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d850 ||
EN_putException && !putException_exp[0] &&
(putException_exp[138:134] == 5'd2 ||
putException_exp[138:134] == 5'd3 ||
putException_exp[138:134] == 5'd4 ||
putException_exp[138:134] == 5'd5 ||
putException_exp[138:134] == 5'd6 ||
putException_exp[138:134] == 5'd7 ||
putException_exp[138:134] == 5'd1 ||
putException_exp[138:134] == 5'd8 ||
putException_exp[138:134] == 5'd9 ||
putException_exp[138:134] == 5'd10) ||
WILL_FIRE_RL_readTlb ;
// register tlbEntryLo0
assign tlbEntryLo0$D_IN =
MUX_tlbEntryLo0$write_1__SEL_1 ?
MUX_tlbEntryLo0$write_1__VAL_1 :
MUX_tlbEntryLo0$write_1__VAL_2 ;
assign tlbEntryLo0$EN =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d825 ||
WILL_FIRE_RL_readTlb ;
// register tlbEntryLo1
assign tlbEntryLo1$D_IN =
MUX_tlbEntryLo1$write_1__SEL_1 ?
MUX_tlbEntryLo0$write_1__VAL_1 :
MUX_tlbEntryLo1$write_1__VAL_2 ;
assign tlbEntryLo1$EN =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d837 ||
WILL_FIRE_RL_readTlb ;
// register tlbIndex
assign tlbIndex$D_IN =
tlb_rsp_fifos$EMPTY_N ?
MUX_tlbIndex$write_1__VAL_1 :
MUX_tlbIndex$write_1__VAL_2 ;
assign tlbIndex$EN =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d820 ||
tlb_rsp_fifos$EMPTY_N ;
// register tlbPageMask
assign tlbPageMask$D_IN =
MUX_tlbPageMask$write_1__SEL_1 ?
dataUpdate$D_OUT[11:0] :
MUX_tlbPageMask$write_1__VAL_2 ;
assign tlbPageMask$EN =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d842 ||
WILL_FIRE_RL_readTlb ;
// register tlbWired
assign tlbWired$D_IN = dataUpdate$D_OUT[2:0] ;
assign tlbWired$EN =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd6 ;
// register tlbXContext
assign tlbXContext$D_IN =
{ v__h19480, badVAddr[63:62], badVAddr[39:13], 4'b0 } ;
assign tlbXContext$EN = 1'd1 ;
// register tlb_asid
assign tlb_asid$D_IN = 8'h0 ;
assign tlb_asid$EN = 1'b0 ;
// register tlb_count
assign tlb_count$D_IN = tlb_count + 5'd1 ;
assign tlb_count$EN = tlb_tlbState == 3'd0 ;
// register tlb_entryLo0Reg
assign tlb_entryLo0Reg$D_IN = MUX_tlbEntryLo0$write_1__VAL_2 ;
assign tlb_entryLo0Reg$EN = WILL_FIRE_RL_tlb_readTLB ;
// register tlb_entryLo1Reg
assign tlb_entryLo1Reg$D_IN = MUX_tlbEntryLo1$write_1__VAL_2 ;
assign tlb_entryLo1Reg$EN = WILL_FIRE_RL_tlb_readTLB ;
// register tlb_entrySrch
assign tlb_entrySrch$D_IN =
(MUX_tlb_entrySrch$write_1__SEL_2 ||
MUX_tlb_entrySrch$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd0 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd0 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd0 ;
// register tlb_entrySrch_1
assign tlb_entrySrch_1$D_IN =
(MUX_tlb_entrySrch_1$write_1__SEL_2 ||
MUX_tlb_entrySrch_1$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch_1$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd1 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd1 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd1 ;
// register tlb_entrySrch_2
assign tlb_entrySrch_2$D_IN =
(MUX_tlb_entrySrch_2$write_1__SEL_2 ||
MUX_tlb_entrySrch_2$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch_2$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd2 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd2 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd2 ;
// register tlb_entrySrch_3
assign tlb_entrySrch_3$D_IN =
(MUX_tlb_entrySrch_3$write_1__SEL_2 ||
MUX_tlb_entrySrch_3$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch_3$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd3 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd3 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd3 ;
// register tlb_entrySrch_4
assign tlb_entrySrch_4$D_IN =
(MUX_tlb_entrySrch_4$write_1__SEL_2 ||
MUX_tlb_entrySrch_4$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch_4$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd4 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd4 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd4 ;
// register tlb_entrySrch_5
assign tlb_entrySrch_5$D_IN =
(MUX_tlb_entrySrch_5$write_1__SEL_2 ||
MUX_tlb_entrySrch_5$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch_5$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd5 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd5 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd5 ;
// register tlb_entrySrch_6
assign tlb_entrySrch_6$D_IN =
(MUX_tlb_entrySrch_6$write_1__SEL_2 ||
MUX_tlb_entrySrch_6$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch_6$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd6 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd6 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd6 ;
// register tlb_entrySrch_7
assign tlb_entrySrch_7$D_IN =
(MUX_tlb_entrySrch_7$write_1__SEL_2 ||
MUX_tlb_entrySrch_7$write_1__SEL_3) ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entrySrch_7$EN =
tlb_tlbState == 3'd0 && tlb_count[2:0] == 3'd7 ||
tlb_tlbState == 3'd4 &&
tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_readWrite_fifo$D_OUT[147:142] == 6'd7 ||
tlb_tlbState == 3'd5 && tlb_randomIndex == 3'd7 ;
// register tlb_last_hit
assign tlb_last_hit$D_IN =
MUX_tlb_last_hit$write_1__SEL_1 ?
MUX_tlb_last_hit$write_1__VAL_1 :
MUX_tlb_last_hit$write_1__VAL_2 ;
assign tlb_last_hit$EN =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd0 ||
tlb_tlbState == 3'd4 ;
// register tlb_last_hit_1
assign tlb_last_hit_1$D_IN =
MUX_tlb_last_hit_1$write_1__SEL_1 ?
MUX_tlb_last_hit$write_1__VAL_1 :
MUX_tlb_last_hit_1$write_1__VAL_2 ;
assign tlb_last_hit_1$EN =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd1 ||
tlb_tlbState == 3'd4 ;
// register tlb_last_hit_2
assign tlb_last_hit_2$D_IN =
MUX_tlb_last_hit_2$write_1__SEL_1 ?
MUX_tlb_last_hit$write_1__VAL_1 :
MUX_tlb_last_hit_2$write_1__VAL_2 ;
assign tlb_last_hit_2$EN =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd2 ||
tlb_tlbState == 3'd4 ;
// register tlb_last_hit_3
assign tlb_last_hit_3$D_IN =
MUX_tlb_last_hit_3$write_1__SEL_1 ?
MUX_tlb_last_hit$write_1__VAL_1 :
MUX_tlb_last_hit_3$write_1__VAL_2 ;
assign tlb_last_hit_3$EN =
WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
tlb_read_fifo$D_OUT[2:0] == 3'd3 ||
tlb_tlbState == 3'd4 ;
// register tlb_randomIndex
assign tlb_randomIndex$D_IN =
(tlb_randomIndex <= tlbWired) ? 3'd7 : x__h17372 ;
assign tlb_randomIndex$EN = 1'd1 ;
// register tlb_tlbState
always@(MUX_tlb_tlbState$write_1__SEL_2 or
MUX_tlb_tlbState$write_1__VAL_2 or
WILL_FIRE_RL_tlb_doRead or
MUX_tlb_tlbState$write_1__VAL_3 or
tlb_tlbState or
MUX_tlb_tlbState$write_1__VAL_4 or
MUX_tlb_tlbState$write_1__SEL_1 or MUX_tlb_tlbState$write_1__SEL_5)
begin
case (1'b1) // synopsys parallel_case
MUX_tlb_tlbState$write_1__SEL_2:
tlb_tlbState$D_IN = MUX_tlb_tlbState$write_1__VAL_2;
WILL_FIRE_RL_tlb_doRead:
tlb_tlbState$D_IN = MUX_tlb_tlbState$write_1__VAL_3;
tlb_tlbState == 3'd4:
tlb_tlbState$D_IN = MUX_tlb_tlbState$write_1__VAL_4;
MUX_tlb_tlbState$write_1__SEL_1 || MUX_tlb_tlbState$write_1__SEL_5:
tlb_tlbState$D_IN = 3'd1;
default: tlb_tlbState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign tlb_tlbState$EN =
tlb_tlbState == 3'd0 && tlb_count == 5'd31 ||
WILL_FIRE_RL_tlb_startTLB &&
(tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 ||
tlb_readWrite_fifo$EMPTY_N) ||
WILL_FIRE_RL_tlb_doRead ||
tlb_tlbState == 3'd4 ||
WILL_FIRE_RL_readTlb ||
WILL_FIRE_RL_tlb_readTLB ||
tlb_tlbState == 3'd5 ;
// register watchHi
assign watchHi$D_IN = dataUpdate$D_OUT[3:0] ;
assign watchHi$EN =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd19 ;
// register watchLo
assign watchLo$D_IN =
{ dataUpdate$D_OUT[31:3], 1'b0, dataUpdate$D_OUT[1:0] } ;
assign watchLo$EN =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd18 ;
// submodule avaddrs
assign avaddrs$D_IN =
{ tlbLookupCoprocessors_0_request_put[74:11],
tlbLookupCoprocessors_0_request_put[3:0] } ;
assign avaddrs$ENQ = EN_tlbLookupCoprocessors_0_request_put ;
assign avaddrs$DEQ =
EN_putException && avaddrs$EMPTY_N &&
avaddrs_first__198_BITS_3_TO_0_199_EQ_putExcep_ETC___d2058 ;
assign avaddrs$CLR = 1'b0 ;
// submodule causeUpdate0
assign causeUpdate0$D_IN =
{ dataUpdate$D_OUT[31:7],
CASE_dataUpdateD_OUT_BITS_6_TO_2_31_0_dataUpd_ETC__q17,
dataUpdate$D_OUT[1:0] } ;
assign causeUpdate0$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd13 ;
assign causeUpdate0$DEQ = causeUpdate0$EMPTY_N ;
assign causeUpdate0$CLR = 1'b0 ;
// submodule causeUpdate1
assign causeUpdate1$D_IN =
{ putException_exp[5],
24'd0,
CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18,
2'd0 } ;
assign causeUpdate1$ENQ = MUX_epc$write_1__SEL_2 ;
assign causeUpdate1$DEQ = !causeUpdate0$EMPTY_N && causeUpdate1$EMPTY_N ;
assign causeUpdate1$CLR = 1'b0 ;
// submodule causeUpdate2
assign causeUpdate2$D_IN =
(rnUpdate$D_OUT == 5'd11) ? x__h21478 : x__h20699 ;
assign causeUpdate2$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d877 ;
assign causeUpdate2$DEQ =
!causeUpdate0$EMPTY_N && !causeUpdate1$EMPTY_N &&
causeUpdate2$EMPTY_N ;
assign causeUpdate2$CLR = 1'b0 ;
// submodule causeUpdate3
assign causeUpdate3$D_IN = { 1'd1, cause[14:8] } ;
assign causeUpdate3$ENQ = count == compare && causeUpdate3$FULL_N ;
assign causeUpdate3$DEQ =
!causeUpdate0$EMPTY_N && !causeUpdate1$EMPTY_N &&
!causeUpdate2$EMPTY_N &&
causeUpdate3$EMPTY_N ;
assign causeUpdate3$CLR = 1'b0 ;
// submodule contxtUpdate
assign contxtUpdate$D_IN = dataUpdate$D_OUT[63:23] ;
assign contxtUpdate$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd4 ;
assign contxtUpdate$DEQ = contxtUpdate$EMPTY_N ;
assign contxtUpdate$CLR = 1'b0 ;
// submodule counterInt
assign counterInt$D_IN = 5'h0 ;
assign counterInt$ENQ = 1'b0 ;
assign counterInt$DEQ = 1'b0 ;
assign counterInt$CLR = 1'b0 ;
// submodule dataUpdate
assign dataUpdate$D_IN = writeReg_data ;
assign dataUpdate$ENQ = EN_writeReg && writeReg_writeBack ;
assign dataUpdate$DEQ = WILL_FIRE_RL_updateCP0Registers ;
assign dataUpdate$CLR = 1'b0 ;
// submodule dvaddrs
assign dvaddrs$D_IN =
{ tlbLookupData_request_put[74:11],
tlbLookupData_request_put[3:0] } ;
assign dvaddrs$ENQ = EN_tlbLookupData_request_put ;
assign dvaddrs$DEQ =
EN_putException && dvaddrs$EMPTY_N &&
dvaddrs_first__193_BITS_3_TO_0_194_EQ_putExcep_ETC___d2057 ;
assign dvaddrs$CLR = 1'b0 ;
// submodule eretHappened
assign eretHappened$D_IN = 1'd1 ;
assign eretHappened$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d1045 ;
assign eretHappened$DEQ =
EN_tlbLookupData_response_get && eretHappened$EMPTY_N ;
assign eretHappened$CLR = 1'b0 ;
// submodule eretReport
assign eretReport$D_IN = 1'd1 ;
assign eretReport$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d1046 ;
assign eretReport$DEQ = EN_getExceptionReturn ;
assign eretReport$CLR = 1'b0 ;
// submodule expectWrites
assign expectWrites$D_IN = 1'd1 ;
assign expectWrites$ENQ = EN_readGet && readGet_goingToWrite ;
assign expectWrites$DEQ = EN_writeReg ;
assign expectWrites$CLR = 1'b0 ;
// submodule forceUpdate
assign forceUpdate$D_IN = writeReg_forceKernelMode ;
assign forceUpdate$ENQ = EN_writeReg && writeReg_writeBack ;
assign forceUpdate$DEQ = WILL_FIRE_RL_updateCP0Registers ;
assign forceUpdate$CLR = 1'b0 ;
// submodule ivaddrs
assign ivaddrs$D_IN =
{ tlbLookupInstruction_request_put[74:11],
tlbLookupInstruction_request_put[3:0] } ;
assign ivaddrs$ENQ = EN_tlbLookupInstruction_request_put ;
assign ivaddrs$DEQ =
EN_putException && ivaddrs$EMPTY_N &&
ivaddrs_first__187_BITS_3_TO_0_188_EQ_putExcep_ETC___d2054 ;
assign ivaddrs$CLR = 1'b0 ;
// submodule readReqs
assign readReqs$D_IN = { readReq_rn, readReq_sel } ;
assign readReqs$ENQ = EN_readReq ;
assign readReqs$DEQ = EN_readGet ;
assign readReqs$CLR = 1'b0 ;
// submodule resetRandom
assign resetRandom$D_IN = 1'd1 ;
assign resetRandom$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd6 &&
resetRandom$FULL_N ;
assign resetRandom$DEQ = 1'b0 ;
assign resetRandom$CLR = 1'b0 ;
// submodule rnUpdate
assign rnUpdate$D_IN = writeReg_rn ;
assign rnUpdate$ENQ = EN_writeReg && writeReg_writeBack ;
assign rnUpdate$DEQ = WILL_FIRE_RL_updateCP0Registers ;
assign rnUpdate$CLR = 1'b0 ;
// submodule tlbProbeResponses
assign tlbProbeResponses$D_IN = 1'd1 ;
assign tlbProbeResponses$ENQ =
tlb_tlbState == 3'd1 && !tlb_req_fifos$EMPTY_N &&
tlbProbes$EMPTY_N ;
assign tlbProbeResponses$DEQ = tlb_rsp_fifos$EMPTY_N ;
assign tlbProbeResponses$CLR = 1'b0 ;
// submodule tlbProbes
assign tlbProbes$D_IN = { tlbEntryHi[63:13], 13'b0 } ;
assign tlbProbes$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd31 &&
dataUpdate$D_OUT[5:0] == 6'd8 ;
assign tlbProbes$DEQ =
tlb_tlbState == 3'd1 && !tlb_req_fifos$EMPTY_N &&
tlbProbes$EMPTY_N ;
assign tlbProbes$CLR = 1'b0 ;
// submodule tlbReads
assign tlbReads$D_IN = 1'd1 ;
assign tlbReads$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd31 &&
dataUpdate$D_OUT[5:0] == 6'd1 ;
assign tlbReads$DEQ = WILL_FIRE_RL_readTlb ;
assign tlbReads$CLR = 1'b0 ;
// submodule tlb_entryHiHash
assign tlb_entryHiHash$ADDRA =
MUX_tlb_entryHiHash$a_put_1__SEL_1 ?
_theResult____h7635 :
hashKey__h14215 ;
assign tlb_entryHiHash$ADDRB =
MUX_tlb_entryHiHash$b_put_1__SEL_1 ?
hashKey___1__h7990 :
tlb_count ;
assign tlb_entryHiHash$DIA =
MUX_tlb_entryHiHash$a_put_1__SEL_1 ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign tlb_entryHiHash$DIB =
MUX_tlb_entryHiHash$b_put_1__SEL_1 ?
tlb_readWrite_fifo$D_OUT[141:64] :
78'h2AAAAAAAAAAAAAAA8AAA ;
assign tlb_entryHiHash$WEA = 1'd0 ;
assign tlb_entryHiHash$WEB = 1'd1 ;
assign tlb_entryHiHash$ENA =
WILL_FIRE_RL_tlb_doRead &&
!tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 ||
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 ;
assign tlb_entryHiHash$ENB =
tlb_tlbState == 3'd4 &&
!tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 ||
tlb_tlbState == 3'd0 ;
// submodule tlb_entryLo0
assign tlb_entryLo0$ADDRA =
MUX_tlb_entryHiHash$a_put_1__SEL_2 ?
MUX_tlb_entryLo0$a_put_2__VAL_1 :
MUX_tlb_entryLo0$a_put_2__VAL_2 ;
assign tlb_entryLo0$ADDRB =
(tlb_tlbState == 3'd5) ?
MUX_tlb_entryLo0$b_put_2__VAL_1 :
MUX_tlb_entryLo0$b_put_2__VAL_2 ;
assign tlb_entryLo0$DIA =
MUX_tlb_entryHiHash$a_put_1__SEL_2 ?
32'hAAAAAAAA /* unspecified value */ :
MUX_tlb_entryLo0$a_put_3__VAL_2 ;
assign tlb_entryLo0$DIB =
(tlb_tlbState == 3'd5) ?
MUX_tlb_entryLo0$a_put_3__VAL_2 :
MUX_tlb_entryLo0$a_put_3__VAL_2 ;
assign tlb_entryLo0$WEA = 1'd0 ;
assign tlb_entryLo0$WEB = 1'd1 ;
assign tlb_entryLo0$ENA =
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 ||
WILL_FIRE_RL_tlb_doRead ;
assign tlb_entryLo0$ENB = tlb_tlbState == 3'd5 || tlb_tlbState == 3'd4 ;
// submodule tlb_entryLo1
assign tlb_entryLo1$ADDRA =
MUX_tlb_entryHiHash$a_put_1__SEL_2 ?
MUX_tlb_entryLo0$a_put_2__VAL_1 :
MUX_tlb_entryLo0$a_put_2__VAL_2 ;
assign tlb_entryLo1$ADDRB =
(tlb_tlbState == 3'd5) ?
MUX_tlb_entryLo0$b_put_2__VAL_1 :
MUX_tlb_entryLo0$b_put_2__VAL_2 ;
assign tlb_entryLo1$DIA =
MUX_tlb_entryHiHash$a_put_1__SEL_2 ?
32'hAAAAAAAA /* unspecified value */ :
MUX_tlb_entryLo1$a_put_3__VAL_2 ;
assign tlb_entryLo1$DIB =
(tlb_tlbState == 3'd5) ?
MUX_tlb_entryLo1$a_put_3__VAL_2 :
MUX_tlb_entryLo1$a_put_3__VAL_2 ;
assign tlb_entryLo1$WEA = 1'd0 ;
assign tlb_entryLo1$WEB = 1'd1 ;
assign tlb_entryLo1$ENA =
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 ||
WILL_FIRE_RL_tlb_doRead ;
assign tlb_entryLo1$ENB = tlb_tlbState == 3'd5 || tlb_tlbState == 3'd4 ;
// submodule tlb_readOut_fifo
assign tlb_readOut_fifo$D_IN = MUX_tlb_entryLo0$a_put_2__VAL_2 ;
assign tlb_readOut_fifo$ENQ =
WILL_FIRE_RL_tlb_doRead && !tlb_readWrite_fifo$D_OUT[149] ;
assign tlb_readOut_fifo$DEQ = WILL_FIRE_RL_readTlb ;
assign tlb_readOut_fifo$CLR = 1'b0 ;
// submodule tlb_readWrite_fifo
assign tlb_readWrite_fifo$D_IN =
MUX_tlb_readWrite_fifo$enq_1__SEL_1 ?
MUX_tlb_readWrite_fifo$enq_1__VAL_1 :
MUX_tlb_readWrite_fifo$enq_1__VAL_2 ;
assign tlb_readWrite_fifo$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d989 ||
tlb_tlbState == 3'd4 &&
!tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 &&
tlb_entryHiHash$DOA[13] &&
tlb_readWrite_fifo$D_OUT[148] ;
assign tlb_readWrite_fifo$DEQ =
WILL_FIRE_RL_tlb_doRead && !tlb_readWrite_fifo$D_OUT[149] ||
tlb_tlbState == 3'd5 ||
tlb_tlbState == 3'd4 ;
assign tlb_readWrite_fifo$CLR = 1'b0 ;
// submodule tlb_read_fifo
assign tlb_read_fifo$D_IN =
{ tlb_entrySrch_7_02_BIT_13_03_AND_tlb_entrySrch_ETC___d1921 ||
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1950,
x2__h14355,
CASE_requestSource___11175_tlb_req_fifos_3D_O_ETC__q19,
requestSource___1__h11175 } ;
assign tlb_read_fifo$ENQ = MUX_tlb_entryHiHash$a_put_1__SEL_2 ;
assign tlb_read_fifo$DEQ = WILL_FIRE_RL_tlb_readTLB ;
assign tlb_read_fifo$CLR = 1'b0 ;
// submodule tlb_req_fifos
assign tlb_req_fifos$D_IN = { tlbProbes$D_OUT, 11'd400 } ;
assign tlb_req_fifos$ENQ =
tlb_tlbState == 3'd1 && !tlb_req_fifos$EMPTY_N &&
tlbProbes$EMPTY_N ;
assign tlb_req_fifos$DEQ =
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
requestSource___1__h11175 == 3'd0 ;
assign tlb_req_fifos$CLR = 1'b0 ;
// submodule tlb_req_fifos_1
assign tlb_req_fifos_1$D_IN = tlbLookupInstruction_request_put ;
assign tlb_req_fifos_1$ENQ =
EN_tlbLookupInstruction_request_put &&
tlbLookupInstruction_request_put[74:67] != 8'h98 &&
tlbLookupInstruction_request_put[74:67] != 8'h90 &&
tlbLookupInstruction_request_put[74:67] != 8'hA0 &&
tlbLookupInstruction_request_put[74:67] != 8'hA8 &&
tlbLookupInstruction_request_put[74:67] != 8'hB0 &&
tlbLookupInstruction_request_put[8:4] == 5'd25 &&
NOT_tlbLookupInstruction_request_put_BITS_74_T_ETC___d1405 ;
assign tlb_req_fifos_1$DEQ =
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
requestSource___1__h11175 == 3'd1 ;
assign tlb_req_fifos_1$CLR = 1'b0 ;
// submodule tlb_req_fifos_2
assign tlb_req_fifos_2$D_IN = tlbLookupData_request_put ;
assign tlb_req_fifos_2$ENQ =
EN_tlbLookupData_request_put &&
tlbLookupData_request_put[74:67] != 8'h98 &&
tlbLookupData_request_put[74:67] != 8'h90 &&
tlbLookupData_request_put[74:67] != 8'hA0 &&
tlbLookupData_request_put[74:67] != 8'hA8 &&
tlbLookupData_request_put[74:67] != 8'hB0 &&
tlbLookupData_request_put[8:4] == 5'd25 &&
NOT_tlbLookupData_request_put_BITS_74_TO_43_45_ETC___d1547 ;
assign tlb_req_fifos_2$DEQ =
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
requestSource___1__h11175 == 3'd2 ;
assign tlb_req_fifos_2$CLR = 1'b0 ;
// submodule tlb_req_fifos_3
assign tlb_req_fifos_3$D_IN = tlbLookupCoprocessors_0_request_put ;
assign tlb_req_fifos_3$ENQ =
EN_tlbLookupCoprocessors_0_request_put &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'h98 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'h90 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hA0 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hA8 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hB0 &&
tlbLookupCoprocessors_0_request_put[8:4] == 5'd25 &&
NOT_tlbLookupCoprocessors_0_request_put_BITS_7_ETC___d1720 ;
assign tlb_req_fifos_3$DEQ =
WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
requestSource___1__h11175 == 3'd3 ;
assign tlb_req_fifos_3$CLR = 1'b0 ;
// submodule tlb_rsp_fifos
assign tlb_rsp_fifos$D_IN =
{ _theResult_____5__h15306,
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845,
tlb_read_fifo_first__52_BITS_13_TO_12_16_CONCA_ETC___d427 } ;
assign tlb_rsp_fifos$ENQ =
WILL_FIRE_RL_tlb_readTLB && tlb_read_fifo$D_OUT[2:0] == 3'd0 ;
assign tlb_rsp_fifos$DEQ = tlb_rsp_fifos$EMPTY_N ;
assign tlb_rsp_fifos$CLR = 1'b0 ;
// submodule tlb_rsp_fifos_1
assign tlb_rsp_fifos_1$D_IN = tlb_rsp_fifos$D_IN ;
assign tlb_rsp_fifos_1$ENQ =
WILL_FIRE_RL_tlb_readTLB && tlb_read_fifo$D_OUT[2:0] == 3'd1 ;
assign tlb_rsp_fifos_1$DEQ =
EN_tlbLookupInstruction_response_get &&
!tlb_smt_fifos_1$EMPTY_N ;
assign tlb_rsp_fifos_1$CLR = 1'b0 ;
// submodule tlb_rsp_fifos_2
assign tlb_rsp_fifos_2$D_IN = tlb_rsp_fifos$D_IN ;
assign tlb_rsp_fifos_2$ENQ =
WILL_FIRE_RL_tlb_readTLB && tlb_read_fifo$D_OUT[2:0] == 3'd2 ;
assign tlb_rsp_fifos_2$DEQ =
EN_tlbLookupData_response_get && !tlb_smt_fifos_2$EMPTY_N ;
assign tlb_rsp_fifos_2$CLR = 1'b0 ;
// submodule tlb_rsp_fifos_3
assign tlb_rsp_fifos_3$D_IN = tlb_rsp_fifos$D_IN ;
assign tlb_rsp_fifos_3$ENQ =
WILL_FIRE_RL_tlb_readTLB && tlb_read_fifo$D_OUT[2:0] == 3'd3 ;
assign tlb_rsp_fifos_3$DEQ =
EN_tlbLookupCoprocessors_0_response_get &&
!tlb_smt_fifos_3$EMPTY_N ;
assign tlb_rsp_fifos_3$CLR = 1'b0 ;
// submodule tlb_smt_fifos
assign tlb_smt_fifos$D_IN = 50'h0 ;
assign tlb_smt_fifos$ENQ = 1'b0 ;
assign tlb_smt_fifos$DEQ = 1'b0 ;
assign tlb_smt_fifos$CLR = 1'b0 ;
// submodule tlb_smt_fifos_1
assign tlb_smt_fifos_1$D_IN =
{ (tlbLookupInstruction_request_put[74:67] == 8'h98 ||
tlbLookupInstruction_request_put[74:67] == 8'h90 ||
tlbLookupInstruction_request_put[74:67] == 8'hA0 ||
tlbLookupInstruction_request_put[74:67] == 8'hA8 ||
tlbLookupInstruction_request_put[74:67] == 8'hB0 ||
tlbLookupInstruction_request_put[8:4] != 5'd25) ?
tlbLookupInstruction_request_put[46:11] :
IF_tlbLookupInstruction_request_put_BITS_74_TO_ETC___d1345,
(tlbLookupInstruction_request_put[74:67] == 8'h98 ||
tlbLookupInstruction_request_put[74:67] == 8'h90 ||
tlbLookupInstruction_request_put[74:67] == 8'hA0 ||
tlbLookupInstruction_request_put[74:67] == 8'hA8 ||
tlbLookupInstruction_request_put[74:67] == 8'hB0 ||
tlbLookupInstruction_request_put[8:4] != 5'd25 ||
tlbLookupInstruction_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupInstruction_request_put[42:40] == 3'b100 ||
tlbLookupInstruction_request_put[42:40] == 3'b101)) ?
5'd25 :
((IF_tlbLookupInstruction_request_put_BITS_8_TO__ETC___d2060 ==
5'd25 &&
tlbLookupInstruction_request_put[10] &&
!tlb_last_hit_1[2]) ?
5'd1 :
IF_tlbLookupInstruction_request_put_BITS_8_TO__ETC___d2060),
tlbLookupInstruction_request_put[10:9],
(tlbLookupInstruction_request_put[74:67] == 8'h98 ||
tlbLookupInstruction_request_put[74:67] == 8'h90 ||
tlbLookupInstruction_request_put[74:67] == 8'hA0 ||
tlbLookupInstruction_request_put[74:67] == 8'hA8 ||
tlbLookupInstruction_request_put[74:67] == 8'hB0 ||
tlbLookupInstruction_request_put[8:4] != 5'd25 ||
tlbLookupInstruction_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupInstruction_request_put[42:40] == 3'b100 ||
tlbLookupInstruction_request_put[42:40] == 3'b101)) ?
tlbLookupInstruction_request_put[74:67] != 8'h90 &&
(tlbLookupInstruction_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupInstruction_request_put[42:40] != 3'b101) :
tlb_last_hit_1[5:3] != 3'd2,
(tlbLookupInstruction_request_put[74:67] == 8'h98 ||
tlbLookupInstruction_request_put[74:67] == 8'h90 ||
tlbLookupInstruction_request_put[74:67] == 8'hA0 ||
tlbLookupInstruction_request_put[74:67] == 8'hA8 ||
tlbLookupInstruction_request_put[74:67] == 8'hB0 ||
tlbLookupInstruction_request_put[8:4] != 5'd25 ||
tlbLookupInstruction_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupInstruction_request_put[42:40] == 3'b100 ||
tlbLookupInstruction_request_put[42:40] == 3'b101)) ?
2'd2 :
((tlbLookupInstruction_request_put[74:71] < 4'h8) ?
((tlbLookupInstruction_request_put[74:71] < 4'h4) ?
2'd0 :
2'd1) :
2'd2),
tlbLookupInstruction_request_put[3:0] } ;
assign tlb_smt_fifos_1$ENQ =
EN_tlbLookupInstruction_request_put &&
(tlbLookupInstruction_request_put[74:67] == 8'h98 ||
tlbLookupInstruction_request_put[74:67] == 8'h90 ||
tlbLookupInstruction_request_put[74:67] == 8'hA0 ||
tlbLookupInstruction_request_put[74:67] == 8'hA8 ||
tlbLookupInstruction_request_put[74:67] == 8'hB0 ||
tlbLookupInstruction_request_put[8:4] != 5'd25 ||
tlbLookupInstruction_request_put_BITS_74_TO_43_ETC___d1337) ;
assign tlb_smt_fifos_1$DEQ =
EN_tlbLookupInstruction_response_get && tlb_smt_fifos_1$EMPTY_N ;
assign tlb_smt_fifos_1$CLR = 1'b0 ;
// submodule tlb_smt_fifos_2
assign tlb_smt_fifos_2$D_IN =
{ (tlbLookupData_request_put[74:67] == 8'h98 ||
tlbLookupData_request_put[74:67] == 8'h90 ||
tlbLookupData_request_put[74:67] == 8'hA0 ||
tlbLookupData_request_put[74:67] == 8'hA8 ||
tlbLookupData_request_put[74:67] == 8'hB0 ||
tlbLookupData_request_put[8:4] != 5'd25) ?
tlbLookupData_request_put[46:11] :
IF_tlbLookupData_request_put_BITS_74_TO_43_459_ETC___d1486,
(tlbLookupData_request_put[74:67] == 8'h98 ||
tlbLookupData_request_put[74:67] == 8'h90 ||
tlbLookupData_request_put[74:67] == 8'hA0 ||
tlbLookupData_request_put[74:67] == 8'hA8 ||
tlbLookupData_request_put[74:67] == 8'hB0 ||
tlbLookupData_request_put[8:4] != 5'd25 ||
tlbLookupData_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupData_request_put[42:40] == 3'b100 ||
tlbLookupData_request_put[42:40] == 3'b101)) ?
5'd25 :
((IF_tlbLookupData_request_put_BITS_8_TO_4_455_E_ETC___d2066 ==
5'd25 &&
tlbLookupData_request_put[10] &&
!tlb_last_hit_2[2]) ?
5'd1 :
IF_tlbLookupData_request_put_BITS_8_TO_4_455_E_ETC___d2066),
tlbLookupData_request_put[10:9],
(tlbLookupData_request_put[74:67] == 8'h98 ||
tlbLookupData_request_put[74:67] == 8'h90 ||
tlbLookupData_request_put[74:67] == 8'hA0 ||
tlbLookupData_request_put[74:67] == 8'hA8 ||
tlbLookupData_request_put[74:67] == 8'hB0 ||
tlbLookupData_request_put[8:4] != 5'd25 ||
tlbLookupData_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupData_request_put[42:40] == 3'b100 ||
tlbLookupData_request_put[42:40] == 3'b101)) ?
tlbLookupData_request_put[74:67] != 8'h90 &&
(tlbLookupData_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupData_request_put[42:40] != 3'b101) :
tlb_last_hit_2[5:3] != 3'd2,
(tlbLookupData_request_put[74:67] == 8'h98 ||
tlbLookupData_request_put[74:67] == 8'h90 ||
tlbLookupData_request_put[74:67] == 8'hA0 ||
tlbLookupData_request_put[74:67] == 8'hA8 ||
tlbLookupData_request_put[74:67] == 8'hB0 ||
tlbLookupData_request_put[8:4] != 5'd25 ||
tlbLookupData_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupData_request_put[42:40] == 3'b100 ||
tlbLookupData_request_put[42:40] == 3'b101)) ?
2'd2 :
((tlbLookupData_request_put[74:71] < 4'h8) ?
((tlbLookupData_request_put[74:71] < 4'h4) ?
2'd0 :
2'd1) :
2'd2),
tlbLookupData_request_put[3:0] } ;
assign tlb_smt_fifos_2$ENQ =
EN_tlbLookupData_request_put &&
(tlbLookupData_request_put[74:67] == 8'h98 ||
tlbLookupData_request_put[74:67] == 8'h90 ||
tlbLookupData_request_put[74:67] == 8'hA0 ||
tlbLookupData_request_put[74:67] == 8'hA8 ||
tlbLookupData_request_put[74:67] == 8'hB0 ||
tlbLookupData_request_put[8:4] != 5'd25 ||
tlbLookupData_request_put_BITS_74_TO_43_459_EQ_ETC___d1478) ;
assign tlb_smt_fifos_2$DEQ =
EN_tlbLookupData_response_get && tlb_smt_fifos_2$EMPTY_N ;
assign tlb_smt_fifos_2$CLR = 1'b0 ;
// submodule tlb_smt_fifos_3
assign tlb_smt_fifos_3$D_IN =
{ (tlbLookupCoprocessors_0_request_put[74:67] == 8'h98 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'h90 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA0 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA8 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hB0 ||
tlbLookupCoprocessors_0_request_put[8:4] != 5'd25) ?
tlbLookupCoprocessors_0_request_put[46:11] :
IF_tlbLookupCoprocessors_0_request_put_BITS_74_ETC___d1659,
(tlbLookupCoprocessors_0_request_put[74:67] == 8'h98 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'h90 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA0 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA8 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hB0 ||
tlbLookupCoprocessors_0_request_put[8:4] != 5'd25 ||
tlbLookupCoprocessors_0_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupCoprocessors_0_request_put[42:40] == 3'b100 ||
tlbLookupCoprocessors_0_request_put[42:40] == 3'b101)) ?
5'd25 :
((IF_tlbLookupCoprocessors_0_request_put_BITS_8__ETC___d2072 ==
5'd25 &&
tlbLookupCoprocessors_0_request_put[10] &&
!tlb_last_hit_3[2]) ?
5'd1 :
IF_tlbLookupCoprocessors_0_request_put_BITS_8__ETC___d2072),
tlbLookupCoprocessors_0_request_put[10:9],
(tlbLookupCoprocessors_0_request_put[74:67] == 8'h98 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'h90 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA0 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA8 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hB0 ||
tlbLookupCoprocessors_0_request_put[8:4] != 5'd25 ||
tlbLookupCoprocessors_0_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupCoprocessors_0_request_put[42:40] == 3'b100 ||
tlbLookupCoprocessors_0_request_put[42:40] == 3'b101)) ?
tlbLookupCoprocessors_0_request_put[74:67] != 8'h90 &&
(tlbLookupCoprocessors_0_request_put[74:43] !=
32'hFFFFFFFF ||
tlbLookupCoprocessors_0_request_put[42:40] != 3'b101) :
tlb_last_hit_3[5:3] != 3'd2,
(tlbLookupCoprocessors_0_request_put[74:67] == 8'h98 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'h90 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA0 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA8 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hB0 ||
tlbLookupCoprocessors_0_request_put[8:4] != 5'd25 ||
tlbLookupCoprocessors_0_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupCoprocessors_0_request_put[42:40] == 3'b100 ||
tlbLookupCoprocessors_0_request_put[42:40] == 3'b101)) ?
2'd2 :
((tlbLookupCoprocessors_0_request_put[74:71] < 4'h8) ?
((tlbLookupCoprocessors_0_request_put[74:71] < 4'h4) ?
2'd0 :
2'd1) :
2'd2),
tlbLookupCoprocessors_0_request_put[3:0] } ;
assign tlb_smt_fifos_3$ENQ =
EN_tlbLookupCoprocessors_0_request_put &&
(tlbLookupCoprocessors_0_request_put[74:67] == 8'h98 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'h90 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA0 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hA8 ||
tlbLookupCoprocessors_0_request_put[74:67] == 8'hB0 ||
tlbLookupCoprocessors_0_request_put[8:4] != 5'd25 ||
tlbLookupCoprocessors_0_request_put_BITS_74_TO_ETC___d1651) ;
assign tlb_smt_fifos_3$DEQ =
EN_tlbLookupCoprocessors_0_response_get &&
tlb_smt_fifos_3$EMPTY_N ;
assign tlb_smt_fifos_3$CLR = 1'b0 ;
// submodule xcntxtUpdate
assign xcntxtUpdate$D_IN = dataUpdate$D_OUT[63:33] ;
assign xcntxtUpdate$ENQ =
WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd20 ;
assign xcntxtUpdate$DEQ = xcntxtUpdate$EMPTY_N ;
assign xcntxtUpdate$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 =
IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_ETC___d414 ?
5'd1 :
IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_ETC___d2015 ;
assign IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_ETC___d2015 =
IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_AN_ETC___d403 ?
((tlb_read_fifo$D_OUT[2:0] == 3'd1) ?
5'd3 :
(tlb_read_fifo$D_OUT[13] ? 5'd7 : 5'd6)) :
IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_AN_ETC___d2014 ;
assign IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_ETC___d414 =
IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_ETC___d2015 ==
5'd25 &&
tlb_read_fifo$D_OUT[13] &&
(tlb_read_fifo$D_OUT[26] ?
!tlb_entryLo1$DOA[2] :
!tlb_entryLo0$DOA[2]) ;
assign IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d481 =
(tlb_read_fifo$D_OUT[26] ?
tlb_entryLo1$DOA[5:3] == 3'd3 :
tlb_entryLo0$DOA[5:3] == 3'd3) ?
3'd3 :
3'd4 ;
assign IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d482 =
(tlb_read_fifo$D_OUT[26] ?
tlb_entryLo1$DOA[5:3] == 3'd2 :
tlb_entryLo0$DOA[5:3] == 3'd2) ?
3'd2 :
IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d481 ;
assign IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d483 =
(tlb_read_fifo$D_OUT[26] ?
tlb_entryLo1$DOA[5:3] == 3'd0 :
tlb_entryLo0$DOA[5:3] == 3'd0) ?
3'd0 :
IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d482 ;
assign IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d485 =
{ IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d483,
tlb_read_fifo$D_OUT[26] ?
tlb_entryLo1$DOA[2:0] :
tlb_entryLo0$DOA[2:0] } ;
assign IF_IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_ETC___d1436 =
(IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2063 ==
2'd2 ||
IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2063 ==
2'd1 &&
sr[4:3] != 2'd1) ?
5'd8 :
IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2099 ;
assign IF_IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_ETC___d1588 =
(IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2069 ==
2'd2 ||
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2069 ==
2'd1 &&
sr[4:3] != 2'd1) ?
(IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1931 ?
5'd10 :
5'd9) :
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2102 ;
assign IF_IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_ETC___d1862 =
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1576 ?
((IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2070 ==
5'd25) ?
5'd23 :
IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2070) :
IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2070 ;
assign IF_IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_ETC___d1745 =
(tlb_smt_fifos_3$EMPTY_N ?
tlb_smt_fifos_3$D_OUT[8] :
tlb_rsp_fifos_3$D_OUT[8]) ?
5'd10 :
5'd9 ;
assign IF_IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_ETC___d1749 =
(IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2075 ==
2'd2 ||
IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2075 ==
2'd1 &&
sr[4:3] != 2'd1) ?
IF_IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_ETC___d1745 :
IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2103 ;
assign IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2064 =
(sr[4:3] != 2'd0 && !sr[1]) ?
IF_IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_ETC___d1436 :
IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2099 ;
assign IF_NOT_sr_read__09_BITS_4_TO_3_10_EQ_0_11_422__ETC___d2070 =
(sr[4:3] != 2'd0 && !sr[1]) ?
IF_IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_ETC___d1588 :
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2102 ;
assign IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_AN_ETC___d2014 =
(NOT_tlb_read_fifo_first__52_BIT_84_55_80_AND_N_ETC___d388 &&
tlb_read_fifo$D_OUT[11:7] == 5'd25) ?
((tlb_read_fifo$D_OUT[2:0] == 3'd1) ?
5'd2 :
(tlb_read_fifo$D_OUT[13] ? 5'd5 : 5'd4)) :
tlb_read_fifo$D_OUT[11:7] ;
assign IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_AN_ETC___d403 =
IF_NOT_tlb_read_fifo_first__52_BIT_84_55_80_AN_ETC___d2014 ==
5'd25 &&
(tlb_read_fifo$D_OUT[26] ?
!tlb_entryLo1$DOA[1] :
!tlb_entryLo0$DOA[1]) ;
assign IF_causeUpdate0_i_notEmpty__66_THEN_IF_cause_7_ETC___d2048 =
causeUpdate0$EMPTY_N ?
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 :
IF_causeUpdate1_i_notEmpty__68_THEN_IF_causeUp_ETC___d708 ;
assign IF_causeUpdate0_i_notEmpty__66_THEN_causeUpdat_ETC___d757 =
{ causeUpdate0$EMPTY_N ? causeUpdate0$D_OUT[22] : cause[22],
cause[21:16],
IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d756 } ;
assign IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d2124 =
causeUpdate0$EMPTY_N ?
y_avValue_ip__h18238 :
x1_avValue_ip__h18517 ;
assign IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d584 =
causeUpdate0$EMPTY_N ?
cause[31] :
(causeUpdate1$EMPTY_N ? causeUpdate1$D_OUT[31] : cause[31]) ;
assign IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d756 =
{ x_ip__h18557,
cause[7],
CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4,
cause[1:0] } ;
assign IF_causeUpdate1_i_notEmpty__68_THEN_IF_causeUp_ETC___d708 =
causeUpdate1$EMPTY_N ?
CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 :
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 ;
assign IF_dataUpdate_first__21_BITS_5_TO_0_22_EQ_1_80_ETC___d1031 =
{ tlbEntryHi,
13'd4096,
tlbEntryLo0[0] && tlbEntryLo1[0],
tlbEntryLo0[31:6],
IF_tlbEntryLo0_read__000_BITS_5_TO_3_007_EQ_0__ETC___d2143,
tlbEntryLo0[2:0],
tlbEntryLo1[31:6],
IF_tlbEntryLo1_read__002_BITS_5_TO_3_017_EQ_0__ETC___d2145,
tlbEntryLo1[2:0] } ;
assign IF_tlbLookupCoprocessors_0_request_put_BITS_74_ETC___d1659 =
(tlbLookupCoprocessors_0_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupCoprocessors_0_request_put[42:40] == 3'b100 ||
tlbLookupCoprocessors_0_request_put[42:40] == 3'b101)) ?
x_addr__h30846 :
addr__h30356 ;
assign IF_tlbLookupCoprocessors_0_request_put_BITS_8__ETC___d2072 =
(tlbLookupCoprocessors_0_request_put[8:4] == 5'd25 &&
!tlb_last_hit_3[1]) ?
(tlbLookupCoprocessors_0_request_put[10] ? 5'd7 : 5'd6) :
tlbLookupCoprocessors_0_request_put[8:4] ;
assign IF_tlbLookupData_request_put_BITS_74_TO_43_459_ETC___d1486 =
(tlbLookupData_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupData_request_put[42:40] == 3'b100 ||
tlbLookupData_request_put[42:40] == 3'b101)) ?
x_addr__h28759 :
addr__h28269 ;
assign IF_tlbLookupData_request_put_BITS_8_TO_4_455_E_ETC___d2066 =
(tlbLookupData_request_put[8:4] == 5'd25 && !tlb_last_hit_2[1]) ?
(tlbLookupData_request_put[10] ? 5'd7 : 5'd6) :
tlbLookupData_request_put[8:4] ;
assign IF_tlbLookupInstruction_request_put_BITS_74_TO_ETC___d1345 =
(tlbLookupInstruction_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupInstruction_request_put[42:40] == 3'b100 ||
tlbLookupInstruction_request_put[42:40] == 3'b101)) ?
x_addr__h27037 :
addr__h26547 ;
assign IF_tlbLookupInstruction_request_put_BITS_8_TO__ETC___d2060 =
(tlbLookupInstruction_request_put[8:4] == 5'd25 &&
!tlb_last_hit_1[1]) ?
5'd3 :
tlbLookupInstruction_request_put[8:4] ;
assign IF_tlb_entryHiHash_a_read__5_BIT_13_6_AND_tlb__ETC___d449 =
(tlb_entryHiHash$DOA[13] &&
tlb_entryHiHash_a_read__5_BITS_77_TO_27_57_EQ__ETC___d2121 &&
(tlb_entryHiHash_a_read__5_BITS_21_TO_14_61_EQ__ETC___d2122 ||
tlb_entryHiHash$DOA[0])) ?
tlb_entryHiHash$DOA[0] :
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 ;
assign IF_tlb_entryHiHash_a_read__5_BIT_13_6_AND_tlb__ETC___d473 =
(tlb_entryHiHash$DOA[13] &&
tlb_entryHiHash_a_read__5_BITS_77_TO_27_57_EQ__ETC___d2121 &&
(tlb_entryHiHash_a_read__5_BITS_21_TO_14_61_EQ__ETC___d2122 ||
tlb_entryHiHash$DOA[0])) ?
tlb_entryHiHash$DOA[77:14] :
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 ;
assign IF_tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entryS_ETC___d1769 =
tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entrySrch_ETC___d1909 ?
3'd1 :
3'd0 ;
assign IF_tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entryS_ETC___d1770 =
tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entrySrch_ETC___d1911 ?
3'd2 :
IF_tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entryS_ETC___d1769 ;
assign IF_tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entryS_ETC___d1771 =
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1913 ?
3'd3 :
IF_tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entryS_ETC___d1770 ;
assign IF_tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entryS_ETC___d1772 =
tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entrySrch_ETC___d1915 ?
3'd4 :
IF_tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entryS_ETC___d1771 ;
assign IF_tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entryS_ETC___d1773 =
tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entrySrch_ETC___d1917 ?
3'd5 :
IF_tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entryS_ETC___d1772 ;
assign IF_tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entryS_ETC___d1774 =
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1919 ?
3'd6 :
IF_tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entryS_ETC___d1773 ;
assign IF_tlb_read_fifo_first__52_BIT_84_55_THEN_IF_t_ETC___d487 =
{ tlb_read_fifo$D_OUT[84] ?
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 :
IF_tlb_entryHiHash_a_read__5_BIT_13_6_AND_tlb__ETC___d449,
tlb_read_fifo$D_OUT[84] ?
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 :
IF_tlb_entryHiHash_a_read__5_BIT_13_6_AND_tlb__ETC___d473,
_theResult___zeros__h15801,
_theResult___pfn__h15802,
IF_IF_tlb_read_fifo_first__52_BIT_26_73_THEN_t_ETC___d485 } ;
assign IF_tlb_req_fifos_1_i_notEmpty__69_AND_NOT_tlb__ETC___d1766 =
(tlb_req_fifos_1$EMPTY_N && !tlb_req_fifos$EMPTY_N) ?
tlb_req_fifos_1$D_OUT[74:11] :
tlb_req_fifos$D_OUT[74:11] ;
assign IF_tlb_req_fifos_2_i_notEmpty__70_AND_NOT_tlb__ETC___d1767 =
(tlb_req_fifos_2$EMPTY_N && !tlb_req_fifos_1$EMPTY_N &&
!tlb_req_fifos$EMPTY_N) ?
3'd2 :
((tlb_req_fifos_1$EMPTY_N && !tlb_req_fifos$EMPTY_N) ?
3'd1 :
3'd0) ;
assign IF_tlb_req_fifos_2_i_notEmpty__70_AND_NOT_tlb__ETC___d1776 =
(tlb_req_fifos_2$EMPTY_N && !tlb_req_fifos_1$EMPTY_N &&
!tlb_req_fifos$EMPTY_N) ?
tlb_req_fifos_2$D_OUT[74:11] :
IF_tlb_req_fifos_1_i_notEmpty__69_AND_NOT_tlb__ETC___d1766 ;
assign IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759 =
tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb_req_ETC___d1756 ?
tlb_req_fifos_3$D_OUT[74:11] :
IF_tlb_req_fifos_2_i_notEmpty__70_AND_NOT_tlb__ETC___d1776 ;
assign IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d1761 =
tlb_smt_fifos_1$EMPTY_N ?
tlb_smt_fifos_1$D_OUT[49:14] :
tlb_rsp_fifos_1$D_OUT[49:14] ;
assign IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2063 =
tlb_smt_fifos_1$EMPTY_N ?
tlb_smt_fifos_1$D_OUT[5:4] :
tlb_rsp_fifos_1$D_OUT[5:4] ;
assign IF_tlb_smt_fifos_1_i_notEmpty__410_THEN_tlb_sm_ETC___d2099 =
tlb_smt_fifos_1$EMPTY_N ?
tlb_smt_fifos_1$D_OUT[13:9] :
tlb_rsp_fifos_1$D_OUT[13:9] ;
assign IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_NOT_tl_ETC___d2125 =
tlb_smt_fifos_2$EMPTY_N ?
!tlb_smt_fifos_2$D_OUT[8] :
!tlb_rsp_fifos_2$D_OUT[8] ;
assign IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1576 =
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1760 ==
{ watchHi, watchLo[31:3], 3'b0 } &&
(watchLo[1] &&
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_NOT_tl_ETC___d2125 ||
watchLo[0] &&
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1931) ;
assign IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1760 =
tlb_smt_fifos_2$EMPTY_N ?
tlb_smt_fifos_2$D_OUT[49:14] :
tlb_rsp_fifos_2$D_OUT[49:14] ;
assign IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1931 =
tlb_smt_fifos_2$EMPTY_N ?
tlb_smt_fifos_2$D_OUT[8] :
tlb_rsp_fifos_2$D_OUT[8] ;
assign IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1972 =
tlb_smt_fifos_2$EMPTY_N ?
tlb_smt_fifos_2$D_OUT[7] :
tlb_rsp_fifos_2$D_OUT[7] ;
assign IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2069 =
tlb_smt_fifos_2$EMPTY_N ?
tlb_smt_fifos_2$D_OUT[5:4] :
tlb_rsp_fifos_2$D_OUT[5:4] ;
assign IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d2102 =
tlb_smt_fifos_2$EMPTY_N ?
tlb_smt_fifos_2$D_OUT[13:9] :
tlb_rsp_fifos_2$D_OUT[13:9] ;
assign IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2075 =
tlb_smt_fifos_3$EMPTY_N ?
tlb_smt_fifos_3$D_OUT[5:4] :
tlb_rsp_fifos_3$D_OUT[5:4] ;
assign IF_tlb_smt_fifos_3_i_notEmpty__728_THEN_tlb_sm_ETC___d2103 =
tlb_smt_fifos_3$EMPTY_N ?
tlb_smt_fifos_3$D_OUT[13:9] :
tlb_rsp_fifos_3$D_OUT[13:9] ;
assign NOT_causeUpdate1_i_notEmpty__68_70_AND_IF_caus_ETC___d588 =
!causeUpdate1$EMPTY_N &&
(causeUpdate2$EMPTY_N ?
cause[30] :
causeUpdate3$EMPTY_N || cause[30]) ;
assign NOT_llScReg_read__133_BIT_64_134_554_OR_NOT_0__ETC___d1595 =
!llScReg[64] ||
{ 28'd0,
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_sm_ETC___d1760 } !=
llScReg[63:0] ||
IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_NOT_tl_ETC___d2125 ||
IF_IF_tlb_smt_fifos_2_i_notEmpty__552_THEN_tlb_ETC___d1862 !=
5'd25 ;
assign NOT_tlbLookupCoprocessors_0_request_put_BITS_7_ETC___d1706 =
(tlbLookupCoprocessors_0_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupCoprocessors_0_request_put[42:40] != 3'b100 &&
tlbLookupCoprocessors_0_request_put[42:40] != 3'b101) &&
tlb_last_hit_3[98] &&
tlb_last_hit_3_41_BITS_95_TO_45_640_CONCAT_tlb_ETC___d1644 &&
(tlb_last_hit_3_41_BITS_39_TO_32_646_EQ_tlbEntr_ETC___d1647 ||
tlb_last_hit_3[96]) ;
assign NOT_tlbLookupCoprocessors_0_request_put_BITS_7_ETC___d1720 =
(tlbLookupCoprocessors_0_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupCoprocessors_0_request_put[42:40] != 3'b100 &&
tlbLookupCoprocessors_0_request_put[42:40] != 3'b101) &&
(!tlb_last_hit_3[98] ||
!tlb_last_hit_3_41_BITS_95_TO_45_640_CONCAT_tlb_ETC___d1644 ||
!tlb_last_hit_3_41_BITS_39_TO_32_646_EQ_tlbEntr_ETC___d1647 &&
!tlb_last_hit_3[96]) ;
assign NOT_tlbLookupData_request_put_BITS_74_TO_43_45_ETC___d1533 =
(tlbLookupData_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupData_request_put[42:40] != 3'b100 &&
tlbLookupData_request_put[42:40] != 3'b101) &&
tlb_last_hit_2[98] &&
tlb_last_hit_2_29_BITS_95_TO_45_467_CONCAT_tlb_ETC___d1471 &&
(tlb_last_hit_2_29_BITS_39_TO_32_473_EQ_tlbEntr_ETC___d1474 ||
tlb_last_hit_2[96]) ;
assign NOT_tlbLookupData_request_put_BITS_74_TO_43_45_ETC___d1547 =
(tlbLookupData_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupData_request_put[42:40] != 3'b100 &&
tlbLookupData_request_put[42:40] != 3'b101) &&
(!tlb_last_hit_2[98] ||
!tlb_last_hit_2_29_BITS_95_TO_45_467_CONCAT_tlb_ETC___d1471 ||
!tlb_last_hit_2_29_BITS_39_TO_32_473_EQ_tlbEntr_ETC___d1474 &&
!tlb_last_hit_2[96]) ;
assign NOT_tlbLookupInstruction_request_put_BITS_74_T_ETC___d1391 =
(tlbLookupInstruction_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupInstruction_request_put[42:40] != 3'b100 &&
tlbLookupInstruction_request_put[42:40] != 3'b101) &&
tlb_last_hit_1[98] &&
tlb_last_hit_1_17_BITS_95_TO_45_326_CONCAT_tlb_ETC___d1330 &&
(tlb_last_hit_1_17_BITS_39_TO_32_332_EQ_tlbEntr_ETC___d1333 ||
tlb_last_hit_1[96]) ;
assign NOT_tlbLookupInstruction_request_put_BITS_74_T_ETC___d1405 =
(tlbLookupInstruction_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupInstruction_request_put[42:40] != 3'b100 &&
tlbLookupInstruction_request_put[42:40] != 3'b101) &&
(!tlb_last_hit_1[98] ||
!tlb_last_hit_1_17_BITS_95_TO_45_326_CONCAT_tlb_ETC___d1330 ||
!tlb_last_hit_1_17_BITS_39_TO_32_332_EQ_tlbEntr_ETC___d1333 &&
!tlb_last_hit_1[96]) ;
assign NOT_tlb_read_fifo_first__52_BIT_84_55_80_AND_N_ETC___d388 =
!tlb_read_fifo$D_OUT[84] &&
(!tlb_entryHiHash$DOA[13] ||
!tlb_entryHiHash_a_read__5_BITS_77_TO_27_57_EQ__ETC___d2121 ||
!tlb_entryHiHash_a_read__5_BITS_21_TO_14_61_EQ__ETC___d2122 &&
!tlb_entryHiHash$DOA[0]) ;
assign _theResult_____5__h15306 =
(tlb_read_fifo$D_OUT[2:0] == 3'd0) ?
response___1__h15677 :
response__h15158 ;
assign _theResult____h7635 =
tlb_readWrite_fifo$D_OUT[149] ?
hashKey___1__h7990 :
hashKey__h7634 ;
assign _theResult___pfn__h15802 =
tlb_read_fifo$D_OUT[26] ?
tlb_entryLo1$DOA[29:6] :
tlb_entryLo0$DOA[29:6] ;
assign _theResult___zeros__h15801 =
tlb_read_fifo$D_OUT[26] ?
tlb_entryLo1$DOA[31:30] :
tlb_entryLo0$DOA[31:30] ;
assign addr__h26547 =
{ tlb_last_hit_1[29:6],
tlbLookupInstruction_request_put[22:11] } ;
assign addr__h28269 =
{ tlb_last_hit_2[29:6], tlbLookupData_request_put[22:11] } ;
assign addr__h30356 =
{ tlb_last_hit_3[29:6],
tlbLookupCoprocessors_0_request_put[22:11] } ;
assign avaddrs_first__198_BITS_3_TO_0_199_EQ_putExcep_ETC___d2058 =
avaddrs$D_OUT[3:0] == putException_exp[4:1] ;
assign cause_79_BITS_26_TO_24_95_CONCAT_IF_causeUpdat_ETC___d758 =
{ cause[26:24],
causeUpdate0$EMPTY_N ? causeUpdate0$D_OUT[23] : cause[23],
IF_causeUpdate0_i_notEmpty__66_THEN_causeUpdat_ETC___d757 } ;
assign cause_79_BITS_29_TO_28_90_CONCAT_IF_causeUpdat_ETC___d759 =
{ cause[29:28],
causeUpdate0$EMPTY_N ? causeUpdate0$D_OUT[27] : cause[27],
cause_79_BITS_26_TO_24_95_CONCAT_IF_causeUpdat_ETC___d758 } ;
assign dataUpdate_i_notEmpty__91_AND_forceUpdate_i_no_ETC___d801 =
dataUpdate$EMPTY_N && forceUpdate$EMPTY_N &&
tlb_tlbState == 3'd1 &&
!tlb_readWrite_fifo$EMPTY_N &&
tlbReads$FULL_N &&
eretReport$FULL_N &&
tlbProbes$FULL_N ;
assign dvaddrs_first__193_BITS_3_TO_0_194_EQ_putExcep_ETC___d2057 =
dvaddrs$D_OUT[3:0] == putException_exp[4:1] ;
assign foundIndex___1__h15741 = { 1'd0, hashKey__h15193 } + 6'd8 ;
assign hashKey___1__h7990 = tlb_readWrite_fifo$D_OUT[95:91] - 5'd8 ;
assign hashKey__h14215 =
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[17:13] -
5'd8 ;
assign hashKey__h15193 = tlb_read_fifo$D_OUT[31:27] - 5'd8 ;
assign hashKey__h20299 = tlbEntryHi[17:13] - 5'd8 ;
assign hashKey__h7634 = tlb_readWrite_fifo$D_OUT[146:142] - 5'd8 ;
assign ivaddrs_first__187_BITS_3_TO_0_188_EQ_putExcep_ETC___d2054 =
ivaddrs$D_OUT[3:0] == putException_exp[4:1] ;
assign key__h14213 =
tlb_entrySrch_7_02_BIT_13_03_AND_tlb_entrySrch_ETC___d1921 ?
3'd7 :
IF_tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entryS_ETC___d1774 ;
assign requestSource___1__h11175 =
tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb_req_ETC___d1756 ?
3'd3 :
IF_tlb_req_fifos_2_i_notEmpty__70_AND_NOT_tlb__ETC___d1767 ;
assign response___1__h15677 = { 30'd0, x__h15680 } ;
assign response__h15158 =
{ _theResult___pfn__h15802, tlb_read_fifo$D_OUT[25:14] } ;
assign rv__h23510 = { {32{x__h23513[31]}}, x__h23513 } ;
assign rv__h23551 =
{ 32'd0,
tlbEntryLo0[31:6],
IF_tlbEntryLo0_read__000_BITS_5_TO_3_007_EQ_0__ETC___d2143,
tlbEntryLo0[2:0] } ;
assign rv__h23577 =
{ 32'd0,
tlbEntryLo1[31:6],
IF_tlbEntryLo1_read__002_BITS_5_TO_3_017_EQ_0__ETC___d2145,
tlbEntryLo1[2:0] } ;
assign rv__h23612 = { 52'd0, tlbPageMask } ;
assign rv__h23621 = { 61'd0, tlbWired } ;
assign rv__h23634 = { 32'd0, count } ;
assign rv__h23650 = { 32'd0, compare } ;
assign rv__h23658 = { 32'd0, sr } ;
assign rv__h23688 = { 32'd0, x__h23691 } ;
assign rv__h23771 = { 32'd0, procid } ;
assign rv__h23813 = { 32'd0, x__h23816 } ;
assign rv__h23926 = { 32'd0, configReg1 } ;
assign rv__h24032 = { 32'd0, configReg2 } ;
assign rv__h24107 = { 33'd0, configReg3 } ;
assign rv__h24236 = { 32'd0, watchLo } ;
assign rv__h24245 = { 60'd0, watchHi } ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d1045 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd31 &&
dataUpdate$D_OUT[5:0] == 6'd24 &&
!sr[2] &&
!eretHappened$EMPTY_N ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d1046 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd31 &&
dataUpdate$D_OUT[5:0] == 6'd24 &&
!sr[2] ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d820 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd0 ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d825 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd2 ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d837 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd3 ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d842 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd5 ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d850 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd10 ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d877 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
(rnUpdate$D_OUT == 5'd11 ||
rnUpdate$D_OUT == 5'd12 &&
(!dataUpdate$D_OUT[5] || !dataUpdate$D_OUT[6] ||
!dataUpdate$D_OUT[7])) ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d900 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
(rnUpdate$D_OUT == 5'd12 ||
rnUpdate$D_OUT == 5'd31 && dataUpdate$D_OUT[5:0] == 6'd24 &&
!sr[2]) ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d967 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd14 ;
assign sr_read__09_BITS_4_TO_3_10_EQ_0_11_OR_sr_read__ETC___d989 =
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd31 &&
(dataUpdate$D_OUT[5:0] == 6'd1 ||
dataUpdate$D_OUT[5:0] == 6'd2 && tlbIndex[6] ||
dataUpdate$D_OUT[5:0] == 6'd6) ;
assign te_tlbAddr__h23031 = { 1'd0, hashKey__h20299 } + 6'd8 ;
assign tlbIndexBase__h23491 = { 25'd0, x__h23535 } ;
assign tlbLookupCoprocessors_0_request_put_BITS_74_TO_ETC___d1651 =
tlbLookupCoprocessors_0_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupCoprocessors_0_request_put[42:40] == 3'b100 ||
tlbLookupCoprocessors_0_request_put[42:40] == 3'b101) ||
tlb_last_hit_3[98] &&
tlb_last_hit_3_41_BITS_95_TO_45_640_CONCAT_tlb_ETC___d1644 &&
(tlb_last_hit_3_41_BITS_39_TO_32_646_EQ_tlbEntr_ETC___d1647 ||
tlb_last_hit_3[96]) ;
assign tlbLookupData_request_put_BITS_74_TO_43_459_EQ_ETC___d1478 =
tlbLookupData_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupData_request_put[42:40] == 3'b100 ||
tlbLookupData_request_put[42:40] == 3'b101) ||
tlb_last_hit_2[98] &&
tlb_last_hit_2_29_BITS_95_TO_45_467_CONCAT_tlb_ETC___d1471 &&
(tlb_last_hit_2_29_BITS_39_TO_32_473_EQ_tlbEntr_ETC___d1474 ||
tlb_last_hit_2[96]) ;
assign tlbLookupInstruction_request_put_BITS_74_TO_43_ETC___d1337 =
tlbLookupInstruction_request_put[74:43] == 32'hFFFFFFFF &&
(tlbLookupInstruction_request_put[42:40] == 3'b100 ||
tlbLookupInstruction_request_put[42:40] == 3'b101) ||
tlb_last_hit_1[98] &&
tlb_last_hit_1_17_BITS_95_TO_45_326_CONCAT_tlb_ETC___d1330 &&
(tlb_last_hit_1_17_BITS_39_TO_32_332_EQ_tlbEntr_ETC___d1333 ||
tlb_last_hit_1[96]) ;
assign tlb_entryHiHash_a_read__5_BITS_21_TO_14_61_EQ__ETC___d2122 =
tlb_entryHiHash$DOA[21:14] == tlbEntryHi[7:0] ;
assign tlb_entryHiHash_a_read__5_BITS_77_TO_27_57_EQ__ETC___d2121 =
tlb_entryHiHash$DOA[77:27] == tlb_read_fifo$D_OUT[77:27] ;
assign tlb_entrySrch_13_BIT_13_14_AND_tlb_entrySrch_1_ETC___d1907 =
tlb_entrySrch[13] &&
tlb_entrySrch[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch[21:14] == tlbEntryHi[7:0] || tlb_entrySrch[0]) ;
assign tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entrySrch_ETC___d1909 =
tlb_entrySrch_1[13] &&
tlb_entrySrch_1[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch_1[21:14] == tlbEntryHi[7:0] ||
tlb_entrySrch_1[0]) ;
assign tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entrySrch_ETC___d1911 =
tlb_entrySrch_2[13] &&
tlb_entrySrch_2[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch_2[21:14] == tlbEntryHi[7:0] ||
tlb_entrySrch_2[0]) ;
assign tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1913 =
tlb_entrySrch_3[13] &&
tlb_entrySrch_3[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch_3[21:14] == tlbEntryHi[7:0] ||
tlb_entrySrch_3[0]) ;
assign tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1944 =
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1913 ||
tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entrySrch_ETC___d1911 ||
tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entrySrch_ETC___d1909 ||
tlb_entrySrch_13_BIT_13_14_AND_tlb_entrySrch_1_ETC___d1907 ;
assign tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entrySrch_ETC___d1915 =
tlb_entrySrch_4[13] &&
tlb_entrySrch_4[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch_4[21:14] == tlbEntryHi[7:0] ||
tlb_entrySrch_4[0]) ;
assign tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entrySrch_ETC___d1917 =
tlb_entrySrch_5[13] &&
tlb_entrySrch_5[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch_5[21:14] == tlbEntryHi[7:0] ||
tlb_entrySrch_5[0]) ;
assign tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1919 =
tlb_entrySrch_6[13] &&
tlb_entrySrch_6[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch_6[21:14] == tlbEntryHi[7:0] ||
tlb_entrySrch_6[0]) ;
assign tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1950 =
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1919 ||
tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entrySrch_ETC___d1917 ||
tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entrySrch_ETC___d1915 ||
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1944 ;
assign tlb_entrySrch_7_02_BIT_13_03_AND_tlb_entrySrch_ETC___d1921 =
tlb_entrySrch_7[13] &&
tlb_entrySrch_7[77:27] ==
IF_tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb__ETC___d1759[63:13] &&
(tlb_entrySrch_7[21:14] == tlbEntryHi[7:0] ||
tlb_entrySrch_7[0]) ;
assign tlb_last_hit_1_17_BITS_39_TO_32_332_EQ_tlbEntr_ETC___d1333 =
tlb_last_hit_1[39:32] == tlbEntryHi[7:0] ;
assign tlb_last_hit_1_17_BITS_95_TO_45_326_CONCAT_tlb_ETC___d1330 =
{ tlb_last_hit_1[95:45], tlb_last_hit_1[97] } ==
tlbLookupInstruction_request_put[74:23] ;
assign tlb_last_hit_2_29_BITS_39_TO_32_473_EQ_tlbEntr_ETC___d1474 =
tlb_last_hit_2[39:32] == tlbEntryHi[7:0] ;
assign tlb_last_hit_2_29_BITS_95_TO_45_467_CONCAT_tlb_ETC___d1471 =
{ tlb_last_hit_2[95:45], tlb_last_hit_2[97] } ==
tlbLookupData_request_put[74:23] ;
assign tlb_last_hit_3_41_BITS_39_TO_32_646_EQ_tlbEntr_ETC___d1647 =
tlb_last_hit_3[39:32] == tlbEntryHi[7:0] ;
assign tlb_last_hit_3_41_BITS_95_TO_45_640_CONCAT_tlb_ETC___d1644 =
{ tlb_last_hit_3[95:45], tlb_last_hit_3[97] } ==
tlbLookupCoprocessors_0_request_put[74:23] ;
assign tlb_readOut_fifo_first__09_ULT_8___d1869 =
tlb_readOut_fifo$D_OUT < 6'd8 ;
assign tlb_readWrite_fifo_first__9_BITS_147_TO_142_0__ETC___d1867 =
tlb_readWrite_fifo$D_OUT[147:142] < 6'd8 ;
assign tlb_read_fifo_first__52_BITS_13_TO_12_16_CONCA_ETC___d427 =
{ tlb_read_fifo$D_OUT[13:12],
tlb_read_fifo$D_OUT[26] ?
tlb_entryLo1$DOA[5:3] != 3'd2 :
tlb_entryLo0$DOA[5:3] != 3'd2,
(tlb_read_fifo$D_OUT[77:74] < 4'h8) ?
((tlb_read_fifo$D_OUT[77:74] < 4'h4) ? 2'd0 : 2'd1) :
2'd2,
tlb_read_fifo$D_OUT[6:3] } ;
assign tlb_req_fifos_3_i_notEmpty__71_AND_NOT_tlb_req_ETC___d1756 =
tlb_req_fifos_3$EMPTY_N && !tlb_req_fifos_2$EMPTY_N &&
!tlb_req_fifos_1$EMPTY_N &&
!tlb_req_fifos$EMPTY_N ;
assign tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 =
tlb_req_fifos$EMPTY_N || tlb_req_fifos_1$EMPTY_N ||
tlb_req_fifos_2$EMPTY_N ||
tlb_req_fifos_3$EMPTY_N ;
assign v__h19352 =
contxtUpdate$EMPTY_N ? contxtUpdate$D_OUT : tlbContext[63:23] ;
assign v__h19480 =
xcntxtUpdate$EMPTY_N ? xcntxtUpdate$D_OUT : tlbXContext[63:33] ;
assign v__h24510 = ivaddrs$EMPTY_N ? v__h24520 : 64'b0 ;
assign v__h24520 =
ivaddrs_first__187_BITS_3_TO_0_188_EQ_putExcep_ETC___d2054 ?
v__h24572 :
64'b0 ;
assign v__h24653 = dvaddrs$EMPTY_N ? v__h24663 : v__h24510 ;
assign v__h24663 =
dvaddrs_first__193_BITS_3_TO_0_194_EQ_putExcep_ETC___d2057 ?
v__h24691 :
v__h24510 ;
assign v__h24795 = avaddrs$EMPTY_N ? v__h24890 : v__h24653 ;
assign v__h24890 =
avaddrs_first__198_BITS_3_TO_0_199_EQ_putExcep_ETC___d2058 ?
v__h24929 :
v__h24653 ;
assign x1_avValue_ip__h18475 =
causeUpdate3$EMPTY_N ? causeUpdate3$D_OUT : cause[15:8] ;
assign x1_avValue_ip__h18496 =
causeUpdate2$EMPTY_N ?
causeUpdate2$D_OUT :
x1_avValue_ip__h18475 ;
assign x1_avValue_ip__h18517 =
causeUpdate1$EMPTY_N ? cause[15:8] : x1_avValue_ip__h18496 ;
assign x2__h14355 = { 3'd0, key__h14213 } ;
assign x2__h14503 = x__h14519 + 6'd8 ;
assign x2__h8105 = x__h8136 + 6'd8 ;
assign x2__h9311 = x__h9327 + 6'd8 ;
assign x__h14519 = { 1'd0, hashKey__h14215 } ;
assign x__h15680 =
tlb_read_fifo$D_OUT[84] ?
tlb_read_fifo$D_OUT[83:78] :
y_avValue_snd_fst__h15681 ;
assign x__h17372 = tlb_randomIndex - 3'd1 ;
assign x__h20699 = { cause[15:9], 1'd1 } ;
assign x__h21478 = { 1'd0, cause[14:8] } ;
assign x__h23513 = { !tlbIndex[6], tlbIndexBase__h23491 } ;
assign x__h23535 = tlbIndex[6] ? tlbIndex[5:0] : 6'd0 ;
assign x__h23691 =
{ cause[31:7],
CASE_cause_BITS_6_TO_2_31_0_cause_BITS_6_TO_2__ETC__q2,
cause[1:0] } ;
assign x__h23816 =
{ configReg0[31:3],
CASE_configReg0_BITS_2_TO_0_4_0_configReg0_BIT_ETC__q1 } ;
assign x__h8136 = { 1'd0, _theResult____h7635 } ;
assign x__h9327 = { 1'd0, hashKey___1__h7990 } ;
assign x_addr__h27037 = { 7'b0, tlbLookupInstruction_request_put[39:11] } ;
assign x_addr__h28759 = { 7'b0, tlbLookupData_request_put[39:11] } ;
assign x_addr__h30846 =
{ 7'b0, tlbLookupCoprocessors_0_request_put[39:11] } ;
assign x_ip__h18557 =
{ IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d2124[7],
exInterrupts,
IF_causeUpdate0_i_notEmpty__66_THEN_cause_79_B_ETC___d2124[1:0] } ;
assign y_avValue_ip__h18238 = { cause[15:10], causeUpdate0$D_OUT[9:8] } ;
assign y_avValue_snd_fst__h15681 =
(tlb_entryHiHash$DOA[13] &&
tlb_entryHiHash_a_read__5_BITS_77_TO_27_57_EQ__ETC___d2121 &&
(tlb_entryHiHash_a_read__5_BITS_21_TO_14_61_EQ__ETC___d2122 ||
tlb_entryHiHash$DOA[0])) ?
foundIndex___1__h15741 :
tlb_read_fifo$D_OUT[83:78] ;
always@(putException_exp or ivaddrs$D_OUT)
begin
case (putException_exp[138:134])
5'd2, 5'd3, 5'd8: v__h24572 = ivaddrs$D_OUT[67:4];
default: v__h24572 = 64'b0;
endcase
end
always@(configReg0)
begin
case (configReg0[2:0])
3'd0, 3'd2, 3'd3:
CASE_configReg0_BITS_2_TO_0_4_0_configReg0_BIT_ETC__q1 =
configReg0[2:0];
default: CASE_configReg0_BITS_2_TO_0_4_0_configReg0_BIT_ETC__q1 = 3'd4;
endcase
end
always@(cause)
begin
case (cause[6:2])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
CASE_cause_BITS_6_TO_2_31_0_cause_BITS_6_TO_2__ETC__q2 = cause[6:2];
default: CASE_cause_BITS_6_TO_2_31_0_cause_BITS_6_TO_2__ETC__q2 = 5'd31;
endcase
end
always@(tlb_readOut_fifo$D_OUT or
tlb_entrySrch_7 or
tlb_entrySrch or
tlb_entrySrch_1 or
tlb_entrySrch_2 or
tlb_entrySrch_3 or
tlb_entrySrch_4 or tlb_entrySrch_5 or tlb_entrySrch_6)
begin
case (tlb_readOut_fifo$D_OUT)
6'd0:
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch[12:1];
6'd1:
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch_1[12:1];
6'd2:
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch_2[12:1];
6'd3:
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch_3[12:1];
6'd4:
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch_4[12:1];
6'd5:
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch_5[12:1];
6'd6:
IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch_6[12:1];
default: IF_tlb_readOut_fifo_first__09_EQ_0_11_THEN_tlb_ETC___d534 =
tlb_entrySrch_7[12:1];
endcase
end
always@(readReqs$D_OUT or
rv__h23813 or rv__h23926 or rv__h24032 or rv__h24107)
begin
case (readReqs$D_OUT[2:0])
3'd0:
IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131 =
rv__h23813;
3'd1:
IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131 =
rv__h23926;
3'd2:
IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131 =
rv__h24032;
3'd3:
IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131 =
rv__h24107;
default: IF_readReqs_first__048_BITS_2_TO_0_106_EQ_0_10_ETC___d1131 =
64'b0;
endcase
end
always@(tlbEntryLo1)
begin
case (tlbEntryLo1[5:3])
3'd0, 3'd2, 3'd3:
IF_tlbEntryLo1_read__002_BITS_5_TO_3_017_EQ_0__ETC___d2145 =
tlbEntryLo1[5:3];
default: IF_tlbEntryLo1_read__002_BITS_5_TO_3_017_EQ_0__ETC___d2145 =
3'd4;
endcase
end
always@(tlbEntryLo0)
begin
case (tlbEntryLo0[5:3])
3'd0, 3'd2, 3'd3:
IF_tlbEntryLo0_read__000_BITS_5_TO_3_007_EQ_0__ETC___d2143 =
tlbEntryLo0[5:3];
default: IF_tlbEntryLo0_read__000_BITS_5_TO_3_007_EQ_0__ETC___d2143 =
3'd4;
endcase
end
always@(putException_exp or v__h24510 or dvaddrs$D_OUT)
begin
case (putException_exp[138:134])
5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd9, 5'd10:
v__h24691 = dvaddrs$D_OUT[67:4];
default: v__h24691 = v__h24510;
endcase
end
always@(putException_exp or v__h24653 or avaddrs$D_OUT)
begin
case (putException_exp[138:134])
5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd9, 5'd10:
v__h24929 = avaddrs$D_OUT[67:4];
default: v__h24929 = v__h24653;
endcase
end
always@(tlb_read_fifo$D_OUT or
tlb_entrySrch_7 or
tlb_entrySrch or
tlb_entrySrch_1 or
tlb_entrySrch_2 or
tlb_entrySrch_3 or
tlb_entrySrch_4 or tlb_entrySrch_5 or tlb_entrySrch_6)
begin
case (tlb_read_fifo$D_OUT[83:78])
6'd0:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch[0];
6'd1:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch_1[0];
6'd2:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch_2[0];
6'd3:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch_3[0];
6'd4:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch_4[0];
6'd5:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch_5[0];
6'd6:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch_6[0];
default: IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2079 =
tlb_entrySrch_7[0];
endcase
end
always@(cause)
begin
case (cause[6:2])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 =
cause[6:2];
5'd15:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd14;
5'd18:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd15;
5'd22:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd16;
5'd23:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd17;
5'd24:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd18;
5'd25:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd19;
5'd26:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd20;
5'd30:
IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 = 5'd21;
default: IF_cause_79_BITS_6_TO_2_18_EQ_0_19_OR_cause_79_ETC___d2087 =
5'd22;
endcase
end
always@(causeUpdate1$D_OUT)
begin
case (causeUpdate1$D_OUT[6:2])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13:
CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 =
causeUpdate1$D_OUT[6:2];
5'd15: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd14;
5'd18: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd15;
5'd22: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd16;
5'd23: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd17;
5'd24: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd18;
5'd25: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd19;
5'd26: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd20;
5'd30: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd21;
default: CASE_causeUpdate1D_OUT_BITS_6_TO_2_22_0_cause_ETC__q3 = 5'd22;
endcase
end
always@(IF_causeUpdate0_i_notEmpty__66_THEN_IF_cause_7_ETC___d2048)
begin
case (IF_causeUpdate0_i_notEmpty__66_THEN_IF_cause_7_ETC___d2048)
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13:
CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 =
IF_causeUpdate0_i_notEmpty__66_THEN_IF_cause_7_ETC___d2048;
5'd14: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd15;
5'd15: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd18;
5'd16: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd22;
5'd17: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd23;
5'd18: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd24;
5'd19: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd25;
5'd20: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd26;
5'd21: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd30;
default: CASE_IF_causeUpdate0_i_notEmpty__66_THEN_IF_ca_ETC__q4 = 5'd31;
endcase
end
always@(tlb_read_fifo$D_OUT or
tlb_entrySrch_7 or
tlb_entrySrch or
tlb_entrySrch_1 or
tlb_entrySrch_2 or
tlb_entrySrch_3 or
tlb_entrySrch_4 or tlb_entrySrch_5 or tlb_entrySrch_6)
begin
case (tlb_read_fifo$D_OUT[83:78])
6'd0:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch[77:14];
6'd1:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_1[77:14];
6'd2:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_2[77:14];
6'd3:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_3[77:14];
6'd4:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_4[77:14];
6'd5:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_5[77:14];
6'd6:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_6[77:14];
6'd7:
IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_7[77:14];
default: IF_tlb_read_fifo_first__52_BITS_83_TO_78_56_EQ_ETC___d2140 =
tlb_entrySrch_7[77:14];
endcase
end
always@(tlb_readOut_fifo$D_OUT or
tlb_entrySrch_7 or
tlb_entrySrch or
tlb_entrySrch_1 or
tlb_entrySrch_2 or
tlb_entrySrch_3 or
tlb_entrySrch_4 or tlb_entrySrch_5 or tlb_entrySrch_6)
begin
case (tlb_readOut_fifo$D_OUT)
6'd0:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch[77:14];
6'd1:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_1[77:14];
6'd2:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_2[77:14];
6'd3:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_3[77:14];
6'd4:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_4[77:14];
6'd5:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_5[77:14];
6'd6:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_6[77:14];
6'd7:
CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_7[77:14];
default: CASE_tlb_readOut_fifoD_OUT_tlb_entrySrch_7_BI_ETC__q5 =
tlb_entrySrch_7[77:14];
endcase
end
always@(tlb_entryLo0$DOA)
begin
case (tlb_entryLo0$DOA[5:3])
3'd0, 3'd2, 3'd3:
CASE_tlb_entryLo0DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q6 =
tlb_entryLo0$DOA[5:3];
default: CASE_tlb_entryLo0DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q6 = 3'd4;
endcase
end
always@(dataUpdate$D_OUT)
begin
case (dataUpdate$D_OUT[5:3])
3'd0, 3'd2, 3'd3:
CASE_dataUpdateD_OUT_BITS_5_TO_3_4_0_dataUpda_ETC__q7 =
dataUpdate$D_OUT[5:3];
default: CASE_dataUpdateD_OUT_BITS_5_TO_3_4_0_dataUpda_ETC__q7 = 3'd4;
endcase
end
always@(tlb_entryLo1$DOA)
begin
case (tlb_entryLo1$DOA[5:3])
3'd0, 3'd2, 3'd3:
CASE_tlb_entryLo1DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q8 =
tlb_entryLo1$DOA[5:3];
default: CASE_tlb_entryLo1DOA_BITS_5_TO_3_4_0_tlb_entr_ETC__q8 = 3'd4;
endcase
end
always@(tlb_readWrite_fifo$D_OUT)
begin
case (tlb_readWrite_fifo$D_OUT[37:35])
3'd0, 3'd2, 3'd3:
CASE_tlb_readWrite_fifoD_OUT_BITS_37_TO_35_4__ETC__q9 =
tlb_readWrite_fifo$D_OUT[37:35];
default: CASE_tlb_readWrite_fifoD_OUT_BITS_37_TO_35_4__ETC__q9 = 3'd4;
endcase
end
always@(tlb_readWrite_fifo$D_OUT)
begin
case (tlb_readWrite_fifo$D_OUT[5:3])
3'd0, 3'd2, 3'd3:
CASE_tlb_readWrite_fifoD_OUT_BITS_5_TO_3_4_0__ETC__q10 =
tlb_readWrite_fifo$D_OUT[5:3];
default: CASE_tlb_readWrite_fifoD_OUT_BITS_5_TO_3_4_0__ETC__q10 = 3'd4;
endcase
end
always@(tlb_last_hit)
begin
case (tlb_last_hit[5:3])
3'd0, 3'd2, 3'd3:
CASE_tlb_last_hit_BITS_5_TO_3_4_0_tlb_last_hit_ETC__q11 =
tlb_last_hit[5:3];
default: CASE_tlb_last_hit_BITS_5_TO_3_4_0_tlb_last_hit_ETC__q11 = 3'd4;
endcase
end
always@(tlb_last_hit_1)
begin
case (tlb_last_hit_1[5:3])
3'd0, 3'd2, 3'd3:
CASE_tlb_last_hit_1_BITS_5_TO_3_4_0_tlb_last_h_ETC__q12 =
tlb_last_hit_1[5:3];
default: CASE_tlb_last_hit_1_BITS_5_TO_3_4_0_tlb_last_h_ETC__q12 = 3'd4;
endcase
end
always@(tlb_last_hit_2)
begin
case (tlb_last_hit_2[5:3])
3'd0, 3'd2, 3'd3:
CASE_tlb_last_hit_2_BITS_5_TO_3_4_0_tlb_last_h_ETC__q13 =
tlb_last_hit_2[5:3];
default: CASE_tlb_last_hit_2_BITS_5_TO_3_4_0_tlb_last_h_ETC__q13 = 3'd4;
endcase
end
always@(tlb_last_hit_3)
begin
case (tlb_last_hit_3[5:3])
3'd0, 3'd2, 3'd3:
CASE_tlb_last_hit_3_BITS_5_TO_3_4_0_tlb_last_h_ETC__q14 =
tlb_last_hit_3[5:3];
default: CASE_tlb_last_hit_3_BITS_5_TO_3_4_0_tlb_last_h_ETC__q14 = 3'd4;
endcase
end
always@(dataUpdate$D_OUT)
begin
case (dataUpdate$D_OUT[5:0])
6'd1: CASE_dataUpdateD_OUT_BITS_5_TO_0_3_1_0_2_2__q15 = 2'd0;
6'd2: CASE_dataUpdateD_OUT_BITS_5_TO_0_3_1_0_2_2__q15 = 2'd2;
default: CASE_dataUpdateD_OUT_BITS_5_TO_0_3_1_0_2_2__q15 = 2'd3;
endcase
end
always@(dataUpdate$D_OUT or te_tlbAddr__h23031 or tlbIndex)
begin
case (dataUpdate$D_OUT[5:0])
6'd1, 6'd2:
CASE_dataUpdateD_OUT_BITS_5_TO_0_te_tlbAddr30_ETC__q16 =
tlbIndex[5:0];
default: CASE_dataUpdateD_OUT_BITS_5_TO_0_te_tlbAddr30_ETC__q16 =
te_tlbAddr__h23031;
endcase
end
always@(dataUpdate$D_OUT)
begin
case (dataUpdate$D_OUT[6:2])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
CASE_dataUpdateD_OUT_BITS_6_TO_2_31_0_dataUpd_ETC__q17 =
dataUpdate$D_OUT[6:2];
default: CASE_dataUpdateD_OUT_BITS_6_TO_2_31_0_dataUpd_ETC__q17 = 5'd31;
endcase
end
always@(putException_exp)
begin
case (putException_exp[138:134])
5'd0, 5'd1, 5'd23:
CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 =
putException_exp[138:134];
5'd2, 5'd3, 5'd4, 5'd6:
CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd2;
5'd5, 5'd7:
CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd3;
5'd8, 5'd9:
CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd4;
5'd10: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd5;
5'd11: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd6;
5'd12: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd7;
5'd13: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd8;
5'd14: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd9;
5'd15: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd10;
5'd16, 5'd17, 5'd18, 5'd19:
CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd11;
5'd20: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd12;
5'd21: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd13;
5'd22: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 = 5'd18;
default: CASE_putException_exp_BITS_138_TO_134_31_0_put_ETC__q18 =
5'd31;
endcase
end
always@(requestSource___1__h11175 or
tlb_req_fifos_3$D_OUT or
tlb_req_fifos$D_OUT or
tlb_req_fifos_1$D_OUT or tlb_req_fifos_2$D_OUT)
begin
case (requestSource___1__h11175)
3'd0:
CASE_requestSource___11175_tlb_req_fifos_3D_O_ETC__q19 =
tlb_req_fifos$D_OUT;
3'd1:
CASE_requestSource___11175_tlb_req_fifos_3D_O_ETC__q19 =
tlb_req_fifos_1$D_OUT;
3'd2:
CASE_requestSource___11175_tlb_req_fifos_3D_O_ETC__q19 =
tlb_req_fifos_2$D_OUT;
3'd3:
CASE_requestSource___11175_tlb_req_fifos_3D_O_ETC__q19 =
tlb_req_fifos_3$D_OUT;
default: CASE_requestSource___11175_tlb_req_fifos_3D_O_ETC__q19 =
tlb_req_fifos_3$D_OUT;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
badVAddr <= `BSV_ASSIGNMENT_DELAY 64'b0;
cause <= `BSV_ASSIGNMENT_DELAY 32'd0;
compare <= `BSV_ASSIGNMENT_DELAY 32'b0;
configReg0 <= `BSV_ASSIGNMENT_DELAY 32'h8000C083;
configReg1 <= `BSV_ASSIGNMENT_DELAY 32'hCEE03040;
configReg2 <= `BSV_ASSIGNMENT_DELAY 32'h80003840;
configReg3 <= `BSV_ASSIGNMENT_DELAY 31'd0;
count <= `BSV_ASSIGNMENT_DELAY 32'b0;
epc <= `BSV_ASSIGNMENT_DELAY 64'b0;
errorEPC <= `BSV_ASSIGNMENT_DELAY 64'b0;
exInterrupts <= `BSV_ASSIGNMENT_DELAY 5'b0;
llScReg <= `BSV_ASSIGNMENT_DELAY 65'h10000000000000000;
procid <= `BSV_ASSIGNMENT_DELAY 32'd1024;
sr <= `BSV_ASSIGNMENT_DELAY 32'd4194528;
tlbContext <= `BSV_ASSIGNMENT_DELAY 64'd0;
tlbEntryHi <= `BSV_ASSIGNMENT_DELAY 64'd0;
tlbEntryLo0 <= `BSV_ASSIGNMENT_DELAY 32'd30;
tlbEntryLo1 <= `BSV_ASSIGNMENT_DELAY 32'd30;
tlbIndex <= `BSV_ASSIGNMENT_DELAY 7'd64;
tlbPageMask <= `BSV_ASSIGNMENT_DELAY 12'b0;
tlbWired <= `BSV_ASSIGNMENT_DELAY 3'b0;
tlbXContext <= `BSV_ASSIGNMENT_DELAY 64'd0;
tlb_asid <= `BSV_ASSIGNMENT_DELAY 8'd0;
tlb_count <= `BSV_ASSIGNMENT_DELAY 5'd0;
tlb_last_hit <= `BSV_ASSIGNMENT_DELAY 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_last_hit_1 <= `BSV_ASSIGNMENT_DELAY 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_last_hit_2 <= `BSV_ASSIGNMENT_DELAY 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_last_hit_3 <= `BSV_ASSIGNMENT_DELAY 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_randomIndex <= `BSV_ASSIGNMENT_DELAY 3'h7;
tlb_tlbState <= `BSV_ASSIGNMENT_DELAY 3'd0;
watchHi <= `BSV_ASSIGNMENT_DELAY 4'b0;
watchLo <= `BSV_ASSIGNMENT_DELAY 32'b0;
end
else
begin
if (badVAddr$EN) badVAddr <= `BSV_ASSIGNMENT_DELAY badVAddr$D_IN;
if (cause$EN) cause <= `BSV_ASSIGNMENT_DELAY cause$D_IN;
if (compare$EN) compare <= `BSV_ASSIGNMENT_DELAY compare$D_IN;
if (configReg0$EN)
configReg0 <= `BSV_ASSIGNMENT_DELAY configReg0$D_IN;
if (configReg1$EN)
configReg1 <= `BSV_ASSIGNMENT_DELAY configReg1$D_IN;
if (configReg2$EN)
configReg2 <= `BSV_ASSIGNMENT_DELAY configReg2$D_IN;
if (configReg3$EN)
configReg3 <= `BSV_ASSIGNMENT_DELAY configReg3$D_IN;
if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (epc$EN) epc <= `BSV_ASSIGNMENT_DELAY epc$D_IN;
if (errorEPC$EN) errorEPC <= `BSV_ASSIGNMENT_DELAY errorEPC$D_IN;
if (exInterrupts$EN)
exInterrupts <= `BSV_ASSIGNMENT_DELAY exInterrupts$D_IN;
if (llScReg$EN) llScReg <= `BSV_ASSIGNMENT_DELAY llScReg$D_IN;
if (procid$EN) procid <= `BSV_ASSIGNMENT_DELAY procid$D_IN;
if (sr$EN) sr <= `BSV_ASSIGNMENT_DELAY sr$D_IN;
if (tlbContext$EN)
tlbContext <= `BSV_ASSIGNMENT_DELAY tlbContext$D_IN;
if (tlbEntryHi$EN)
tlbEntryHi <= `BSV_ASSIGNMENT_DELAY tlbEntryHi$D_IN;
if (tlbEntryLo0$EN)
tlbEntryLo0 <= `BSV_ASSIGNMENT_DELAY tlbEntryLo0$D_IN;
if (tlbEntryLo1$EN)
tlbEntryLo1 <= `BSV_ASSIGNMENT_DELAY tlbEntryLo1$D_IN;
if (tlbIndex$EN) tlbIndex <= `BSV_ASSIGNMENT_DELAY tlbIndex$D_IN;
if (tlbPageMask$EN)
tlbPageMask <= `BSV_ASSIGNMENT_DELAY tlbPageMask$D_IN;
if (tlbWired$EN) tlbWired <= `BSV_ASSIGNMENT_DELAY tlbWired$D_IN;
if (tlbXContext$EN)
tlbXContext <= `BSV_ASSIGNMENT_DELAY tlbXContext$D_IN;
if (tlb_asid$EN) tlb_asid <= `BSV_ASSIGNMENT_DELAY tlb_asid$D_IN;
if (tlb_count$EN) tlb_count <= `BSV_ASSIGNMENT_DELAY tlb_count$D_IN;
if (tlb_last_hit$EN)
tlb_last_hit <= `BSV_ASSIGNMENT_DELAY tlb_last_hit$D_IN;
if (tlb_last_hit_1$EN)
tlb_last_hit_1 <= `BSV_ASSIGNMENT_DELAY tlb_last_hit_1$D_IN;
if (tlb_last_hit_2$EN)
tlb_last_hit_2 <= `BSV_ASSIGNMENT_DELAY tlb_last_hit_2$D_IN;
if (tlb_last_hit_3$EN)
tlb_last_hit_3 <= `BSV_ASSIGNMENT_DELAY tlb_last_hit_3$D_IN;
if (tlb_randomIndex$EN)
tlb_randomIndex <= `BSV_ASSIGNMENT_DELAY tlb_randomIndex$D_IN;
if (tlb_tlbState$EN)
tlb_tlbState <= `BSV_ASSIGNMENT_DELAY tlb_tlbState$D_IN;
if (watchHi$EN) watchHi <= `BSV_ASSIGNMENT_DELAY watchHi$D_IN;
if (watchLo$EN) watchLo <= `BSV_ASSIGNMENT_DELAY watchLo$D_IN;
end
if (tlb_entryLo0Reg$EN)
tlb_entryLo0Reg <= `BSV_ASSIGNMENT_DELAY tlb_entryLo0Reg$D_IN;
if (tlb_entryLo1Reg$EN)
tlb_entryLo1Reg <= `BSV_ASSIGNMENT_DELAY tlb_entryLo1Reg$D_IN;
if (tlb_entrySrch$EN)
tlb_entrySrch <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch$D_IN;
if (tlb_entrySrch_1$EN)
tlb_entrySrch_1 <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch_1$D_IN;
if (tlb_entrySrch_2$EN)
tlb_entrySrch_2 <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch_2$D_IN;
if (tlb_entrySrch_3$EN)
tlb_entrySrch_3 <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch_3$D_IN;
if (tlb_entrySrch_4$EN)
tlb_entrySrch_4 <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch_4$D_IN;
if (tlb_entrySrch_5$EN)
tlb_entrySrch_5 <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch_5$D_IN;
if (tlb_entrySrch_6$EN)
tlb_entrySrch_6 <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch_6$D_IN;
if (tlb_entrySrch_7$EN)
tlb_entrySrch_7 <= `BSV_ASSIGNMENT_DELAY tlb_entrySrch_7$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
badVAddr = 64'hAAAAAAAAAAAAAAAA;
cause = 32'hAAAAAAAA;
compare = 32'hAAAAAAAA;
configReg0 = 32'hAAAAAAAA;
configReg1 = 32'hAAAAAAAA;
configReg2 = 32'hAAAAAAAA;
configReg3 = 31'h2AAAAAAA;
count = 32'hAAAAAAAA;
epc = 64'hAAAAAAAAAAAAAAAA;
errorEPC = 64'hAAAAAAAAAAAAAAAA;
exInterrupts = 5'h0A;
llScReg = 65'h0AAAAAAAAAAAAAAAA;
procid = 32'hAAAAAAAA;
sr = 32'hAAAAAAAA;
tlbContext = 64'hAAAAAAAAAAAAAAAA;
tlbEntryHi = 64'hAAAAAAAAAAAAAAAA;
tlbEntryLo0 = 32'hAAAAAAAA;
tlbEntryLo1 = 32'hAAAAAAAA;
tlbIndex = 7'h2A;
tlbPageMask = 12'hAAA;
tlbWired = 3'h2;
tlbXContext = 64'hAAAAAAAAAAAAAAAA;
tlb_asid = 8'hAA;
tlb_count = 5'h0A;
tlb_entryLo0Reg = 32'hAAAAAAAA;
tlb_entryLo1Reg = 32'hAAAAAAAA;
tlb_entrySrch = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_entrySrch_1 = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_entrySrch_2 = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_entrySrch_3 = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_entrySrch_4 = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_entrySrch_5 = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_entrySrch_6 = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_entrySrch_7 = 78'h2AAAAAAAAAAAAAAAAAAA;
tlb_last_hit = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_last_hit_1 = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_last_hit_2 = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_last_hit_3 = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
tlb_randomIndex = 3'h2;
tlb_tlbState = 3'h2;
watchHi = 4'hA;
watchLo = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (EN_putException && putException_exp[138:134] == 5'd25 &&
!putException_exp[0])
begin
TASK_testplusargs___d1294 =
$test$plusargs("instructionBasedCycleCounter");
#0;
end
if (RST_N)
if (EN_tlbLookupInstruction_request_put &&
tlbLookupInstruction_request_put[74:67] != 8'h98 &&
tlbLookupInstruction_request_put[74:67] != 8'h90 &&
tlbLookupInstruction_request_put[74:67] != 8'hA0 &&
tlbLookupInstruction_request_put[74:67] != 8'hA8 &&
tlbLookupInstruction_request_put[74:67] != 8'hB0 &&
tlbLookupInstruction_request_put[8:4] == 5'd25 &&
NOT_tlbLookupInstruction_request_put_BITS_74_T_ETC___d1391)
begin
TASK_testplusargs___d1393 = $test$plusargs("showTranslations");
#0;
end
if (RST_N)
if (EN_tlbLookupInstruction_request_put &&
tlbLookupInstruction_request_put[74:67] != 8'h98 &&
tlbLookupInstruction_request_put[74:67] != 8'h90 &&
tlbLookupInstruction_request_put[74:67] != 8'hA0 &&
tlbLookupInstruction_request_put[74:67] != 8'hA8 &&
tlbLookupInstruction_request_put[74:67] != 8'hB0 &&
tlbLookupInstruction_request_put[8:4] == 5'd25 &&
(tlbLookupInstruction_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupInstruction_request_put[42:40] != 3'b100 &&
tlbLookupInstruction_request_put[42:40] != 3'b101) &&
tlb_last_hit_1[98] &&
tlb_last_hit_1_17_BITS_95_TO_45_326_CONCAT_tlb_ETC___d1330 &&
(tlb_last_hit_1_17_BITS_39_TO_32_332_EQ_tlbEntr_ETC___d1333 ||
tlb_last_hit_1[96]) &&
TASK_testplusargs___d1393)
$display("(lookup %s %x->%x)",
"instruction",
tlbLookupInstruction_request_put[74:11],
addr__h26547);
if (RST_N)
if (EN_tlbLookupData_request_put &&
tlbLookupData_request_put[74:67] != 8'h98 &&
tlbLookupData_request_put[74:67] != 8'h90 &&
tlbLookupData_request_put[74:67] != 8'hA0 &&
tlbLookupData_request_put[74:67] != 8'hA8 &&
tlbLookupData_request_put[74:67] != 8'hB0 &&
tlbLookupData_request_put[8:4] == 5'd25 &&
NOT_tlbLookupData_request_put_BITS_74_TO_43_45_ETC___d1533)
begin
TASK_testplusargs___d1535 = $test$plusargs("showTranslations");
#0;
end
if (RST_N)
if (EN_tlbLookupData_request_put &&
tlbLookupData_request_put[74:67] != 8'h98 &&
tlbLookupData_request_put[74:67] != 8'h90 &&
tlbLookupData_request_put[74:67] != 8'hA0 &&
tlbLookupData_request_put[74:67] != 8'hA8 &&
tlbLookupData_request_put[74:67] != 8'hB0 &&
tlbLookupData_request_put[8:4] == 5'd25 &&
(tlbLookupData_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupData_request_put[42:40] != 3'b100 &&
tlbLookupData_request_put[42:40] != 3'b101) &&
tlb_last_hit_2[98] &&
tlb_last_hit_2_29_BITS_95_TO_45_467_CONCAT_tlb_ETC___d1471 &&
(tlb_last_hit_2_29_BITS_39_TO_32_473_EQ_tlbEntr_ETC___d1474 ||
tlb_last_hit_2[96]) &&
TASK_testplusargs___d1535)
$display("(lookup %s %x->%x)",
"data",
tlbLookupData_request_put[74:11],
addr__h28269);
if (RST_N)
if (EN_tlbLookupCoprocessors_0_request_put &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'h98 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'h90 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hA0 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hA8 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hB0 &&
tlbLookupCoprocessors_0_request_put[8:4] == 5'd25 &&
NOT_tlbLookupCoprocessors_0_request_put_BITS_7_ETC___d1706)
begin
TASK_testplusargs___d1708 = $test$plusargs("showTranslations");
#0;
end
if (RST_N)
if (EN_tlbLookupCoprocessors_0_request_put &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'h98 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'h90 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hA0 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hA8 &&
tlbLookupCoprocessors_0_request_put[74:67] != 8'hB0 &&
tlbLookupCoprocessors_0_request_put[8:4] == 5'd25 &&
(tlbLookupCoprocessors_0_request_put[74:43] != 32'hFFFFFFFF ||
tlbLookupCoprocessors_0_request_put[42:40] != 3'b100 &&
tlbLookupCoprocessors_0_request_put[42:40] != 3'b101) &&
tlb_last_hit_3[98] &&
tlb_last_hit_3_41_BITS_95_TO_45_640_CONCAT_tlb_ETC___d1644 &&
(tlb_last_hit_3_41_BITS_39_TO_32_646_EQ_tlbEntr_ETC___d1647 ||
tlb_last_hit_3[96]) &&
TASK_testplusargs___d1708)
$display("(lookup %s %x->%x)",
"capability",
tlbLookupCoprocessors_0_request_put[74:11],
addr__h30356);
if (RST_N)
begin
TASK_testplusargs___d779 =
$test$plusargs("instructionBasedCycleCounter");
#0;
end
if (RST_N)
if (WILL_FIRE_RL_updateCP0Registers &&
(sr[4:3] == 2'd0 || sr[1] || forceUpdate$D_OUT || sr[28]) &&
rnUpdate$D_OUT == 5'd23)
$finish(32'd1);
if (RST_N)
if (WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entrySrch_ETC___d1909 &&
tlb_entrySrch_13_BIT_13_14_AND_tlb_entrySrch_1_ETC___d1907)
$display("Two matching TLB indices! %d and %d.",
3'd0,
$signed(32'd1));
if (RST_N)
if (WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entrySrch_ETC___d1911 &&
(tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entrySrch_ETC___d1909 ||
tlb_entrySrch_13_BIT_13_14_AND_tlb_entrySrch_1_ETC___d1907))
$display("Two matching TLB indices! %d and %d.",
IF_tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entryS_ETC___d1769,
$signed(32'd2));
if (RST_N)
if (WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1913 &&
(tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entrySrch_ETC___d1911 ||
tlb_entrySrch_1_78_BIT_13_79_AND_tlb_entrySrch_ETC___d1909 ||
tlb_entrySrch_13_BIT_13_14_AND_tlb_entrySrch_1_ETC___d1907))
$display("Two matching TLB indices! %d and %d.",
IF_tlb_entrySrch_2_27_BIT_13_28_AND_tlb_entryS_ETC___d1770,
$signed(32'd3));
if (RST_N)
if (WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entrySrch_ETC___d1915 &&
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1944)
$display("Two matching TLB indices! %d and %d.",
IF_tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entryS_ETC___d1771,
$signed(32'd4));
if (RST_N)
if (WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entrySrch_ETC___d1917 &&
(tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entrySrch_ETC___d1915 ||
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1944))
$display("Two matching TLB indices! %d and %d.",
IF_tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entryS_ETC___d1772,
$signed(32'd5));
if (RST_N)
if (WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1919 &&
(tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entrySrch_ETC___d1917 ||
tlb_entrySrch_4_57_BIT_13_58_AND_tlb_entrySrch_ETC___d1915 ||
tlb_entrySrch_3_42_BIT_13_43_AND_tlb_entrySrch_ETC___d1944))
$display("Two matching TLB indices! %d and %d.",
IF_tlb_entrySrch_5_72_BIT_13_73_AND_tlb_entryS_ETC___d1773,
$signed(32'd6));
if (RST_N)
if (WILL_FIRE_RL_tlb_startTLB &&
tlb_req_fifos_i_notEmpty__68_OR_tlb_req_fifos__ETC___d2154 &&
tlb_entrySrch_7_02_BIT_13_03_AND_tlb_entrySrch_ETC___d1921 &&
tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entrySrch_ETC___d1950)
$display("Two matching TLB indices! %d and %d.",
IF_tlb_entrySrch_6_87_BIT_13_88_AND_tlb_entryS_ETC___d1774,
$signed(32'd7));
if (RST_N)
if (WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 == 5'd25)
begin
TASK_testplusargs___d492 = $test$plusargs("showTranslations");
#0;
end
if (RST_N)
if (WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 ==
5'd25 &&
TASK_testplusargs___d492)
if (tlb_read_fifo$D_OUT[2:0] == 3'd0)
$display("(lookup %s %x->%x)",
"Probe",
tlb_read_fifo$D_OUT[77:14],
_theResult_____5__h15306);
else
if (tlb_read_fifo$D_OUT[2:0] == 3'd1)
$display("(lookup %s %x->%x)",
"Instruction",
tlb_read_fifo$D_OUT[77:14],
_theResult_____5__h15306);
else
if (tlb_read_fifo$D_OUT[2:0] == 3'd2)
$display("(lookup %s %x->%x)",
"Data",
tlb_read_fifo$D_OUT[77:14],
_theResult_____5__h15306);
else
if (tlb_read_fifo$D_OUT[2:0] == 3'd3)
$display("(lookup %s %x->%x)",
"Capability",
tlb_read_fifo$D_OUT[77:14],
_theResult_____5__h15306);
else
$display("(lookup %s %x->%x)",
"Coprocessor",
tlb_read_fifo$D_OUT[77:14],
_theResult_____5__h15306);
if (RST_N)
if (WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 != 5'd25)
begin
TASK_testplusargs___d500 = $test$plusargs("showTranslations");
#0;
end
if (RST_N)
if (WILL_FIRE_RL_tlb_readTLB &&
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845 !=
5'd25 &&
TASK_testplusargs___d500)
if (tlb_read_fifo$D_OUT[2:0] == 3'd0)
$display("(lookup %s on %x was a miss, ExpCode:%d)",
"Probe",
tlb_read_fifo$D_OUT[77:14],
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845);
else
if (tlb_read_fifo$D_OUT[2:0] == 3'd1)
$display("(lookup %s on %x was a miss, ExpCode:%d)",
"Instruction",
tlb_read_fifo$D_OUT[77:14],
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845);
else
if (tlb_read_fifo$D_OUT[2:0] == 3'd2)
$display("(lookup %s on %x was a miss, ExpCode:%d)",
"Data",
tlb_read_fifo$D_OUT[77:14],
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845);
else
if (tlb_read_fifo$D_OUT[2:0] == 3'd3)
$display("(lookup %s on %x was a miss, ExpCode:%d)",
"Capability",
tlb_read_fifo$D_OUT[77:14],
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845);
else
$display("(lookup %s on %x was a miss, ExpCode:%d)",
"Coprocessor",
tlb_read_fifo$D_OUT[77:14],
IF_IF_IF_NOT_tlb_read_fifo_first__52_BIT_84_55_ETC___d1845);
end
// synopsys translate_on
endmodule // mkCP0
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:44:48 BST 2012
//
// Method conflict info:
// Method: stream_request_put
// Conflict-free: stream_response_get,
// messages_request_get,
// messages_response_put
// Conflicts: stream_request_put
//
// Method: stream_response_get
// Conflict-free: stream_request_put, messages_request_get, messages_response_put
// Conflicts: stream_response_get
//
// Method: messages_request_get
// Conflict-free: stream_request_put, stream_response_get, messages_response_put
// Conflicts: messages_request_get
//
// Method: messages_response_put
// Conflict-free: stream_request_put, stream_response_get, messages_request_get
// Conflicts: messages_response_put
//
//
// Ports:
// Name I/O size props
// RDY_stream_request_put O 1 reg
// stream_response_get O 8 reg
// RDY_stream_response_get O 1 reg
// messages_request_get O 272
// RDY_messages_request_get O 1 reg
// RDY_messages_response_put O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// stream_request_put I 8 reg
// messages_response_put I 272
// EN_stream_request_put I 1
// EN_messages_response_put I 1
// EN_stream_response_get I 1
// EN_messages_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkDebugConvert(CLK,
RST_N,
stream_request_put,
EN_stream_request_put,
RDY_stream_request_put,
EN_stream_response_get,
stream_response_get,
RDY_stream_response_get,
EN_messages_request_get,
messages_request_get,
RDY_messages_request_get,
messages_response_put,
EN_messages_response_put,
RDY_messages_response_put);
input CLK;
input RST_N;
// action method stream_request_put
input [7 : 0] stream_request_put;
input EN_stream_request_put;
output RDY_stream_request_put;
// actionvalue method stream_response_get
input EN_stream_response_get;
output [7 : 0] stream_response_get;
output RDY_stream_response_get;
// actionvalue method messages_request_get
input EN_messages_request_get;
output [271 : 0] messages_request_get;
output RDY_messages_request_get;
// action method messages_response_put
input [271 : 0] messages_response_put;
input EN_messages_response_put;
output RDY_messages_response_put;
// signals for module outputs
wire [271 : 0] messages_request_get;
wire [7 : 0] stream_response_get;
wire RDY_messages_request_get,
RDY_messages_response_put,
RDY_stream_request_put,
RDY_stream_response_get;
// register command
reg [271 : 0] command;
wire [271 : 0] command$D_IN;
wire command$EN;
// register commandCount
reg [7 : 0] commandCount;
wire [7 : 0] commandCount$D_IN;
wire commandCount$EN;
// register commandState
reg [1 : 0] commandState;
reg [1 : 0] commandState$D_IN;
wire commandState$EN;
// register responseCount
reg [7 : 0] responseCount;
wire [7 : 0] responseCount$D_IN;
wire responseCount$EN;
// register responseState
reg [1 : 0] responseState;
reg [1 : 0] responseState$D_IN;
wire responseState$EN;
// ports of submodule commands
wire [271 : 0] commands$D_IN, commands$D_OUT;
wire commands$CLR,
commands$DEQ,
commands$EMPTY_N,
commands$ENQ,
commands$FULL_N;
// ports of submodule inChar
wire [7 : 0] inChar$D_IN, inChar$D_OUT;
wire inChar$CLR, inChar$DEQ, inChar$EMPTY_N, inChar$ENQ, inChar$FULL_N;
// ports of submodule outChar
reg [7 : 0] outChar$D_IN;
wire [7 : 0] outChar$D_OUT;
wire outChar$CLR, outChar$DEQ, outChar$EMPTY_N, outChar$ENQ, outChar$FULL_N;
// ports of submodule responses
wire [271 : 0] responses$D_IN, responses$D_OUT;
wire responses$CLR,
responses$DEQ,
responses$EMPTY_N,
responses$ENQ,
responses$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_deliverResponse, WILL_FIRE_RL_getCommand;
// remaining internal signals
reg [263 : 0] IF_commandState_EQ_0_THEN_0b0_CONCAT_DONTCARE__ETC___d369;
reg [7 : 0] CASE_command_BITS_271_TO_264_32_0_command_BITS_ETC__q2,
CASE_commandsD_OUT_BITS_271_TO_264_32_0_comma_ETC__q1,
CASE_messages_response_put_BITS_271_TO_264_32__ETC__q3,
x__h14752,
x__h15152;
wire [263 : 0] IF_NOT_inChar_first__7_EQ_0_8_9_AND_inChar_fir_ETC___d365;
wire [255 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d747;
wire [239 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d221;
wire [223 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d214;
wire [207 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d207;
wire [191 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d200;
wire [175 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d193;
wire [159 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d186;
wire [143 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d179;
wire [127 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d172;
wire [111 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d165;
wire [95 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d158;
wire [79 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d151;
wire [63 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d144;
wire [47 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d137;
wire [31 : 0] IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d130;
wire [7 : 0] IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d309,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d310,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d311,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d312,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d313,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d314,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d315,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d316,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d317,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d318,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d319,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d320,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d321,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d322,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d323,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d324,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d325,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d326,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d327,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d328,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d329,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d330,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d331,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d332,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d333,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d334,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d335,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d336,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d337,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d338,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d339,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d340,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d341,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d342,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d343,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d344,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d345,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d346,
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d347;
wire commandState_EQ_1_AND_inChar_first__7_EQ_0_8_O_ETC___d34,
commandState_EQ_1_OR_commandState_EQ_2_AND_NOT_ETC___d15,
inChar_first__7_ULE_32___d745,
responseState_74_EQ_1_76_AND_responses_first___ETC___d572,
responseState_74_EQ_1_76_OR_responseState_74_E_ETC___d564;
// action method stream_request_put
assign RDY_stream_request_put = inChar$FULL_N ;
// actionvalue method stream_response_get
assign stream_response_get = outChar$D_OUT ;
assign RDY_stream_response_get = outChar$EMPTY_N ;
// actionvalue method messages_request_get
assign messages_request_get =
{ CASE_commandsD_OUT_BITS_271_TO_264_32_0_comma_ETC__q1,
commands$D_OUT[263:0] } ;
assign RDY_messages_request_get = commands$EMPTY_N ;
// action method messages_response_put
assign RDY_messages_response_put = responses$FULL_N ;
// submodule commands
FIFO1 #(.width(32'd272), .guarded(32'd1)) commands(.RST_N(RST_N),
.CLK(CLK),
.D_IN(commands$D_IN),
.ENQ(commands$ENQ),
.DEQ(commands$DEQ),
.CLR(commands$CLR),
.D_OUT(commands$D_OUT),
.FULL_N(commands$FULL_N),
.EMPTY_N(commands$EMPTY_N));
// submodule inChar
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd1024),
.p3cntr_width(32'd10),
.guarded(32'd1)) inChar(.RST_N(RST_N),
.CLK(CLK),
.D_IN(inChar$D_IN),
.ENQ(inChar$ENQ),
.DEQ(inChar$DEQ),
.CLR(inChar$CLR),
.D_OUT(inChar$D_OUT),
.FULL_N(inChar$FULL_N),
.EMPTY_N(inChar$EMPTY_N));
// submodule outChar
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd1024),
.p3cntr_width(32'd10),
.guarded(32'd1)) outChar(.RST_N(RST_N),
.CLK(CLK),
.D_IN(outChar$D_IN),
.ENQ(outChar$ENQ),
.DEQ(outChar$DEQ),
.CLR(outChar$CLR),
.D_OUT(outChar$D_OUT),
.FULL_N(outChar$FULL_N),
.EMPTY_N(outChar$EMPTY_N));
// submodule responses
FIFO1 #(.width(32'd272), .guarded(32'd1)) responses(.RST_N(RST_N),
.CLK(CLK),
.D_IN(responses$D_IN),
.ENQ(responses$ENQ),
.DEQ(responses$DEQ),
.CLR(responses$CLR),
.D_OUT(responses$D_OUT),
.FULL_N(responses$FULL_N),
.EMPTY_N(responses$EMPTY_N));
// rule RL_getCommand
assign WILL_FIRE_RL_getCommand = inChar$EMPTY_N && commands$FULL_N ;
// rule RL_deliverResponse
assign WILL_FIRE_RL_deliverResponse = responses$EMPTY_N && outChar$FULL_N ;
// register command
assign command$D_IN =
{ IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d347,
IF_commandState_EQ_0_THEN_0b0_CONCAT_DONTCARE__ETC___d369 } ;
assign command$EN = WILL_FIRE_RL_getCommand ;
// register commandCount
assign commandCount$D_IN =
(commandState == 2'd1) ? 8'd0 : commandCount + 8'd1 ;
assign commandCount$EN =
WILL_FIRE_RL_getCommand &&
(commandState == 2'd1 && inChar$D_OUT != 8'd0 &&
inChar_first__7_ULE_32___d745 ||
commandState == 2'd2) ;
// register commandState
always@(commandState or inChar$D_OUT or inChar_first__7_ULE_32___d745)
begin
case (commandState)
2'd0: commandState$D_IN = 2'd1;
2'd1:
commandState$D_IN =
(inChar$D_OUT != 8'd0 && inChar_first__7_ULE_32___d745) ?
2'd2 :
2'd0;
default: commandState$D_IN = 2'd0;
endcase
end
assign commandState$EN =
WILL_FIRE_RL_getCommand &&
(commandState == 2'd0 ||
commandState_EQ_1_OR_commandState_EQ_2_AND_NOT_ETC___d15) ;
// register responseCount
assign responseCount$D_IN =
(responseState == 2'd1) ? 8'd0 : responseCount + 8'd1 ;
assign responseCount$EN =
WILL_FIRE_RL_deliverResponse &&
(responseState == 2'd1 && responses$D_OUT[263:256] != 8'd0 ||
responseState == 2'd2) ;
// register responseState
always@(responseState or responses$D_OUT)
begin
case (responseState)
2'd0: responseState$D_IN = 2'd1;
2'd1:
responseState$D_IN =
(responses$D_OUT[263:256] == 8'd0) ? 2'd0 : 2'd2;
default: responseState$D_IN = 2'd0;
endcase
end
assign responseState$EN =
WILL_FIRE_RL_deliverResponse &&
(responseState == 2'd0 ||
responseState_74_EQ_1_76_OR_responseState_74_E_ETC___d564) ;
// submodule commands
assign commands$D_IN =
{ CASE_command_BITS_271_TO_264_32_0_command_BITS_ETC__q2,
(commandState == 2'd1) ?
{ 8'd0, command[255:0] } :
{ command[263:256],
IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d747 } } ;
assign commands$ENQ =
WILL_FIRE_RL_getCommand && commandState != 2'd0 &&
commandState_EQ_1_AND_inChar_first__7_EQ_0_8_O_ETC___d34 ;
assign commands$DEQ = EN_messages_request_get ;
assign commands$CLR = 1'b0 ;
// submodule inChar
assign inChar$D_IN = stream_request_put ;
assign inChar$ENQ = EN_stream_request_put ;
assign inChar$DEQ = WILL_FIRE_RL_getCommand ;
assign inChar$CLR = 1'b0 ;
// submodule outChar
always@(responseState or x__h15152 or x__h14752 or responses$D_OUT)
begin
case (responseState)
2'd0: outChar$D_IN = x__h14752;
2'd1: outChar$D_IN = responses$D_OUT[263:256];
default: outChar$D_IN = x__h15152;
endcase
end
assign outChar$ENQ =
WILL_FIRE_RL_deliverResponse &&
(responseState == 2'd0 || responseState == 2'd1 ||
responseState == 2'd2) ;
assign outChar$DEQ = EN_stream_response_get ;
assign outChar$CLR = 1'b0 ;
// submodule responses
assign responses$D_IN =
{ CASE_messages_response_put_BITS_271_TO_264_32__ETC__q3,
messages_response_put[263:0] } ;
assign responses$ENQ = EN_messages_response_put ;
assign responses$DEQ =
WILL_FIRE_RL_deliverResponse && responseState != 2'd0 &&
responseState_74_EQ_1_76_AND_responses_first___ETC___d572 ;
assign responses$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d309 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd255 :
command[271:264] == 8'd255) ?
8'd255 :
8'd32 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d310 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd211 :
command[271:264] == 8'd211) ?
8'd211 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d309 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d311 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd245 :
command[271:264] == 8'd245) ?
8'd245 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d310 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d312 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd227 :
command[271:264] == 8'd227) ?
8'd227 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d311 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d313 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd244 :
command[271:264] == 8'd244) ?
8'd244 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d312 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d314 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd243 :
command[271:264] == 8'd243) ?
8'd243 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d313 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d315 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd242 :
command[271:264] == 8'd242) ?
8'd242 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d314 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d316 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd240 :
command[271:264] == 8'd240) ?
8'd240 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d315 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d317 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd228 :
command[271:264] == 8'd228) ?
8'd228 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d316 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d318 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd197 :
command[271:264] == 8'd197) ?
8'd197 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d317 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d319 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd229 :
command[271:264] == 8'd229) ?
8'd229 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d318 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d320 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd205 :
command[271:264] == 8'd205) ?
8'd205 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d319 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d321 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd195 :
command[271:264] == 8'd195) ?
8'd195 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d320 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d322 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd179 :
command[271:264] == 8'd179) ?
8'd179 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d321 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d323 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd178 :
command[271:264] == 8'd178) ?
8'd178 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d322 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d324 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd177 :
command[271:264] == 8'd177) ?
8'd177 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d323 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d325 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd176 :
command[271:264] == 8'd176) ?
8'd176 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d324 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d326 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd226 :
command[271:264] == 8'd226) ?
8'd226 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d325 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d327 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd225 :
command[271:264] == 8'd225) ?
8'd225 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d326 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d328 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd233 :
command[271:264] == 8'd233) ?
8'd233 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d327 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d329 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd83 :
command[271:264] == 8'd83) ?
8'd83 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d328 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d330 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd116 :
command[271:264] == 8'd116) ?
8'd116 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d329 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d331 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd117 :
command[271:264] == 8'd117) ?
8'd117 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d330 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d332 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd99 :
command[271:264] == 8'd99) ?
8'd99 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d331 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d333 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd115 :
command[271:264] == 8'd115) ?
8'd115 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d332 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d334 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd114 :
command[271:264] == 8'd114) ?
8'd114 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d333 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d335 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd112 :
command[271:264] == 8'd112) ?
8'd112 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d334 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d336 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd100 :
command[271:264] == 8'd100) ?
8'd100 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d335 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d337 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd101 :
command[271:264] == 8'd101) ?
8'd101 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d336 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d338 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd77 :
command[271:264] == 8'd77) ?
8'd77 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d337 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d339 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd67 :
command[271:264] == 8'd67) ?
8'd67 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d338 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d340 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd51 :
command[271:264] == 8'd51) ?
8'd51 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d339 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d341 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd50 :
command[271:264] == 8'd50) ?
8'd50 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d340 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d342 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd49 :
command[271:264] == 8'd49) ?
8'd49 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d341 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d343 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd48 :
command[271:264] == 8'd48) ?
8'd48 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d342 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d344 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd98 :
command[271:264] == 8'd98) ?
8'd98 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d343 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d345 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd97 :
command[271:264] == 8'd97) ?
8'd97 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d344 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d346 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd105 :
command[271:264] == 8'd105) ?
8'd105 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d345 ;
assign IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d347 =
((commandState == 2'd0) ?
inChar$D_OUT == 8'd0 :
command[271:264] == 8'd0) ?
8'd0 :
IF_IF_commandState_EQ_0_THEN_inChar_first__7_E_ETC___d346 ;
assign IF_NOT_inChar_first__7_EQ_0_8_9_AND_inChar_fir_ETC___d365 =
{ (inChar$D_OUT != 8'd0 && inChar_first__7_ULE_32___d745) ?
inChar$D_OUT :
8'd0,
command[255:0] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d130 =
{ (commandCount == 8'd31) ? inChar$D_OUT : command[255:248],
(commandCount == 8'd30) ? inChar$D_OUT : command[247:240],
(commandCount == 8'd29) ? inChar$D_OUT : command[239:232],
(commandCount == 8'd28) ? inChar$D_OUT : command[231:224] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d137 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d130,
(commandCount == 8'd27) ? inChar$D_OUT : command[223:216],
(commandCount == 8'd26) ? inChar$D_OUT : command[215:208] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d144 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d137,
(commandCount == 8'd25) ? inChar$D_OUT : command[207:200],
(commandCount == 8'd24) ? inChar$D_OUT : command[199:192] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d151 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d144,
(commandCount == 8'd23) ? inChar$D_OUT : command[191:184],
(commandCount == 8'd22) ? inChar$D_OUT : command[183:176] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d158 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d151,
(commandCount == 8'd21) ? inChar$D_OUT : command[175:168],
(commandCount == 8'd20) ? inChar$D_OUT : command[167:160] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d165 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d158,
(commandCount == 8'd19) ? inChar$D_OUT : command[159:152],
(commandCount == 8'd18) ? inChar$D_OUT : command[151:144] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d172 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d165,
(commandCount == 8'd17) ? inChar$D_OUT : command[143:136],
(commandCount == 8'd16) ? inChar$D_OUT : command[135:128] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d179 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d172,
(commandCount == 8'd15) ? inChar$D_OUT : command[127:120],
(commandCount == 8'd14) ? inChar$D_OUT : command[119:112] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d186 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d179,
(commandCount == 8'd13) ? inChar$D_OUT : command[111:104],
(commandCount == 8'd12) ? inChar$D_OUT : command[103:96] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d193 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d186,
(commandCount == 8'd11) ? inChar$D_OUT : command[95:88],
(commandCount == 8'd10) ? inChar$D_OUT : command[87:80] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d200 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d193,
(commandCount == 8'd9) ? inChar$D_OUT : command[79:72],
(commandCount == 8'd8) ? inChar$D_OUT : command[71:64] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d207 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d200,
(commandCount == 8'd7) ? inChar$D_OUT : command[63:56],
(commandCount == 8'd6) ? inChar$D_OUT : command[55:48] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d214 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d207,
(commandCount == 8'd5) ? inChar$D_OUT : command[47:40],
(commandCount == 8'd4) ? inChar$D_OUT : command[39:32] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d221 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d214,
(commandCount == 8'd3) ? inChar$D_OUT : command[31:24],
(commandCount == 8'd2) ? inChar$D_OUT : command[23:16] } ;
assign IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d747 =
{ IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d221,
(commandCount == 8'd1) ? inChar$D_OUT : command[15:8],
(commandCount == 8'd0) ? inChar$D_OUT : command[7:0] } ;
assign commandState_EQ_1_AND_inChar_first__7_EQ_0_8_O_ETC___d34 =
commandState == 2'd1 &&
(inChar$D_OUT == 8'd0 || !inChar_first__7_ULE_32___d745) ||
commandState == 2'd2 && commandCount >= command[263:256] - 8'd1 ;
assign commandState_EQ_1_OR_commandState_EQ_2_AND_NOT_ETC___d15 =
commandState == 2'd1 ||
commandState == 2'd2 && commandCount >= command[263:256] - 8'd1 ;
assign inChar_first__7_ULE_32___d745 = inChar$D_OUT <= 8'd32 ;
assign responseState_74_EQ_1_76_AND_responses_first___ETC___d572 =
responseState == 2'd1 && responses$D_OUT[263:256] == 8'd0 ||
responseState == 2'd2 &&
responseCount >= responses$D_OUT[263:256] - 8'd1 ;
assign responseState_74_EQ_1_76_OR_responseState_74_E_ETC___d564 =
responseState == 2'd1 ||
responseState == 2'd2 &&
responseCount >= responses$D_OUT[263:256] - 8'd1 ;
always@(commands$D_OUT)
begin
case (commands$D_OUT[271:264])
8'd0,
8'd48,
8'd49,
8'd50,
8'd51,
8'd67,
8'd77,
8'd83,
8'd97,
8'd98,
8'd99,
8'd100,
8'd101,
8'd105,
8'd112,
8'd114,
8'd115,
8'd116,
8'd117,
8'd176,
8'd177,
8'd178,
8'd179,
8'd195,
8'd197,
8'd205,
8'd211,
8'd225,
8'd226,
8'd227,
8'd228,
8'd229,
8'd233,
8'd240,
8'd242,
8'd243,
8'd244,
8'd245,
8'd255:
CASE_commandsD_OUT_BITS_271_TO_264_32_0_comma_ETC__q1 =
commands$D_OUT[271:264];
default: CASE_commandsD_OUT_BITS_271_TO_264_32_0_comma_ETC__q1 = 8'd32;
endcase
end
always@(responseCount or responses$D_OUT)
begin
case (responseCount)
8'd0: x__h15152 = responses$D_OUT[7:0];
8'd1: x__h15152 = responses$D_OUT[15:8];
8'd2: x__h15152 = responses$D_OUT[23:16];
8'd3: x__h15152 = responses$D_OUT[31:24];
8'd4: x__h15152 = responses$D_OUT[39:32];
8'd5: x__h15152 = responses$D_OUT[47:40];
8'd6: x__h15152 = responses$D_OUT[55:48];
8'd7: x__h15152 = responses$D_OUT[63:56];
8'd8: x__h15152 = responses$D_OUT[71:64];
8'd9: x__h15152 = responses$D_OUT[79:72];
8'd10: x__h15152 = responses$D_OUT[87:80];
8'd11: x__h15152 = responses$D_OUT[95:88];
8'd12: x__h15152 = responses$D_OUT[103:96];
8'd13: x__h15152 = responses$D_OUT[111:104];
8'd14: x__h15152 = responses$D_OUT[119:112];
8'd15: x__h15152 = responses$D_OUT[127:120];
8'd16: x__h15152 = responses$D_OUT[135:128];
8'd17: x__h15152 = responses$D_OUT[143:136];
8'd18: x__h15152 = responses$D_OUT[151:144];
8'd19: x__h15152 = responses$D_OUT[159:152];
8'd20: x__h15152 = responses$D_OUT[167:160];
8'd21: x__h15152 = responses$D_OUT[175:168];
8'd22: x__h15152 = responses$D_OUT[183:176];
8'd23: x__h15152 = responses$D_OUT[191:184];
8'd24: x__h15152 = responses$D_OUT[199:192];
8'd25: x__h15152 = responses$D_OUT[207:200];
8'd26: x__h15152 = responses$D_OUT[215:208];
8'd27: x__h15152 = responses$D_OUT[223:216];
8'd28: x__h15152 = responses$D_OUT[231:224];
8'd29: x__h15152 = responses$D_OUT[239:232];
8'd30: x__h15152 = responses$D_OUT[247:240];
default: x__h15152 = responses$D_OUT[255:248];
endcase
end
always@(responses$D_OUT)
begin
case (responses$D_OUT[271:264])
8'd0,
8'd48,
8'd49,
8'd50,
8'd51,
8'd67,
8'd77,
8'd83,
8'd97,
8'd98,
8'd99,
8'd100,
8'd101,
8'd105,
8'd112,
8'd114,
8'd115,
8'd116,
8'd117,
8'd176,
8'd177,
8'd178,
8'd179,
8'd195,
8'd197,
8'd205,
8'd211,
8'd225,
8'd226,
8'd227,
8'd228,
8'd229,
8'd233,
8'd240,
8'd242,
8'd243,
8'd244,
8'd245,
8'd255:
x__h14752 = responses$D_OUT[271:264];
default: x__h14752 = 8'd32;
endcase
end
always@(commandState or
command or
IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d747 or
IF_NOT_inChar_first__7_EQ_0_8_9_AND_inChar_fir_ETC___d365)
begin
case (commandState)
2'd0:
IF_commandState_EQ_0_THEN_0b0_CONCAT_DONTCARE__ETC___d369 =
{ 8'b0, command[255:0] };
2'd1:
IF_commandState_EQ_0_THEN_0b0_CONCAT_DONTCARE__ETC___d369 =
IF_NOT_inChar_first__7_EQ_0_8_9_AND_inChar_fir_ETC___d365;
default: IF_commandState_EQ_0_THEN_0b0_CONCAT_DONTCARE__ETC___d369 =
{ command[263:256],
(commandState == 2'd2) ?
IF_commandCount_EQ_31_17_THEN_inChar_first__7__ETC___d747 :
command[255:0] };
endcase
end
always@(command)
begin
case (command[271:264])
8'd0,
8'd48,
8'd49,
8'd50,
8'd51,
8'd67,
8'd77,
8'd83,
8'd97,
8'd98,
8'd99,
8'd100,
8'd101,
8'd105,
8'd112,
8'd114,
8'd115,
8'd116,
8'd117,
8'd176,
8'd177,
8'd178,
8'd179,
8'd195,
8'd197,
8'd205,
8'd211,
8'd225,
8'd226,
8'd227,
8'd228,
8'd229,
8'd233,
8'd240,
8'd242,
8'd243,
8'd244,
8'd245,
8'd255:
CASE_command_BITS_271_TO_264_32_0_command_BITS_ETC__q2 =
command[271:264];
default: CASE_command_BITS_271_TO_264_32_0_command_BITS_ETC__q2 = 8'd32;
endcase
end
always@(messages_response_put)
begin
case (messages_response_put[271:264])
8'd0,
8'd48,
8'd49,
8'd50,
8'd51,
8'd67,
8'd77,
8'd83,
8'd97,
8'd98,
8'd99,
8'd100,
8'd101,
8'd105,
8'd112,
8'd114,
8'd115,
8'd116,
8'd117,
8'd176,
8'd177,
8'd178,
8'd179,
8'd195,
8'd197,
8'd205,
8'd211,
8'd225,
8'd226,
8'd227,
8'd228,
8'd229,
8'd233,
8'd240,
8'd242,
8'd243,
8'd244,
8'd245,
8'd255:
CASE_messages_response_put_BITS_271_TO_264_32__ETC__q3 =
messages_response_put[271:264];
default: CASE_messages_response_put_BITS_271_TO_264_32__ETC__q3 = 8'd32;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
commandCount <= `BSV_ASSIGNMENT_DELAY 8'd0;
commandState <= `BSV_ASSIGNMENT_DELAY 2'd0;
responseCount <= `BSV_ASSIGNMENT_DELAY 8'd0;
responseState <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (commandCount$EN)
commandCount <= `BSV_ASSIGNMENT_DELAY commandCount$D_IN;
if (commandState$EN)
commandState <= `BSV_ASSIGNMENT_DELAY commandState$D_IN;
if (responseCount$EN)
responseCount <= `BSV_ASSIGNMENT_DELAY responseCount$D_IN;
if (responseState$EN)
responseState <= `BSV_ASSIGNMENT_DELAY responseState$D_IN;
end
if (command$EN) command <= `BSV_ASSIGNMENT_DELAY command$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
command =
272'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commandCount = 8'hAA;
commandState = 2'h2;
responseCount = 8'hAA;
responseState = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkDebugConvert
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:44:40 BST 2012
//
// Method conflict info:
// Method: cache_request_put
// Conflict-free: cache_response_get, memory_request_get, memory_response_put
// Conflicts: cache_request_put
//
// Method: cache_response_get
// Conflict-free: cache_request_put, memory_request_get
// Sequenced after (restricted): memory_response_put
// Conflicts: cache_response_get
//
// Method: memory_request_get
// Conflict-free: cache_request_put, cache_response_get, memory_response_put
// Conflicts: memory_request_get
//
// Method: memory_response_put
// Conflict-free: cache_request_put, memory_request_get
// Sequenced before (restricted): cache_response_get
// Conflicts: memory_response_put
//
//
// Ports:
// Name I/O size props
// RDY_cache_request_put O 1
// cache_response_get O 256
// RDY_cache_response_get O 1
// memory_request_get O 317
// RDY_memory_request_get O 1
// RDY_memory_response_put O 1
// CLK I 1 clock
// RST_N I 1 reset
// cache_request_put I 317 reg
// memory_response_put I 256
// EN_cache_request_put I 1
// EN_memory_response_put I 1
// EN_cache_response_get I 1
// EN_memory_request_get I 1
//
// Combinational paths from inputs to outputs:
// (memory_response_put, EN_memory_response_put) -> cache_response_get
// EN_memory_response_put -> RDY_cache_response_get
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkL2Cache(CLK,
RST_N,
cache_request_put,
EN_cache_request_put,
RDY_cache_request_put,
EN_cache_response_get,
cache_response_get,
RDY_cache_response_get,
EN_memory_request_get,
memory_request_get,
RDY_memory_request_get,
memory_response_put,
EN_memory_response_put,
RDY_memory_response_put);
input CLK;
input RST_N;
// action method cache_request_put
input [316 : 0] cache_request_put;
input EN_cache_request_put;
output RDY_cache_request_put;
// actionvalue method cache_response_get
input EN_cache_response_get;
output [255 : 0] cache_response_get;
output RDY_cache_response_get;
// actionvalue method memory_request_get
input EN_memory_request_get;
output [316 : 0] memory_request_get;
output RDY_memory_request_get;
// action method memory_response_put
input [255 : 0] memory_response_put;
input EN_memory_response_put;
output RDY_memory_response_put;
// signals for module outputs
wire [316 : 0] memory_request_get;
wire [255 : 0] cache_response_get;
wire RDY_cache_request_put,
RDY_cache_response_get,
RDY_memory_request_get,
RDY_memory_response_put;
// inlined wires
wire [316 : 0] memReq_fifo_rw_enq$wget;
wire [255 : 0] out_fifo_rw_enq$wget;
wire memReq_fifo_rw_enq$whas, out_fifo_rw_enq$whas;
// register addrReg
reg [31 : 0] addrReg;
wire [31 : 0] addrReg$D_IN;
wire addrReg$EN;
// register bank_lastReadAddrA
reg [10 : 0] bank_lastReadAddrA;
wire [10 : 0] bank_lastReadAddrA$D_IN;
wire bank_lastReadAddrA$EN;
// register bank_lastReadAddrA_1
reg [10 : 0] bank_lastReadAddrA_1;
wire [10 : 0] bank_lastReadAddrA_1$D_IN;
wire bank_lastReadAddrA_1$EN;
// register bank_lastReadAddrA_2
reg [10 : 0] bank_lastReadAddrA_2;
wire [10 : 0] bank_lastReadAddrA_2$D_IN;
wire bank_lastReadAddrA_2$EN;
// register bank_lastReadAddrA_3
reg [10 : 0] bank_lastReadAddrA_3;
wire [10 : 0] bank_lastReadAddrA_3$D_IN;
wire bank_lastReadAddrA_3$EN;
// register bank_lastReadAddrB
reg [10 : 0] bank_lastReadAddrB;
wire [10 : 0] bank_lastReadAddrB$D_IN;
wire bank_lastReadAddrB$EN;
// register bank_lastReadAddrB_1
reg [10 : 0] bank_lastReadAddrB_1;
wire [10 : 0] bank_lastReadAddrB_1$D_IN;
wire bank_lastReadAddrB_1$EN;
// register bank_lastReadAddrB_2
reg [10 : 0] bank_lastReadAddrB_2;
wire [10 : 0] bank_lastReadAddrB_2$D_IN;
wire bank_lastReadAddrB_2$EN;
// register bank_lastReadAddrB_3
reg [10 : 0] bank_lastReadAddrB_3;
wire [10 : 0] bank_lastReadAddrB_3$D_IN;
wire bank_lastReadAddrB_3$EN;
// register bank_lastWriteAddrA
reg [10 : 0] bank_lastWriteAddrA;
wire [10 : 0] bank_lastWriteAddrA$D_IN;
wire bank_lastWriteAddrA$EN;
// register bank_lastWriteAddrA_1
reg [10 : 0] bank_lastWriteAddrA_1;
wire [10 : 0] bank_lastWriteAddrA_1$D_IN;
wire bank_lastWriteAddrA_1$EN;
// register bank_lastWriteAddrA_2
reg [10 : 0] bank_lastWriteAddrA_2;
wire [10 : 0] bank_lastWriteAddrA_2$D_IN;
wire bank_lastWriteAddrA_2$EN;
// register bank_lastWriteAddrA_3
reg [10 : 0] bank_lastWriteAddrA_3;
wire [10 : 0] bank_lastWriteAddrA_3$D_IN;
wire bank_lastWriteAddrA_3$EN;
// register bank_lastWriteAddrB
reg [10 : 0] bank_lastWriteAddrB;
wire [10 : 0] bank_lastWriteAddrB$D_IN;
wire bank_lastWriteAddrB$EN;
// register bank_lastWriteAddrB_1
reg [10 : 0] bank_lastWriteAddrB_1;
wire [10 : 0] bank_lastWriteAddrB_1$D_IN;
wire bank_lastWriteAddrB_1$EN;
// register bank_lastWriteAddrB_2
reg [10 : 0] bank_lastWriteAddrB_2;
wire [10 : 0] bank_lastWriteAddrB_2$D_IN;
wire bank_lastWriteAddrB_2$EN;
// register bank_lastWriteAddrB_3
reg [10 : 0] bank_lastWriteAddrB_3;
wire [10 : 0] bank_lastWriteAddrB_3$D_IN;
wire bank_lastWriteAddrB_3$EN;
// register bank_lastWriteDataA
reg [63 : 0] bank_lastWriteDataA;
wire [63 : 0] bank_lastWriteDataA$D_IN;
wire bank_lastWriteDataA$EN;
// register bank_lastWriteDataA_1
reg [63 : 0] bank_lastWriteDataA_1;
wire [63 : 0] bank_lastWriteDataA_1$D_IN;
wire bank_lastWriteDataA_1$EN;
// register bank_lastWriteDataA_2
reg [63 : 0] bank_lastWriteDataA_2;
wire [63 : 0] bank_lastWriteDataA_2$D_IN;
wire bank_lastWriteDataA_2$EN;
// register bank_lastWriteDataA_3
reg [63 : 0] bank_lastWriteDataA_3;
wire [63 : 0] bank_lastWriteDataA_3$D_IN;
wire bank_lastWriteDataA_3$EN;
// register bank_lastWriteDataB
reg [63 : 0] bank_lastWriteDataB;
wire [63 : 0] bank_lastWriteDataB$D_IN;
wire bank_lastWriteDataB$EN;
// register bank_lastWriteDataB_1
reg [63 : 0] bank_lastWriteDataB_1;
wire [63 : 0] bank_lastWriteDataB_1$D_IN;
wire bank_lastWriteDataB_1$EN;
// register bank_lastWriteDataB_2
reg [63 : 0] bank_lastWriteDataB_2;
wire [63 : 0] bank_lastWriteDataB_2$D_IN;
wire bank_lastWriteDataB_2$EN;
// register bank_lastWriteDataB_3
reg [63 : 0] bank_lastWriteDataB_3;
wire [63 : 0] bank_lastWriteDataB_3$D_IN;
wire bank_lastWriteDataB_3$EN;
// register byteWriteReg_0
reg [7 : 0] byteWriteReg_0;
wire [7 : 0] byteWriteReg_0$D_IN;
wire byteWriteReg_0$EN;
// register byteWriteReg_1
reg [7 : 0] byteWriteReg_1;
wire [7 : 0] byteWriteReg_1$D_IN;
wire byteWriteReg_1$EN;
// register byteWriteReg_2
reg [7 : 0] byteWriteReg_2;
wire [7 : 0] byteWriteReg_2$D_IN;
wire byteWriteReg_2$EN;
// register byteWriteReg_3
reg [7 : 0] byteWriteReg_3;
wire [7 : 0] byteWriteReg_3$D_IN;
wire byteWriteReg_3$EN;
// register cacheState
reg [1 : 0] cacheState;
wire [1 : 0] cacheState$D_IN;
wire cacheState$EN;
// register count
reg [10 : 0] count;
wire [10 : 0] count$D_IN;
wire count$EN;
// register dataReg
reg [255 : 0] dataReg;
wire [255 : 0] dataReg$D_IN;
wire dataReg$EN;
// register memReq_fifo_taggedReg
reg [317 : 0] memReq_fifo_taggedReg;
wire [317 : 0] memReq_fifo_taggedReg$D_IN;
wire memReq_fifo_taggedReg$EN;
// register memResp_fifo_taggedReg
reg [256 : 0] memResp_fifo_taggedReg;
wire [256 : 0] memResp_fifo_taggedReg$D_IN;
wire memResp_fifo_taggedReg$EN;
// register missCached
reg missCached;
wire missCached$D_IN, missCached$EN;
// register missWriteReg
reg missWriteReg;
wire missWriteReg$D_IN, missWriteReg$EN;
// register out_fifo_taggedReg
reg [256 : 0] out_fifo_taggedReg;
wire [256 : 0] out_fifo_taggedReg$D_IN;
wire out_fifo_taggedReg$EN;
// register tags_lastReadAddrA
reg [10 : 0] tags_lastReadAddrA;
wire [10 : 0] tags_lastReadAddrA$D_IN;
wire tags_lastReadAddrA$EN;
// register tags_lastReadAddrB
reg [10 : 0] tags_lastReadAddrB;
wire [10 : 0] tags_lastReadAddrB$D_IN;
wire tags_lastReadAddrB$EN;
// register tags_lastWriteAddrA
reg [10 : 0] tags_lastWriteAddrA;
wire [10 : 0] tags_lastWriteAddrA$D_IN;
wire tags_lastWriteAddrA$EN;
// register tags_lastWriteAddrB
reg [10 : 0] tags_lastWriteAddrB;
reg [10 : 0] tags_lastWriteAddrB$D_IN;
wire tags_lastWriteAddrB$EN;
// register tags_lastWriteDataA
reg [17 : 0] tags_lastWriteDataA;
wire [17 : 0] tags_lastWriteDataA$D_IN;
wire tags_lastWriteDataA$EN;
// register tags_lastWriteDataB
reg [17 : 0] tags_lastWriteDataB;
reg [17 : 0] tags_lastWriteDataB$D_IN;
wire tags_lastWriteDataB$EN;
// register updateReg
reg [255 : 0] updateReg;
wire [255 : 0] updateReg$D_IN;
wire updateReg$EN;
// ports of submodule bank_bram
wire [63 : 0] bank_bram$DIA, bank_bram$DIB, bank_bram$DOA;
wire [10 : 0] bank_bram$ADDRA, bank_bram$ADDRB;
wire bank_bram$ENA, bank_bram$ENB, bank_bram$WEA, bank_bram$WEB;
// ports of submodule bank_bram_1
wire [63 : 0] bank_bram_1$DIA, bank_bram_1$DIB, bank_bram_1$DOA;
wire [10 : 0] bank_bram_1$ADDRA, bank_bram_1$ADDRB;
wire bank_bram_1$ENA, bank_bram_1$ENB, bank_bram_1$WEA, bank_bram_1$WEB;
// ports of submodule bank_bram_2
wire [63 : 0] bank_bram_2$DIA, bank_bram_2$DIB, bank_bram_2$DOA;
wire [10 : 0] bank_bram_2$ADDRA, bank_bram_2$ADDRB;
wire bank_bram_2$ENA, bank_bram_2$ENB, bank_bram_2$WEA, bank_bram_2$WEB;
// ports of submodule bank_bram_3
wire [63 : 0] bank_bram_3$DIA, bank_bram_3$DIB, bank_bram_3$DOA;
wire [10 : 0] bank_bram_3$ADDRA, bank_bram_3$ADDRB;
wire bank_bram_3$ENA, bank_bram_3$ENB, bank_bram_3$WEA, bank_bram_3$WEB;
// ports of submodule evict_fifo
wire [287 : 0] evict_fifo$D_IN, evict_fifo$D_OUT;
wire evict_fifo$CLR,
evict_fifo$DEQ,
evict_fifo$EMPTY_N,
evict_fifo$ENQ,
evict_fifo$FULL_N;
// ports of submodule req_fifo
wire [316 : 0] req_fifo$D_IN, req_fifo$D_OUT;
wire req_fifo$CLR,
req_fifo$DEQ,
req_fifo$EMPTY_N,
req_fifo$ENQ,
req_fifo$FULL_N;
// ports of submodule tags_bram
reg [17 : 0] tags_bram$DIB;
reg [10 : 0] tags_bram$ADDRB;
wire [17 : 0] tags_bram$DIA, tags_bram$DOA;
wire [10 : 0] tags_bram$ADDRA;
wire tags_bram$ENA, tags_bram$ENB, tags_bram$WEA, tags_bram$WEB;
// ports of submodule tags_fifo
wire [17 : 0] tags_fifo$D_IN;
wire tags_fifo$CLR, tags_fifo$DEQ, tags_fifo$ENQ;
// ports of submodule toServing_fifo
wire toServing_fifo$CLR,
toServing_fifo$DEQ,
toServing_fifo$D_IN,
toServing_fifo$EMPTY_N,
toServing_fifo$ENQ,
toServing_fifo$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_clearNewRequests,
WILL_FIRE_RL_getCacheResponse,
WILL_FIRE_RL_memReq_fifo_rule_enq,
WILL_FIRE_RL_memResp_fifo_rule_deq,
WILL_FIRE_RL_memResp_fifo_rule_enq,
WILL_FIRE_RL_out_fifo_rule_enq;
// inputs to muxes for submodule ports
wire [317 : 0] MUX_memReq_fifo_taggedReg$write_1__VAL_1;
wire [316 : 0] MUX_memReq_fifo_rw_enq$wset_1__VAL_1,
MUX_memReq_fifo_rw_enq$wset_1__VAL_2;
wire [256 : 0] MUX_memResp_fifo_taggedReg$write_1__VAL_1,
MUX_out_fifo_taggedReg$write_1__VAL_1;
wire [63 : 0] MUX_bank_bram$b_put_3__VAL_1,
MUX_bank_bram$b_put_3__VAL_2,
MUX_bank_bram_1$b_put_3__VAL_1,
MUX_bank_bram_1$b_put_3__VAL_2,
MUX_bank_bram_2$b_put_3__VAL_1,
MUX_bank_bram_2$b_put_3__VAL_2,
MUX_bank_bram_3$b_put_3__VAL_1,
MUX_bank_bram_3$b_put_3__VAL_2;
wire [17 : 0] MUX_tags_bram$b_put_3__VAL_1, MUX_tags_bram$b_put_3__VAL_2;
wire MUX_bank_bram$b_put_1__SEL_1,
MUX_cacheState$write_1__SEL_1,
MUX_cacheState$write_1__SEL_2,
MUX_memReq_fifo_rw_enq$wset_1__SEL_1,
MUX_memReq_fifo_rw_enq$wset_1__SEL_2,
MUX_out_fifo_rw_enq$wset_1__SEL_1,
MUX_tags_bram$b_put_1__SEL_2;
// remaining internal signals
wire [255 : 0] resp__h13851, v__h4661;
wire [63 : 0] IF_bank_lastReadAddrA_1_read__35_EQ_bank_lastW_ETC___d580,
IF_bank_lastReadAddrA_2_read__88_EQ_bank_lastW_ETC___d574,
IF_bank_lastReadAddrA_3_read__41_EQ_bank_lastW_ETC___d569,
IF_bank_lastReadAddrA_read__2_EQ_bank_lastWrit_ETC___d586,
IF_req_fifo_first__0_BIT_10_33_THEN_IF_req_fif_ETC___d578,
IF_req_fifo_first__0_BIT_11_32_THEN_IF_req_fif_ETC___d577,
IF_req_fifo_first__0_BIT_12_31_THEN_IF_req_fif_ETC___d576,
IF_req_fifo_first__0_BIT_13_30_THEN_IF_req_fif_ETC___d575,
IF_req_fifo_first__0_BIT_14_29_THEN_IF_req_fif_ETC___d547,
IF_req_fifo_first__0_BIT_15_28_THEN_IF_req_fif_ETC___d555,
IF_req_fifo_first__0_BIT_16_26_THEN_req_fifo_f_ETC___d589,
IF_req_fifo_first__0_BIT_17_87_THEN_IF_bank_la_ETC___d573,
IF_req_fifo_first__0_BIT_18_86_THEN_IF_req_fif_ETC___d572,
IF_req_fifo_first__0_BIT_19_85_THEN_IF_req_fif_ETC___d548,
IF_req_fifo_first__0_BIT_1_1_THEN_IF_bank_last_ETC___d585,
IF_req_fifo_first__0_BIT_20_84_THEN_IF_req_fif_ETC___d571,
IF_req_fifo_first__0_BIT_21_83_THEN_IF_req_fif_ETC___d570,
IF_req_fifo_first__0_BIT_22_82_THEN_IF_req_fif_ETC___d592,
IF_req_fifo_first__0_BIT_23_81_THEN_IF_req_fif_ETC___d554,
IF_req_fifo_first__0_BIT_24_79_THEN_req_fifo_f_ETC___d588,
IF_req_fifo_first__0_BIT_25_40_THEN_IF_bank_la_ETC___d568,
IF_req_fifo_first__0_BIT_26_39_THEN_IF_req_fif_ETC___d567,
IF_req_fifo_first__0_BIT_27_38_THEN_IF_req_fif_ETC___d566,
IF_req_fifo_first__0_BIT_28_37_THEN_IF_req_fif_ETC___d565,
IF_req_fifo_first__0_BIT_29_36_THEN_IF_req_fif_ETC___d564,
IF_req_fifo_first__0_BIT_2_0_THEN_IF_req_fifo__ETC___d584,
IF_req_fifo_first__0_BIT_30_35_THEN_IF_req_fif_ETC___d591,
IF_req_fifo_first__0_BIT_31_34_THEN_IF_req_fif_ETC___d553,
IF_req_fifo_first__0_BIT_32_32_THEN_req_fifo_f_ETC___d587,
IF_req_fifo_first__0_BIT_3_9_THEN_IF_req_fifo__ETC___d583,
IF_req_fifo_first__0_BIT_4_8_THEN_IF_req_fifo__ETC___d582,
IF_req_fifo_first__0_BIT_5_7_THEN_IF_req_fifo__ETC___d581,
IF_req_fifo_first__0_BIT_6_6_THEN_IF_req_fifo__ETC___d593,
IF_req_fifo_first__0_BIT_7_5_THEN_IF_req_fifo__ETC___d557,
IF_req_fifo_first__0_BIT_8_3_THEN_req_fifo_fir_ETC___d590,
IF_req_fifo_first__0_BIT_9_34_THEN_IF_bank_las_ETC___d579;
wire [31 : 0] byteenable__h4327, x_addr__h12399;
wire [15 : 0] x_a_read_tag__h4514;
wire [7 : 0] IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_0_ETC___d382,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_1_ETC___d377,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_2_ETC___d372,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_3_ETC___d367,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_4_ETC___d362,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_5_ETC___d357,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_6_ETC___d352,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_7_ETC___d347,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_0_ETC___d427,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_1_ETC___d422,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_2_ETC___d417,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_3_ETC___d412,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_4_ETC___d407,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_5_ETC___d402,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_6_ETC___d397,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_7_ETC___d392,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_0_ETC___d472,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_1_ETC___d467,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_2_ETC___d462,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_3_ETC___d457,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_4_ETC___d452,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_5_ETC___d447,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_6_ETC___d442,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_7_ETC___d437,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_0_ETC___d517,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_1_ETC___d512,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_2_ETC___d507,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_3_ETC___d502,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_4_ETC___d497,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_5_ETC___d492,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_6_ETC___d487,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_7_ETC___d482;
wire IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d317,
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607,
NOT_req_fifo_first__0_BITS_315_TO_300_5_EQ_IF__ETC___d296,
_dand1req_fifo$EN_deq,
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558,
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d65,
tags_lastReadAddrA_read__6_EQ_tags_lastWriteAd_ETC___d622;
// action method cache_request_put
assign RDY_cache_request_put = req_fifo$FULL_N ;
// actionvalue method cache_response_get
assign cache_response_get =
out_fifo_rw_enq$whas ?
out_fifo_rw_enq$wget :
out_fifo_taggedReg[255:0] ;
assign RDY_cache_response_get =
out_fifo_taggedReg[256] || out_fifo_rw_enq$whas ;
// actionvalue method memory_request_get
assign memory_request_get =
memReq_fifo_rw_enq$whas ?
memReq_fifo_rw_enq$wget :
memReq_fifo_taggedReg[316:0] ;
assign RDY_memory_request_get =
memReq_fifo_taggedReg[317] || memReq_fifo_rw_enq$whas ;
// action method memory_response_put
assign RDY_memory_response_put = !memResp_fifo_taggedReg[256] ;
// submodule bank_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd64),
.MEMSIZE(12'd2048)) bank_bram(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bank_bram$ADDRA),
.ADDRB(bank_bram$ADDRB),
.DIA(bank_bram$DIA),
.DIB(bank_bram$DIB),
.WEA(bank_bram$WEA),
.WEB(bank_bram$WEB),
.ENA(bank_bram$ENA),
.ENB(bank_bram$ENB),
.DOA(bank_bram$DOA),
.DOB());
// submodule bank_bram_1
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd64),
.MEMSIZE(12'd2048)) bank_bram_1(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bank_bram_1$ADDRA),
.ADDRB(bank_bram_1$ADDRB),
.DIA(bank_bram_1$DIA),
.DIB(bank_bram_1$DIB),
.WEA(bank_bram_1$WEA),
.WEB(bank_bram_1$WEB),
.ENA(bank_bram_1$ENA),
.ENB(bank_bram_1$ENB),
.DOA(bank_bram_1$DOA),
.DOB());
// submodule bank_bram_2
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd64),
.MEMSIZE(12'd2048)) bank_bram_2(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bank_bram_2$ADDRA),
.ADDRB(bank_bram_2$ADDRB),
.DIA(bank_bram_2$DIA),
.DIB(bank_bram_2$DIB),
.WEA(bank_bram_2$WEA),
.WEB(bank_bram_2$WEB),
.ENA(bank_bram_2$ENA),
.ENB(bank_bram_2$ENB),
.DOA(bank_bram_2$DOA),
.DOB());
// submodule bank_bram_3
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd64),
.MEMSIZE(12'd2048)) bank_bram_3(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bank_bram_3$ADDRA),
.ADDRB(bank_bram_3$ADDRB),
.DIA(bank_bram_3$DIA),
.DIB(bank_bram_3$DIB),
.WEA(bank_bram_3$WEA),
.WEB(bank_bram_3$WEB),
.ENA(bank_bram_3$ENA),
.ENB(bank_bram_3$ENB),
.DOA(bank_bram_3$DOA),
.DOB());
// submodule evict_fifo
FIFO1 #(.width(32'd288), .guarded(32'd1)) evict_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(evict_fifo$D_IN),
.ENQ(evict_fifo$ENQ),
.DEQ(evict_fifo$DEQ),
.CLR(evict_fifo$CLR),
.D_OUT(evict_fifo$D_OUT),
.FULL_N(evict_fifo$FULL_N),
.EMPTY_N(evict_fifo$EMPTY_N));
// submodule req_fifo
FIFOL1 #(.width(32'd317)) req_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(req_fifo$D_IN),
.ENQ(req_fifo$ENQ),
.DEQ(req_fifo$DEQ),
.CLR(req_fifo$CLR),
.D_OUT(req_fifo$D_OUT),
.FULL_N(req_fifo$FULL_N),
.EMPTY_N(req_fifo$EMPTY_N));
// submodule tags_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd18),
.MEMSIZE(12'd2048)) tags_bram(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tags_bram$ADDRA),
.ADDRB(tags_bram$ADDRB),
.DIA(tags_bram$DIA),
.DIB(tags_bram$DIB),
.WEA(tags_bram$WEA),
.WEB(tags_bram$WEB),
.ENA(tags_bram$ENA),
.ENB(tags_bram$ENB),
.DOA(tags_bram$DOA),
.DOB());
// submodule tags_fifo
FIFOL1 #(.width(32'd18)) tags_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(tags_fifo$D_IN),
.ENQ(tags_fifo$ENQ),
.DEQ(tags_fifo$DEQ),
.CLR(tags_fifo$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule toServing_fifo
FIFO2 #(.width(32'd1), .guarded(32'd1)) toServing_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(toServing_fifo$D_IN),
.ENQ(toServing_fifo$ENQ),
.DEQ(toServing_fifo$DEQ),
.CLR(toServing_fifo$CLR),
.D_OUT(),
.FULL_N(toServing_fifo$FULL_N),
.EMPTY_N(toServing_fifo$EMPTY_N));
// rule RL_getCacheResponse
assign WILL_FIRE_RL_getCacheResponse =
req_fifo$EMPTY_N && !out_fifo_taggedReg[256] &&
!memReq_fifo_taggedReg[317] &&
evict_fifo$FULL_N &&
cacheState == 2'd1 ;
// rule RL_clearNewRequests
assign WILL_FIRE_RL_clearNewRequests =
req_fifo$EMPTY_N && toServing_fifo$EMPTY_N &&
cacheState == 2'd2 ;
// rule RL_out_fifo_rule_enq
assign WILL_FIRE_RL_out_fifo_rule_enq =
out_fifo_rw_enq$whas && !EN_cache_response_get ;
// rule RL_memReq_fifo_rule_enq
assign WILL_FIRE_RL_memReq_fifo_rule_enq =
memReq_fifo_rw_enq$whas && !EN_memory_request_get ;
// rule RL_memResp_fifo_rule_enq
assign WILL_FIRE_RL_memResp_fifo_rule_enq =
EN_memory_response_put && !WILL_FIRE_RL_memResp_fifo_rule_deq ;
// rule RL_memResp_fifo_rule_deq
assign WILL_FIRE_RL_memResp_fifo_rule_deq =
(memResp_fifo_taggedReg[256] || EN_memory_response_put) &&
toServing_fifo$FULL_N &&
!out_fifo_taggedReg[256] &&
cacheState == 2'd2 ;
// inputs to muxes for submodule ports
assign MUX_bank_bram$b_put_1__SEL_1 =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ;
assign MUX_cacheState$write_1__SEL_1 =
cacheState == 2'd0 && count == 11'd2047 ;
assign MUX_cacheState$write_1__SEL_2 =
WILL_FIRE_RL_getCacheResponse &&
(NOT_req_fifo_first__0_BITS_315_TO_300_5_EQ_IF__ETC___d296 ||
!req_fifo$D_OUT[0]) &&
(req_fifo$D_OUT[0] || !req_fifo$D_OUT[316]) ;
assign MUX_memReq_fifo_rw_enq$wset_1__SEL_1 =
WILL_FIRE_RL_getCacheResponse &&
(NOT_req_fifo_first__0_BITS_315_TO_300_5_EQ_IF__ETC___d296 ||
!req_fifo$D_OUT[0]) ;
assign MUX_memReq_fifo_rw_enq$wset_1__SEL_2 =
!memReq_fifo_taggedReg[317] && evict_fifo$EMPTY_N &&
cacheState == 2'd2 ;
assign MUX_out_fifo_rw_enq$wset_1__SEL_1 =
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
!req_fifo$D_OUT[316] ;
assign MUX_tags_bram$b_put_1__SEL_2 =
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d65 ;
assign MUX_bank_bram$b_put_3__VAL_1 =
{ IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_7_ETC___d347,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_6_ETC___d352,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_5_ETC___d357,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_4_ETC___d362,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_3_ETC___d367,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_2_ETC___d372,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_1_ETC___d377,
IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_0_ETC___d382 } ;
assign MUX_bank_bram$b_put_3__VAL_2 =
(req_fifo$D_OUT[316] &&
(req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 ||
!req_fifo$D_OUT[0])) ?
IF_req_fifo_first__0_BIT_8_3_THEN_req_fifo_fir_ETC___d590 :
IF_bank_lastReadAddrA_read__2_EQ_bank_lastWrit_ETC___d586 ;
assign MUX_bank_bram_1$b_put_3__VAL_1 =
{ IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_7_ETC___d392,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_6_ETC___d397,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_5_ETC___d402,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_4_ETC___d407,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_3_ETC___d412,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_2_ETC___d417,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_1_ETC___d422,
IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_0_ETC___d427 } ;
assign MUX_bank_bram_1$b_put_3__VAL_2 =
(req_fifo$D_OUT[316] &&
(req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 ||
!req_fifo$D_OUT[0])) ?
IF_req_fifo_first__0_BIT_16_26_THEN_req_fifo_f_ETC___d589 :
IF_bank_lastReadAddrA_1_read__35_EQ_bank_lastW_ETC___d580 ;
assign MUX_bank_bram_2$b_put_3__VAL_1 =
{ IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_7_ETC___d437,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_6_ETC___d442,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_5_ETC___d447,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_4_ETC___d452,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_3_ETC___d457,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_2_ETC___d462,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_1_ETC___d467,
IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_0_ETC___d472 } ;
assign MUX_bank_bram_2$b_put_3__VAL_2 =
(req_fifo$D_OUT[316] &&
(req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 ||
!req_fifo$D_OUT[0])) ?
IF_req_fifo_first__0_BIT_24_79_THEN_req_fifo_f_ETC___d588 :
IF_bank_lastReadAddrA_2_read__88_EQ_bank_lastW_ETC___d574 ;
assign MUX_bank_bram_3$b_put_3__VAL_1 =
{ IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_7_ETC___d482,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_6_ETC___d487,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_5_ETC___d492,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_4_ETC___d497,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_3_ETC___d502,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_2_ETC___d507,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_1_ETC___d512,
IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_0_ETC___d517 } ;
assign MUX_bank_bram_3$b_put_3__VAL_2 =
(req_fifo$D_OUT[316] &&
(req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 ||
!req_fifo$D_OUT[0])) ?
IF_req_fifo_first__0_BIT_32_32_THEN_req_fifo_f_ETC___d587 :
IF_bank_lastReadAddrA_3_read__41_EQ_bank_lastW_ETC___d569 ;
assign MUX_memReq_fifo_rw_enq$wset_1__VAL_1 =
{ req_fifo$D_OUT[316] && !req_fifo$D_OUT[0],
req_fifo$D_OUT[315:289],
v__h4661,
byteenable__h4327,
1'd0 } ;
assign MUX_memReq_fifo_rw_enq$wset_1__VAL_2 =
{ 1'd1,
evict_fifo$D_OUT[287:261],
evict_fifo$D_OUT[255:0],
33'h1FFFFFFFE } ;
assign MUX_memReq_fifo_taggedReg$write_1__VAL_1 =
{ 1'd1, memReq_fifo_rw_enq$wget } ;
assign MUX_memResp_fifo_taggedReg$write_1__VAL_1 =
{ 1'd1, memory_response_put } ;
assign MUX_out_fifo_taggedReg$write_1__VAL_1 =
{ 1'd1, out_fifo_rw_enq$wget } ;
assign MUX_tags_bram$b_put_3__VAL_1 =
{ addrReg[31:16], 1'd1, missWriteReg } ;
assign MUX_tags_bram$b_put_3__VAL_2 =
{ x_a_read_tag__h4514,
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0],
1'd1 } ;
// inlined wires
assign out_fifo_rw_enq$wget =
MUX_out_fifo_rw_enq$wset_1__SEL_1 ? v__h4661 : resp__h13851 ;
assign out_fifo_rw_enq$whas =
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
!req_fifo$D_OUT[316] ||
WILL_FIRE_RL_memResp_fifo_rule_deq && !missWriteReg ;
assign memReq_fifo_rw_enq$wget =
MUX_memReq_fifo_rw_enq$wset_1__SEL_1 ?
MUX_memReq_fifo_rw_enq$wset_1__VAL_1 :
MUX_memReq_fifo_rw_enq$wset_1__VAL_2 ;
assign memReq_fifo_rw_enq$whas =
WILL_FIRE_RL_getCacheResponse &&
(NOT_req_fifo_first__0_BITS_315_TO_300_5_EQ_IF__ETC___d296 ||
!req_fifo$D_OUT[0]) ||
!memReq_fifo_taggedReg[317] && evict_fifo$EMPTY_N &&
cacheState == 2'd2 ;
// register addrReg
assign addrReg$D_IN = { req_fifo$D_OUT[315:289], 5'b0 } ;
assign addrReg$EN = WILL_FIRE_RL_getCacheResponse ;
// register bank_lastReadAddrA
assign bank_lastReadAddrA$D_IN = cache_request_put[299:289] ;
assign bank_lastReadAddrA$EN = EN_cache_request_put ;
// register bank_lastReadAddrA_1
assign bank_lastReadAddrA_1$D_IN = cache_request_put[299:289] ;
assign bank_lastReadAddrA_1$EN = EN_cache_request_put ;
// register bank_lastReadAddrA_2
assign bank_lastReadAddrA_2$D_IN = cache_request_put[299:289] ;
assign bank_lastReadAddrA_2$EN = EN_cache_request_put ;
// register bank_lastReadAddrA_3
assign bank_lastReadAddrA_3$D_IN = cache_request_put[299:289] ;
assign bank_lastReadAddrA_3$EN = EN_cache_request_put ;
// register bank_lastReadAddrB
assign bank_lastReadAddrB$D_IN = 11'h0 ;
assign bank_lastReadAddrB$EN = 1'b0 ;
// register bank_lastReadAddrB_1
assign bank_lastReadAddrB_1$D_IN = 11'h0 ;
assign bank_lastReadAddrB_1$EN = 1'b0 ;
// register bank_lastReadAddrB_2
assign bank_lastReadAddrB_2$D_IN = 11'h0 ;
assign bank_lastReadAddrB_2$EN = 1'b0 ;
// register bank_lastReadAddrB_3
assign bank_lastReadAddrB_3$D_IN = 11'h0 ;
assign bank_lastReadAddrB_3$EN = 1'b0 ;
// register bank_lastWriteAddrA
assign bank_lastWriteAddrA$D_IN = 11'h0 ;
assign bank_lastWriteAddrA$EN = 1'b0 ;
// register bank_lastWriteAddrA_1
assign bank_lastWriteAddrA_1$D_IN = 11'h0 ;
assign bank_lastWriteAddrA_1$EN = 1'b0 ;
// register bank_lastWriteAddrA_2
assign bank_lastWriteAddrA_2$D_IN = 11'h0 ;
assign bank_lastWriteAddrA_2$EN = 1'b0 ;
// register bank_lastWriteAddrA_3
assign bank_lastWriteAddrA_3$D_IN = 11'h0 ;
assign bank_lastWriteAddrA_3$EN = 1'b0 ;
// register bank_lastWriteAddrB
assign bank_lastWriteAddrB$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_lastWriteAddrB$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register bank_lastWriteAddrB_1
assign bank_lastWriteAddrB_1$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_lastWriteAddrB_1$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register bank_lastWriteAddrB_2
assign bank_lastWriteAddrB_2$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_lastWriteAddrB_2$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register bank_lastWriteAddrB_3
assign bank_lastWriteAddrB_3$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_lastWriteAddrB_3$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register bank_lastWriteDataA
assign bank_lastWriteDataA$D_IN = 64'h0 ;
assign bank_lastWriteDataA$EN = 1'b0 ;
// register bank_lastWriteDataA_1
assign bank_lastWriteDataA_1$D_IN = 64'h0 ;
assign bank_lastWriteDataA_1$EN = 1'b0 ;
// register bank_lastWriteDataA_2
assign bank_lastWriteDataA_2$D_IN = 64'h0 ;
assign bank_lastWriteDataA_2$EN = 1'b0 ;
// register bank_lastWriteDataA_3
assign bank_lastWriteDataA_3$D_IN = 64'h0 ;
assign bank_lastWriteDataA_3$EN = 1'b0 ;
// register bank_lastWriteDataB
assign bank_lastWriteDataB$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram$b_put_3__VAL_1 :
MUX_bank_bram$b_put_3__VAL_2 ;
assign bank_lastWriteDataB$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register bank_lastWriteDataB_1
assign bank_lastWriteDataB_1$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram_1$b_put_3__VAL_1 :
MUX_bank_bram_1$b_put_3__VAL_2 ;
assign bank_lastWriteDataB_1$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register bank_lastWriteDataB_2
assign bank_lastWriteDataB_2$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram_2$b_put_3__VAL_1 :
MUX_bank_bram_2$b_put_3__VAL_2 ;
assign bank_lastWriteDataB_2$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register bank_lastWriteDataB_3
assign bank_lastWriteDataB_3$D_IN =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram_3$b_put_3__VAL_1 :
MUX_bank_bram_3$b_put_3__VAL_2 ;
assign bank_lastWriteDataB_3$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// register byteWriteReg_0
assign byteWriteReg_0$D_IN =
req_fifo$D_OUT[316] ? req_fifo$D_OUT[8:1] : 8'd0 ;
assign byteWriteReg_0$EN = MUX_cacheState$write_1__SEL_2 ;
// register byteWriteReg_1
assign byteWriteReg_1$D_IN =
req_fifo$D_OUT[316] ? req_fifo$D_OUT[16:9] : 8'd0 ;
assign byteWriteReg_1$EN = MUX_cacheState$write_1__SEL_2 ;
// register byteWriteReg_2
assign byteWriteReg_2$D_IN =
req_fifo$D_OUT[316] ? req_fifo$D_OUT[24:17] : 8'd0 ;
assign byteWriteReg_2$EN = MUX_cacheState$write_1__SEL_2 ;
// register byteWriteReg_3
assign byteWriteReg_3$D_IN =
req_fifo$D_OUT[316] ? req_fifo$D_OUT[32:25] : 8'd0 ;
assign byteWriteReg_3$EN = MUX_cacheState$write_1__SEL_2 ;
// register cacheState
assign cacheState$D_IN =
(MUX_cacheState$write_1__SEL_1 ||
WILL_FIRE_RL_clearNewRequests) ?
2'd1 :
2'd2 ;
assign cacheState$EN =
cacheState == 2'd0 && count == 11'd2047 ||
WILL_FIRE_RL_getCacheResponse &&
(NOT_req_fifo_first__0_BITS_315_TO_300_5_EQ_IF__ETC___d296 ||
!req_fifo$D_OUT[0]) &&
(req_fifo$D_OUT[0] || !req_fifo$D_OUT[316]) ||
WILL_FIRE_RL_clearNewRequests ;
// register count
assign count$D_IN = count + 11'd1 ;
assign count$EN = cacheState == 2'd0 ;
// register dataReg
assign dataReg$D_IN = req_fifo$D_OUT[288:33] ;
assign dataReg$EN = WILL_FIRE_RL_getCacheResponse ;
// register memReq_fifo_taggedReg
assign memReq_fifo_taggedReg$D_IN =
WILL_FIRE_RL_memReq_fifo_rule_enq ?
MUX_memReq_fifo_taggedReg$write_1__VAL_1 :
318'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign memReq_fifo_taggedReg$EN =
WILL_FIRE_RL_memReq_fifo_rule_enq || EN_memory_request_get ;
// register memResp_fifo_taggedReg
assign memResp_fifo_taggedReg$D_IN =
WILL_FIRE_RL_memResp_fifo_rule_enq ?
MUX_memResp_fifo_taggedReg$write_1__VAL_1 :
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign memResp_fifo_taggedReg$EN =
WILL_FIRE_RL_memResp_fifo_rule_enq ||
WILL_FIRE_RL_memResp_fifo_rule_deq ;
// register missCached
assign missCached$D_IN = req_fifo$D_OUT[0] ;
assign missCached$EN = WILL_FIRE_RL_getCacheResponse ;
// register missWriteReg
assign missWriteReg$D_IN = req_fifo$D_OUT[316] ;
assign missWriteReg$EN = MUX_cacheState$write_1__SEL_2 ;
// register out_fifo_taggedReg
assign out_fifo_taggedReg$D_IN =
WILL_FIRE_RL_out_fifo_rule_enq ?
MUX_out_fifo_taggedReg$write_1__VAL_1 :
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign out_fifo_taggedReg$EN =
WILL_FIRE_RL_out_fifo_rule_enq || EN_cache_response_get ;
// register tags_lastReadAddrA
assign tags_lastReadAddrA$D_IN = cache_request_put[299:289] ;
assign tags_lastReadAddrA$EN = EN_cache_request_put ;
// register tags_lastReadAddrB
assign tags_lastReadAddrB$D_IN = 11'h0 ;
assign tags_lastReadAddrB$EN = 1'b0 ;
// register tags_lastWriteAddrA
assign tags_lastWriteAddrA$D_IN = 11'h0 ;
assign tags_lastWriteAddrA$EN = 1'b0 ;
// register tags_lastWriteAddrB
always@(MUX_bank_bram$b_put_1__SEL_1 or
addrReg or
MUX_tags_bram$b_put_1__SEL_2 or
req_fifo$D_OUT or cacheState or count)
begin
case (1'b1) // synopsys parallel_case
MUX_bank_bram$b_put_1__SEL_1: tags_lastWriteAddrB$D_IN = addrReg[15:5];
MUX_tags_bram$b_put_1__SEL_2:
tags_lastWriteAddrB$D_IN = req_fifo$D_OUT[299:289];
cacheState == 2'd0: tags_lastWriteAddrB$D_IN = count;
default: tags_lastWriteAddrB$D_IN =
11'b01010101010 /* unspecified value */ ;
endcase
end
assign tags_lastWriteAddrB$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d65 ||
cacheState == 2'd0 ;
// register tags_lastWriteDataA
assign tags_lastWriteDataA$D_IN = 18'h0 ;
assign tags_lastWriteDataA$EN = 1'b0 ;
// register tags_lastWriteDataB
always@(MUX_bank_bram$b_put_1__SEL_1 or
MUX_tags_bram$b_put_3__VAL_1 or
MUX_tags_bram$b_put_1__SEL_2 or
MUX_tags_bram$b_put_3__VAL_2 or cacheState)
begin
case (1'b1) // synopsys parallel_case
MUX_bank_bram$b_put_1__SEL_1:
tags_lastWriteDataB$D_IN = MUX_tags_bram$b_put_3__VAL_1;
MUX_tags_bram$b_put_1__SEL_2:
tags_lastWriteDataB$D_IN = MUX_tags_bram$b_put_3__VAL_2;
cacheState == 2'd0: tags_lastWriteDataB$D_IN = 18'h2AAA8;
default: tags_lastWriteDataB$D_IN =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign tags_lastWriteDataB$EN =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d65 ||
cacheState == 2'd0 ;
// register updateReg
assign updateReg$D_IN = 256'h0 ;
assign updateReg$EN = 1'b0 ;
// submodule bank_bram
assign bank_bram$ADDRA = cache_request_put[299:289] ;
assign bank_bram$ADDRB =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_bram$DIA = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign bank_bram$DIB =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram$b_put_3__VAL_1 :
MUX_bank_bram$b_put_3__VAL_2 ;
assign bank_bram$WEA = 1'd0 ;
assign bank_bram$WEB = 1'd1 ;
assign bank_bram$ENA = EN_cache_request_put ;
assign bank_bram$ENB =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// submodule bank_bram_1
assign bank_bram_1$ADDRA = cache_request_put[299:289] ;
assign bank_bram_1$ADDRB =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_bram_1$DIA = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign bank_bram_1$DIB =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram_1$b_put_3__VAL_1 :
MUX_bank_bram_1$b_put_3__VAL_2 ;
assign bank_bram_1$WEA = 1'd0 ;
assign bank_bram_1$WEB = 1'd1 ;
assign bank_bram_1$ENA = EN_cache_request_put ;
assign bank_bram_1$ENB =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// submodule bank_bram_2
assign bank_bram_2$ADDRA = cache_request_put[299:289] ;
assign bank_bram_2$ADDRB =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_bram_2$DIA = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign bank_bram_2$DIB =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram_2$b_put_3__VAL_1 :
MUX_bank_bram_2$b_put_3__VAL_2 ;
assign bank_bram_2$WEA = 1'd0 ;
assign bank_bram_2$WEB = 1'd1 ;
assign bank_bram_2$ENA = EN_cache_request_put ;
assign bank_bram_2$ENB =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// submodule bank_bram_3
assign bank_bram_3$ADDRA = cache_request_put[299:289] ;
assign bank_bram_3$ADDRB =
MUX_bank_bram$b_put_1__SEL_1 ?
addrReg[15:5] :
req_fifo$D_OUT[299:289] ;
assign bank_bram_3$DIA = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign bank_bram_3$DIB =
MUX_bank_bram$b_put_1__SEL_1 ?
MUX_bank_bram_3$b_put_3__VAL_1 :
MUX_bank_bram_3$b_put_3__VAL_2 ;
assign bank_bram_3$WEA = 1'd0 ;
assign bank_bram_3$WEB = 1'd1 ;
assign bank_bram_3$ENA = EN_cache_request_put ;
assign bank_bram_3$ENB =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ;
// submodule evict_fifo
assign evict_fifo$D_IN = { x_addr__h12399, v__h4661 } ;
assign evict_fifo$ENQ =
WILL_FIRE_RL_getCacheResponse &&
(NOT_req_fifo_first__0_BITS_315_TO_300_5_EQ_IF__ETC___d296 ||
!req_fifo$D_OUT[0]) &&
(req_fifo$D_OUT[316] && req_fifo$D_OUT[0] &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d317 ||
!req_fifo$D_OUT[316] &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d317) ;
assign evict_fifo$DEQ = MUX_memReq_fifo_rw_enq$wset_1__SEL_2 ;
assign evict_fifo$CLR = 1'b0 ;
// submodule req_fifo
assign req_fifo$D_IN = cache_request_put ;
assign req_fifo$ENQ = EN_cache_request_put ;
assign req_fifo$DEQ =
_dand1req_fifo$EN_deq || WILL_FIRE_RL_clearNewRequests ;
assign req_fifo$CLR = 1'b0 ;
// submodule tags_bram
assign tags_bram$ADDRA = cache_request_put[299:289] ;
always@(MUX_bank_bram$b_put_1__SEL_1 or
addrReg or
MUX_tags_bram$b_put_1__SEL_2 or
req_fifo$D_OUT or cacheState or count)
begin
case (1'b1) // synopsys parallel_case
MUX_bank_bram$b_put_1__SEL_1: tags_bram$ADDRB = addrReg[15:5];
MUX_tags_bram$b_put_1__SEL_2: tags_bram$ADDRB = req_fifo$D_OUT[299:289];
cacheState == 2'd0: tags_bram$ADDRB = count;
default: tags_bram$ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
assign tags_bram$DIA = 18'b101010101010101010 /* unspecified value */ ;
always@(MUX_bank_bram$b_put_1__SEL_1 or
MUX_tags_bram$b_put_3__VAL_1 or
MUX_tags_bram$b_put_1__SEL_2 or
MUX_tags_bram$b_put_3__VAL_2 or cacheState)
begin
case (1'b1) // synopsys parallel_case
MUX_bank_bram$b_put_1__SEL_1:
tags_bram$DIB = MUX_tags_bram$b_put_3__VAL_1;
MUX_tags_bram$b_put_1__SEL_2:
tags_bram$DIB = MUX_tags_bram$b_put_3__VAL_2;
cacheState == 2'd0: tags_bram$DIB = 18'h2AAA8;
default: tags_bram$DIB =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign tags_bram$WEA = 1'd0 ;
assign tags_bram$WEB = 1'd1 ;
assign tags_bram$ENA = EN_cache_request_put ;
assign tags_bram$ENB =
WILL_FIRE_RL_memResp_fifo_rule_deq && missCached ||
WILL_FIRE_RL_getCacheResponse &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d65 ||
cacheState == 2'd0 ;
// submodule tags_fifo
assign tags_fifo$D_IN = 18'h0 ;
assign tags_fifo$ENQ = 1'b0 ;
assign tags_fifo$DEQ = 1'b0 ;
assign tags_fifo$CLR = 1'b0 ;
// submodule toServing_fifo
assign toServing_fifo$D_IN = 1'd1 ;
assign toServing_fifo$ENQ = WILL_FIRE_RL_memResp_fifo_rule_deq ;
assign toServing_fifo$DEQ = WILL_FIRE_RL_clearNewRequests ;
assign toServing_fifo$CLR = 1'b0 ;
// remaining internal signals
assign IF_bank_lastReadAddrA_1_read__35_EQ_bank_lastW_ETC___d580 =
(bank_lastReadAddrA_1 == bank_lastWriteAddrB_1) ?
bank_lastWriteDataB_1 :
bank_bram_1$DOA ;
assign IF_bank_lastReadAddrA_2_read__88_EQ_bank_lastW_ETC___d574 =
(bank_lastReadAddrA_2 == bank_lastWriteAddrB_2) ?
bank_lastWriteDataB_2 :
bank_bram_2$DOA ;
assign IF_bank_lastReadAddrA_3_read__41_EQ_bank_lastW_ETC___d569 =
(bank_lastReadAddrA_3 == bank_lastWriteAddrB_3) ?
bank_lastWriteDataB_3 :
bank_bram_3$DOA ;
assign IF_bank_lastReadAddrA_read__2_EQ_bank_lastWrit_ETC___d586 =
(bank_lastReadAddrA == bank_lastWriteAddrB) ?
bank_lastWriteDataB :
bank_bram$DOA ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_0_ETC___d382 =
(missWriteReg && byteWriteReg_0[0]) ?
dataReg[7:0] :
resp__h13851[7:0] ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_1_ETC___d377 =
(missWriteReg && byteWriteReg_0[1]) ?
dataReg[15:8] :
resp__h13851[15:8] ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_2_ETC___d372 =
(missWriteReg && byteWriteReg_0[2]) ?
dataReg[23:16] :
resp__h13851[23:16] ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_3_ETC___d367 =
(missWriteReg && byteWriteReg_0[3]) ?
dataReg[31:24] :
resp__h13851[31:24] ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_4_ETC___d362 =
(missWriteReg && byteWriteReg_0[4]) ?
dataReg[39:32] :
resp__h13851[39:32] ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_5_ETC___d357 =
(missWriteReg && byteWriteReg_0[5]) ?
dataReg[47:40] :
resp__h13851[47:40] ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_6_ETC___d352 =
(missWriteReg && byteWriteReg_0[6]) ?
dataReg[55:48] :
resp__h13851[55:48] ;
assign IF_missWriteReg_33_AND_byteWriteReg_0_41_BIT_7_ETC___d347 =
(missWriteReg && byteWriteReg_0[7]) ?
dataReg[63:56] :
resp__h13851[63:56] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_0_ETC___d427 =
(missWriteReg && byteWriteReg_1[0]) ?
dataReg[71:64] :
resp__h13851[71:64] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_1_ETC___d422 =
(missWriteReg && byteWriteReg_1[1]) ?
dataReg[79:72] :
resp__h13851[79:72] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_2_ETC___d417 =
(missWriteReg && byteWriteReg_1[2]) ?
dataReg[87:80] :
resp__h13851[87:80] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_3_ETC___d412 =
(missWriteReg && byteWriteReg_1[3]) ?
dataReg[95:88] :
resp__h13851[95:88] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_4_ETC___d407 =
(missWriteReg && byteWriteReg_1[4]) ?
dataReg[103:96] :
resp__h13851[103:96] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_5_ETC___d402 =
(missWriteReg && byteWriteReg_1[5]) ?
dataReg[111:104] :
resp__h13851[111:104] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_6_ETC___d397 =
(missWriteReg && byteWriteReg_1[6]) ?
dataReg[119:112] :
resp__h13851[119:112] ;
assign IF_missWriteReg_33_AND_byteWriteReg_1_87_BIT_7_ETC___d392 =
(missWriteReg && byteWriteReg_1[7]) ?
dataReg[127:120] :
resp__h13851[127:120] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_0_ETC___d472 =
(missWriteReg && byteWriteReg_2[0]) ?
dataReg[135:128] :
resp__h13851[135:128] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_1_ETC___d467 =
(missWriteReg && byteWriteReg_2[1]) ?
dataReg[143:136] :
resp__h13851[143:136] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_2_ETC___d462 =
(missWriteReg && byteWriteReg_2[2]) ?
dataReg[151:144] :
resp__h13851[151:144] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_3_ETC___d457 =
(missWriteReg && byteWriteReg_2[3]) ?
dataReg[159:152] :
resp__h13851[159:152] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_4_ETC___d452 =
(missWriteReg && byteWriteReg_2[4]) ?
dataReg[167:160] :
resp__h13851[167:160] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_5_ETC___d447 =
(missWriteReg && byteWriteReg_2[5]) ?
dataReg[175:168] :
resp__h13851[175:168] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_6_ETC___d442 =
(missWriteReg && byteWriteReg_2[6]) ?
dataReg[183:176] :
resp__h13851[183:176] ;
assign IF_missWriteReg_33_AND_byteWriteReg_2_32_BIT_7_ETC___d437 =
(missWriteReg && byteWriteReg_2[7]) ?
dataReg[191:184] :
resp__h13851[191:184] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_0_ETC___d517 =
(missWriteReg && byteWriteReg_3[0]) ?
dataReg[199:192] :
resp__h13851[199:192] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_1_ETC___d512 =
(missWriteReg && byteWriteReg_3[1]) ?
dataReg[207:200] :
resp__h13851[207:200] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_2_ETC___d507 =
(missWriteReg && byteWriteReg_3[2]) ?
dataReg[215:208] :
resp__h13851[215:208] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_3_ETC___d502 =
(missWriteReg && byteWriteReg_3[3]) ?
dataReg[223:216] :
resp__h13851[223:216] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_4_ETC___d497 =
(missWriteReg && byteWriteReg_3[4]) ?
dataReg[231:224] :
resp__h13851[231:224] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_5_ETC___d492 =
(missWriteReg && byteWriteReg_3[5]) ?
dataReg[239:232] :
resp__h13851[239:232] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_6_ETC___d487 =
(missWriteReg && byteWriteReg_3[6]) ?
dataReg[247:240] :
resp__h13851[247:240] ;
assign IF_missWriteReg_33_AND_byteWriteReg_3_77_BIT_7_ETC___d482 =
(missWriteReg && byteWriteReg_3[7]) ?
dataReg[255:248] :
resp__h13851[255:248] ;
assign IF_req_fifo_first__0_BIT_10_33_THEN_IF_req_fif_ETC___d578 =
req_fifo$D_OUT[10] ?
{ IF_req_fifo_first__0_BIT_9_34_THEN_IF_bank_las_ETC___d579[63:16],
req_fifo$D_OUT[112:105],
IF_req_fifo_first__0_BIT_9_34_THEN_IF_bank_las_ETC___d579[7:0] } :
IF_req_fifo_first__0_BIT_9_34_THEN_IF_bank_las_ETC___d579 ;
assign IF_req_fifo_first__0_BIT_11_32_THEN_IF_req_fif_ETC___d577 =
req_fifo$D_OUT[11] ?
{ IF_req_fifo_first__0_BIT_10_33_THEN_IF_req_fif_ETC___d578[63:24],
req_fifo$D_OUT[120:113],
IF_req_fifo_first__0_BIT_10_33_THEN_IF_req_fif_ETC___d578[15:0] } :
IF_req_fifo_first__0_BIT_10_33_THEN_IF_req_fif_ETC___d578 ;
assign IF_req_fifo_first__0_BIT_12_31_THEN_IF_req_fif_ETC___d576 =
req_fifo$D_OUT[12] ?
{ IF_req_fifo_first__0_BIT_11_32_THEN_IF_req_fif_ETC___d577[63:32],
req_fifo$D_OUT[128:121],
IF_req_fifo_first__0_BIT_11_32_THEN_IF_req_fif_ETC___d577[23:0] } :
IF_req_fifo_first__0_BIT_11_32_THEN_IF_req_fif_ETC___d577 ;
assign IF_req_fifo_first__0_BIT_13_30_THEN_IF_req_fif_ETC___d575 =
req_fifo$D_OUT[13] ?
{ IF_req_fifo_first__0_BIT_12_31_THEN_IF_req_fif_ETC___d576[63:40],
req_fifo$D_OUT[136:129],
IF_req_fifo_first__0_BIT_12_31_THEN_IF_req_fif_ETC___d576[31:0] } :
IF_req_fifo_first__0_BIT_12_31_THEN_IF_req_fif_ETC___d576 ;
assign IF_req_fifo_first__0_BIT_14_29_THEN_IF_req_fif_ETC___d547 =
req_fifo$D_OUT[14] ?
{ IF_req_fifo_first__0_BIT_13_30_THEN_IF_req_fif_ETC___d575[63:48],
req_fifo$D_OUT[144:137],
IF_req_fifo_first__0_BIT_13_30_THEN_IF_req_fif_ETC___d575[39:0] } :
IF_req_fifo_first__0_BIT_13_30_THEN_IF_req_fif_ETC___d575 ;
assign IF_req_fifo_first__0_BIT_15_28_THEN_IF_req_fif_ETC___d555 =
req_fifo$D_OUT[15] ?
{ IF_req_fifo_first__0_BIT_14_29_THEN_IF_req_fif_ETC___d547[63:56],
req_fifo$D_OUT[152:145],
IF_req_fifo_first__0_BIT_14_29_THEN_IF_req_fif_ETC___d547[47:0] } :
IF_req_fifo_first__0_BIT_14_29_THEN_IF_req_fif_ETC___d547 ;
assign IF_req_fifo_first__0_BIT_16_26_THEN_req_fifo_f_ETC___d589 =
req_fifo$D_OUT[16] ?
{ req_fifo$D_OUT[160:153],
IF_req_fifo_first__0_BIT_15_28_THEN_IF_req_fif_ETC___d555[55:0] } :
IF_req_fifo_first__0_BIT_15_28_THEN_IF_req_fif_ETC___d555 ;
assign IF_req_fifo_first__0_BIT_17_87_THEN_IF_bank_la_ETC___d573 =
req_fifo$D_OUT[17] ?
{ IF_bank_lastReadAddrA_2_read__88_EQ_bank_lastW_ETC___d574[63:8],
req_fifo$D_OUT[168:161] } :
IF_bank_lastReadAddrA_2_read__88_EQ_bank_lastW_ETC___d574 ;
assign IF_req_fifo_first__0_BIT_18_86_THEN_IF_req_fif_ETC___d572 =
req_fifo$D_OUT[18] ?
{ IF_req_fifo_first__0_BIT_17_87_THEN_IF_bank_la_ETC___d573[63:16],
req_fifo$D_OUT[176:169],
IF_req_fifo_first__0_BIT_17_87_THEN_IF_bank_la_ETC___d573[7:0] } :
IF_req_fifo_first__0_BIT_17_87_THEN_IF_bank_la_ETC___d573 ;
assign IF_req_fifo_first__0_BIT_19_85_THEN_IF_req_fif_ETC___d548 =
req_fifo$D_OUT[19] ?
{ IF_req_fifo_first__0_BIT_18_86_THEN_IF_req_fif_ETC___d572[63:24],
req_fifo$D_OUT[184:177],
IF_req_fifo_first__0_BIT_18_86_THEN_IF_req_fif_ETC___d572[15:0] } :
IF_req_fifo_first__0_BIT_18_86_THEN_IF_req_fif_ETC___d572 ;
assign IF_req_fifo_first__0_BIT_1_1_THEN_IF_bank_last_ETC___d585 =
req_fifo$D_OUT[1] ?
{ IF_bank_lastReadAddrA_read__2_EQ_bank_lastWrit_ETC___d586[63:8],
req_fifo$D_OUT[40:33] } :
IF_bank_lastReadAddrA_read__2_EQ_bank_lastWrit_ETC___d586 ;
assign IF_req_fifo_first__0_BIT_20_84_THEN_IF_req_fif_ETC___d571 =
req_fifo$D_OUT[20] ?
{ IF_req_fifo_first__0_BIT_19_85_THEN_IF_req_fif_ETC___d548[63:32],
req_fifo$D_OUT[192:185],
IF_req_fifo_first__0_BIT_19_85_THEN_IF_req_fif_ETC___d548[23:0] } :
IF_req_fifo_first__0_BIT_19_85_THEN_IF_req_fif_ETC___d548 ;
assign IF_req_fifo_first__0_BIT_21_83_THEN_IF_req_fif_ETC___d570 =
req_fifo$D_OUT[21] ?
{ IF_req_fifo_first__0_BIT_20_84_THEN_IF_req_fif_ETC___d571[63:40],
req_fifo$D_OUT[200:193],
IF_req_fifo_first__0_BIT_20_84_THEN_IF_req_fif_ETC___d571[31:0] } :
IF_req_fifo_first__0_BIT_20_84_THEN_IF_req_fif_ETC___d571 ;
assign IF_req_fifo_first__0_BIT_22_82_THEN_IF_req_fif_ETC___d592 =
req_fifo$D_OUT[22] ?
{ IF_req_fifo_first__0_BIT_21_83_THEN_IF_req_fif_ETC___d570[63:48],
req_fifo$D_OUT[208:201],
IF_req_fifo_first__0_BIT_21_83_THEN_IF_req_fif_ETC___d570[39:0] } :
IF_req_fifo_first__0_BIT_21_83_THEN_IF_req_fif_ETC___d570 ;
assign IF_req_fifo_first__0_BIT_23_81_THEN_IF_req_fif_ETC___d554 =
req_fifo$D_OUT[23] ?
{ IF_req_fifo_first__0_BIT_22_82_THEN_IF_req_fif_ETC___d592[63:56],
req_fifo$D_OUT[216:209],
IF_req_fifo_first__0_BIT_22_82_THEN_IF_req_fif_ETC___d592[47:0] } :
IF_req_fifo_first__0_BIT_22_82_THEN_IF_req_fif_ETC___d592 ;
assign IF_req_fifo_first__0_BIT_24_79_THEN_req_fifo_f_ETC___d588 =
req_fifo$D_OUT[24] ?
{ req_fifo$D_OUT[224:217],
IF_req_fifo_first__0_BIT_23_81_THEN_IF_req_fif_ETC___d554[55:0] } :
IF_req_fifo_first__0_BIT_23_81_THEN_IF_req_fif_ETC___d554 ;
assign IF_req_fifo_first__0_BIT_25_40_THEN_IF_bank_la_ETC___d568 =
req_fifo$D_OUT[25] ?
{ IF_bank_lastReadAddrA_3_read__41_EQ_bank_lastW_ETC___d569[63:8],
req_fifo$D_OUT[232:225] } :
IF_bank_lastReadAddrA_3_read__41_EQ_bank_lastW_ETC___d569 ;
assign IF_req_fifo_first__0_BIT_26_39_THEN_IF_req_fif_ETC___d567 =
req_fifo$D_OUT[26] ?
{ IF_req_fifo_first__0_BIT_25_40_THEN_IF_bank_la_ETC___d568[63:16],
req_fifo$D_OUT[240:233],
IF_req_fifo_first__0_BIT_25_40_THEN_IF_bank_la_ETC___d568[7:0] } :
IF_req_fifo_first__0_BIT_25_40_THEN_IF_bank_la_ETC___d568 ;
assign IF_req_fifo_first__0_BIT_27_38_THEN_IF_req_fif_ETC___d566 =
req_fifo$D_OUT[27] ?
{ IF_req_fifo_first__0_BIT_26_39_THEN_IF_req_fif_ETC___d567[63:24],
req_fifo$D_OUT[248:241],
IF_req_fifo_first__0_BIT_26_39_THEN_IF_req_fif_ETC___d567[15:0] } :
IF_req_fifo_first__0_BIT_26_39_THEN_IF_req_fif_ETC___d567 ;
assign IF_req_fifo_first__0_BIT_28_37_THEN_IF_req_fif_ETC___d565 =
req_fifo$D_OUT[28] ?
{ IF_req_fifo_first__0_BIT_27_38_THEN_IF_req_fif_ETC___d566[63:32],
req_fifo$D_OUT[256:249],
IF_req_fifo_first__0_BIT_27_38_THEN_IF_req_fif_ETC___d566[23:0] } :
IF_req_fifo_first__0_BIT_27_38_THEN_IF_req_fif_ETC___d566 ;
assign IF_req_fifo_first__0_BIT_29_36_THEN_IF_req_fif_ETC___d564 =
req_fifo$D_OUT[29] ?
{ IF_req_fifo_first__0_BIT_28_37_THEN_IF_req_fif_ETC___d565[63:40],
req_fifo$D_OUT[264:257],
IF_req_fifo_first__0_BIT_28_37_THEN_IF_req_fif_ETC___d565[31:0] } :
IF_req_fifo_first__0_BIT_28_37_THEN_IF_req_fif_ETC___d565 ;
assign IF_req_fifo_first__0_BIT_2_0_THEN_IF_req_fifo__ETC___d584 =
req_fifo$D_OUT[2] ?
{ IF_req_fifo_first__0_BIT_1_1_THEN_IF_bank_last_ETC___d585[63:16],
req_fifo$D_OUT[48:41],
IF_req_fifo_first__0_BIT_1_1_THEN_IF_bank_last_ETC___d585[7:0] } :
IF_req_fifo_first__0_BIT_1_1_THEN_IF_bank_last_ETC___d585 ;
assign IF_req_fifo_first__0_BIT_30_35_THEN_IF_req_fif_ETC___d591 =
req_fifo$D_OUT[30] ?
{ IF_req_fifo_first__0_BIT_29_36_THEN_IF_req_fif_ETC___d564[63:48],
req_fifo$D_OUT[272:265],
IF_req_fifo_first__0_BIT_29_36_THEN_IF_req_fif_ETC___d564[39:0] } :
IF_req_fifo_first__0_BIT_29_36_THEN_IF_req_fif_ETC___d564 ;
assign IF_req_fifo_first__0_BIT_31_34_THEN_IF_req_fif_ETC___d553 =
req_fifo$D_OUT[31] ?
{ IF_req_fifo_first__0_BIT_30_35_THEN_IF_req_fif_ETC___d591[63:56],
req_fifo$D_OUT[280:273],
IF_req_fifo_first__0_BIT_30_35_THEN_IF_req_fif_ETC___d591[47:0] } :
IF_req_fifo_first__0_BIT_30_35_THEN_IF_req_fif_ETC___d591 ;
assign IF_req_fifo_first__0_BIT_32_32_THEN_req_fifo_f_ETC___d587 =
req_fifo$D_OUT[32] ?
{ req_fifo$D_OUT[288:281],
IF_req_fifo_first__0_BIT_31_34_THEN_IF_req_fif_ETC___d553[55:0] } :
IF_req_fifo_first__0_BIT_31_34_THEN_IF_req_fif_ETC___d553 ;
assign IF_req_fifo_first__0_BIT_3_9_THEN_IF_req_fifo__ETC___d583 =
req_fifo$D_OUT[3] ?
{ IF_req_fifo_first__0_BIT_2_0_THEN_IF_req_fifo__ETC___d584[63:24],
req_fifo$D_OUT[56:49],
IF_req_fifo_first__0_BIT_2_0_THEN_IF_req_fifo__ETC___d584[15:0] } :
IF_req_fifo_first__0_BIT_2_0_THEN_IF_req_fifo__ETC___d584 ;
assign IF_req_fifo_first__0_BIT_4_8_THEN_IF_req_fifo__ETC___d582 =
req_fifo$D_OUT[4] ?
{ IF_req_fifo_first__0_BIT_3_9_THEN_IF_req_fifo__ETC___d583[63:32],
req_fifo$D_OUT[64:57],
IF_req_fifo_first__0_BIT_3_9_THEN_IF_req_fifo__ETC___d583[23:0] } :
IF_req_fifo_first__0_BIT_3_9_THEN_IF_req_fifo__ETC___d583 ;
assign IF_req_fifo_first__0_BIT_5_7_THEN_IF_req_fifo__ETC___d581 =
req_fifo$D_OUT[5] ?
{ IF_req_fifo_first__0_BIT_4_8_THEN_IF_req_fifo__ETC___d582[63:40],
req_fifo$D_OUT[72:65],
IF_req_fifo_first__0_BIT_4_8_THEN_IF_req_fifo__ETC___d582[31:0] } :
IF_req_fifo_first__0_BIT_4_8_THEN_IF_req_fifo__ETC___d582 ;
assign IF_req_fifo_first__0_BIT_6_6_THEN_IF_req_fifo__ETC___d593 =
req_fifo$D_OUT[6] ?
{ IF_req_fifo_first__0_BIT_5_7_THEN_IF_req_fifo__ETC___d581[63:48],
req_fifo$D_OUT[80:73],
IF_req_fifo_first__0_BIT_5_7_THEN_IF_req_fifo__ETC___d581[39:0] } :
IF_req_fifo_first__0_BIT_5_7_THEN_IF_req_fifo__ETC___d581 ;
assign IF_req_fifo_first__0_BIT_7_5_THEN_IF_req_fifo__ETC___d557 =
req_fifo$D_OUT[7] ?
{ IF_req_fifo_first__0_BIT_6_6_THEN_IF_req_fifo__ETC___d593[63:56],
req_fifo$D_OUT[88:81],
IF_req_fifo_first__0_BIT_6_6_THEN_IF_req_fifo__ETC___d593[47:0] } :
IF_req_fifo_first__0_BIT_6_6_THEN_IF_req_fifo__ETC___d593 ;
assign IF_req_fifo_first__0_BIT_8_3_THEN_req_fifo_fir_ETC___d590 =
req_fifo$D_OUT[8] ?
{ req_fifo$D_OUT[96:89],
IF_req_fifo_first__0_BIT_7_5_THEN_IF_req_fifo__ETC___d557[55:0] } :
IF_req_fifo_first__0_BIT_7_5_THEN_IF_req_fifo__ETC___d557 ;
assign IF_req_fifo_first__0_BIT_9_34_THEN_IF_bank_las_ETC___d579 =
req_fifo$D_OUT[9] ?
{ IF_bank_lastReadAddrA_1_read__35_EQ_bank_lastW_ETC___d580[63:8],
req_fifo$D_OUT[104:97] } :
IF_bank_lastReadAddrA_1_read__35_EQ_bank_lastW_ETC___d580 ;
assign IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d317 =
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
(tags_lastReadAddrA_read__6_EQ_tags_lastWriteAd_ETC___d622 ?
tags_lastWriteDataB[0] :
tags_bram$DOA[0]) ;
assign IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 =
tags_lastReadAddrA_read__6_EQ_tags_lastWriteAd_ETC___d622 ?
tags_lastWriteDataB[1] :
tags_bram$DOA[1] ;
assign NOT_req_fifo_first__0_BITS_315_TO_300_5_EQ_IF__ETC___d296 =
!req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 ||
(tags_lastReadAddrA_read__6_EQ_tags_lastWriteAd_ETC___d622 ?
!tags_lastWriteDataB[1] :
!tags_bram$DOA[1]) ;
assign _dand1req_fifo$EN_deq =
WILL_FIRE_RL_getCacheResponse &&
(req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] ||
req_fifo$D_OUT[316] && !req_fifo$D_OUT[0]) ;
assign byteenable__h4327 =
req_fifo$D_OUT[0] ? 32'hFFFFFFFF : req_fifo$D_OUT[32:1] ;
assign req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 =
req_fifo$D_OUT[315:300] == x_a_read_tag__h4514 ;
assign req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d65 =
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 &&
req_fifo$D_OUT[0] &&
req_fifo$D_OUT[316] ||
req_fifo$D_OUT[316] && !req_fifo$D_OUT[0] &&
req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 ;
assign resp__h13851 =
EN_memory_response_put ?
memory_response_put :
memResp_fifo_taggedReg[255:0] ;
assign tags_lastReadAddrA_read__6_EQ_tags_lastWriteAd_ETC___d622 =
tags_lastReadAddrA == tags_lastWriteAddrB ;
assign v__h4661 =
(req_fifo$D_OUT[316] &&
(req_fifo_first__0_BITS_315_TO_300_5_EQ_IF_tags_ETC___d558 &&
IF_tags_lastReadAddrA_read__6_EQ_tags_lastWrit_ETC___d607 ||
!req_fifo$D_OUT[0])) ?
{ IF_req_fifo_first__0_BIT_32_32_THEN_req_fifo_f_ETC___d587,
IF_req_fifo_first__0_BIT_24_79_THEN_req_fifo_f_ETC___d588,
IF_req_fifo_first__0_BIT_16_26_THEN_req_fifo_f_ETC___d589,
IF_req_fifo_first__0_BIT_8_3_THEN_req_fifo_fir_ETC___d590 } :
{ IF_bank_lastReadAddrA_3_read__41_EQ_bank_lastW_ETC___d569,
IF_bank_lastReadAddrA_2_read__88_EQ_bank_lastW_ETC___d574,
IF_bank_lastReadAddrA_1_read__35_EQ_bank_lastW_ETC___d580,
IF_bank_lastReadAddrA_read__2_EQ_bank_lastWrit_ETC___d586 } ;
assign x_a_read_tag__h4514 =
tags_lastReadAddrA_read__6_EQ_tags_lastWriteAd_ETC___d622 ?
tags_lastWriteDataB[17:2] :
tags_bram$DOA[17:2] ;
assign x_addr__h12399 =
{ x_a_read_tag__h4514, req_fifo$D_OUT[299:289], 5'b0 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
bank_lastReadAddrA <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastReadAddrA_1 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastReadAddrA_2 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastReadAddrA_3 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastReadAddrB <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastReadAddrB_1 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastReadAddrB_2 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastReadAddrB_3 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrA <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrA_1 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrA_2 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrA_3 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrB <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrB_1 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrB_2 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteAddrB_3 <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
bank_lastWriteDataA <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataA_1 <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataA_2 <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataA_3 <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB_1 <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB_2 <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB_3 <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
byteWriteReg_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
byteWriteReg_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
byteWriteReg_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
byteWriteReg_3 <= `BSV_ASSIGNMENT_DELAY 8'd0;
cacheState <= `BSV_ASSIGNMENT_DELAY 2'd0;
count <= `BSV_ASSIGNMENT_DELAY 11'd0;
memReq_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY
318'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
memResp_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
missCached <= `BSV_ASSIGNMENT_DELAY 1'd0;
missWriteReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
out_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tags_lastReadAddrA <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
tags_lastReadAddrB <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
tags_lastWriteAddrA <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
tags_lastWriteAddrB <= `BSV_ASSIGNMENT_DELAY 11'h2AA;
tags_lastWriteDataA <= `BSV_ASSIGNMENT_DELAY 18'h2AAAA;
tags_lastWriteDataB <= `BSV_ASSIGNMENT_DELAY 18'h2AAAA;
end
else
begin
if (bank_lastReadAddrA$EN)
bank_lastReadAddrA <= `BSV_ASSIGNMENT_DELAY bank_lastReadAddrA$D_IN;
if (bank_lastReadAddrA_1$EN)
bank_lastReadAddrA_1 <= `BSV_ASSIGNMENT_DELAY
bank_lastReadAddrA_1$D_IN;
if (bank_lastReadAddrA_2$EN)
bank_lastReadAddrA_2 <= `BSV_ASSIGNMENT_DELAY
bank_lastReadAddrA_2$D_IN;
if (bank_lastReadAddrA_3$EN)
bank_lastReadAddrA_3 <= `BSV_ASSIGNMENT_DELAY
bank_lastReadAddrA_3$D_IN;
if (bank_lastReadAddrB$EN)
bank_lastReadAddrB <= `BSV_ASSIGNMENT_DELAY bank_lastReadAddrB$D_IN;
if (bank_lastReadAddrB_1$EN)
bank_lastReadAddrB_1 <= `BSV_ASSIGNMENT_DELAY
bank_lastReadAddrB_1$D_IN;
if (bank_lastReadAddrB_2$EN)
bank_lastReadAddrB_2 <= `BSV_ASSIGNMENT_DELAY
bank_lastReadAddrB_2$D_IN;
if (bank_lastReadAddrB_3$EN)
bank_lastReadAddrB_3 <= `BSV_ASSIGNMENT_DELAY
bank_lastReadAddrB_3$D_IN;
if (bank_lastWriteAddrA$EN)
bank_lastWriteAddrA <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrA$D_IN;
if (bank_lastWriteAddrA_1$EN)
bank_lastWriteAddrA_1 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrA_1$D_IN;
if (bank_lastWriteAddrA_2$EN)
bank_lastWriteAddrA_2 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrA_2$D_IN;
if (bank_lastWriteAddrA_3$EN)
bank_lastWriteAddrA_3 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrA_3$D_IN;
if (bank_lastWriteAddrB$EN)
bank_lastWriteAddrB <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrB$D_IN;
if (bank_lastWriteAddrB_1$EN)
bank_lastWriteAddrB_1 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrB_1$D_IN;
if (bank_lastWriteAddrB_2$EN)
bank_lastWriteAddrB_2 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrB_2$D_IN;
if (bank_lastWriteAddrB_3$EN)
bank_lastWriteAddrB_3 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteAddrB_3$D_IN;
if (bank_lastWriteDataA$EN)
bank_lastWriteDataA <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataA$D_IN;
if (bank_lastWriteDataA_1$EN)
bank_lastWriteDataA_1 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataA_1$D_IN;
if (bank_lastWriteDataA_2$EN)
bank_lastWriteDataA_2 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataA_2$D_IN;
if (bank_lastWriteDataA_3$EN)
bank_lastWriteDataA_3 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataA_3$D_IN;
if (bank_lastWriteDataB$EN)
bank_lastWriteDataB <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataB$D_IN;
if (bank_lastWriteDataB_1$EN)
bank_lastWriteDataB_1 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataB_1$D_IN;
if (bank_lastWriteDataB_2$EN)
bank_lastWriteDataB_2 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataB_2$D_IN;
if (bank_lastWriteDataB_3$EN)
bank_lastWriteDataB_3 <= `BSV_ASSIGNMENT_DELAY
bank_lastWriteDataB_3$D_IN;
if (byteWriteReg_0$EN)
byteWriteReg_0 <= `BSV_ASSIGNMENT_DELAY byteWriteReg_0$D_IN;
if (byteWriteReg_1$EN)
byteWriteReg_1 <= `BSV_ASSIGNMENT_DELAY byteWriteReg_1$D_IN;
if (byteWriteReg_2$EN)
byteWriteReg_2 <= `BSV_ASSIGNMENT_DELAY byteWriteReg_2$D_IN;
if (byteWriteReg_3$EN)
byteWriteReg_3 <= `BSV_ASSIGNMENT_DELAY byteWriteReg_3$D_IN;
if (cacheState$EN)
cacheState <= `BSV_ASSIGNMENT_DELAY cacheState$D_IN;
if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (memReq_fifo_taggedReg$EN)
memReq_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY
memReq_fifo_taggedReg$D_IN;
if (memResp_fifo_taggedReg$EN)
memResp_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY
memResp_fifo_taggedReg$D_IN;
if (missCached$EN)
missCached <= `BSV_ASSIGNMENT_DELAY missCached$D_IN;
if (missWriteReg$EN)
missWriteReg <= `BSV_ASSIGNMENT_DELAY missWriteReg$D_IN;
if (out_fifo_taggedReg$EN)
out_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY out_fifo_taggedReg$D_IN;
if (tags_lastReadAddrA$EN)
tags_lastReadAddrA <= `BSV_ASSIGNMENT_DELAY tags_lastReadAddrA$D_IN;
if (tags_lastReadAddrB$EN)
tags_lastReadAddrB <= `BSV_ASSIGNMENT_DELAY tags_lastReadAddrB$D_IN;
if (tags_lastWriteAddrA$EN)
tags_lastWriteAddrA <= `BSV_ASSIGNMENT_DELAY
tags_lastWriteAddrA$D_IN;
if (tags_lastWriteAddrB$EN)
tags_lastWriteAddrB <= `BSV_ASSIGNMENT_DELAY
tags_lastWriteAddrB$D_IN;
if (tags_lastWriteDataA$EN)
tags_lastWriteDataA <= `BSV_ASSIGNMENT_DELAY
tags_lastWriteDataA$D_IN;
if (tags_lastWriteDataB$EN)
tags_lastWriteDataB <= `BSV_ASSIGNMENT_DELAY
tags_lastWriteDataB$D_IN;
end
if (addrReg$EN) addrReg <= `BSV_ASSIGNMENT_DELAY addrReg$D_IN;
if (dataReg$EN) dataReg <= `BSV_ASSIGNMENT_DELAY dataReg$D_IN;
if (updateReg$EN) updateReg <= `BSV_ASSIGNMENT_DELAY updateReg$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
addrReg = 32'hAAAAAAAA;
bank_lastReadAddrA = 11'h2AA;
bank_lastReadAddrA_1 = 11'h2AA;
bank_lastReadAddrA_2 = 11'h2AA;
bank_lastReadAddrA_3 = 11'h2AA;
bank_lastReadAddrB = 11'h2AA;
bank_lastReadAddrB_1 = 11'h2AA;
bank_lastReadAddrB_2 = 11'h2AA;
bank_lastReadAddrB_3 = 11'h2AA;
bank_lastWriteAddrA = 11'h2AA;
bank_lastWriteAddrA_1 = 11'h2AA;
bank_lastWriteAddrA_2 = 11'h2AA;
bank_lastWriteAddrA_3 = 11'h2AA;
bank_lastWriteAddrB = 11'h2AA;
bank_lastWriteAddrB_1 = 11'h2AA;
bank_lastWriteAddrB_2 = 11'h2AA;
bank_lastWriteAddrB_3 = 11'h2AA;
bank_lastWriteDataA = 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataA_1 = 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataA_2 = 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataA_3 = 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB = 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB_1 = 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB_2 = 64'hAAAAAAAAAAAAAAAA;
bank_lastWriteDataB_3 = 64'hAAAAAAAAAAAAAAAA;
byteWriteReg_0 = 8'hAA;
byteWriteReg_1 = 8'hAA;
byteWriteReg_2 = 8'hAA;
byteWriteReg_3 = 8'hAA;
cacheState = 2'h2;
count = 11'h2AA;
dataReg =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
memReq_fifo_taggedReg =
318'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
memResp_fifo_taggedReg =
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
missCached = 1'h0;
missWriteReg = 1'h0;
out_fifo_taggedReg =
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tags_lastReadAddrA = 11'h2AA;
tags_lastReadAddrB = 11'h2AA;
tags_lastWriteAddrA = 11'h2AA;
tags_lastWriteAddrB = 11'h2AA;
tags_lastWriteDataA = 18'h2AAAA;
tags_lastWriteDataB = 18'h2AAAA;
updateReg =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkL2Cache
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:45:09 BST 2012
//
// Method conflict info:
// Method: memory_request_get
// Conflict-free: memory_response_put,
// putIrqs,
// debugStream_request_put,
// debugStream_response_get
// Conflicts: memory_request_get
//
// Method: memory_response_put
// Conflict-free: memory_request_get,
// putIrqs,
// debugStream_request_put,
// debugStream_response_get
// Conflicts: memory_response_put
//
// Method: putIrqs
// Conflict-free: memory_request_get,
// memory_response_put,
// debugStream_request_put,
// debugStream_response_get
// Sequenced before (restricted): putIrqs
//
// Method: debugStream_request_put
// Conflict-free: memory_request_get,
// memory_response_put,
// putIrqs,
// debugStream_response_get
// Conflicts: debugStream_request_put
//
// Method: debugStream_response_get
// Conflict-free: memory_request_get,
// memory_response_put,
// putIrqs,
// debugStream_request_put
// Conflicts: debugStream_response_get
//
//
// Ports:
// Name I/O size props
// memory_request_get O 317
// RDY_memory_request_get O 1
// RDY_memory_response_put O 1
// RDY_putIrqs O 1 const
// RDY_debugStream_request_put O 1 reg
// debugStream_response_get O 8 reg
// RDY_debugStream_response_get O 1 reg
// csi_c0_clk I 1 clock
// csi_c0_reset_n I 1 reset
// memory_response_put I 256
// putIrqs_interruptLines I 5 reg
// debugStream_request_put I 8 reg
// EN_memory_response_put I 1
// EN_putIrqs I 1
// EN_debugStream_request_put I 1
// EN_memory_request_get I 1
// EN_debugStream_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkMIPSTop(csi_c0_clk,
csi_c0_reset_n,
EN_memory_request_get,
memory_request_get,
RDY_memory_request_get,
memory_response_put,
EN_memory_response_put,
RDY_memory_response_put,
putIrqs_interruptLines,
EN_putIrqs,
RDY_putIrqs,
debugStream_request_put,
EN_debugStream_request_put,
RDY_debugStream_request_put,
EN_debugStream_response_get,
debugStream_response_get,
RDY_debugStream_response_get);
input csi_c0_clk;
input csi_c0_reset_n;
// actionvalue method memory_request_get
input EN_memory_request_get;
output [316 : 0] memory_request_get;
output RDY_memory_request_get;
// action method memory_response_put
input [255 : 0] memory_response_put;
input EN_memory_response_put;
output RDY_memory_response_put;
// action method putIrqs
input [4 : 0] putIrqs_interruptLines;
input EN_putIrqs;
output RDY_putIrqs;
// action method debugStream_request_put
input [7 : 0] debugStream_request_put;
input EN_debugStream_request_put;
output RDY_debugStream_request_put;
// actionvalue method debugStream_response_get
input EN_debugStream_response_get;
output [7 : 0] debugStream_response_get;
output RDY_debugStream_response_get;
// signals for module outputs
wire [316 : 0] memory_request_get;
wire [7 : 0] debugStream_response_get;
wire RDY_debugStream_request_put,
RDY_debugStream_response_get,
RDY_memory_request_get,
RDY_memory_response_put,
RDY_putIrqs;
// inlined wires
reg [68 : 0] theMem_dCache_out_fifo_enqw$wget,
theMem_iCache_out_fifo_enqw$wget;
wire [49 : 0] theMem_dCache_tags_serverAdapterA_outData_outData$wget;
wire [24 : 0] theMem_iCache_tags_serverAdapterA_outData_outData$wget;
wire [1 : 0] theMem_dCache_data_serverAdapterA_s1_1$wget,
theMem_dCache_data_serverAdapterB_s1_1$wget,
theMem_dCache_tags_serverAdapterB_s1_1$wget,
theMem_iCache_bank_serverAdapterA_s1_1$wget,
theMem_iCache_bank_serverAdapterB_s1_1$wget,
theMem_iCache_tags_serverAdapterA_s1_1$wget,
theMem_iCache_tags_serverAdapterB_s1_1$wget;
wire freeRenameReg_r_enq$whas,
theDebug_trace_buf_doEnq$whas,
theMem_dCache_data_serverAdapterA_cnt_1$whas,
theMem_dCache_data_serverAdapterA_outData_deqCalled$whas,
theMem_dCache_data_serverAdapterA_outData_enqData$whas,
theMem_dCache_data_serverAdapterA_outData_outData$whas,
theMem_dCache_data_serverAdapterA_writeWithResp$whas,
theMem_dCache_data_serverAdapterB_cnt_1$whas,
theMem_dCache_data_serverAdapterB_outData_enqData$whas,
theMem_dCache_data_serverAdapterB_writeWithResp$whas,
theMem_dCache_out_fifo_enqw$whas,
theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas,
theMem_dCache_tags_serverAdapterA_outData_enqData$whas,
theMem_dCache_tags_serverAdapterA_outData_outData$whas,
theMem_dCache_tags_serverAdapterB_cnt_1$whas,
theMem_dCache_tags_serverAdapterB_outData_enqData$whas,
theMem_iCache_bank_serverAdapterA_cnt_1$whas,
theMem_iCache_bank_serverAdapterA_outData_enqData$whas,
theMem_iCache_bank_serverAdapterA_outData_outData$whas,
theMem_iCache_bank_serverAdapterA_writeWithResp$whas,
theMem_iCache_bank_serverAdapterB_cnt_1$whas,
theMem_iCache_bank_serverAdapterB_outData_enqData$whas,
theMem_iCache_bank_serverAdapterB_writeWithResp$whas,
theMem_iCache_out_fifo_enqw$whas,
theMem_iCache_tags_serverAdapterA_cnt_1$whas,
theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas,
theMem_iCache_tags_serverAdapterA_outData_enqData$whas,
theMem_iCache_tags_serverAdapterA_outData_outData$whas,
theMem_iCache_tags_serverAdapterA_writeWithResp$whas,
theMem_iCache_tags_serverAdapterB_cnt_1$whas,
theMem_iCache_tags_serverAdapterB_outData_enqData$whas;
// register execute_hi
reg [63 : 0] execute_hi;
wire [63 : 0] execute_hi$D_IN;
wire execute_hi$EN;
// register execute_lo
reg [63 : 0] execute_lo;
wire [63 : 0] execute_lo$D_IN;
wire execute_lo$EN;
// register execute_loadsDone
reg [3 : 0] execute_loadsDone;
wire [3 : 0] execute_loadsDone$D_IN;
wire execute_loadsDone$EN;
// register execute_loadsIn
reg [3 : 0] execute_loadsIn;
wire [3 : 0] execute_loadsIn$D_IN;
wire execute_loadsIn$EN;
// register execute_renameRegsVector
reg [64 : 0] execute_renameRegsVector;
reg [64 : 0] execute_renameRegsVector$D_IN;
wire execute_renameRegsVector$EN;
// register execute_renameRegsVector_1
reg [64 : 0] execute_renameRegsVector_1;
reg [64 : 0] execute_renameRegsVector_1$D_IN;
wire execute_renameRegsVector_1$EN;
// register execute_renameRegsVector_2
reg [64 : 0] execute_renameRegsVector_2;
reg [64 : 0] execute_renameRegsVector_2$D_IN;
wire execute_renameRegsVector_2$EN;
// register execute_renameRegsVector_3
reg [64 : 0] execute_renameRegsVector_3;
reg [64 : 0] execute_renameRegsVector_3$D_IN;
wire execute_renameRegsVector_3$EN;
// register freeRenameReg_countReg
reg [2 : 0] freeRenameReg_countReg;
wire [2 : 0] freeRenameReg_countReg$D_IN;
wire freeRenameReg_countReg$EN;
// register freeRenameReg_levelsValid
reg freeRenameReg_levelsValid;
wire freeRenameReg_levelsValid$D_IN, freeRenameReg_levelsValid$EN;
// register init
reg [2 : 0] init;
wire [2 : 0] init$D_IN;
wire init$EN;
// register initState
reg initState;
wire initState$D_IN, initState$EN;
// register lastEpoch
reg [2 : 0] lastEpoch;
wire [2 : 0] lastEpoch$D_IN;
wire lastEpoch$EN;
// register lastWasBranch
reg lastWasBranch;
wire lastWasBranch$D_IN, lastWasBranch$EN;
// register nextId
reg [3 : 0] nextId;
wire [3 : 0] nextId$D_IN;
wire nextId$EN;
// register nextInstruction_taggedReg
reg [69 : 0] nextInstruction_taggedReg;
wire [69 : 0] nextInstruction_taggedReg$D_IN;
wire nextInstruction_taggedReg$EN;
// register regRenameTable
reg [47 : 0] regRenameTable;
wire [47 : 0] regRenameTable$D_IN;
wire regRenameTable$EN;
// register theCapCop_capState
reg [2 : 0] theCapCop_capState;
reg [2 : 0] theCapCop_capState$D_IN;
wire theCapCop_capState$EN;
// register theCapCop_capWriteback
reg [268 : 0] theCapCop_capWriteback;
wire [268 : 0] theCapCop_capWriteback$D_IN;
wire theCapCop_capWriteback$EN;
// register theCapCop_commitWritebackFifo_taggedReg
reg [1 : 0] theCapCop_commitWritebackFifo_taggedReg;
wire [1 : 0] theCapCop_commitWritebackFifo_taggedReg$D_IN;
wire theCapCop_commitWritebackFifo_taggedReg$EN;
// register theCapCop_count
reg [4 : 0] theCapCop_count;
wire [4 : 0] theCapCop_count$D_IN;
wire theCapCop_count$EN;
// register theCapCop_pcc
reg [255 : 0] theCapCop_pcc;
wire [255 : 0] theCapCop_pcc$D_IN;
wire theCapCop_pcc$EN;
// register theCapCop_pipeEmpty
reg theCapCop_pipeEmpty;
wire theCapCop_pipeEmpty$D_IN, theCapCop_pipeEmpty$EN;
// register theCapCop_writesCalculated
reg [4 : 0] theCapCop_writesCalculated;
wire [4 : 0] theCapCop_writesCalculated$D_IN;
wire theCapCop_writesCalculated$EN;
// register theCapCop_writesDone
reg [4 : 0] theCapCop_writesDone;
wire [4 : 0] theCapCop_writesDone$D_IN;
wire theCapCop_writesDone$EN;
// register theCapCop_writesIn
reg [4 : 0] theCapCop_writesIn;
wire [4 : 0] theCapCop_writesIn$D_IN;
wire theCapCop_writesIn$EN;
// register theDebug_bp
reg [64 : 0] theDebug_bp;
wire [64 : 0] theDebug_bp$D_IN;
wire theDebug_bp$EN;
// register theDebug_bp_1
reg [64 : 0] theDebug_bp_1;
wire [64 : 0] theDebug_bp_1$D_IN;
wire theDebug_bp_1$EN;
// register theDebug_bp_2
reg [64 : 0] theDebug_bp_2;
wire [64 : 0] theDebug_bp_2$D_IN;
wire theDebug_bp_2$EN;
// register theDebug_bp_3
reg [64 : 0] theDebug_bp_3;
wire [64 : 0] theDebug_bp_3$D_IN;
wire theDebug_bp_3$EN;
// register theDebug_dest
reg [63 : 0] theDebug_dest;
wire [63 : 0] theDebug_dest$D_IN;
wire theDebug_dest$EN;
// register theDebug_idleCount
reg [27 : 0] theDebug_idleCount;
wire [27 : 0] theDebug_idleCount$D_IN;
wire theDebug_idleCount$EN;
// register theDebug_instDelay
reg [5 : 0] theDebug_instDelay;
wire [5 : 0] theDebug_instDelay$D_IN;
wire theDebug_instDelay$EN;
// register theDebug_instQnotEmpty
reg theDebug_instQnotEmpty;
wire theDebug_instQnotEmpty$D_IN, theDebug_instQnotEmpty$EN;
// register theDebug_instruction
reg [31 : 0] theDebug_instruction;
wire [31 : 0] theDebug_instruction$D_IN;
wire theDebug_instruction$EN;
// register theDebug_mipsPC
reg [63 : 0] theDebug_mipsPC;
reg [63 : 0] theDebug_mipsPC$D_IN;
wire theDebug_mipsPC$EN;
// register theDebug_opA
reg [63 : 0] theDebug_opA;
wire [63 : 0] theDebug_opA$D_IN;
wire theDebug_opA$EN;
// register theDebug_opB
reg [63 : 0] theDebug_opB;
wire [63 : 0] theDebug_opB$D_IN;
wire theDebug_opB$EN;
// register theDebug_pauseForInst
reg theDebug_pauseForInst;
wire theDebug_pauseForInst$D_IN, theDebug_pauseForInst$EN;
// register theDebug_pausePipe
reg theDebug_pausePipe;
reg theDebug_pausePipe$D_IN;
wire theDebug_pausePipe$EN;
// register theDebug_pipeCount
reg [2 : 0] theDebug_pipeCount;
wire [2 : 0] theDebug_pipeCount$D_IN;
wire theDebug_pipeCount$EN;
// register theDebug_pollCount
reg [23 : 0] theDebug_pollCount;
wire [23 : 0] theDebug_pollCount$D_IN;
wire theDebug_pollCount$EN;
// register theDebug_previousPausePipe
reg theDebug_previousPausePipe;
wire theDebug_previousPausePipe$D_IN, theDebug_previousPausePipe$EN;
// register theDebug_state
reg [1 : 0] theDebug_state;
reg [1 : 0] theDebug_state$D_IN;
wire theDebug_state$EN;
// register theDebug_traceCmp
reg [255 : 0] theDebug_traceCmp;
wire [255 : 0] theDebug_traceCmp$D_IN;
wire theDebug_traceCmp$EN;
// register theDebug_traceCmpMask
reg [255 : 0] theDebug_traceCmpMask;
wire [255 : 0] theDebug_traceCmpMask$D_IN;
wire theDebug_traceCmpMask$EN;
// register theDebug_trace_buf_headPtr
reg [11 : 0] theDebug_trace_buf_headPtr;
wire [11 : 0] theDebug_trace_buf_headPtr$D_IN;
wire theDebug_trace_buf_headPtr$EN;
// register theDebug_trace_buf_readDelay
reg theDebug_trace_buf_readDelay;
wire theDebug_trace_buf_readDelay$D_IN, theDebug_trace_buf_readDelay$EN;
// register theDebug_trace_buf_tailPtr
reg [11 : 0] theDebug_trace_buf_tailPtr;
wire [11 : 0] theDebug_trace_buf_tailPtr$D_IN;
wire theDebug_trace_buf_tailPtr$EN;
// register theDebug_unPipeline
reg theDebug_unPipeline;
wire theDebug_unPipeline$D_IN, theDebug_unPipeline$EN;
// register theMem_dCache_addrReg
reg [35 : 0] theMem_dCache_addrReg;
wire [35 : 0] theMem_dCache_addrReg$D_IN;
wire theMem_dCache_addrReg$EN;
// register theMem_dCache_byteWriteReg
reg [7 : 0] theMem_dCache_byteWriteReg;
wire [7 : 0] theMem_dCache_byteWriteReg$D_IN;
wire theMem_dCache_byteWriteReg$EN;
// register theMem_dCache_cacheState
reg [2 : 0] theMem_dCache_cacheState;
reg [2 : 0] theMem_dCache_cacheState$D_IN;
wire theMem_dCache_cacheState$EN;
// register theMem_dCache_count
reg [6 : 0] theMem_dCache_count;
wire [6 : 0] theMem_dCache_count$D_IN;
wire theMem_dCache_count$EN;
// register theMem_dCache_data_serverAdapterA_cnt
reg [2 : 0] theMem_dCache_data_serverAdapterA_cnt;
wire [2 : 0] theMem_dCache_data_serverAdapterA_cnt$D_IN;
wire theMem_dCache_data_serverAdapterA_cnt$EN;
// register theMem_dCache_data_serverAdapterA_s1
reg [1 : 0] theMem_dCache_data_serverAdapterA_s1;
wire [1 : 0] theMem_dCache_data_serverAdapterA_s1$D_IN;
wire theMem_dCache_data_serverAdapterA_s1$EN;
// register theMem_dCache_data_serverAdapterB_cnt
reg [2 : 0] theMem_dCache_data_serverAdapterB_cnt;
wire [2 : 0] theMem_dCache_data_serverAdapterB_cnt$D_IN;
wire theMem_dCache_data_serverAdapterB_cnt$EN;
// register theMem_dCache_data_serverAdapterB_s1
reg [1 : 0] theMem_dCache_data_serverAdapterB_s1;
wire [1 : 0] theMem_dCache_data_serverAdapterB_s1$D_IN;
wire theMem_dCache_data_serverAdapterB_s1$EN;
// register theMem_dCache_fillCount
reg [1 : 0] theMem_dCache_fillCount;
wire [1 : 0] theMem_dCache_fillCount$D_IN;
wire theMem_dCache_fillCount$EN;
// register theMem_dCache_lastKey
reg [6 : 0] theMem_dCache_lastKey;
wire [6 : 0] theMem_dCache_lastKey$D_IN;
wire theMem_dCache_lastKey$EN;
// register theMem_dCache_missCached
reg theMem_dCache_missCached;
wire theMem_dCache_missCached$D_IN, theMem_dCache_missCached$EN;
// register theMem_dCache_recentlyUsedWay
reg theMem_dCache_recentlyUsedWay;
wire theMem_dCache_recentlyUsedWay$D_IN, theMem_dCache_recentlyUsedWay$EN;
// register theMem_dCache_tags_serverAdapterA_cnt
reg [2 : 0] theMem_dCache_tags_serverAdapterA_cnt;
wire [2 : 0] theMem_dCache_tags_serverAdapterA_cnt$D_IN;
wire theMem_dCache_tags_serverAdapterA_cnt$EN;
// register theMem_dCache_tags_serverAdapterA_s1
reg [1 : 0] theMem_dCache_tags_serverAdapterA_s1;
wire [1 : 0] theMem_dCache_tags_serverAdapterA_s1$D_IN;
wire theMem_dCache_tags_serverAdapterA_s1$EN;
// register theMem_dCache_tags_serverAdapterB_cnt
reg [2 : 0] theMem_dCache_tags_serverAdapterB_cnt;
wire [2 : 0] theMem_dCache_tags_serverAdapterB_cnt$D_IN;
wire theMem_dCache_tags_serverAdapterB_cnt$EN;
// register theMem_dCache_tags_serverAdapterB_s1
reg [1 : 0] theMem_dCache_tags_serverAdapterB_s1;
wire [1 : 0] theMem_dCache_tags_serverAdapterB_s1$D_IN;
wire theMem_dCache_tags_serverAdapterB_s1$EN;
// register theMem_dCache_updateReg
reg [255 : 0] theMem_dCache_updateReg;
wire [255 : 0] theMem_dCache_updateReg$D_IN;
wire theMem_dCache_updateReg$EN;
// register theMem_iCache_bank_serverAdapterA_cnt
reg [2 : 0] theMem_iCache_bank_serverAdapterA_cnt;
wire [2 : 0] theMem_iCache_bank_serverAdapterA_cnt$D_IN;
wire theMem_iCache_bank_serverAdapterA_cnt$EN;
// register theMem_iCache_bank_serverAdapterA_s1
reg [1 : 0] theMem_iCache_bank_serverAdapterA_s1;
wire [1 : 0] theMem_iCache_bank_serverAdapterA_s1$D_IN;
wire theMem_iCache_bank_serverAdapterA_s1$EN;
// register theMem_iCache_bank_serverAdapterB_cnt
reg [2 : 0] theMem_iCache_bank_serverAdapterB_cnt;
wire [2 : 0] theMem_iCache_bank_serverAdapterB_cnt$D_IN;
wire theMem_iCache_bank_serverAdapterB_cnt$EN;
// register theMem_iCache_bank_serverAdapterB_s1
reg [1 : 0] theMem_iCache_bank_serverAdapterB_s1;
wire [1 : 0] theMem_iCache_bank_serverAdapterB_s1$D_IN;
wire theMem_iCache_bank_serverAdapterB_s1$EN;
// register theMem_iCache_byteWriteReg
reg [7 : 0] theMem_iCache_byteWriteReg;
wire [7 : 0] theMem_iCache_byteWriteReg$D_IN;
wire theMem_iCache_byteWriteReg$EN;
// register theMem_iCache_cacheState
reg [1 : 0] theMem_iCache_cacheState;
reg [1 : 0] theMem_iCache_cacheState$D_IN;
wire theMem_iCache_cacheState$EN;
// register theMem_iCache_count
reg [8 : 0] theMem_iCache_count;
wire [8 : 0] theMem_iCache_count$D_IN;
wire theMem_iCache_count$EN;
// register theMem_iCache_fillCount
reg [1 : 0] theMem_iCache_fillCount;
wire [1 : 0] theMem_iCache_fillCount$D_IN;
wire theMem_iCache_fillCount$EN;
// register theMem_iCache_missCached
reg theMem_iCache_missCached;
wire theMem_iCache_missCached$D_IN, theMem_iCache_missCached$EN;
// register theMem_iCache_phyAddrReg
reg [35 : 0] theMem_iCache_phyAddrReg;
wire [35 : 0] theMem_iCache_phyAddrReg$D_IN;
wire theMem_iCache_phyAddrReg$EN;
// register theMem_iCache_tags_serverAdapterA_cnt
reg [2 : 0] theMem_iCache_tags_serverAdapterA_cnt;
wire [2 : 0] theMem_iCache_tags_serverAdapterA_cnt$D_IN;
wire theMem_iCache_tags_serverAdapterA_cnt$EN;
// register theMem_iCache_tags_serverAdapterA_s1
reg [1 : 0] theMem_iCache_tags_serverAdapterA_s1;
wire [1 : 0] theMem_iCache_tags_serverAdapterA_s1$D_IN;
wire theMem_iCache_tags_serverAdapterA_s1$EN;
// register theMem_iCache_tags_serverAdapterB_cnt
reg [2 : 0] theMem_iCache_tags_serverAdapterB_cnt;
wire [2 : 0] theMem_iCache_tags_serverAdapterB_cnt$D_IN;
wire theMem_iCache_tags_serverAdapterB_cnt$EN;
// register theMem_iCache_tags_serverAdapterB_s1
reg [1 : 0] theMem_iCache_tags_serverAdapterB_s1;
wire [1 : 0] theMem_iCache_tags_serverAdapterB_s1$D_IN;
wire theMem_iCache_tags_serverAdapterB_s1$EN;
// register theMem_iCache_updateReg
reg [255 : 0] theMem_iCache_updateReg;
wire [255 : 0] theMem_iCache_updateReg$D_IN;
wire theMem_iCache_updateReg$EN;
// register theMem_iCache_validFillLine
reg theMem_iCache_validFillLine;
wire theMem_iCache_validFillLine$D_IN, theMem_iCache_validFillLine$EN;
// register theMem_iCache_virAddrReg
reg [63 : 0] theMem_iCache_virAddrReg;
wire [63 : 0] theMem_iCache_virAddrReg$D_IN;
wire theMem_iCache_virAddrReg$EN;
// register theRF_count
reg [4 : 0] theRF_count;
wire [4 : 0] theRF_count$D_IN;
wire theRF_count$EN;
// register theRF_regFileState
reg theRF_regFileState;
wire theRF_regFileState$D_IN, theRF_regFileState$EN;
// register writeback_cyclCount
reg [15 : 0] writeback_cyclCount;
wire [15 : 0] writeback_cyclCount$D_IN;
wire writeback_cyclCount$EN;
// register writeback_instCount
reg [63 : 0] writeback_instCount;
reg [63 : 0] writeback_instCount$D_IN;
wire writeback_instCount$EN;
// register writeback_lsInCycCt
reg [15 : 0] writeback_lsInCycCt;
wire [15 : 0] writeback_lsInCycCt$D_IN;
wire writeback_lsInCycCt$EN;
// ports of submodule branch
reg [64 : 0] branch$pcWriteback_truePc;
reg branch$pcWriteback_exception;
wire [66 : 0] branch$getPc;
wire [63 : 0] branch$putRegisterTarget_target, branch$putTarget_target;
wire [3 : 0] branch$getPc_id,
branch$putRegisterTarget_id,
branch$putTarget_id;
wire [2 : 0] branch$getEpoch,
branch$putRegisterTarget_instEpoch,
branch$putTarget_instEpoch;
wire [1 : 0] branch$putTarget_branchType;
wire branch$EN_getPc,
branch$EN_pcWriteback,
branch$EN_putRegisterTarget,
branch$EN_putTarget,
branch$RDY_getPc,
branch$RDY_pcWriteback,
branch$RDY_putRegisterTarget,
branch$RDY_putTarget,
branch$getPc_fromDebug,
branch$pcWriteback_fromDebug,
branch$putRegisterTarget_fromDebug,
branch$putTarget_fromDebug;
// ports of submodule decode_inQ
wire [444 : 0] decode_inQ$D_IN, decode_inQ$D_OUT;
wire decode_inQ$CLR,
decode_inQ$DEQ,
decode_inQ$EMPTY_N,
decode_inQ$ENQ,
decode_inQ$FULL_N;
// ports of submodule execute_hiLoPending
wire execute_hiLoPending$CLR,
execute_hiLoPending$DEQ,
execute_hiLoPending$D_IN,
execute_hiLoPending$EMPTY_N,
execute_hiLoPending$ENQ,
execute_hiLoPending$FULL_N;
// ports of submodule execute_inQ
wire [444 : 0] execute_inQ$D_IN, execute_inQ$D_OUT;
wire execute_inQ$CLR,
execute_inQ$DEQ,
execute_inQ$EMPTY_N,
execute_inQ$ENQ,
execute_inQ$FULL_N;
// ports of submodule execute_mul
wire [262 : 0] execute_mul$muldiv_request_put;
wire [129 : 0] execute_mul$muldiv_response_get;
wire execute_mul$EN_muldiv_request_put,
execute_mul$EN_muldiv_response_get,
execute_mul$RDY_muldiv_request_put,
execute_mul$RDY_muldiv_response_get;
// ports of submodule execute_pendingOps
wire [444 : 0] execute_pendingOps$D_IN, execute_pendingOps$D_OUT;
wire execute_pendingOps$CLR,
execute_pendingOps$DEQ,
execute_pendingOps$EMPTY_N,
execute_pendingOps$ENQ,
execute_pendingOps$FULL_N;
// ports of submodule fetchedControlToken
wire [444 : 0] fetchedControlToken$D_IN, fetchedControlToken$D_OUT;
wire fetchedControlToken$CLR,
fetchedControlToken$DEQ,
fetchedControlToken$EMPTY_N,
fetchedControlToken$ENQ,
fetchedControlToken$FULL_N;
// ports of submodule freeRenameReg
wire [1 : 0] freeRenameReg$D_IN;
wire freeRenameReg$CLR,
freeRenameReg$DEQ,
freeRenameReg$EMPTY_N,
freeRenameReg$ENQ,
freeRenameReg$FULL_N;
// ports of submodule memAccessToWriteback
wire [444 : 0] memAccessToWriteback$D_IN, memAccessToWriteback$D_OUT;
wire memAccessToWriteback$CLR,
memAccessToWriteback$DEQ,
memAccessToWriteback$EMPTY_N,
memAccessToWriteback$ENQ,
memAccessToWriteback$FULL_N;
// ports of submodule memAccess_inQ
wire [444 : 0] memAccess_inQ$D_IN, memAccess_inQ$D_OUT;
wire memAccess_inQ$CLR,
memAccess_inQ$DEQ,
memAccess_inQ$EMPTY_N,
memAccess_inQ$ENQ,
memAccess_inQ$FULL_N;
// ports of submodule theCP0
reg [138 : 0] theCP0$putException_exp;
reg theCP0$writeReg_writeBack;
wire [74 : 0] theCP0$tlbLookupCoprocessors_0_request_put,
theCP0$tlbLookupData_request_put,
theCP0$tlbLookupInstruction_request_put;
wire [63 : 0] theCP0$getLlScReg_matchAddress,
theCP0$readGet,
theCP0$writeReg_data;
wire [49 : 0] theCP0$tlbLookupCoprocessors_0_response_get,
theCP0$tlbLookupData_response_get,
theCP0$tlbLookupInstruction_response_get;
wire [6 : 0] theCP0$getException;
wire [4 : 0] theCP0$interrupts_interruptLines,
theCP0$readReq_rn,
theCP0$writeReg_rn;
wire [3 : 0] theCP0$getCoprocessorEnables;
wire [2 : 0] theCP0$readReq_sel;
wire theCP0$EN_getException,
theCP0$EN_getExceptionReturn,
theCP0$EN_interrupts,
theCP0$EN_putException,
theCP0$EN_readGet,
theCP0$EN_readReq,
theCP0$EN_tlbLookupCoprocessors_0_request_put,
theCP0$EN_tlbLookupCoprocessors_0_response_get,
theCP0$EN_tlbLookupData_request_put,
theCP0$EN_tlbLookupData_response_get,
theCP0$EN_tlbLookupInstruction_request_put,
theCP0$EN_tlbLookupInstruction_response_get,
theCP0$EN_writeReg,
theCP0$RDY_getExceptionReturn,
theCP0$RDY_readGet,
theCP0$RDY_readReq,
theCP0$RDY_tlbLookupCoprocessors_0_request_put,
theCP0$RDY_tlbLookupCoprocessors_0_response_get,
theCP0$RDY_tlbLookupData_request_put,
theCP0$RDY_tlbLookupData_response_get,
theCP0$RDY_tlbLookupInstruction_request_put,
theCP0$RDY_tlbLookupInstruction_response_get,
theCP0$RDY_writeReg,
theCP0$getLlScReg,
theCP0$readGet_goingToWrite,
theCP0$writeReg_forceKernelMode;
// ports of submodule theCapCop_baseRegs
reg [63 : 0] theCapCop_baseRegs$D_IN;
reg [4 : 0] theCapCop_baseRegs$ADDR_IN;
wire [63 : 0] theCapCop_baseRegs$D_OUT_1, theCapCop_baseRegs$D_OUT_2;
wire [4 : 0] theCapCop_baseRegs$ADDR_1,
theCapCop_baseRegs$ADDR_2,
theCapCop_baseRegs$ADDR_3,
theCapCop_baseRegs$ADDR_4,
theCapCop_baseRegs$ADDR_5;
wire theCapCop_baseRegs$WE;
// ports of submodule theCapCop_capInsts
wire [99 : 0] theCapCop_capInsts$D_IN, theCapCop_capInsts$D_OUT;
wire theCapCop_capInsts$CLR,
theCapCop_capInsts$DEQ,
theCapCop_capInsts$EMPTY_N,
theCapCop_capInsts$ENQ,
theCapCop_capInsts$FULL_N;
// ports of submodule theCapCop_capMemInsts
wire [337 : 0] theCapCop_capMemInsts$D_IN, theCapCop_capMemInsts$D_OUT;
wire theCapCop_capMemInsts$CLR,
theCapCop_capMemInsts$DEQ,
theCapCop_capMemInsts$EMPTY_N,
theCapCop_capMemInsts$ENQ,
theCapCop_capMemInsts$FULL_N;
// ports of submodule theCapCop_capWritebackTags
wire [12 : 0] theCapCop_capWritebackTags$D_IN,
theCapCop_capWritebackTags$D_OUT;
wire theCapCop_capWritebackTags$CLR,
theCapCop_capWritebackTags$DEQ,
theCapCop_capWritebackTags$EMPTY_N,
theCapCop_capWritebackTags$ENQ,
theCapCop_capWritebackTags$FULL_N;
// ports of submodule theCapCop_commitStore
wire theCapCop_commitStore$CLR,
theCapCop_commitStore$DEQ,
theCapCop_commitStore$D_IN,
theCapCop_commitStore$ENQ;
// ports of submodule theCapCop_exception
wire theCapCop_exception$CLR,
theCapCop_exception$DEQ,
theCapCop_exception$D_IN,
theCapCop_exception$D_OUT,
theCapCop_exception$EMPTY_N,
theCapCop_exception$ENQ,
theCapCop_exception$FULL_N;
// ports of submodule theCapCop_fetchFifoA
wire [4 : 0] theCapCop_fetchFifoA$D_IN, theCapCop_fetchFifoA$D_OUT;
wire theCapCop_fetchFifoA$CLR,
theCapCop_fetchFifoA$DEQ,
theCapCop_fetchFifoA$EMPTY_N,
theCapCop_fetchFifoA$ENQ,
theCapCop_fetchFifoA$FULL_N;
// ports of submodule theCapCop_fetchFifoB
wire [4 : 0] theCapCop_fetchFifoB$D_IN, theCapCop_fetchFifoB$D_OUT;
wire theCapCop_fetchFifoB$CLR,
theCapCop_fetchFifoB$DEQ,
theCapCop_fetchFifoB$EMPTY_N,
theCapCop_fetchFifoB$ENQ,
theCapCop_fetchFifoB$FULL_N;
// ports of submodule theCapCop_insts
wire theCapCop_insts$CLR,
theCapCop_insts$DEQ,
theCapCop_insts$D_IN,
theCapCop_insts$EMPTY_N,
theCapCop_insts$ENQ,
theCapCop_insts$FULL_N;
// ports of submodule theCapCop_lengthRegs
reg [63 : 0] theCapCop_lengthRegs$D_IN;
reg [4 : 0] theCapCop_lengthRegs$ADDR_IN;
wire [63 : 0] theCapCop_lengthRegs$D_OUT_1, theCapCop_lengthRegs$D_OUT_2;
wire [4 : 0] theCapCop_lengthRegs$ADDR_1,
theCapCop_lengthRegs$ADDR_2,
theCapCop_lengthRegs$ADDR_3,
theCapCop_lengthRegs$ADDR_4,
theCapCop_lengthRegs$ADDR_5;
wire theCapCop_lengthRegs$WE;
// ports of submodule theCapCop_memResponse
wire [255 : 0] theCapCop_memResponse$D_IN;
wire theCapCop_memResponse$CLR,
theCapCop_memResponse$DEQ,
theCapCop_memResponse$ENQ,
theCapCop_memResponse$FULL_N;
// ports of submodule theCapCop_nextCapState
wire [2 : 0] theCapCop_nextCapState$D_IN;
wire theCapCop_nextCapState$CLR,
theCapCop_nextCapState$DEQ,
theCapCop_nextCapState$ENQ;
// ports of submodule theCapCop_nextWillWriteback
wire theCapCop_nextWillWriteback$CLR,
theCapCop_nextWillWriteback$DEQ,
theCapCop_nextWillWriteback$D_IN,
theCapCop_nextWillWriteback$D_OUT,
theCapCop_nextWillWriteback$EMPTY_N,
theCapCop_nextWillWriteback$ENQ,
theCapCop_nextWillWriteback$FULL_N;
// ports of submodule theCapCop_oTypeRegs
reg [63 : 0] theCapCop_oTypeRegs$D_IN;
reg [4 : 0] theCapCop_oTypeRegs$ADDR_IN;
wire [63 : 0] theCapCop_oTypeRegs$D_OUT_1;
wire [4 : 0] theCapCop_oTypeRegs$ADDR_1,
theCapCop_oTypeRegs$ADDR_2,
theCapCop_oTypeRegs$ADDR_3,
theCapCop_oTypeRegs$ADDR_4,
theCapCop_oTypeRegs$ADDR_5;
wire theCapCop_oTypeRegs$WE;
// ports of submodule theCapCop_permRegs
reg [63 : 0] theCapCop_permRegs$D_IN;
reg [4 : 0] theCapCop_permRegs$ADDR_IN;
wire [63 : 0] theCapCop_permRegs$D_OUT_1;
wire [4 : 0] theCapCop_permRegs$ADDR_1,
theCapCop_permRegs$ADDR_2,
theCapCop_permRegs$ADDR_3,
theCapCop_permRegs$ADDR_4,
theCapCop_permRegs$ADDR_5;
wire theCapCop_permRegs$WE;
// ports of submodule theCapCop_startExp
wire theCapCop_startExp$CLR,
theCapCop_startExp$DEQ,
theCapCop_startExp$D_IN,
theCapCop_startExp$EMPTY_N,
theCapCop_startExp$ENQ,
theCapCop_startExp$FULL_N;
// ports of submodule theDebug_bpReport
wire [271 : 0] theDebug_bpReport$D_IN, theDebug_bpReport$D_OUT;
wire theDebug_bpReport$CLR,
theDebug_bpReport$DEQ,
theDebug_bpReport$EMPTY_N,
theDebug_bpReport$ENQ,
theDebug_bpReport$FULL_N;
// ports of submodule theDebug_curCommand
wire [271 : 0] theDebug_curCommand$D_IN, theDebug_curCommand$D_OUT;
wire theDebug_curCommand$CLR,
theDebug_curCommand$DEQ,
theDebug_curCommand$EMPTY_N,
theDebug_curCommand$ENQ,
theDebug_curCommand$FULL_N;
// ports of submodule theDebug_debugConvert
reg [271 : 0] theDebug_debugConvert$messages_response_put;
wire [271 : 0] theDebug_debugConvert$messages_request_get;
wire [7 : 0] theDebug_debugConvert$stream_request_put,
theDebug_debugConvert$stream_response_get;
wire theDebug_debugConvert$EN_messages_request_get,
theDebug_debugConvert$EN_messages_response_put,
theDebug_debugConvert$EN_stream_request_put,
theDebug_debugConvert$EN_stream_response_get,
theDebug_debugConvert$RDY_messages_request_get,
theDebug_debugConvert$RDY_messages_response_put,
theDebug_debugConvert$RDY_stream_request_put,
theDebug_debugConvert$RDY_stream_response_get;
// ports of submodule theDebug_doneInst
wire theDebug_doneInst$CLR,
theDebug_doneInst$DEQ,
theDebug_doneInst$D_IN,
theDebug_doneInst$ENQ;
// ports of submodule theDebug_instQ
wire [31 : 0] theDebug_instQ$D_IN, theDebug_instQ$D_OUT;
wire theDebug_instQ$CLR,
theDebug_instQ$DEQ,
theDebug_instQ$EMPTY_N,
theDebug_instQ$ENQ,
theDebug_instQ$FULL_N;
// ports of submodule theDebug_trace_buf_bram
wire [255 : 0] theDebug_trace_buf_bram$DIA,
theDebug_trace_buf_bram$DIB,
theDebug_trace_buf_bram$DOB;
wire [11 : 0] theDebug_trace_buf_bram$ADDRA, theDebug_trace_buf_bram$ADDRB;
wire theDebug_trace_buf_bram$ENA,
theDebug_trace_buf_bram$ENB,
theDebug_trace_buf_bram$WEA,
theDebug_trace_buf_bram$WEB;
// ports of submodule theDebug_writebacks
reg [69 : 0] theDebug_writebacks$D_IN;
wire [69 : 0] theDebug_writebacks$D_OUT;
wire theDebug_writebacks$CLR,
theDebug_writebacks$DEQ,
theDebug_writebacks$EMPTY_N,
theDebug_writebacks$ENQ,
theDebug_writebacks$FULL_N;
// ports of submodule theMem_capExceptions
wire [8 : 0] theMem_capExceptions$D_IN, theMem_capExceptions$D_OUT;
wire theMem_capExceptions$CLR,
theMem_capExceptions$DEQ,
theMem_capExceptions$EMPTY_N,
theMem_capExceptions$ENQ,
theMem_capExceptions$FULL_N;
// ports of submodule theMem_capPackets
wire [325 : 0] theMem_capPackets$D_IN, theMem_capPackets$D_OUT;
wire theMem_capPackets$CLR,
theMem_capPackets$DEQ,
theMem_capPackets$EMPTY_N,
theMem_capPackets$ENQ,
theMem_capPackets$FULL_N;
// ports of submodule theMem_capTlbResp
wire [49 : 0] theMem_capTlbResp$D_IN, theMem_capTlbResp$D_OUT;
wire theMem_capTlbResp$CLR,
theMem_capTlbResp$DEQ,
theMem_capTlbResp$EMPTY_N,
theMem_capTlbResp$ENQ,
theMem_capTlbResp$FULL_N;
// ports of submodule theMem_commitCapStore
wire theMem_commitCapStore$CLR,
theMem_commitCapStore$DEQ,
theMem_commitCapStore$D_IN,
theMem_commitCapStore$D_OUT,
theMem_commitCapStore$EMPTY_N,
theMem_commitCapStore$ENQ,
theMem_commitCapStore$FULL_N;
// ports of submodule theMem_dCache_data_memory
reg [63 : 0] theMem_dCache_data_memory$DIB;
reg [9 : 0] theMem_dCache_data_memory$ADDRB;
wire [63 : 0] theMem_dCache_data_memory$DIA,
theMem_dCache_data_memory$DOA,
theMem_dCache_data_memory$DOB;
wire [9 : 0] theMem_dCache_data_memory$ADDRA;
wire theMem_dCache_data_memory$ENA,
theMem_dCache_data_memory$ENB,
theMem_dCache_data_memory$WEA,
theMem_dCache_data_memory$WEB;
// ports of submodule theMem_dCache_data_serverAdapterA_outDataCore
wire [63 : 0] theMem_dCache_data_serverAdapterA_outDataCore$D_IN,
theMem_dCache_data_serverAdapterA_outDataCore$D_OUT;
wire theMem_dCache_data_serverAdapterA_outDataCore$CLR,
theMem_dCache_data_serverAdapterA_outDataCore$DEQ,
theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N,
theMem_dCache_data_serverAdapterA_outDataCore$ENQ,
theMem_dCache_data_serverAdapterA_outDataCore$FULL_N;
// ports of submodule theMem_dCache_data_serverAdapterB_outDataCore
wire [63 : 0] theMem_dCache_data_serverAdapterB_outDataCore$D_IN;
wire theMem_dCache_data_serverAdapterB_outDataCore$CLR,
theMem_dCache_data_serverAdapterB_outDataCore$DEQ,
theMem_dCache_data_serverAdapterB_outDataCore$ENQ,
theMem_dCache_data_serverAdapterB_outDataCore$FULL_N;
// ports of submodule theMem_dCache_invalidateFifo
wire [11 : 0] theMem_dCache_invalidateFifo$D_IN,
theMem_dCache_invalidateFifo$D_OUT;
wire theMem_dCache_invalidateFifo$CLR,
theMem_dCache_invalidateFifo$DEQ,
theMem_dCache_invalidateFifo$EMPTY_N,
theMem_dCache_invalidateFifo$ENQ,
theMem_dCache_invalidateFifo$FULL_N;
// ports of submodule theMem_dCache_out_fifo_ff
wire [68 : 0] theMem_dCache_out_fifo_ff$D_IN,
theMem_dCache_out_fifo_ff$D_OUT;
wire theMem_dCache_out_fifo_ff$CLR,
theMem_dCache_out_fifo_ff$DEQ,
theMem_dCache_out_fifo_ff$EMPTY_N,
theMem_dCache_out_fifo_ff$ENQ,
theMem_dCache_out_fifo_ff$FULL_N;
// ports of submodule theMem_dCache_out_fifo_firstValid
wire theMem_dCache_out_fifo_firstValid$D_IN,
theMem_dCache_out_fifo_firstValid$EN,
theMem_dCache_out_fifo_firstValid$Q_OUT;
// ports of submodule theMem_dCache_req_fifo
wire [138 : 0] theMem_dCache_req_fifo$D_IN, theMem_dCache_req_fifo$D_OUT;
wire theMem_dCache_req_fifo$CLR,
theMem_dCache_req_fifo$DEQ,
theMem_dCache_req_fifo$EMPTY_N,
theMem_dCache_req_fifo$ENQ,
theMem_dCache_req_fifo$FULL_N;
// ports of submodule theMem_dCache_set_fifo
wire theMem_dCache_set_fifo$CLR,
theMem_dCache_set_fifo$DEQ,
theMem_dCache_set_fifo$D_IN,
theMem_dCache_set_fifo$ENQ;
// ports of submodule theMem_dCache_tags_fifo
wire [49 : 0] theMem_dCache_tags_fifo$D_IN, theMem_dCache_tags_fifo$D_OUT;
wire theMem_dCache_tags_fifo$CLR,
theMem_dCache_tags_fifo$DEQ,
theMem_dCache_tags_fifo$EMPTY_N,
theMem_dCache_tags_fifo$ENQ,
theMem_dCache_tags_fifo$FULL_N;
// ports of submodule theMem_dCache_tags_memory
reg [49 : 0] theMem_dCache_tags_memory$DIB;
reg [6 : 0] theMem_dCache_tags_memory$ADDRB;
wire [49 : 0] theMem_dCache_tags_memory$DIA,
theMem_dCache_tags_memory$DOA,
theMem_dCache_tags_memory$DOB;
wire [6 : 0] theMem_dCache_tags_memory$ADDRA;
wire theMem_dCache_tags_memory$ENA,
theMem_dCache_tags_memory$ENB,
theMem_dCache_tags_memory$WEA,
theMem_dCache_tags_memory$WEB;
// ports of submodule theMem_dCache_tags_serverAdapterA_outDataCore
wire [49 : 0] theMem_dCache_tags_serverAdapterA_outDataCore$D_IN,
theMem_dCache_tags_serverAdapterA_outDataCore$D_OUT;
wire theMem_dCache_tags_serverAdapterA_outDataCore$CLR,
theMem_dCache_tags_serverAdapterA_outDataCore$DEQ,
theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N,
theMem_dCache_tags_serverAdapterA_outDataCore$ENQ,
theMem_dCache_tags_serverAdapterA_outDataCore$FULL_N;
// ports of submodule theMem_dCache_tags_serverAdapterB_outDataCore
wire [49 : 0] theMem_dCache_tags_serverAdapterB_outDataCore$D_IN;
wire theMem_dCache_tags_serverAdapterB_outDataCore$CLR,
theMem_dCache_tags_serverAdapterB_outDataCore$DEQ,
theMem_dCache_tags_serverAdapterB_outDataCore$ENQ,
theMem_dCache_tags_serverAdapterB_outDataCore$FULL_N;
// ports of submodule theMem_dCache_wayKey
wire [6 : 0] theMem_dCache_wayKey$D_IN, theMem_dCache_wayKey$D_OUT;
wire theMem_dCache_wayKey$CLR,
theMem_dCache_wayKey$DEQ,
theMem_dCache_wayKey$EMPTY_N,
theMem_dCache_wayKey$ENQ,
theMem_dCache_wayKey$FULL_N;
// ports of submodule theMem_dCache_wayPredicted
wire theMem_dCache_wayPredicted$CLR,
theMem_dCache_wayPredicted$DEQ,
theMem_dCache_wayPredicted$D_IN,
theMem_dCache_wayPredicted$D_OUT,
theMem_dCache_wayPredicted$EMPTY_N,
theMem_dCache_wayPredicted$ENQ,
theMem_dCache_wayPredicted$FULL_N;
// ports of submodule theMem_dCache_wayTable
wire [6 : 0] theMem_dCache_wayTable$ADDR_1,
theMem_dCache_wayTable$ADDR_2,
theMem_dCache_wayTable$ADDR_3,
theMem_dCache_wayTable$ADDR_4,
theMem_dCache_wayTable$ADDR_5,
theMem_dCache_wayTable$ADDR_IN;
wire theMem_dCache_wayTable$D_IN,
theMem_dCache_wayTable$D_OUT_1,
theMem_dCache_wayTable$WE;
// ports of submodule theMem_dataByte
wire [2 : 0] theMem_dataByte$D_IN, theMem_dataByte$D_OUT;
wire theMem_dataByte$CLR,
theMem_dataByte$DEQ,
theMem_dataByte$EMPTY_N,
theMem_dataByte$ENQ,
theMem_dataByte$FULL_N;
// ports of submodule theMem_dataSize
wire [3 : 0] theMem_dataSize$D_IN, theMem_dataSize$D_OUT;
wire theMem_dataSize$CLR,
theMem_dataSize$DEQ,
theMem_dataSize$EMPTY_N,
theMem_dataSize$ENQ,
theMem_dataSize$FULL_N;
// ports of submodule theMem_iCacheOp
wire [138 : 0] theMem_iCacheOp$D_IN, theMem_iCacheOp$D_OUT;
wire theMem_iCacheOp$CLR,
theMem_iCacheOp$DEQ,
theMem_iCacheOp$EMPTY_N,
theMem_iCacheOp$ENQ,
theMem_iCacheOp$FULL_N;
// ports of submodule theMem_iCache_bank_memory
reg [63 : 0] theMem_iCache_bank_memory$DIA;
reg [10 : 0] theMem_iCache_bank_memory$ADDRA;
wire [63 : 0] theMem_iCache_bank_memory$DIB,
theMem_iCache_bank_memory$DOA,
theMem_iCache_bank_memory$DOB;
wire [10 : 0] theMem_iCache_bank_memory$ADDRB;
wire theMem_iCache_bank_memory$ENA,
theMem_iCache_bank_memory$ENB,
theMem_iCache_bank_memory$WEA,
theMem_iCache_bank_memory$WEB;
// ports of submodule theMem_iCache_bank_serverAdapterA_outDataCore
wire [63 : 0] theMem_iCache_bank_serverAdapterA_outDataCore$D_IN,
theMem_iCache_bank_serverAdapterA_outDataCore$D_OUT;
wire theMem_iCache_bank_serverAdapterA_outDataCore$CLR,
theMem_iCache_bank_serverAdapterA_outDataCore$DEQ,
theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N,
theMem_iCache_bank_serverAdapterA_outDataCore$ENQ,
theMem_iCache_bank_serverAdapterA_outDataCore$FULL_N;
// ports of submodule theMem_iCache_bank_serverAdapterB_outDataCore
wire [63 : 0] theMem_iCache_bank_serverAdapterB_outDataCore$D_IN;
wire theMem_iCache_bank_serverAdapterB_outDataCore$CLR,
theMem_iCache_bank_serverAdapterB_outDataCore$DEQ,
theMem_iCache_bank_serverAdapterB_outDataCore$ENQ,
theMem_iCache_bank_serverAdapterB_outDataCore$FULL_N;
// ports of submodule theMem_iCache_delayedReq
wire [138 : 0] theMem_iCache_delayedReq$D_IN;
wire theMem_iCache_delayedReq$CLR,
theMem_iCache_delayedReq$DEQ,
theMem_iCache_delayedReq$ENQ;
// ports of submodule theMem_iCache_invalidateFifo
wire [13 : 0] theMem_iCache_invalidateFifo$D_IN,
theMem_iCache_invalidateFifo$D_OUT;
wire theMem_iCache_invalidateFifo$CLR,
theMem_iCache_invalidateFifo$DEQ,
theMem_iCache_invalidateFifo$EMPTY_N,
theMem_iCache_invalidateFifo$ENQ;
// ports of submodule theMem_iCache_out_fifo_ff
wire [68 : 0] theMem_iCache_out_fifo_ff$D_IN,
theMem_iCache_out_fifo_ff$D_OUT;
wire theMem_iCache_out_fifo_ff$CLR,
theMem_iCache_out_fifo_ff$DEQ,
theMem_iCache_out_fifo_ff$EMPTY_N,
theMem_iCache_out_fifo_ff$ENQ,
theMem_iCache_out_fifo_ff$FULL_N;
// ports of submodule theMem_iCache_out_fifo_firstValid
wire theMem_iCache_out_fifo_firstValid$D_IN,
theMem_iCache_out_fifo_firstValid$EN,
theMem_iCache_out_fifo_firstValid$Q_OUT;
// ports of submodule theMem_iCache_req_fifo
reg [138 : 0] theMem_iCache_req_fifo$D_IN;
wire [138 : 0] theMem_iCache_req_fifo$D_OUT;
wire theMem_iCache_req_fifo$CLR,
theMem_iCache_req_fifo$DEQ,
theMem_iCache_req_fifo$EMPTY_N,
theMem_iCache_req_fifo$ENQ,
theMem_iCache_req_fifo$FULL_N;
// ports of submodule theMem_iCache_tags_memory
reg [24 : 0] theMem_iCache_tags_memory$DIA;
reg [8 : 0] theMem_iCache_tags_memory$ADDRA,
theMem_iCache_tags_memory$ADDRB;
wire [24 : 0] theMem_iCache_tags_memory$DIB,
theMem_iCache_tags_memory$DOA,
theMem_iCache_tags_memory$DOB;
wire theMem_iCache_tags_memory$ENA,
theMem_iCache_tags_memory$ENB,
theMem_iCache_tags_memory$WEA,
theMem_iCache_tags_memory$WEB;
// ports of submodule theMem_iCache_tags_serverAdapterA_outDataCore
wire [24 : 0] theMem_iCache_tags_serverAdapterA_outDataCore$D_IN,
theMem_iCache_tags_serverAdapterA_outDataCore$D_OUT;
wire theMem_iCache_tags_serverAdapterA_outDataCore$CLR,
theMem_iCache_tags_serverAdapterA_outDataCore$DEQ,
theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N,
theMem_iCache_tags_serverAdapterA_outDataCore$ENQ,
theMem_iCache_tags_serverAdapterA_outDataCore$FULL_N;
// ports of submodule theMem_iCache_tags_serverAdapterB_outDataCore
wire [24 : 0] theMem_iCache_tags_serverAdapterB_outDataCore$D_IN;
wire theMem_iCache_tags_serverAdapterB_outDataCore$CLR,
theMem_iCache_tags_serverAdapterB_outDataCore$DEQ,
theMem_iCache_tags_serverAdapterB_outDataCore$ENQ,
theMem_iCache_tags_serverAdapterB_outDataCore$FULL_N;
// ports of submodule theMem_iCache_writeActive
wire theMem_iCache_writeActive$CLR,
theMem_iCache_writeActive$DEQ,
theMem_iCache_writeActive$D_IN,
theMem_iCache_writeActive$ENQ;
// ports of submodule theMem_instructionWord
wire theMem_instructionWord$CLR,
theMem_instructionWord$DEQ,
theMem_instructionWord$D_IN,
theMem_instructionWord$D_OUT,
theMem_instructionWord$EMPTY_N,
theMem_instructionWord$ENQ,
theMem_instructionWord$FULL_N;
// ports of submodule theMem_l2Cache
wire [316 : 0] theMem_l2Cache$cache_request_put,
theMem_l2Cache$memory_request_get;
wire [255 : 0] theMem_l2Cache$cache_response_get,
theMem_l2Cache$memory_response_put;
wire theMem_l2Cache$EN_cache_request_put,
theMem_l2Cache$EN_cache_response_get,
theMem_l2Cache$EN_memory_request_get,
theMem_l2Cache$EN_memory_response_put,
theMem_l2Cache$RDY_cache_request_put,
theMem_l2Cache$RDY_cache_response_get,
theMem_l2Cache$RDY_memory_request_get,
theMem_l2Cache$RDY_memory_response_put;
// ports of submodule theMem_pendingExcRpt
wire theMem_pendingExcRpt$CLR,
theMem_pendingExcRpt$DEQ,
theMem_pendingExcRpt$D_IN,
theMem_pendingExcRpt$EMPTY_N,
theMem_pendingExcRpt$ENQ;
// ports of submodule theMem_theMemMerge_nextReq
wire [316 : 0] theMem_theMemMerge_nextReq$D_IN,
theMem_theMemMerge_nextReq$D_OUT;
wire theMem_theMemMerge_nextReq$CLR,
theMem_theMemMerge_nextReq$DEQ,
theMem_theMemMerge_nextReq$EMPTY_N,
theMem_theMemMerge_nextReq$ENQ,
theMem_theMemMerge_nextReq$FULL_N;
// ports of submodule theMem_theMemMerge_pendingReqs
wire [3 : 0] theMem_theMemMerge_pendingReqs$D_IN,
theMem_theMemMerge_pendingReqs$D_OUT;
wire theMem_theMemMerge_pendingReqs$CLR,
theMem_theMemMerge_pendingReqs$DEQ,
theMem_theMemMerge_pendingReqs$EMPTY_N,
theMem_theMemMerge_pendingReqs$ENQ,
theMem_theMemMerge_pendingReqs$FULL_N;
// ports of submodule theMem_theMemMerge_req_fifos
wire [316 : 0] theMem_theMemMerge_req_fifos$D_IN,
theMem_theMemMerge_req_fifos$D_OUT;
wire theMem_theMemMerge_req_fifos$CLR,
theMem_theMemMerge_req_fifos$DEQ,
theMem_theMemMerge_req_fifos$EMPTY_N,
theMem_theMemMerge_req_fifos$ENQ,
theMem_theMemMerge_req_fifos$FULL_N;
// ports of submodule theMem_theMemMerge_req_fifos_1
wire [316 : 0] theMem_theMemMerge_req_fifos_1$D_IN,
theMem_theMemMerge_req_fifos_1$D_OUT;
wire theMem_theMemMerge_req_fifos_1$CLR,
theMem_theMemMerge_req_fifos_1$DEQ,
theMem_theMemMerge_req_fifos_1$EMPTY_N,
theMem_theMemMerge_req_fifos_1$ENQ,
theMem_theMemMerge_req_fifos_1$FULL_N;
// ports of submodule theMem_theMemMerge_req_fifos_2
wire [316 : 0] theMem_theMemMerge_req_fifos_2$D_IN,
theMem_theMemMerge_req_fifos_2$D_OUT;
wire theMem_theMemMerge_req_fifos_2$CLR,
theMem_theMemMerge_req_fifos_2$DEQ,
theMem_theMemMerge_req_fifos_2$EMPTY_N,
theMem_theMemMerge_req_fifos_2$ENQ,
theMem_theMemMerge_req_fifos_2$FULL_N;
// ports of submodule theMem_theMemMerge_rsp_fifos
wire [255 : 0] theMem_theMemMerge_rsp_fifos$D_IN,
theMem_theMemMerge_rsp_fifos$D_OUT;
wire theMem_theMemMerge_rsp_fifos$CLR,
theMem_theMemMerge_rsp_fifos$DEQ,
theMem_theMemMerge_rsp_fifos$EMPTY_N,
theMem_theMemMerge_rsp_fifos$ENQ,
theMem_theMemMerge_rsp_fifos$FULL_N;
// ports of submodule theMem_theMemMerge_rsp_fifos_1
wire [255 : 0] theMem_theMemMerge_rsp_fifos_1$D_IN,
theMem_theMemMerge_rsp_fifos_1$D_OUT;
wire theMem_theMemMerge_rsp_fifos_1$CLR,
theMem_theMemMerge_rsp_fifos_1$DEQ,
theMem_theMemMerge_rsp_fifos_1$EMPTY_N,
theMem_theMemMerge_rsp_fifos_1$ENQ,
theMem_theMemMerge_rsp_fifos_1$FULL_N;
// ports of submodule theMem_theMemMerge_rsp_fifos_2
wire [255 : 0] theMem_theMemMerge_rsp_fifos_2$D_IN,
theMem_theMemMerge_rsp_fifos_2$D_OUT;
wire theMem_theMemMerge_rsp_fifos_2$CLR,
theMem_theMemMerge_rsp_fifos_2$DEQ,
theMem_theMemMerge_rsp_fifos_2$EMPTY_N,
theMem_theMemMerge_rsp_fifos_2$ENQ,
theMem_theMemMerge_rsp_fifos_2$FULL_N;
// ports of submodule theRF_idsA
wire [3 : 0] theRF_idsA$D_IN;
wire theRF_idsA$CLR, theRF_idsA$DEQ, theRF_idsA$ENQ;
// ports of submodule theRF_idsB
wire [3 : 0] theRF_idsB$D_IN;
wire theRF_idsB$CLR, theRF_idsB$DEQ, theRF_idsB$ENQ;
// ports of submodule theRF_regFile
reg [63 : 0] theRF_regFile$D_IN;
wire [63 : 0] theRF_regFile$D_OUT_1, theRF_regFile$D_OUT_2;
wire [4 : 0] theRF_regFile$ADDR_1,
theRF_regFile$ADDR_2,
theRF_regFile$ADDR_3,
theRF_regFile$ADDR_4,
theRF_regFile$ADDR_5,
theRF_regFile$ADDR_IN;
wire theRF_regFile$WE;
// ports of submodule theRF_reqA
wire [4 : 0] theRF_reqA$D_IN, theRF_reqA$D_OUT;
wire theRF_reqA$CLR,
theRF_reqA$DEQ,
theRF_reqA$EMPTY_N,
theRF_reqA$ENQ,
theRF_reqA$FULL_N;
// ports of submodule theRF_reqB
wire [4 : 0] theRF_reqB$D_IN, theRF_reqB$D_OUT;
wire theRF_reqB$CLR,
theRF_reqB$DEQ,
theRF_reqB$EMPTY_N,
theRF_reqB$ENQ,
theRF_reqB$FULL_N;
// ports of submodule writeback_destRenamed
wire [1 : 0] writeback_destRenamed$D_IN, writeback_destRenamed$D_OUT;
wire writeback_destRenamed$CLR,
writeback_destRenamed$DEQ,
writeback_destRenamed$EMPTY_N,
writeback_destRenamed$ENQ;
// ports of submodule writeback_exception
reg [4 : 0] writeback_exception$D_IN;
wire writeback_exception$CLR,
writeback_exception$DEQ,
writeback_exception$EMPTY_N,
writeback_exception$ENQ,
writeback_exception$FULL_N;
// ports of submodule writeback_hiLoCommit
reg writeback_hiLoCommit$D_IN;
wire writeback_hiLoCommit$CLR,
writeback_hiLoCommit$DEQ,
writeback_hiLoCommit$D_OUT,
writeback_hiLoCommit$EMPTY_N,
writeback_hiLoCommit$ENQ,
writeback_hiLoCommit$FULL_N;
// ports of submodule writeback_instructionReport
reg [508 : 0] writeback_instructionReport$D_IN;
wire [508 : 0] writeback_instructionReport$D_OUT;
wire writeback_instructionReport$CLR,
writeback_instructionReport$DEQ,
writeback_instructionReport$EMPTY_N,
writeback_instructionReport$ENQ,
writeback_instructionReport$FULL_N;
// ports of submodule writeback_results
wire [63 : 0] writeback_results$D_IN, writeback_results$D_OUT;
wire writeback_results$CLR,
writeback_results$DEQ,
writeback_results$EMPTY_N,
writeback_results$ENQ;
// rule scheduling signals
wire CAN_FIRE_RL_memAccess_doMemAccess,
CAN_FIRE_RL_reportExceptionReturnToCapabilityCoprocessor,
CAN_FIRE_RL_theMem_dCache_invalidateEntry,
WILL_FIRE_RL_capToMem,
WILL_FIRE_RL_debugInstructionFetch,
WILL_FIRE_RL_doDecode,
WILL_FIRE_RL_execute_deliverPendingOp,
WILL_FIRE_RL_execute_doExecute,
WILL_FIRE_RL_execute_doReadReport,
WILL_FIRE_RL_execute_finishMultiplyOrDivide,
WILL_FIRE_RL_freeRenameReg_reset,
WILL_FIRE_RL_initialize,
WILL_FIRE_RL_instructionFetch,
WILL_FIRE_RL_memAccess_doDummy,
WILL_FIRE_RL_memAccess_doMemAccess,
WILL_FIRE_RL_memToCap,
WILL_FIRE_RL_registerFetch,
WILL_FIRE_RL_reportExceptionToCapabilityCoprocessor,
WILL_FIRE_RL_theCapCop_finishException,
WILL_FIRE_RL_theCapCop_startException,
WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction,
WILL_FIRE_RL_theDebug_countIdleCyclesStreamTrace,
WILL_FIRE_RL_theDebug_doCommands,
WILL_FIRE_RL_theDebug_finishExecute,
WILL_FIRE_RL_theDebug_popTrace,
WILL_FIRE_RL_theDebug_reportBreakPoint,
WILL_FIRE_RL_theDebug_step,
WILL_FIRE_RL_theDebug_unpipelinedStep,
WILL_FIRE_RL_theMem_dCache_checkTags,
WILL_FIRE_RL_theMem_dCache_data_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_theMem_dCache_doCacheInstructions,
WILL_FIRE_RL_theMem_dCache_getResponseUncached,
WILL_FIRE_RL_theMem_dCache_initialize,
WILL_FIRE_RL_theMem_dCache_invalidateEntry,
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways,
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_theMem_dCache_updateCache,
WILL_FIRE_RL_theMem_dCache_wayMiss,
WILL_FIRE_RL_theMem_iCacheOperation,
WILL_FIRE_RL_theMem_iCache_bank_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_theMem_iCache_doCacheInstructions,
WILL_FIRE_RL_theMem_iCache_doRead,
WILL_FIRE_RL_theMem_iCache_getMemoryResponse,
WILL_FIRE_RL_theMem_iCache_initialize,
WILL_FIRE_RL_theMem_iCache_invalidateEntry,
WILL_FIRE_RL_theMem_iCache_respondDuringUpdate,
WILL_FIRE_RL_theMem_iCache_tags_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_theMem_iCache_tags_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_theMem_iCache_updateCache,
WILL_FIRE_RL_theMem_l2Tomerge,
WILL_FIRE_RL_theMem_submitCapRequest,
WILL_FIRE_RL_theMem_theMemMerge_mergeInputs,
WILL_FIRE_RL_writeback_doInstructionReport,
WILL_FIRE_RL_writeback_doWriteBack,
WILL_FIRE_RL_writeback_doWriteBackWithRead,
WILL_FIRE_RL_writeback_doWriteBackWithWrite;
// inputs to muxes for submodule ports
reg [271 : 0] MUX_theDebug_debugConvert$messages_response_put_1__VAL_1;
reg [63 : 0] MUX_theMem_dCache_data_memory$b_put_3__VAL_3,
MUX_theMem_iCache_bank_memory$b_put_3__VAL_2;
reg [1 : 0] MUX_theDebug_state$write_1__VAL_1;
wire [508 : 0] MUX_writeback_instructionReport$enq_1__VAL_1,
MUX_writeback_instructionReport$enq_1__VAL_2,
MUX_writeback_instructionReport$enq_1__VAL_3;
wire [444 : 0] MUX_fetchedControlToken$enq_1__VAL_1,
MUX_fetchedControlToken$enq_1__VAL_2,
MUX_memAccessToWriteback$enq_1__VAL_1,
MUX_memAccessToWriteback$enq_1__VAL_2,
MUX_memAccess_inQ$enq_1__VAL_1,
MUX_memAccess_inQ$enq_1__VAL_2;
wire [316 : 0] MUX_theMem_theMemMerge_req_fifos_1$enq_1__VAL_1,
MUX_theMem_theMemMerge_req_fifos_1$enq_1__VAL_2;
wire [271 : 0] MUX_theDebug_curCommand$enq_1__VAL_1,
MUX_theDebug_debugConvert$messages_response_put_1__VAL_4,
MUX_theDebug_debugConvert$messages_response_put_1__VAL_5,
MUX_theDebug_debugConvert$messages_response_put_1__VAL_6,
MUX_theDebug_debugConvert$messages_response_put_1__VAL_7;
wire [268 : 0] MUX_theCapCop_capWriteback$write_1__VAL_1,
MUX_theCapCop_capWriteback$write_1__VAL_2;
wire [255 : 0] MUX_theCapCop_pcc$write_1__VAL_2;
wire [138 : 0] MUX_theCP0$putException_1__VAL_1,
MUX_theCP0$putException_1__VAL_2,
MUX_theCP0$putException_1__VAL_3,
MUX_theMem_iCache_req_fifo$enq_1__VAL_2,
MUX_theMem_iCache_req_fifo$enq_1__VAL_3;
wire [74 : 0] MUX_theCP0$tlbLookupInstruction_request_put_1__VAL_1,
MUX_theCP0$tlbLookupInstruction_request_put_1__VAL_2;
wire [69 : 0] MUX_theDebug_writebacks$enq_1__VAL_1,
MUX_theDebug_writebacks$enq_1__VAL_2,
MUX_theDebug_writebacks$enq_1__VAL_3;
wire [68 : 0] MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_1,
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_2,
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_3,
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_1,
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_2,
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_3;
wire [64 : 0] MUX_branch$pcWriteback_1__VAL_1,
MUX_branch$pcWriteback_1__VAL_2,
MUX_branch$pcWriteback_1__VAL_3,
MUX_execute_renameRegsVector$write_1__VAL_1,
MUX_execute_renameRegsVector$write_1__VAL_2,
MUX_execute_renameRegsVector$write_1__VAL_3,
MUX_execute_renameRegsVector_1$write_1__VAL_2,
MUX_execute_renameRegsVector_1$write_1__VAL_3,
MUX_execute_renameRegsVector_2$write_1__VAL_2,
MUX_execute_renameRegsVector_2$write_1__VAL_3,
MUX_execute_renameRegsVector_3$write_1__VAL_2,
MUX_execute_renameRegsVector_3$write_1__VAL_3;
wire [63 : 0] MUX_writeback_instCount$write_1__VAL_1;
wire [49 : 0] MUX_theMem_dCache_tags_memory$b_put_3__VAL_2,
MUX_theMem_dCache_tags_memory$b_put_3__VAL_3;
wire [27 : 0] MUX_theDebug_idleCount$write_1__VAL_1;
wire [24 : 0] MUX_theMem_iCache_tags_memory$b_put_3__VAL_3;
wire [12 : 0] MUX_theCapCop_capWritebackTags$enq_1__VAL_1,
MUX_theCapCop_capWritebackTags$enq_1__VAL_2;
wire [10 : 0] MUX_theMem_iCache_bank_memory$b_put_2__VAL_1,
MUX_theMem_iCache_bank_memory$b_put_2__VAL_2;
wire [9 : 0] MUX_theMem_dCache_data_memory$a_put_2__VAL_1,
MUX_theMem_dCache_data_memory$a_put_2__VAL_2,
MUX_theMem_dCache_data_memory$b_put_2__VAL_1,
MUX_theMem_dCache_data_memory$b_put_2__VAL_3;
wire [4 : 0] MUX_theCapCop_fetchFifoA$enq_1__VAL_1,
MUX_theCapCop_fetchFifoA$enq_1__VAL_2,
MUX_theCapCop_writesCalculated$write_1__VAL_1;
wire [2 : 0] MUX_theCapCop_capState$write_1__VAL_5,
MUX_theMem_dCache_cacheState$write_1__VAL_2,
MUX_theMem_dCache_cacheState$write_1__VAL_4;
wire [1 : 0] MUX_theMem_dCache_fillCount$write_1__VAL_2,
MUX_theMem_iCache_cacheState$write_1__VAL_4,
MUX_theMem_iCache_fillCount$write_1__VAL_2;
wire MUX_branch$pcWriteback_2__VAL_1,
MUX_branch$pcWriteback_2__VAL_2,
MUX_branch$pcWriteback_2__VAL_3,
MUX_execute_renameRegsVector$write_1__SEL_1,
MUX_execute_renameRegsVector_1$write_1__SEL_1,
MUX_execute_renameRegsVector_2$write_1__SEL_1,
MUX_execute_renameRegsVector_3$write_1__SEL_1,
MUX_freeRenameReg$enq_1__SEL_1,
MUX_memAccess_inQ$enq_1__SEL_1,
MUX_theCP0$writeReg_1__SEL_1,
MUX_theCP0$writeReg_1__SEL_2,
MUX_theCP0$writeReg_1__SEL_3,
MUX_theCP0$writeReg_4__VAL_1,
MUX_theCP0$writeReg_4__VAL_2,
MUX_theCP0$writeReg_4__VAL_3,
MUX_theCapCop_baseRegs$upd_1__SEL_1,
MUX_theCapCop_baseRegs$upd_1__SEL_2,
MUX_theCapCop_baseRegs$upd_1__SEL_3,
MUX_theCapCop_baseRegs$upd_1__SEL_4,
MUX_theCapCop_capState$write_1__SEL_1,
MUX_theCapCop_capState$write_1__SEL_3,
MUX_theCapCop_capState$write_1__SEL_6,
MUX_theCapCop_capWriteback$write_1__SEL_1,
MUX_theCapCop_capWritebackTags$enq_1__SEL_1,
MUX_theCapCop_exception$enq_1__SEL_2,
MUX_theCapCop_pcc$write_1__SEL_1,
MUX_theCapCop_writesCalculated$write_1__SEL_1,
MUX_theDebug_curCommand$enq_1__SEL_1,
MUX_theDebug_debugConvert$messages_response_put_1__SEL_1,
MUX_theDebug_debugConvert$messages_response_put_1__SEL_2,
MUX_theDebug_debugConvert$messages_response_put_1__SEL_3,
MUX_theDebug_debugConvert$messages_response_put_1__SEL_4,
MUX_theDebug_dest$write_1__SEL_1,
MUX_theDebug_mipsPC$write_1__SEL_1,
MUX_theDebug_mipsPC$write_1__SEL_2,
MUX_theDebug_mipsPC$write_1__SEL_3,
MUX_theDebug_pausePipe$write_1__SEL_1,
MUX_theDebug_pausePipe$write_1__SEL_6,
MUX_theDebug_pausePipe$write_1__VAL_1,
MUX_theDebug_state$write_1__PSEL_2,
MUX_theDebug_state$write_1__SEL_1,
MUX_theDebug_state$write_1__SEL_2,
MUX_theDebug_state$write_1__SEL_3,
MUX_theDebug_unPipeline$write_1__SEL_1,
MUX_theDebug_writebacks$enq_1__SEL_1,
MUX_theDebug_writebacks$enq_1__SEL_2,
MUX_theDebug_writebacks$enq_1__SEL_3,
MUX_theMem_dCache_cacheState$write_1__SEL_1,
MUX_theMem_dCache_cacheState$write_1__SEL_2,
MUX_theMem_dCache_cacheState$write_1__SEL_3,
MUX_theMem_dCache_data_memory$a_put_1__SEL_1,
MUX_theMem_dCache_data_memory$b_put_1__SEL_1,
MUX_theMem_dCache_data_memory$b_put_1__SEL_2,
MUX_theMem_dCache_out_fifo_enqw$wset_1__SEL_1,
MUX_theMem_dCache_tags_memory$b_put_1__SEL_1,
MUX_theMem_dCache_tags_memory$b_put_1__SEL_2,
MUX_theMem_dCache_wayTable$upd_1__SEL_1,
MUX_theMem_dCache_wayTable$upd_2__VAL_1,
MUX_theMem_dCache_wayTable$upd_2__VAL_2,
MUX_theMem_iCache_bank_memory$a_put_1__SEL_1,
MUX_theMem_iCache_bank_memory$b_put_1__SEL_1,
MUX_theMem_iCache_bank_serverAdapterA_writeWithResp$wset_1__SEL_2,
MUX_theMem_iCache_cacheState$write_1__SEL_1,
MUX_theMem_iCache_cacheState$write_1__SEL_2,
MUX_theMem_iCache_cacheState$write_1__SEL_3,
MUX_theMem_iCache_out_fifo_enqw$wset_1__SEL_1,
MUX_theMem_iCache_req_fifo$enq_1__SEL_1,
MUX_theMem_iCache_tags_memory$b_put_1__SEL_1,
MUX_theMem_iCache_tags_memory$b_put_1__SEL_2,
MUX_theMem_theMemMerge_req_fifos_1$enq_1__SEL_1,
MUX_theRF_regFile$upd_1__SEL_1,
MUX_theRF_regFile$upd_1__SEL_2,
MUX_theRF_regFile$upd_1__SEL_3,
MUX_writeback_exception$enq_1__SEL_1,
MUX_writeback_exception$enq_1__SEL_2,
MUX_writeback_exception$enq_1__SEL_3,
MUX_writeback_hiLoCommit$enq_1__SEL_1,
MUX_writeback_hiLoCommit$enq_1__SEL_2,
MUX_writeback_hiLoCommit$enq_1__SEL_3,
MUX_writeback_instCount$write_1__SEL_1,
MUX_writeback_instCount$write_1__SEL_2,
MUX_writeback_instCount$write_1__SEL_3;
// remaining internal signals
reg [254 : 0] IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3656,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3681,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9055;
reg [127 : 0] CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q164,
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q166,
CASE_writeback_instructionReportD_OUT_BITS_78_ETC__q6;
reg [64 : 0] calcResult__h221868;
reg [63 : 0] CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q65,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q167,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q168,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q169,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q170,
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q151,
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q158,
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q139,
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q140,
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q141,
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q142,
CASE_theMem_dataSizeD_OUT_temp74691_1_temp746_ETC__q198,
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6080,
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6081,
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6139,
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6143,
IF_decode_inQ_first__909_BITS_427_TO_423_928_E_ETC___d6109,
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d6130,
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593,
IF_execute_inQ_first__341_BITS_316_TO_315_502__ETC___d9058,
IF_execute_inQ_first__341_BITS_328_TO_327_464__ETC___d9046,
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812,
_theResult_____1_opA__h241134,
_theResult_____1_opB__h241135,
_theResult_____4__h170559,
_theResult_____8_fst_oType_eaddr__h203904,
_theResult_____8_fst_oType_eaddr__h207334,
entry__h170816,
entry__h170934,
entry__h175335,
entry__h175453,
entry__h193251,
entry__h193369,
resp_data__h113930,
resp_data__h129680,
val2__h168450,
x1_avValue_fst_opA__h243975,
x1_avValue_fst_opB__h243976,
x1_avValue_opA__h239033,
x1_avValue_opA__h240161,
x1_avValue_opA__h240519,
x1_avValue_opA__h241282,
x1_avValue_opA__h242578,
x1_avValue_opB__h239034,
x1_avValue_opB__h240162,
x1_avValue_opB__h240520,
x1_avValue_opB__h241283,
x1_avValue_opB__h242579,
x1_avValue_storeData__h239035,
x1_avValue_storeData__h242580,
x__h149013,
x__h163529,
x__h213427,
x__h257310,
x__h257489,
x_data__h115034;
reg [31 : 0] IF_theMem_dataSize_first__825_EQ_4_853_THEN_IF_ETC___d7551;
reg [19 : 0] CASE_decode_inQD_OUT_BITS_433_TO_428_4_1_IF_N_ETC__q84;
reg [14 : 0] CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q163,
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q165;
reg [11 : 0] CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q194,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q195,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q196,
CASE_decode_inQD_OUT_BITS_407_TO_402_CASE_dec_ETC__q94,
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q72,
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q74,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q76,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q82,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q92,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q93,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q97,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q66,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q79,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q67,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q77,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q80,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q81,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q87,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q88,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q98,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q78,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q83,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q99;
reg [10 : 0] CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q71,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q73,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q91,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q86,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q96,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q69;
reg [7 : 0] CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178,
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174,
CASE_memAccess_inQD_OUT_BITS_14_TO_13_0x0_0_r_ETC__q204,
CASE_theDebug_bpReportD_OUT_BITS_271_TO_264_3_ETC__q176,
CASE_theDebug_debugConvertmessages_request_ge_ETC__q173,
CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_0x0_ETC__q179,
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852,
req_byteWrite__h140080,
req_byteWrite__h144298;
reg [5 : 0] CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51,
CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52,
CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_IF__ETC__q177,
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666,
IF_theDebug_debugConvert_messages_request_get__ETC___d8630;
reg [4 : 0] CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201,
CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181,
CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180,
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q111,
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q112,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q118,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q119,
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q128,
CASE_decode_inQD_OUT_BITS_427_TO_423_15_0_dec_ETC__q108,
CASE_decode_inQD_OUT_BITS_433_TO_428_15_1_dec_ETC__q110,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q107,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q109,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q113,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q114,
CASE_decode_inQD_OUT_BITS_435_TO_434_IF_decod_ETC__q131,
CASE_execute_inQD_OUT_BITS_379_TO_375_execute_ETC__q161,
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q117,
CASE_theDebug_traceCmp_BITS_250_TO_246_31_0_th_ETC__q9,
CASE_theDebug_trace_buf_bramDOB_BITS_250_TO_2_ETC__q175,
CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5,
IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d7595,
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779,
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d5798,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7585,
IF_theDebug_debugConvert_messages_request_get__ETC___d7855,
_theResult_____1_dest__h241119,
_theResult_____1_dest__h241760,
_theResult_____2_dest__h253551,
_theResult_____7_snd_fst__h282877,
_theResult_____7_snd_fst__h282960,
_theResult_____7_snd_snd_snd_fst__h282775,
regNum__h203787,
x1_avValue_dest__h239018,
x1_avValue_dest__h240146,
x1_avValue_dest__h240504,
x1_avValue_dest__h241267,
x1_avValue_dest__h242563,
x1_avValue_fst_dest__h243960,
x1_avValue_snd_snd_snd_snd_rd__h242905,
x__h102125,
x__h243627,
y_avValue_snd_snd_fst__h282717,
y_avValue_snd_snd_snd_fst__h282686,
y_avValue_snd_snd_snd_fst__h282689,
y_avValue_snd_snd_snd_fst__h282691,
y_avValue_snd_snd_snd_fst__h282782,
y_avValue_snd_snd_snd_snd_fst__h286189,
y_avValue_snd_snd_snd_snd_snd_snd_snd_fst__h285803,
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_fst__h285990,
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst__h286177;
reg [3 : 0] CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q183,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q57,
CASE_decode_inQD_OUT_BITS_422_TO_418_IF_NOT_d_ETC__q53,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q47,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q44,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q45,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q55,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q56,
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7996,
_theResult___fst__h168720,
te_version__h168658;
reg [2 : 0] CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q105,
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100,
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q101,
CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q102,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q29,
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q106,
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q203,
_theResult_____7_fst_coProSelect__h282015,
_theResult___fst_coProSelect__h281974,
x1_avValue_coProSelect__h242564,
x1_avValue_fst_coProSelect__h280726,
x1_avValue_snd_snd_fst_coProSelect__h280767,
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd__h286178;
reg [1 : 0] CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q182,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q184,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q185,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q187,
CASE_decode_inQD_OUT_BITS_407_TO_402_0_0_0_2__ETC__q19,
CASE_decode_inQD_OUT_BITS_407_TO_402_0_28_2_2_ETC__q20,
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_2_1__ETC__q23,
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q60,
CASE_decode_inQD_OUT_BITS_419_TO_418_decode_i_ETC__q30,
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q16,
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q38,
CASE_decode_inQD_OUT_BITS_427_TO_423_1_16_0_1_ETC__q35,
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_0_4__ETC__q14,
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_3_4__ETC__q36,
CASE_decode_inQD_OUT_BITS_427_TO_423_3_16_0_1_ETC__q13,
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q22,
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q61,
CASE_decode_inQD_OUT_BITS_433_TO_428_1_26_0_2_ETC__q39,
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18,
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40,
CASE_decode_inQD_OUT_BITS_433_TO_428_3_26_0_2_ETC__q17,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q15,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q24,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q31,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q37,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q41,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q58,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q59,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q62,
CASE_decode_inQD_OUT_BITS_435_TO_434_3_0_deco_ETC__q202,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q25,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q42,
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q63,
CASE_execute_inQD_OUT_BITS_435_TO_434_3_0_exe_ETC__q49,
CASE_execute_pendingOpsD_OUT_BITS_435_TO_434__ETC__q172,
CASE_memAccessToWritebackD_OUT_BITS_435_TO_43_ETC__q48,
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q116,
CASE_theDebug_instQD_OUT_BITS_31_TO_26_3_0_2__ETC__q171,
CASE_v77714_1_8_0_9_0_10_0_11_0_12_0_14_0__q186,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992,
IF_memAccess_inQ_first__055_BITS_435_TO_434_25_ETC___d8942;
reg CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q188,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q189,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q190,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q191,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q192,
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q193,
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q90,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q124,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q125,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q134,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q135,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q70,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q89,
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q121,
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q32,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q27,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q85,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q95,
CASE_decode_inQD_OUT_BITS_433_TO_428_NOT_deco_ETC__q68,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q12,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q120,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q122,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q123,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q126,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q132,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q133,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q136,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q138,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q26,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q33,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q127,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q137,
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q34,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q154,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q155,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q156,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q157,
CASE_execute_inQD_OUT_BITS_316_TO_315_NOT_exe_ETC__q147,
CASE_execute_inQD_OUT_BITS_328_TO_327_NOT_exe_ETC__q143,
CASE_execute_inQD_OUT_BITS_379_TO_375_NOT_exe_ETC__q162,
CASE_memAccessToWritebackD_OUT_BITS_374_TO_37_ETC__q115,
CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197,
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q145,
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q152,
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q144,
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q150,
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q146,
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q153,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7997,
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818,
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886;
wire [401 : 0] IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4563,
execute_inQ_first__341_BITS_401_TO_372_564_CON_ETC___d4659,
execute_inQ_first__341_BIT_401_522_CONCAT_IF_e_ETC___d4562,
lastWasBranch_778_AND_lastEpoch_779_EQ_fetched_ETC___d7511,
memAccess_inQ_first__055_BITS_401_TO_372_264_C_ETC___d2288;
wire [396 : 0] IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6374;
wire [391 : 0] execute_inQ_first__341_BITS_391_TO_384_433_CON_ETC___d4520;
wire [383 : 0] IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d6372;
wire [380 : 0] IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6371;
wire [379 : 0] execute_inQ_first__341_BITS_379_TO_372_466_CON_ETC___d4518;
wire [374 : 0] IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6370;
wire [371 : 0] IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7507;
wire [366 : 0] decode_inQ_first__909_BITS_366_TO_331_870_CONC_ETC___d6369,
memAccess_inQ_first__055_BITS_366_TO_294_275_C_ETC___d2287;
wire [318 : 0] IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6368;
wire [316 : 0] _dfoo4;
wire [267 : 0] IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d3685,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3683,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9257;
wire [255 : 0] IF_theCP0_tlbLookupData_response_get_777_BITS__ETC___d3085,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d7882,
req_data__h133039,
req_data__h190926,
req_data__h191769,
x__h168654,
x__h169227;
wire [254 : 0] IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054;
wire [127 : 0] IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3645,
IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3676,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3639,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3672,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052;
wire [76 : 0] IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d3537;
wire [64 : 0] IF_execute_inQD_OUT_BIT_381_THEN_theResult____ETC__q148,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d3532,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7777,
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d3754,
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597,
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027,
_theResult_____3_snd__h222037,
_theResult_____4__h222021,
_theResult_____4_snd__h222754,
_theResult_____4_snd__h223554,
_theResult_____4_snd_snd__h222026,
_theResult_____6__h200326,
_theResult_____7__h200324,
calcResult___1__h223433,
calcResult___1__h223584,
calcResult___1__h223707,
calcResult__h221346,
calcResult__h221354,
calcResult__h221414,
calcResult__h221422,
calcResult__h222022,
calcResult__h223403,
calcResult__h223521,
calcResult__h223553,
calcResult__h231541,
memAccessToWriteback_first__516_BITS_391_TO_38_ETC___d9252,
opA__h223616,
opB__h222122,
result__h223255,
signedA__h217100,
signedB__h217989;
wire [63 : 0] IF_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_ETC___d7579,
IF_IF_IF_IF_NOT_theCP0_tlbLookupData_response__ETC___d7584,
IF_IF_IF_IF_memAccessToWriteback_first__516_BI_ETC___d7578,
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7227,
IF_IF_execute_inQ_first__341_BITS_316_TO_315_5_ETC___d3522,
IF_IF_execute_inQ_first__341_BITS_328_TO_327_4_ETC___d3484,
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4735,
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4781,
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4827,
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4873,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4020,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4021,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4022,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4023,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4024,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4025,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4026,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4027,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4028,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4029,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4030,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4031,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4032,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4033,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4034,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4035,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4036,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4037,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4038,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4039,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4040,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4041,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4042,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4043,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4044,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4045,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4046,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4047,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4048,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4049,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4050,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4051,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4052,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4053,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4054,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4055,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4056,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4057,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4058,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4059,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4060,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4061,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4062,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4063,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4064,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4065,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4066,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4067,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4068,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4069,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4070,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4071,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4072,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4073,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4074,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4075,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4076,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4077,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4078,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4079,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4080,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4081,
IF_NOT_decode_inQ_first__909_BITS_427_TO_423_9_ETC___d6153,
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4647,
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d8815,
IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598,
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4742,
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4788,
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4834,
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4880,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4736,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4782,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4828,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4874,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d9064,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4740,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4786,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4832,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4878,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4733,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4779,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4825,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4871,
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7898,
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4739,
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4785,
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4831,
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4877,
IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9217,
IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9218,
IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9219,
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7776,
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7779,
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d8035,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029,
IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599,
IF_theMem_dCache_req_fifo_first__733_BIT_128_0_ETC___d7546,
IF_theMem_dCache_req_fifo_first__733_BIT_129_0_ETC___d7545,
IF_theMem_dCache_req_fifo_first__733_BIT_130_0_ETC___d7544,
IF_theMem_dCache_req_fifo_first__733_BIT_131_0_ETC___d7543,
IF_theMem_dCache_req_fifo_first__733_BIT_132_0_ETC___d7542,
IF_theMem_dCache_req_fifo_first__733_BIT_133_0_ETC___d7591,
IF_theMem_dCache_req_fifo_first__733_BIT_134_0_ETC___d7590,
IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2932,
IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2934,
IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2935,
IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550,
SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041,
_0_CONCAT_IF_IF_theCapCop_capInsts_first__372_B_ETC___d7848,
_0_CONCAT_IF_execute_inQ_first__341_BITS_12_TO__ETC___d7847,
_theResult_____1_opB__h245437,
_theResult_____2___1_victim__h171283,
_theResult_____8_fst_oType_eaddr__h203894,
_theResult_____8_fst_oType_eaddr__h207324,
_theResult___fst__h257318,
_theResult___snd__h257319,
addr__h271109,
b__h202732,
branchTarget__h283587,
branchTarget__h285642,
dataRead___1__h189582,
di___1_opB__h240965,
di_opA__h250012,
di_opA__h252675,
di_opB__h245718,
di_opB__h246406,
di_opB__h248895,
di_opB__h249572,
er___1_opB__h212042,
expWb___1_entry__h170521,
expWb___1_entry__h175093,
expWb___1_entry__h193005,
jumpTarget__h170772,
mask__h174680,
mask__h174690,
newVal__h6189,
put_addr__h272334,
put_addr__h273845,
result__h176159,
result__h223714,
spliced_bits__h223217,
target__h170704,
target__h170730,
te_pc__h24721,
te_regVal1__h24722,
te_regVal2__h24723,
temp__h174677,
temp__h174679,
temp__h174681,
temp__h174689,
temp__h174691,
v__h112420,
v__h188873,
writeLine__h145072,
writeLine__h146667,
writeLine__h147487,
writeLine__h147922,
writeLine__h148412,
writeLine__h148895,
writeLine__h148898,
writeLine__h148954,
writeback___1_base__h203941,
writeback___1_base__h207371,
x1_avValue_base__h200801,
x1_avValue_fst_opA__h243934,
x1_avValue_fst_opB__h212082,
x1_avValue_fst_opB__h243935,
x1_avValue_fst_storeData__h243936,
x1_avValue_oType_eaddr__h200800,
x1_avValue_opA__h161811,
x1_avValue_opA__h237707,
x1_avValue_opA__h241182,
x1_avValue_opB__h237708,
x1_avValue_opB__h241183,
x1_avValue_snd_operand__h242897,
x1_avValue_snd_snd_snd_snd_snd_snd_operand__h242915,
x__h143650,
x__h171528,
x__h176020,
x__h176288,
x__h176684,
x__h177369,
x__h181305,
x__h183015,
x__h193939,
x__h198817,
x__h213493,
x__h217866,
x__h223436,
x__h223587,
x__h223710,
x__h231731,
x__h257736,
x__h266100,
x__h266104,
x__h285659,
x_first_data__h174507,
y__h181306,
y__h183003,
y__h183016,
y__h184714,
y__h285662;
wire [47 : 0] x1_avValue_reserved__h200799, y_avValue_reserved__h259503;
wire [33 : 0] IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7275,
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7276,
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7277,
IF_execute_inQ_first__341_BITS_435_TO_434_699__ETC___d7888,
IF_memAccessToWriteback_first__516_BITS_435_TO_ETC___d7874;
wire [31 : 0] IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4208,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4209,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4210,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4211,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4212,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4213,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4214,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4215,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4216,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4217,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4218,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4219,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4220,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4221,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4222,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4223,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4224,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4225,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4226,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4227,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4228,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4229,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4230,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4231,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4232,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4233,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4234,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4235,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4236,
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4237,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9205,
calcResult21868_BITS_31_TO_0__q159,
calcResult23403_BITS_31_TO_0__q149,
instruction__h274083,
mask__h174653,
mask__h174665,
req_byteenable__h113255,
req_byteenable__h129049,
result__h228964,
spliced_bits__h153740,
spliced_bits__h155293,
spliced_bits__h228898,
te_inst__h24720,
temp__h174650,
temp__h174652,
temp__h174654,
temp__h174664,
x__h177704,
x__h178683,
x__h257533,
y__h177705,
y__h178645,
y__h178684,
y__h179624;
wire [27 : 0] x__h285667;
wire [25 : 0] immediate__h279604,
immediate__h280058,
y_avValue_snd_snd_snd_snd_fst__h283943;
wire [21 : 0] te_reserved__h24719;
wire [19 : 0] IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7502,
memAccessToWritebackD_OUT_BITS_37_TO_18__q10;
wire [17 : 0] IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6364,
execute_inQD_OUT_BITS_417_TO_402_CONCAT_0b0__q160;
wire [15 : 0] decode_inQD_OUT_BITS_417_TO_402__q64,
toInsert__h150906,
x76684_BITS_7_TO_0_CONCAT_x76684_BITS_15_TO_8__q199,
x__h213199,
x__h285670;
wire [14 : 0] IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6363,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031;
wire [11 : 0] IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7383,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7385,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7410,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7412,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7417,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7418,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7336,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7357,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7377,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7403,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9210,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9212,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9213,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9214,
theDebug_trace_buf_tailPtr_read__1_PLUS_1___d7524;
wire [10 : 0] IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7103,
IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7114,
IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7126,
IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7138,
decode_inQD_OUT_BITS_412_TO_402__q11;
wire [9 : 0] IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7334,
IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7355,
IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7375,
IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7401;
wire [8 : 0] IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6362;
wire [7 : 0] IF_memAccess_inQD_OUT_BITS_232_TO_230_EQ_0_TH_ETC__q1,
IF_memAccess_inQD_OUT_BITS_232_TO_231_EQ_0_TH_ETC__q2,
IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_0_C_ETC__q4,
IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_0_C_ETC__q8,
IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_15__q3,
byteMask__h140788,
byteMask__h142387,
byteMask__h143211,
byteMask__h147923,
byteMask__h148413,
byteMask__h148899,
byteMask__h148955,
x76288_BITS_7_TO_0__q200;
wire [5 : 0] IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770,
_7_MINUS_y61581__q7,
addr__h174623,
off__h176682,
off__h177367,
shift__h148897,
shift__h148953,
shift__h174688,
y__h161581;
wire [4 : 0] IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721,
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733,
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712,
IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEm_ETC___d8720,
IF_IF_NOT_theCP0_tlbLookupData_response_get_77_ETC___d8732,
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4616,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d6946,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7236,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7242,
IF_IF_memAccessToWriteback_first__516_BITS_371_ETC___d8711,
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875,
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876,
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868,
IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEmpty_ETC___d8719,
IF_NOT_decode_inQ_first__909_BITS_435_TO_434_9_ETC___d7594,
IF_NOT_theCP0_tlbLookupData_response_get_777_B_ETC___d8731,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7586,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994,
IF_execute_inQ_first__341_BIT_380_712_THEN_IF__ETC___d4487,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764,
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8710,
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8729,
IF_theMem_capExceptions_i_notEmpty__490_THEN_I_ETC___d8802,
IF_theMem_dCache_out_fifo_ff_i_notEmpty__489_T_ETC___d8718,
_theResult___snd__h280672,
destReg__h279602,
reqA__h280962,
shift__h147919,
shift__h148409,
shift__h174651,
shift__h174663,
v__h277714,
v__h278907,
x1_avValue_dest__h241167,
x1_avValue_dest__h241851,
x1_avValue_fst_dest__h243919,
x1_avValue_snd_rd__h242896,
x1_avValue_snd_rt__h242895,
x__h243635,
y_avValue_dest__h253687,
y_avValue_snd_snd_snd_fst__h282779;
wire [3 : 0] IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7281,
mask__h147921,
mask__h148411;
wire [2 : 0] IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7297,
_theResult___fst_coProSelect__h281892,
theMem_dCache_data_serverAdapterA_cnt_633_PLUS_ETC___d1639,
theMem_dCache_tags_serverAdapterA_cnt_519_PLUS_ETC___d1525,
theMem_iCache_bank_serverAdapterA_cnt_236_PLUS_ETC___d1242,
theMem_iCache_tags_serverAdapterA_cnt_122_PLUS_ETC___d1128,
x1_avValue_fst_coProSelect__h243920,
x1_avValue_snd_select__h242898,
x1_avValue_snd_snd_snd_snd_snd_snd_select__h242916,
x__h148959,
x_coProSelect__h290167,
y_avValue_coProSelect__h253688;
wire [1 : 0] IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d5575,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7194,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7195,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7196,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7303,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7304,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8006,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7100,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7111,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7123,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7135,
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7026,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769,
ab__h107013,
ab__h108440,
ab__h110016,
ab__h111421,
ab__h122228,
ab__h124191,
ab__h125596,
x__h148596;
wire IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d6776,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7083,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7159,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7173,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7183,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7185,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7433,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7435,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7449,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7451,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7460,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7462,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7470,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7472,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7479,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7480,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7485,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7486,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7488,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7498,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7500,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8261,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9106,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9115,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7094,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7109,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7121,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7133,
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d2819,
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d3143,
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d2637,
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4590,
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4593,
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4609,
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4612,
IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4716,
IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4762,
IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4808,
IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4854,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4709,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4755,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4801,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4847,
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d8820,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4712,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4758,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4804,
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4850,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4705,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4752,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4798,
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4844,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8036,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8039,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8138,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d9048,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7081,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7494,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9117,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9122,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9124,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9127,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7019,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7420,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7424,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7427,
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7453,
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7437,
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7441,
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7444,
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7464,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8841,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8842,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8845,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8846,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8849,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8850,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8851,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8852,
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d4595,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d4614,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3544,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3595,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3604,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3605,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9049,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9050,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9061,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9062,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045,
NOT_decode_inQ_first__909_BIT_401_097_196_AND__ETC___d6235,
NOT_memAccessToWriteback_first__516_BIT_393_53_ETC___d3089,
NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d1818,
NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d3023,
NOT_theCP0_tlbLookupData_response_get_777_BIT__ETC___d3021,
NOT_theCP0_tlbLookupData_response_get_777_BIT__ETC___d3092,
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548,
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3600,
NOT_theCapCop_capMemInsts_i_notEmpty__482_483__ETC___d2762,
NOT_theDebug_bpReport_notEmpty__0_1_AND_NOT_th_ETC___d6504,
NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d2514,
NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d2760,
NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d3004,
NOT_writeback_instructionReport_first__347_BIT_ETC___d2481,
SEXT_IF_execute_inQ_first__341_BIT_330_463_THE_ETC___d8040,
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8034,
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8038,
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d9060,
_dfoo1,
_dor1execute_loadsDone$EN_write,
_dor1writeback_destRenamed$EN_deq,
_dor1writeback_results$EN_deq,
_theResult_____3_fst__h222045,
_theResult_____3_snd__h222046,
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2655,
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2824,
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d3148,
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935,
branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b0_5_ETC___d8037,
carryOut1__h222047,
carryOut1__h222151,
carryOut2__h222048,
carryOut2__h222152,
execute_loadsDone_248_EQ_execute_loadsIn_249_M_ETC___d3368,
execute_loadsDone_248_EQ_execute_loadsIn_249___d3250,
fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7032,
fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7107,
fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7119,
fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7131,
freeRenameReg_i_notFull__494_AND_theCapCop_cap_ETC___d2757,
lastEpoch_779_EQ_fetchedControlToken_first__66_ETC___d8992,
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705,
regRenameTable_953_BITS_14_TO_12_984_EQ_fetche_ETC___d8368,
regRenameTable_953_BITS_26_TO_24_971_EQ_fetche_ETC___d8366,
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369,
regRenameTable_953_BITS_38_TO_36_959_EQ_fetche_ETC___d8364,
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9102,
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9111,
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9129,
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9130,
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9134,
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9136,
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9139,
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9140,
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8367,
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8372,
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8376,
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8380,
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8384,
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8365,
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8371,
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8375,
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8379,
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8383,
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8363,
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8370,
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8374,
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8378,
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8382,
theCP0_tlbLookupData_response_get_777_BITS_13__ETC___d1813,
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d3016,
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116,
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117,
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324,
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d9145,
theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384,
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4587,
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4606,
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d9255,
theCapCop_capInsts_i_notEmpty__326_AND_theCapC_ETC___d3337,
theCapCop_capState_read__301_EQ_5_335_AND_theC_ETC___d4907,
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2714,
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2980,
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d3191,
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329,
theCapCop_nextWillWriteback_i_notEmpty__313_AN_ETC___d3340,
theCapCop_pcc_read__315_BIT_244_550_OR_NOT_IF__ETC___d4592,
theCapCop_pcc_read__315_BIT_244_550_OR_NOT_IF__ETC___d4611,
theCapCop_writesCalculated_read__320_EQ_theCap_ETC___d3321,
theDebug_bp_1_read__515_BIT_64_516_AND_theDebu_ETC___d6531,
theDebug_bp_read__508_BIT_64_509_AND_theDebug__ETC___d7846,
theDebug_trace_buf_tailPtr_read__1_EQ_theDebug_ETC___d40,
theDebug_trace_buf_tailPtr_read__1_PLUS_1_2_EQ_ETC___d8043,
theMem_capExceptions_first__525_BITS_3_TO_0_52_ETC___d8708,
theMem_dCache_cacheState_read__723_EQ_1_732_AN_ETC___d2049,
theMem_dCache_data_serverAdapterA_cnt_633_SLT_3___d1762,
theMem_dCache_data_serverAdapterA_outData_outD_ETC___d1767,
theMem_dCache_data_serverAdapterB_cnt_690_SLT_3___d1849,
theMem_dCache_req_fifo_i_notEmpty__730_AND_the_ETC___d1844,
theMem_dCache_tags_serverAdapterA_outDataCore__ETC___d1773,
theMem_dCache_tags_serverAdapterA_outDataCore__ETC___d3001,
theMem_dCache_tags_serverAdapterB_cnt_576_SLT_3___d1722,
theMem_dCache_wayKey_i_notEmpty__756_AND_theMe_ETC___d2999,
theMem_iCache_bank_serverAdapterA_cnt_236_SLT_3___d1915,
theMem_iCache_bank_serverAdapterB_cnt_293_SLT_3___d1424,
theMem_iCache_out_fifo_ff_i_notEmpty__092_OR_t_ETC___d6659,
theMem_iCache_req_fifo_first__341_BITS_127_TO__ETC___d1372,
theMem_iCache_req_fifo_i_notFull__917_AND_theM_ETC___d6498,
theMem_iCache_req_fifo_i_notFull__917_AND_theM_ETC___d6580,
theMem_iCache_tags_serverAdapterA_cnt_122_SLT_3___d1914,
theMem_iCache_tags_serverAdapterA_outDataCore__ETC___d1366,
theMem_iCache_tags_serverAdapterA_outDataCore__ETC___d1473,
theMem_iCache_tags_serverAdapterB_cnt_179_SLT_3___d1325,
theMem_instructionWord_i_notEmpty__644_AND_fet_ETC___d6656,
theRF_regFileState_4_AND_writeback_hiLoCommit__ETC___d2751,
theRF_reqA_i_notEmpty__891_AND_theRF_reqB_i_no_ETC___d4903,
writeback_instructionReport_i_notFull__497_AND_ETC___d2508,
writeback_instructionReport_i_notFull__497_AND_ETC___d2993,
x__h129418,
x__h222061,
x__h222165,
x__h222259;
// actionvalue method memory_request_get
assign memory_request_get = theMem_l2Cache$memory_request_get ;
assign RDY_memory_request_get = theMem_l2Cache$RDY_memory_request_get ;
// action method memory_response_put
assign RDY_memory_response_put = theMem_l2Cache$RDY_memory_response_put ;
// action method putIrqs
assign RDY_putIrqs = 1'd1 ;
// action method debugStream_request_put
assign RDY_debugStream_request_put =
theDebug_debugConvert$RDY_stream_request_put ;
// actionvalue method debugStream_response_get
assign debugStream_response_get =
theDebug_debugConvert$stream_response_get ;
assign RDY_debugStream_response_get =
theDebug_debugConvert$RDY_stream_response_get ;
// submodule branch
mkBranch branch(.CLK(csi_c0_clk),
.RST_N(csi_c0_reset_n),
.getPc_fromDebug(branch$getPc_fromDebug),
.getPc_id(branch$getPc_id),
.pcWriteback_exception(branch$pcWriteback_exception),
.pcWriteback_fromDebug(branch$pcWriteback_fromDebug),
.pcWriteback_truePc(branch$pcWriteback_truePc),
.putRegisterTarget_fromDebug(branch$putRegisterTarget_fromDebug),
.putRegisterTarget_id(branch$putRegisterTarget_id),
.putRegisterTarget_instEpoch(branch$putRegisterTarget_instEpoch),
.putRegisterTarget_target(branch$putRegisterTarget_target),
.putTarget_branchType(branch$putTarget_branchType),
.putTarget_fromDebug(branch$putTarget_fromDebug),
.putTarget_id(branch$putTarget_id),
.putTarget_instEpoch(branch$putTarget_instEpoch),
.putTarget_target(branch$putTarget_target),
.EN_getPc(branch$EN_getPc),
.EN_putTarget(branch$EN_putTarget),
.EN_putRegisterTarget(branch$EN_putRegisterTarget),
.EN_pcWriteback(branch$EN_pcWriteback),
.getPc(branch$getPc),
.RDY_getPc(branch$RDY_getPc),
.RDY_putTarget(branch$RDY_putTarget),
.RDY_putRegisterTarget(branch$RDY_putRegisterTarget),
.RDY_pcWriteback(branch$RDY_pcWriteback),
.getEpoch(branch$getEpoch),
.RDY_getEpoch());
// submodule decode_inQ
FIFOL1 #(.width(32'd445)) decode_inQ(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(decode_inQ$D_IN),
.ENQ(decode_inQ$ENQ),
.DEQ(decode_inQ$DEQ),
.CLR(decode_inQ$CLR),
.D_OUT(decode_inQ$D_OUT),
.FULL_N(decode_inQ$FULL_N),
.EMPTY_N(decode_inQ$EMPTY_N));
// submodule execute_hiLoPending
FIFO1 #(.width(32'd1),
.guarded(32'd1)) execute_hiLoPending(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(execute_hiLoPending$D_IN),
.ENQ(execute_hiLoPending$ENQ),
.DEQ(execute_hiLoPending$DEQ),
.CLR(execute_hiLoPending$CLR),
.D_OUT(),
.FULL_N(execute_hiLoPending$FULL_N),
.EMPTY_N(execute_hiLoPending$EMPTY_N));
// submodule execute_inQ
SizedFIFO #(.p1width(32'd445),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) execute_inQ(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(execute_inQ$D_IN),
.ENQ(execute_inQ$ENQ),
.DEQ(execute_inQ$DEQ),
.CLR(execute_inQ$CLR),
.D_OUT(execute_inQ$D_OUT),
.FULL_N(execute_inQ$FULL_N),
.EMPTY_N(execute_inQ$EMPTY_N));
// submodule execute_mul
mkMulDiv execute_mul(.CLK(csi_c0_clk),
.RST_N(csi_c0_reset_n),
.muldiv_request_put(execute_mul$muldiv_request_put),
.EN_muldiv_request_put(execute_mul$EN_muldiv_request_put),
.EN_muldiv_response_get(execute_mul$EN_muldiv_response_get),
.RDY_muldiv_request_put(execute_mul$RDY_muldiv_request_put),
.muldiv_response_get(execute_mul$muldiv_response_get),
.RDY_muldiv_response_get(execute_mul$RDY_muldiv_response_get));
// submodule execute_pendingOps
FIFO1 #(.width(32'd445),
.guarded(32'd1)) execute_pendingOps(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(execute_pendingOps$D_IN),
.ENQ(execute_pendingOps$ENQ),
.DEQ(execute_pendingOps$DEQ),
.CLR(execute_pendingOps$CLR),
.D_OUT(execute_pendingOps$D_OUT),
.FULL_N(execute_pendingOps$FULL_N),
.EMPTY_N(execute_pendingOps$EMPTY_N));
// submodule fetchedControlToken
FIFO2 #(.width(32'd445),
.guarded(32'd1)) fetchedControlToken(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(fetchedControlToken$D_IN),
.ENQ(fetchedControlToken$ENQ),
.DEQ(fetchedControlToken$DEQ),
.CLR(fetchedControlToken$CLR),
.D_OUT(fetchedControlToken$D_OUT),
.FULL_N(fetchedControlToken$FULL_N),
.EMPTY_N(fetchedControlToken$EMPTY_N));
// submodule freeRenameReg
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd5),
.p3cntr_width(32'd2),
.guarded(32'd1)) freeRenameReg(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(freeRenameReg$D_IN),
.ENQ(freeRenameReg$ENQ),
.DEQ(freeRenameReg$DEQ),
.CLR(freeRenameReg$CLR),
.D_OUT(),
.FULL_N(freeRenameReg$FULL_N),
.EMPTY_N(freeRenameReg$EMPTY_N));
// submodule memAccessToWriteback
FIFO2 #(.width(32'd445),
.guarded(32'd1)) memAccessToWriteback(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(memAccessToWriteback$D_IN),
.ENQ(memAccessToWriteback$ENQ),
.DEQ(memAccessToWriteback$DEQ),
.CLR(memAccessToWriteback$CLR),
.D_OUT(memAccessToWriteback$D_OUT),
.FULL_N(memAccessToWriteback$FULL_N),
.EMPTY_N(memAccessToWriteback$EMPTY_N));
// submodule memAccess_inQ
SizedFIFO #(.p1width(32'd445),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) memAccess_inQ(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(memAccess_inQ$D_IN),
.ENQ(memAccess_inQ$ENQ),
.DEQ(memAccess_inQ$DEQ),
.CLR(memAccess_inQ$CLR),
.D_OUT(memAccess_inQ$D_OUT),
.FULL_N(memAccess_inQ$FULL_N),
.EMPTY_N(memAccess_inQ$EMPTY_N));
// submodule theCP0
mkCP0 theCP0(.CLK(csi_c0_clk),
.RST_N(csi_c0_reset_n),
.getLlScReg_matchAddress(theCP0$getLlScReg_matchAddress),
.interrupts_interruptLines(theCP0$interrupts_interruptLines),
.putException_exp(theCP0$putException_exp),
.readGet_goingToWrite(theCP0$readGet_goingToWrite),
.readReq_rn(theCP0$readReq_rn),
.readReq_sel(theCP0$readReq_sel),
.tlbLookupCoprocessors_0_request_put(theCP0$tlbLookupCoprocessors_0_request_put),
.tlbLookupData_request_put(theCP0$tlbLookupData_request_put),
.tlbLookupInstruction_request_put(theCP0$tlbLookupInstruction_request_put),
.writeReg_data(theCP0$writeReg_data),
.writeReg_forceKernelMode(theCP0$writeReg_forceKernelMode),
.writeReg_rn(theCP0$writeReg_rn),
.writeReg_writeBack(theCP0$writeReg_writeBack),
.EN_readReq(theCP0$EN_readReq),
.EN_readGet(theCP0$EN_readGet),
.EN_writeReg(theCP0$EN_writeReg),
.EN_getException(theCP0$EN_getException),
.EN_putException(theCP0$EN_putException),
.EN_interrupts(theCP0$EN_interrupts),
.EN_getExceptionReturn(theCP0$EN_getExceptionReturn),
.EN_tlbLookupInstruction_request_put(theCP0$EN_tlbLookupInstruction_request_put),
.EN_tlbLookupInstruction_response_get(theCP0$EN_tlbLookupInstruction_response_get),
.EN_tlbLookupData_request_put(theCP0$EN_tlbLookupData_request_put),
.EN_tlbLookupData_response_get(theCP0$EN_tlbLookupData_response_get),
.EN_tlbLookupCoprocessors_0_request_put(theCP0$EN_tlbLookupCoprocessors_0_request_put),
.EN_tlbLookupCoprocessors_0_response_get(theCP0$EN_tlbLookupCoprocessors_0_response_get),
.RDY_readReq(theCP0$RDY_readReq),
.readGet(theCP0$readGet),
.RDY_readGet(theCP0$RDY_readGet),
.RDY_writeReg(theCP0$RDY_writeReg),
.getException(theCP0$getException),
.RDY_getException(),
.RDY_putException(),
.getLlScReg(theCP0$getLlScReg),
.RDY_getLlScReg(),
.RDY_interrupts(),
.RDY_getExceptionReturn(theCP0$RDY_getExceptionReturn),
.getCoprocessorEnables(theCP0$getCoprocessorEnables),
.RDY_getCoprocessorEnables(),
.RDY_tlbLookupInstruction_request_put(theCP0$RDY_tlbLookupInstruction_request_put),
.tlbLookupInstruction_response_get(theCP0$tlbLookupInstruction_response_get),
.RDY_tlbLookupInstruction_response_get(theCP0$RDY_tlbLookupInstruction_response_get),
.RDY_tlbLookupData_request_put(theCP0$RDY_tlbLookupData_request_put),
.tlbLookupData_response_get(theCP0$tlbLookupData_response_get),
.RDY_tlbLookupData_response_get(theCP0$RDY_tlbLookupData_response_get),
.RDY_tlbLookupCoprocessors_0_request_put(theCP0$RDY_tlbLookupCoprocessors_0_request_put),
.tlbLookupCoprocessors_0_response_get(theCP0$tlbLookupCoprocessors_0_response_get),
.RDY_tlbLookupCoprocessors_0_response_get(theCP0$RDY_tlbLookupCoprocessors_0_response_get));
// submodule theCapCop_baseRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) theCapCop_baseRegs(.CLK(csi_c0_clk),
.ADDR_1(theCapCop_baseRegs$ADDR_1),
.ADDR_2(theCapCop_baseRegs$ADDR_2),
.ADDR_3(theCapCop_baseRegs$ADDR_3),
.ADDR_4(theCapCop_baseRegs$ADDR_4),
.ADDR_5(theCapCop_baseRegs$ADDR_5),
.ADDR_IN(theCapCop_baseRegs$ADDR_IN),
.D_IN(theCapCop_baseRegs$D_IN),
.WE(theCapCop_baseRegs$WE),
.D_OUT_1(theCapCop_baseRegs$D_OUT_1),
.D_OUT_2(theCapCop_baseRegs$D_OUT_2),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule theCapCop_capInsts
SizedFIFO #(.p1width(32'd100),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) theCapCop_capInsts(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_capInsts$D_IN),
.ENQ(theCapCop_capInsts$ENQ),
.DEQ(theCapCop_capInsts$DEQ),
.CLR(theCapCop_capInsts$CLR),
.D_OUT(theCapCop_capInsts$D_OUT),
.FULL_N(theCapCop_capInsts$FULL_N),
.EMPTY_N(theCapCop_capInsts$EMPTY_N));
// submodule theCapCop_capMemInsts
FIFO1 #(.width(32'd338),
.guarded(32'd0)) theCapCop_capMemInsts(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_capMemInsts$D_IN),
.ENQ(theCapCop_capMemInsts$ENQ),
.DEQ(theCapCop_capMemInsts$DEQ),
.CLR(theCapCop_capMemInsts$CLR),
.D_OUT(theCapCop_capMemInsts$D_OUT),
.FULL_N(theCapCop_capMemInsts$FULL_N),
.EMPTY_N(theCapCop_capMemInsts$EMPTY_N));
// submodule theCapCop_capWritebackTags
SizedFIFO #(.p1width(32'd13),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) theCapCop_capWritebackTags(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_capWritebackTags$D_IN),
.ENQ(theCapCop_capWritebackTags$ENQ),
.DEQ(theCapCop_capWritebackTags$DEQ),
.CLR(theCapCop_capWritebackTags$CLR),
.D_OUT(theCapCop_capWritebackTags$D_OUT),
.FULL_N(theCapCop_capWritebackTags$FULL_N),
.EMPTY_N(theCapCop_capWritebackTags$EMPTY_N));
// submodule theCapCop_commitStore
FIFO2 #(.width(32'd1),
.guarded(32'd1)) theCapCop_commitStore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_commitStore$D_IN),
.ENQ(theCapCop_commitStore$ENQ),
.DEQ(theCapCop_commitStore$DEQ),
.CLR(theCapCop_commitStore$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theCapCop_exception
FIFO1 #(.width(32'd1),
.guarded(32'd1)) theCapCop_exception(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_exception$D_IN),
.ENQ(theCapCop_exception$ENQ),
.DEQ(theCapCop_exception$DEQ),
.CLR(theCapCop_exception$CLR),
.D_OUT(theCapCop_exception$D_OUT),
.FULL_N(theCapCop_exception$FULL_N),
.EMPTY_N(theCapCop_exception$EMPTY_N));
// submodule theCapCop_fetchFifoA
SizedFIFO #(.p1width(32'd5),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) theCapCop_fetchFifoA(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_fetchFifoA$D_IN),
.ENQ(theCapCop_fetchFifoA$ENQ),
.DEQ(theCapCop_fetchFifoA$DEQ),
.CLR(theCapCop_fetchFifoA$CLR),
.D_OUT(theCapCop_fetchFifoA$D_OUT),
.FULL_N(theCapCop_fetchFifoA$FULL_N),
.EMPTY_N(theCapCop_fetchFifoA$EMPTY_N));
// submodule theCapCop_fetchFifoB
SizedFIFO #(.p1width(32'd5),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) theCapCop_fetchFifoB(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_fetchFifoB$D_IN),
.ENQ(theCapCop_fetchFifoB$ENQ),
.DEQ(theCapCop_fetchFifoB$DEQ),
.CLR(theCapCop_fetchFifoB$CLR),
.D_OUT(theCapCop_fetchFifoB$D_OUT),
.FULL_N(theCapCop_fetchFifoB$FULL_N),
.EMPTY_N(theCapCop_fetchFifoB$EMPTY_N));
// submodule theCapCop_insts
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(32'd1)) theCapCop_insts(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_insts$D_IN),
.ENQ(theCapCop_insts$ENQ),
.DEQ(theCapCop_insts$DEQ),
.CLR(theCapCop_insts$CLR),
.D_OUT(),
.FULL_N(theCapCop_insts$FULL_N),
.EMPTY_N(theCapCop_insts$EMPTY_N));
// submodule theCapCop_lengthRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) theCapCop_lengthRegs(.CLK(csi_c0_clk),
.ADDR_1(theCapCop_lengthRegs$ADDR_1),
.ADDR_2(theCapCop_lengthRegs$ADDR_2),
.ADDR_3(theCapCop_lengthRegs$ADDR_3),
.ADDR_4(theCapCop_lengthRegs$ADDR_4),
.ADDR_5(theCapCop_lengthRegs$ADDR_5),
.ADDR_IN(theCapCop_lengthRegs$ADDR_IN),
.D_IN(theCapCop_lengthRegs$D_IN),
.WE(theCapCop_lengthRegs$WE),
.D_OUT_1(theCapCop_lengthRegs$D_OUT_1),
.D_OUT_2(theCapCop_lengthRegs$D_OUT_2),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule theCapCop_memResponse
FIFO2 #(.width(32'd256),
.guarded(32'd0)) theCapCop_memResponse(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_memResponse$D_IN),
.ENQ(theCapCop_memResponse$ENQ),
.DEQ(theCapCop_memResponse$DEQ),
.CLR(theCapCop_memResponse$CLR),
.D_OUT(),
.FULL_N(theCapCop_memResponse$FULL_N),
.EMPTY_N());
// submodule theCapCop_nextCapState
FIFO2 #(.width(32'd3),
.guarded(32'd0)) theCapCop_nextCapState(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_nextCapState$D_IN),
.ENQ(theCapCop_nextCapState$ENQ),
.DEQ(theCapCop_nextCapState$DEQ),
.CLR(theCapCop_nextCapState$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theCapCop_nextWillWriteback
FIFO2 #(.width(32'd1),
.guarded(32'd1)) theCapCop_nextWillWriteback(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_nextWillWriteback$D_IN),
.ENQ(theCapCop_nextWillWriteback$ENQ),
.DEQ(theCapCop_nextWillWriteback$DEQ),
.CLR(theCapCop_nextWillWriteback$CLR),
.D_OUT(theCapCop_nextWillWriteback$D_OUT),
.FULL_N(theCapCop_nextWillWriteback$FULL_N),
.EMPTY_N(theCapCop_nextWillWriteback$EMPTY_N));
// submodule theCapCop_oTypeRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) theCapCop_oTypeRegs(.CLK(csi_c0_clk),
.ADDR_1(theCapCop_oTypeRegs$ADDR_1),
.ADDR_2(theCapCop_oTypeRegs$ADDR_2),
.ADDR_3(theCapCop_oTypeRegs$ADDR_3),
.ADDR_4(theCapCop_oTypeRegs$ADDR_4),
.ADDR_5(theCapCop_oTypeRegs$ADDR_5),
.ADDR_IN(theCapCop_oTypeRegs$ADDR_IN),
.D_IN(theCapCop_oTypeRegs$D_IN),
.WE(theCapCop_oTypeRegs$WE),
.D_OUT_1(theCapCop_oTypeRegs$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule theCapCop_permRegs
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) theCapCop_permRegs(.CLK(csi_c0_clk),
.ADDR_1(theCapCop_permRegs$ADDR_1),
.ADDR_2(theCapCop_permRegs$ADDR_2),
.ADDR_3(theCapCop_permRegs$ADDR_3),
.ADDR_4(theCapCop_permRegs$ADDR_4),
.ADDR_5(theCapCop_permRegs$ADDR_5),
.ADDR_IN(theCapCop_permRegs$ADDR_IN),
.D_IN(theCapCop_permRegs$D_IN),
.WE(theCapCop_permRegs$WE),
.D_OUT_1(theCapCop_permRegs$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule theCapCop_startExp
FIFO1 #(.width(32'd1),
.guarded(32'd1)) theCapCop_startExp(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theCapCop_startExp$D_IN),
.ENQ(theCapCop_startExp$ENQ),
.DEQ(theCapCop_startExp$DEQ),
.CLR(theCapCop_startExp$CLR),
.D_OUT(),
.FULL_N(theCapCop_startExp$FULL_N),
.EMPTY_N(theCapCop_startExp$EMPTY_N));
// submodule theDebug_bpReport
FIFO1 #(.width(32'd272),
.guarded(32'd1)) theDebug_bpReport(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theDebug_bpReport$D_IN),
.ENQ(theDebug_bpReport$ENQ),
.DEQ(theDebug_bpReport$DEQ),
.CLR(theDebug_bpReport$CLR),
.D_OUT(theDebug_bpReport$D_OUT),
.FULL_N(theDebug_bpReport$FULL_N),
.EMPTY_N(theDebug_bpReport$EMPTY_N));
// submodule theDebug_curCommand
FIFO1 #(.width(32'd272),
.guarded(32'd1)) theDebug_curCommand(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theDebug_curCommand$D_IN),
.ENQ(theDebug_curCommand$ENQ),
.DEQ(theDebug_curCommand$DEQ),
.CLR(theDebug_curCommand$CLR),
.D_OUT(theDebug_curCommand$D_OUT),
.FULL_N(theDebug_curCommand$FULL_N),
.EMPTY_N(theDebug_curCommand$EMPTY_N));
// submodule theDebug_debugConvert
mkDebugConvert theDebug_debugConvert(.CLK(csi_c0_clk),
.RST_N(csi_c0_reset_n),
.messages_response_put(theDebug_debugConvert$messages_response_put),
.stream_request_put(theDebug_debugConvert$stream_request_put),
.EN_stream_request_put(theDebug_debugConvert$EN_stream_request_put),
.EN_stream_response_get(theDebug_debugConvert$EN_stream_response_get),
.EN_messages_request_get(theDebug_debugConvert$EN_messages_request_get),
.EN_messages_response_put(theDebug_debugConvert$EN_messages_response_put),
.RDY_stream_request_put(theDebug_debugConvert$RDY_stream_request_put),
.stream_response_get(theDebug_debugConvert$stream_response_get),
.RDY_stream_response_get(theDebug_debugConvert$RDY_stream_response_get),
.messages_request_get(theDebug_debugConvert$messages_request_get),
.RDY_messages_request_get(theDebug_debugConvert$RDY_messages_request_get),
.RDY_messages_response_put(theDebug_debugConvert$RDY_messages_response_put));
// submodule theDebug_doneInst
FIFO2 #(.width(32'd1),
.guarded(32'd0)) theDebug_doneInst(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theDebug_doneInst$D_IN),
.ENQ(theDebug_doneInst$ENQ),
.DEQ(theDebug_doneInst$DEQ),
.CLR(theDebug_doneInst$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theDebug_instQ
FIFO1 #(.width(32'd32),
.guarded(32'd1)) theDebug_instQ(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theDebug_instQ$D_IN),
.ENQ(theDebug_instQ$ENQ),
.DEQ(theDebug_instQ$DEQ),
.CLR(theDebug_instQ$CLR),
.D_OUT(theDebug_instQ$D_OUT),
.FULL_N(theDebug_instQ$FULL_N),
.EMPTY_N(theDebug_instQ$EMPTY_N));
// submodule theDebug_trace_buf_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd12),
.DATA_WIDTH(32'd256),
.MEMSIZE(13'd4096)) theDebug_trace_buf_bram(.CLKA(csi_c0_clk),
.CLKB(csi_c0_clk),
.ADDRA(theDebug_trace_buf_bram$ADDRA),
.ADDRB(theDebug_trace_buf_bram$ADDRB),
.DIA(theDebug_trace_buf_bram$DIA),
.DIB(theDebug_trace_buf_bram$DIB),
.WEA(theDebug_trace_buf_bram$WEA),
.WEB(theDebug_trace_buf_bram$WEB),
.ENA(theDebug_trace_buf_bram$ENA),
.ENB(theDebug_trace_buf_bram$ENB),
.DOA(),
.DOB(theDebug_trace_buf_bram$DOB));
// submodule theDebug_writebacks
FIFO1 #(.width(32'd70),
.guarded(32'd1)) theDebug_writebacks(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theDebug_writebacks$D_IN),
.ENQ(theDebug_writebacks$ENQ),
.DEQ(theDebug_writebacks$DEQ),
.CLR(theDebug_writebacks$CLR),
.D_OUT(theDebug_writebacks$D_OUT),
.FULL_N(theDebug_writebacks$FULL_N),
.EMPTY_N(theDebug_writebacks$EMPTY_N));
// submodule theMem_capExceptions
FIFO2 #(.width(32'd9),
.guarded(32'd0)) theMem_capExceptions(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_capExceptions$D_IN),
.ENQ(theMem_capExceptions$ENQ),
.DEQ(theMem_capExceptions$DEQ),
.CLR(theMem_capExceptions$CLR),
.D_OUT(theMem_capExceptions$D_OUT),
.FULL_N(theMem_capExceptions$FULL_N),
.EMPTY_N(theMem_capExceptions$EMPTY_N));
// submodule theMem_capPackets
FIFO2 #(.width(32'd326),
.guarded(32'd1)) theMem_capPackets(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_capPackets$D_IN),
.ENQ(theMem_capPackets$ENQ),
.DEQ(theMem_capPackets$DEQ),
.CLR(theMem_capPackets$CLR),
.D_OUT(theMem_capPackets$D_OUT),
.FULL_N(theMem_capPackets$FULL_N),
.EMPTY_N(theMem_capPackets$EMPTY_N));
// submodule theMem_capTlbResp
FIFO2 #(.width(32'd50),
.guarded(32'd1)) theMem_capTlbResp(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_capTlbResp$D_IN),
.ENQ(theMem_capTlbResp$ENQ),
.DEQ(theMem_capTlbResp$DEQ),
.CLR(theMem_capTlbResp$CLR),
.D_OUT(theMem_capTlbResp$D_OUT),
.FULL_N(theMem_capTlbResp$FULL_N),
.EMPTY_N(theMem_capTlbResp$EMPTY_N));
// submodule theMem_commitCapStore
FIFO2 #(.width(32'd1),
.guarded(32'd0)) theMem_commitCapStore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_commitCapStore$D_IN),
.ENQ(theMem_commitCapStore$ENQ),
.DEQ(theMem_commitCapStore$DEQ),
.CLR(theMem_commitCapStore$CLR),
.D_OUT(theMem_commitCapStore$D_OUT),
.FULL_N(theMem_commitCapStore$FULL_N),
.EMPTY_N(theMem_commitCapStore$EMPTY_N));
// submodule theMem_dCache_data_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd64),
.MEMSIZE(11'd1024)) theMem_dCache_data_memory(.CLKA(csi_c0_clk),
.CLKB(csi_c0_clk),
.ADDRA(theMem_dCache_data_memory$ADDRA),
.ADDRB(theMem_dCache_data_memory$ADDRB),
.DIA(theMem_dCache_data_memory$DIA),
.DIB(theMem_dCache_data_memory$DIB),
.WEA(theMem_dCache_data_memory$WEA),
.WEB(theMem_dCache_data_memory$WEB),
.ENA(theMem_dCache_data_memory$ENA),
.ENB(theMem_dCache_data_memory$ENB),
.DOA(theMem_dCache_data_memory$DOA),
.DOB(theMem_dCache_data_memory$DOB));
// submodule theMem_dCache_data_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd64),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_dCache_data_serverAdapterA_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_data_serverAdapterA_outDataCore$D_IN),
.ENQ(theMem_dCache_data_serverAdapterA_outDataCore$ENQ),
.DEQ(theMem_dCache_data_serverAdapterA_outDataCore$DEQ),
.CLR(theMem_dCache_data_serverAdapterA_outDataCore$CLR),
.D_OUT(theMem_dCache_data_serverAdapterA_outDataCore$D_OUT),
.FULL_N(theMem_dCache_data_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N));
// submodule theMem_dCache_data_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd64),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_dCache_data_serverAdapterB_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_data_serverAdapterB_outDataCore$D_IN),
.ENQ(theMem_dCache_data_serverAdapterB_outDataCore$ENQ),
.DEQ(theMem_dCache_data_serverAdapterB_outDataCore$DEQ),
.CLR(theMem_dCache_data_serverAdapterB_outDataCore$CLR),
.D_OUT(),
.FULL_N(theMem_dCache_data_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N());
// submodule theMem_dCache_invalidateFifo
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd0)) theMem_dCache_invalidateFifo(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_invalidateFifo$D_IN),
.ENQ(theMem_dCache_invalidateFifo$ENQ),
.DEQ(theMem_dCache_invalidateFifo$DEQ),
.CLR(theMem_dCache_invalidateFifo$CLR),
.D_OUT(theMem_dCache_invalidateFifo$D_OUT),
.FULL_N(theMem_dCache_invalidateFifo$FULL_N),
.EMPTY_N(theMem_dCache_invalidateFifo$EMPTY_N));
// submodule theMem_dCache_out_fifo_ff
FIFO2 #(.width(32'd69),
.guarded(32'd0)) theMem_dCache_out_fifo_ff(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_out_fifo_ff$D_IN),
.ENQ(theMem_dCache_out_fifo_ff$ENQ),
.DEQ(theMem_dCache_out_fifo_ff$DEQ),
.CLR(theMem_dCache_out_fifo_ff$CLR),
.D_OUT(theMem_dCache_out_fifo_ff$D_OUT),
.FULL_N(theMem_dCache_out_fifo_ff$FULL_N),
.EMPTY_N(theMem_dCache_out_fifo_ff$EMPTY_N));
// submodule theMem_dCache_out_fifo_firstValid
RevertReg #(.width(32'd1),
.init(1'd1)) theMem_dCache_out_fifo_firstValid(.CLK(csi_c0_clk),
.D_IN(theMem_dCache_out_fifo_firstValid$D_IN),
.EN(theMem_dCache_out_fifo_firstValid$EN),
.Q_OUT(theMem_dCache_out_fifo_firstValid$Q_OUT));
// submodule theMem_dCache_req_fifo
FIFOL1 #(.width(32'd139)) theMem_dCache_req_fifo(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_req_fifo$D_IN),
.ENQ(theMem_dCache_req_fifo$ENQ),
.DEQ(theMem_dCache_req_fifo$DEQ),
.CLR(theMem_dCache_req_fifo$CLR),
.D_OUT(theMem_dCache_req_fifo$D_OUT),
.FULL_N(theMem_dCache_req_fifo$FULL_N),
.EMPTY_N(theMem_dCache_req_fifo$EMPTY_N));
// submodule theMem_dCache_set_fifo
FIFO1 #(.width(32'd1),
.guarded(32'd1)) theMem_dCache_set_fifo(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_set_fifo$D_IN),
.ENQ(theMem_dCache_set_fifo$ENQ),
.DEQ(theMem_dCache_set_fifo$DEQ),
.CLR(theMem_dCache_set_fifo$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theMem_dCache_tags_fifo
FIFO1 #(.width(32'd50),
.guarded(32'd1)) theMem_dCache_tags_fifo(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_tags_fifo$D_IN),
.ENQ(theMem_dCache_tags_fifo$ENQ),
.DEQ(theMem_dCache_tags_fifo$DEQ),
.CLR(theMem_dCache_tags_fifo$CLR),
.D_OUT(theMem_dCache_tags_fifo$D_OUT),
.FULL_N(theMem_dCache_tags_fifo$FULL_N),
.EMPTY_N(theMem_dCache_tags_fifo$EMPTY_N));
// submodule theMem_dCache_tags_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd7),
.DATA_WIDTH(32'd50),
.MEMSIZE(8'd128)) theMem_dCache_tags_memory(.CLKA(csi_c0_clk),
.CLKB(csi_c0_clk),
.ADDRA(theMem_dCache_tags_memory$ADDRA),
.ADDRB(theMem_dCache_tags_memory$ADDRB),
.DIA(theMem_dCache_tags_memory$DIA),
.DIB(theMem_dCache_tags_memory$DIB),
.WEA(theMem_dCache_tags_memory$WEA),
.WEB(theMem_dCache_tags_memory$WEB),
.ENA(theMem_dCache_tags_memory$ENA),
.ENB(theMem_dCache_tags_memory$ENB),
.DOA(theMem_dCache_tags_memory$DOA),
.DOB(theMem_dCache_tags_memory$DOB));
// submodule theMem_dCache_tags_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd50),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_dCache_tags_serverAdapterA_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_tags_serverAdapterA_outDataCore$D_IN),
.ENQ(theMem_dCache_tags_serverAdapterA_outDataCore$ENQ),
.DEQ(theMem_dCache_tags_serverAdapterA_outDataCore$DEQ),
.CLR(theMem_dCache_tags_serverAdapterA_outDataCore$CLR),
.D_OUT(theMem_dCache_tags_serverAdapterA_outDataCore$D_OUT),
.FULL_N(theMem_dCache_tags_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N));
// submodule theMem_dCache_tags_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd50),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_dCache_tags_serverAdapterB_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_tags_serverAdapterB_outDataCore$D_IN),
.ENQ(theMem_dCache_tags_serverAdapterB_outDataCore$ENQ),
.DEQ(theMem_dCache_tags_serverAdapterB_outDataCore$DEQ),
.CLR(theMem_dCache_tags_serverAdapterB_outDataCore$CLR),
.D_OUT(),
.FULL_N(theMem_dCache_tags_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N());
// submodule theMem_dCache_wayKey
FIFO2 #(.width(32'd7),
.guarded(32'd1)) theMem_dCache_wayKey(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_wayKey$D_IN),
.ENQ(theMem_dCache_wayKey$ENQ),
.DEQ(theMem_dCache_wayKey$DEQ),
.CLR(theMem_dCache_wayKey$CLR),
.D_OUT(theMem_dCache_wayKey$D_OUT),
.FULL_N(theMem_dCache_wayKey$FULL_N),
.EMPTY_N(theMem_dCache_wayKey$EMPTY_N));
// submodule theMem_dCache_wayPredicted
FIFO2 #(.width(32'd1),
.guarded(32'd1)) theMem_dCache_wayPredicted(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dCache_wayPredicted$D_IN),
.ENQ(theMem_dCache_wayPredicted$ENQ),
.DEQ(theMem_dCache_wayPredicted$DEQ),
.CLR(theMem_dCache_wayPredicted$CLR),
.D_OUT(theMem_dCache_wayPredicted$D_OUT),
.FULL_N(theMem_dCache_wayPredicted$FULL_N),
.EMPTY_N(theMem_dCache_wayPredicted$EMPTY_N));
// submodule theMem_dCache_wayTable
RegFile #(.addr_width(32'd7),
.data_width(32'd1),
.lo(7'd0),
.hi(7'd127)) theMem_dCache_wayTable(.CLK(csi_c0_clk),
.ADDR_1(theMem_dCache_wayTable$ADDR_1),
.ADDR_2(theMem_dCache_wayTable$ADDR_2),
.ADDR_3(theMem_dCache_wayTable$ADDR_3),
.ADDR_4(theMem_dCache_wayTable$ADDR_4),
.ADDR_5(theMem_dCache_wayTable$ADDR_5),
.ADDR_IN(theMem_dCache_wayTable$ADDR_IN),
.D_IN(theMem_dCache_wayTable$D_IN),
.WE(theMem_dCache_wayTable$WE),
.D_OUT_1(theMem_dCache_wayTable$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule theMem_dataByte
FIFO2 #(.width(32'd3),
.guarded(32'd0)) theMem_dataByte(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dataByte$D_IN),
.ENQ(theMem_dataByte$ENQ),
.DEQ(theMem_dataByte$DEQ),
.CLR(theMem_dataByte$CLR),
.D_OUT(theMem_dataByte$D_OUT),
.FULL_N(theMem_dataByte$FULL_N),
.EMPTY_N(theMem_dataByte$EMPTY_N));
// submodule theMem_dataSize
FIFO2 #(.width(32'd4),
.guarded(32'd0)) theMem_dataSize(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_dataSize$D_IN),
.ENQ(theMem_dataSize$ENQ),
.DEQ(theMem_dataSize$DEQ),
.CLR(theMem_dataSize$CLR),
.D_OUT(theMem_dataSize$D_OUT),
.FULL_N(theMem_dataSize$FULL_N),
.EMPTY_N(theMem_dataSize$EMPTY_N));
// submodule theMem_iCacheOp
FIFO2 #(.width(32'd139),
.guarded(32'd0)) theMem_iCacheOp(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCacheOp$D_IN),
.ENQ(theMem_iCacheOp$ENQ),
.DEQ(theMem_iCacheOp$DEQ),
.CLR(theMem_iCacheOp$CLR),
.D_OUT(theMem_iCacheOp$D_OUT),
.FULL_N(theMem_iCacheOp$FULL_N),
.EMPTY_N(theMem_iCacheOp$EMPTY_N));
// submodule theMem_iCache_bank_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd64),
.MEMSIZE(12'd2048)) theMem_iCache_bank_memory(.CLKA(csi_c0_clk),
.CLKB(csi_c0_clk),
.ADDRA(theMem_iCache_bank_memory$ADDRA),
.ADDRB(theMem_iCache_bank_memory$ADDRB),
.DIA(theMem_iCache_bank_memory$DIA),
.DIB(theMem_iCache_bank_memory$DIB),
.WEA(theMem_iCache_bank_memory$WEA),
.WEB(theMem_iCache_bank_memory$WEB),
.ENA(theMem_iCache_bank_memory$ENA),
.ENB(theMem_iCache_bank_memory$ENB),
.DOA(theMem_iCache_bank_memory$DOA),
.DOB(theMem_iCache_bank_memory$DOB));
// submodule theMem_iCache_bank_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd64),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_iCache_bank_serverAdapterA_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_bank_serverAdapterA_outDataCore$D_IN),
.ENQ(theMem_iCache_bank_serverAdapterA_outDataCore$ENQ),
.DEQ(theMem_iCache_bank_serverAdapterA_outDataCore$DEQ),
.CLR(theMem_iCache_bank_serverAdapterA_outDataCore$CLR),
.D_OUT(theMem_iCache_bank_serverAdapterA_outDataCore$D_OUT),
.FULL_N(theMem_iCache_bank_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N));
// submodule theMem_iCache_bank_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd64),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_iCache_bank_serverAdapterB_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_bank_serverAdapterB_outDataCore$D_IN),
.ENQ(theMem_iCache_bank_serverAdapterB_outDataCore$ENQ),
.DEQ(theMem_iCache_bank_serverAdapterB_outDataCore$DEQ),
.CLR(theMem_iCache_bank_serverAdapterB_outDataCore$CLR),
.D_OUT(),
.FULL_N(theMem_iCache_bank_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N());
// submodule theMem_iCache_delayedReq
FIFO1 #(.width(32'd139),
.guarded(32'd1)) theMem_iCache_delayedReq(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_delayedReq$D_IN),
.ENQ(theMem_iCache_delayedReq$ENQ),
.DEQ(theMem_iCache_delayedReq$DEQ),
.CLR(theMem_iCache_delayedReq$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theMem_iCache_invalidateFifo
SizedFIFO #(.p1width(32'd14),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd0)) theMem_iCache_invalidateFifo(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_invalidateFifo$D_IN),
.ENQ(theMem_iCache_invalidateFifo$ENQ),
.DEQ(theMem_iCache_invalidateFifo$DEQ),
.CLR(theMem_iCache_invalidateFifo$CLR),
.D_OUT(theMem_iCache_invalidateFifo$D_OUT),
.FULL_N(),
.EMPTY_N(theMem_iCache_invalidateFifo$EMPTY_N));
// submodule theMem_iCache_out_fifo_ff
FIFO2 #(.width(32'd69),
.guarded(32'd0)) theMem_iCache_out_fifo_ff(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_out_fifo_ff$D_IN),
.ENQ(theMem_iCache_out_fifo_ff$ENQ),
.DEQ(theMem_iCache_out_fifo_ff$DEQ),
.CLR(theMem_iCache_out_fifo_ff$CLR),
.D_OUT(theMem_iCache_out_fifo_ff$D_OUT),
.FULL_N(theMem_iCache_out_fifo_ff$FULL_N),
.EMPTY_N(theMem_iCache_out_fifo_ff$EMPTY_N));
// submodule theMem_iCache_out_fifo_firstValid
RevertReg #(.width(32'd1),
.init(1'd1)) theMem_iCache_out_fifo_firstValid(.CLK(csi_c0_clk),
.D_IN(theMem_iCache_out_fifo_firstValid$D_IN),
.EN(theMem_iCache_out_fifo_firstValid$EN),
.Q_OUT(theMem_iCache_out_fifo_firstValid$Q_OUT));
// submodule theMem_iCache_req_fifo
FIFOL1 #(.width(32'd139)) theMem_iCache_req_fifo(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_req_fifo$D_IN),
.ENQ(theMem_iCache_req_fifo$ENQ),
.DEQ(theMem_iCache_req_fifo$DEQ),
.CLR(theMem_iCache_req_fifo$CLR),
.D_OUT(theMem_iCache_req_fifo$D_OUT),
.FULL_N(theMem_iCache_req_fifo$FULL_N),
.EMPTY_N(theMem_iCache_req_fifo$EMPTY_N));
// submodule theMem_iCache_tags_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd25),
.MEMSIZE(10'd512)) theMem_iCache_tags_memory(.CLKA(csi_c0_clk),
.CLKB(csi_c0_clk),
.ADDRA(theMem_iCache_tags_memory$ADDRA),
.ADDRB(theMem_iCache_tags_memory$ADDRB),
.DIA(theMem_iCache_tags_memory$DIA),
.DIB(theMem_iCache_tags_memory$DIB),
.WEA(theMem_iCache_tags_memory$WEA),
.WEB(theMem_iCache_tags_memory$WEB),
.ENA(theMem_iCache_tags_memory$ENA),
.ENB(theMem_iCache_tags_memory$ENB),
.DOA(theMem_iCache_tags_memory$DOA),
.DOB(theMem_iCache_tags_memory$DOB));
// submodule theMem_iCache_tags_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd25),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_iCache_tags_serverAdapterA_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_tags_serverAdapterA_outDataCore$D_IN),
.ENQ(theMem_iCache_tags_serverAdapterA_outDataCore$ENQ),
.DEQ(theMem_iCache_tags_serverAdapterA_outDataCore$DEQ),
.CLR(theMem_iCache_tags_serverAdapterA_outDataCore$CLR),
.D_OUT(theMem_iCache_tags_serverAdapterA_outDataCore$D_OUT),
.FULL_N(theMem_iCache_tags_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N));
// submodule theMem_iCache_tags_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd25),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) theMem_iCache_tags_serverAdapterB_outDataCore(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_tags_serverAdapterB_outDataCore$D_IN),
.ENQ(theMem_iCache_tags_serverAdapterB_outDataCore$ENQ),
.DEQ(theMem_iCache_tags_serverAdapterB_outDataCore$DEQ),
.CLR(theMem_iCache_tags_serverAdapterB_outDataCore$CLR),
.D_OUT(),
.FULL_N(theMem_iCache_tags_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N());
// submodule theMem_iCache_writeActive
FIFO2 #(.width(32'd1),
.guarded(32'd1)) theMem_iCache_writeActive(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_iCache_writeActive$D_IN),
.ENQ(theMem_iCache_writeActive$ENQ),
.DEQ(theMem_iCache_writeActive$DEQ),
.CLR(theMem_iCache_writeActive$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theMem_instructionWord
FIFO2 #(.width(32'd1),
.guarded(32'd1)) theMem_instructionWord(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_instructionWord$D_IN),
.ENQ(theMem_instructionWord$ENQ),
.DEQ(theMem_instructionWord$DEQ),
.CLR(theMem_instructionWord$CLR),
.D_OUT(theMem_instructionWord$D_OUT),
.FULL_N(theMem_instructionWord$FULL_N),
.EMPTY_N(theMem_instructionWord$EMPTY_N));
// submodule theMem_l2Cache
mkL2Cache theMem_l2Cache(.CLK(csi_c0_clk),
.RST_N(csi_c0_reset_n),
.cache_request_put(theMem_l2Cache$cache_request_put),
.memory_response_put(theMem_l2Cache$memory_response_put),
.EN_cache_request_put(theMem_l2Cache$EN_cache_request_put),
.EN_cache_response_get(theMem_l2Cache$EN_cache_response_get),
.EN_memory_request_get(theMem_l2Cache$EN_memory_request_get),
.EN_memory_response_put(theMem_l2Cache$EN_memory_response_put),
.RDY_cache_request_put(theMem_l2Cache$RDY_cache_request_put),
.cache_response_get(theMem_l2Cache$cache_response_get),
.RDY_cache_response_get(theMem_l2Cache$RDY_cache_response_get),
.memory_request_get(theMem_l2Cache$memory_request_get),
.RDY_memory_request_get(theMem_l2Cache$RDY_memory_request_get),
.RDY_memory_response_put(theMem_l2Cache$RDY_memory_response_put));
// submodule theMem_pendingExcRpt
FIFO2 #(.width(32'd1),
.guarded(32'd0)) theMem_pendingExcRpt(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_pendingExcRpt$D_IN),
.ENQ(theMem_pendingExcRpt$ENQ),
.DEQ(theMem_pendingExcRpt$DEQ),
.CLR(theMem_pendingExcRpt$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(theMem_pendingExcRpt$EMPTY_N));
// submodule theMem_theMemMerge_nextReq
FIFO2 #(.width(32'd317),
.guarded(32'd1)) theMem_theMemMerge_nextReq(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_nextReq$D_IN),
.ENQ(theMem_theMemMerge_nextReq$ENQ),
.DEQ(theMem_theMemMerge_nextReq$DEQ),
.CLR(theMem_theMemMerge_nextReq$CLR),
.D_OUT(theMem_theMemMerge_nextReq$D_OUT),
.FULL_N(theMem_theMemMerge_nextReq$FULL_N),
.EMPTY_N(theMem_theMemMerge_nextReq$EMPTY_N));
// submodule theMem_theMemMerge_pendingReqs
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(32'd1)) theMem_theMemMerge_pendingReqs(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_pendingReqs$D_IN),
.ENQ(theMem_theMemMerge_pendingReqs$ENQ),
.DEQ(theMem_theMemMerge_pendingReqs$DEQ),
.CLR(theMem_theMemMerge_pendingReqs$CLR),
.D_OUT(theMem_theMemMerge_pendingReqs$D_OUT),
.FULL_N(theMem_theMemMerge_pendingReqs$FULL_N),
.EMPTY_N(theMem_theMemMerge_pendingReqs$EMPTY_N));
// submodule theMem_theMemMerge_req_fifos
FIFO2 #(.width(32'd317),
.guarded(32'd0)) theMem_theMemMerge_req_fifos(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_req_fifos$D_IN),
.ENQ(theMem_theMemMerge_req_fifos$ENQ),
.DEQ(theMem_theMemMerge_req_fifos$DEQ),
.CLR(theMem_theMemMerge_req_fifos$CLR),
.D_OUT(theMem_theMemMerge_req_fifos$D_OUT),
.FULL_N(theMem_theMemMerge_req_fifos$FULL_N),
.EMPTY_N(theMem_theMemMerge_req_fifos$EMPTY_N));
// submodule theMem_theMemMerge_req_fifos_1
FIFO2 #(.width(32'd317),
.guarded(32'd0)) theMem_theMemMerge_req_fifos_1(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_req_fifos_1$D_IN),
.ENQ(theMem_theMemMerge_req_fifos_1$ENQ),
.DEQ(theMem_theMemMerge_req_fifos_1$DEQ),
.CLR(theMem_theMemMerge_req_fifos_1$CLR),
.D_OUT(theMem_theMemMerge_req_fifos_1$D_OUT),
.FULL_N(theMem_theMemMerge_req_fifos_1$FULL_N),
.EMPTY_N(theMem_theMemMerge_req_fifos_1$EMPTY_N));
// submodule theMem_theMemMerge_req_fifos_2
FIFO2 #(.width(32'd317),
.guarded(32'd0)) theMem_theMemMerge_req_fifos_2(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_req_fifos_2$D_IN),
.ENQ(theMem_theMemMerge_req_fifos_2$ENQ),
.DEQ(theMem_theMemMerge_req_fifos_2$DEQ),
.CLR(theMem_theMemMerge_req_fifos_2$CLR),
.D_OUT(theMem_theMemMerge_req_fifos_2$D_OUT),
.FULL_N(theMem_theMemMerge_req_fifos_2$FULL_N),
.EMPTY_N(theMem_theMemMerge_req_fifos_2$EMPTY_N));
// submodule theMem_theMemMerge_rsp_fifos
FIFO2 #(.width(32'd256),
.guarded(32'd1)) theMem_theMemMerge_rsp_fifos(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_rsp_fifos$D_IN),
.ENQ(theMem_theMemMerge_rsp_fifos$ENQ),
.DEQ(theMem_theMemMerge_rsp_fifos$DEQ),
.CLR(theMem_theMemMerge_rsp_fifos$CLR),
.D_OUT(theMem_theMemMerge_rsp_fifos$D_OUT),
.FULL_N(theMem_theMemMerge_rsp_fifos$FULL_N),
.EMPTY_N(theMem_theMemMerge_rsp_fifos$EMPTY_N));
// submodule theMem_theMemMerge_rsp_fifos_1
FIFO2 #(.width(32'd256),
.guarded(32'd1)) theMem_theMemMerge_rsp_fifos_1(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_rsp_fifos_1$D_IN),
.ENQ(theMem_theMemMerge_rsp_fifos_1$ENQ),
.DEQ(theMem_theMemMerge_rsp_fifos_1$DEQ),
.CLR(theMem_theMemMerge_rsp_fifos_1$CLR),
.D_OUT(theMem_theMemMerge_rsp_fifos_1$D_OUT),
.FULL_N(theMem_theMemMerge_rsp_fifos_1$FULL_N),
.EMPTY_N(theMem_theMemMerge_rsp_fifos_1$EMPTY_N));
// submodule theMem_theMemMerge_rsp_fifos_2
FIFO2 #(.width(32'd256),
.guarded(32'd1)) theMem_theMemMerge_rsp_fifos_2(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theMem_theMemMerge_rsp_fifos_2$D_IN),
.ENQ(theMem_theMemMerge_rsp_fifos_2$ENQ),
.DEQ(theMem_theMemMerge_rsp_fifos_2$DEQ),
.CLR(theMem_theMemMerge_rsp_fifos_2$CLR),
.D_OUT(theMem_theMemMerge_rsp_fifos_2$D_OUT),
.FULL_N(theMem_theMemMerge_rsp_fifos_2$FULL_N),
.EMPTY_N(theMem_theMemMerge_rsp_fifos_2$EMPTY_N));
// submodule theRF_idsA
FIFO2 #(.width(32'd4), .guarded(32'd1)) theRF_idsA(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theRF_idsA$D_IN),
.ENQ(theRF_idsA$ENQ),
.DEQ(theRF_idsA$DEQ),
.CLR(theRF_idsA$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theRF_idsB
FIFO2 #(.width(32'd4), .guarded(32'd1)) theRF_idsB(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theRF_idsB$D_IN),
.ENQ(theRF_idsB$ENQ),
.DEQ(theRF_idsB$DEQ),
.CLR(theRF_idsB$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule theRF_regFile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'd0),
.hi(5'd31)) theRF_regFile(.CLK(csi_c0_clk),
.ADDR_1(theRF_regFile$ADDR_1),
.ADDR_2(theRF_regFile$ADDR_2),
.ADDR_3(theRF_regFile$ADDR_3),
.ADDR_4(theRF_regFile$ADDR_4),
.ADDR_5(theRF_regFile$ADDR_5),
.ADDR_IN(theRF_regFile$ADDR_IN),
.D_IN(theRF_regFile$D_IN),
.WE(theRF_regFile$WE),
.D_OUT_1(theRF_regFile$D_OUT_1),
.D_OUT_2(theRF_regFile$D_OUT_2),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule theRF_reqA
FIFO2 #(.width(32'd5), .guarded(32'd1)) theRF_reqA(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theRF_reqA$D_IN),
.ENQ(theRF_reqA$ENQ),
.DEQ(theRF_reqA$DEQ),
.CLR(theRF_reqA$CLR),
.D_OUT(theRF_reqA$D_OUT),
.FULL_N(theRF_reqA$FULL_N),
.EMPTY_N(theRF_reqA$EMPTY_N));
// submodule theRF_reqB
FIFO2 #(.width(32'd5), .guarded(32'd1)) theRF_reqB(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(theRF_reqB$D_IN),
.ENQ(theRF_reqB$ENQ),
.DEQ(theRF_reqB$DEQ),
.CLR(theRF_reqB$CLR),
.D_OUT(theRF_reqB$D_OUT),
.FULL_N(theRF_reqB$FULL_N),
.EMPTY_N(theRF_reqB$EMPTY_N));
// submodule writeback_destRenamed
FIFO2 #(.width(32'd2),
.guarded(32'd0)) writeback_destRenamed(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(writeback_destRenamed$D_IN),
.ENQ(writeback_destRenamed$ENQ),
.DEQ(writeback_destRenamed$DEQ),
.CLR(writeback_destRenamed$CLR),
.D_OUT(writeback_destRenamed$D_OUT),
.FULL_N(),
.EMPTY_N(writeback_destRenamed$EMPTY_N));
// submodule writeback_exception
FIFO1 #(.width(32'd5),
.guarded(32'd1)) writeback_exception(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(writeback_exception$D_IN),
.ENQ(writeback_exception$ENQ),
.DEQ(writeback_exception$DEQ),
.CLR(writeback_exception$CLR),
.D_OUT(),
.FULL_N(writeback_exception$FULL_N),
.EMPTY_N(writeback_exception$EMPTY_N));
// submodule writeback_hiLoCommit
FIFO2 #(.width(32'd1),
.guarded(32'd1)) writeback_hiLoCommit(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(writeback_hiLoCommit$D_IN),
.ENQ(writeback_hiLoCommit$ENQ),
.DEQ(writeback_hiLoCommit$DEQ),
.CLR(writeback_hiLoCommit$CLR),
.D_OUT(writeback_hiLoCommit$D_OUT),
.FULL_N(writeback_hiLoCommit$FULL_N),
.EMPTY_N(writeback_hiLoCommit$EMPTY_N));
// submodule writeback_instructionReport
FIFO2 #(.width(32'd509),
.guarded(32'd1)) writeback_instructionReport(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(writeback_instructionReport$D_IN),
.ENQ(writeback_instructionReport$ENQ),
.DEQ(writeback_instructionReport$DEQ),
.CLR(writeback_instructionReport$CLR),
.D_OUT(writeback_instructionReport$D_OUT),
.FULL_N(writeback_instructionReport$FULL_N),
.EMPTY_N(writeback_instructionReport$EMPTY_N));
// submodule writeback_results
FIFO2 #(.width(32'd64),
.guarded(32'd0)) writeback_results(.RST_N(csi_c0_reset_n),
.CLK(csi_c0_clk),
.D_IN(writeback_results$D_IN),
.ENQ(writeback_results$ENQ),
.DEQ(writeback_results$DEQ),
.CLR(writeback_results$CLR),
.D_OUT(writeback_results$D_OUT),
.FULL_N(),
.EMPTY_N(writeback_results$EMPTY_N));
// rule RL_doDecode
assign WILL_FIRE_RL_doDecode =
theRF_regFileState &&
theCapCop_capState_read__301_EQ_5_335_AND_theC_ETC___d4907 ;
// rule RL_capToMem
assign WILL_FIRE_RL_capToMem =
theCapCop_capMemInsts$EMPTY_N && theCapCop_capState == 3'd1 &&
theCP0$RDY_tlbLookupCoprocessors_0_request_put &&
theMem_capPackets$FULL_N ;
// rule RL_memToCap
assign WILL_FIRE_RL_memToCap =
theCapCop_memResponse$FULL_N && theCapCop_capMemInsts$EMPTY_N &&
theCapCop_capState == 3'd2 &&
theCapCop_capWritebackTags$FULL_N &&
theMem_theMemMerge_rsp_fifos_2$EMPTY_N ;
// rule RL_initialize
assign WILL_FIRE_RL_initialize = freeRenameReg$FULL_N && initState ;
// rule RL_theDebug_popTrace
assign WILL_FIRE_RL_theDebug_popTrace =
theDebug_debugConvert$RDY_messages_response_put &&
!theDebug_trace_buf_tailPtr_read__1_EQ_theDebug_ETC___d40 &&
!theDebug_trace_buf_readDelay &&
theDebug_state == 2'd3 &&
!theDebug_bpReport$EMPTY_N ;
// rule RL_theDebug_countIdleCyclesStreamTrace
assign WILL_FIRE_RL_theDebug_countIdleCyclesStreamTrace =
theDebug_debugConvert$RDY_messages_response_put &&
theDebug_state == 2'd3 &&
(theDebug_trace_buf_tailPtr_read__1_EQ_theDebug_ETC___d40 ||
theDebug_trace_buf_readDelay) &&
!theDebug_bpReport$EMPTY_N ;
// rule RL_theDebug_countIdleCyclesExecuteInstruction
assign WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction =
theDebug_debugConvert$RDY_messages_response_put &&
theDebug_curCommand$EMPTY_N &&
theDebug_state == 2'd1 &&
!theDebug_writebacks$EMPTY_N &&
!theDebug_bpReport$EMPTY_N ;
// rule RL_theDebug_reportBreakPoint
assign WILL_FIRE_RL_theDebug_reportBreakPoint =
theDebug_debugConvert$RDY_messages_response_put &&
theDebug_bpReport$EMPTY_N &&
theDebug_state == 2'd0 ;
// rule RL_theDebug_unpipelinedStep
assign WILL_FIRE_RL_theDebug_unpipelinedStep =
theDebug_curCommand$FULL_N && theDebug_unPipeline &&
theDebug_pipeCount == 3'd0 &&
theDebug_state == 2'd0 ;
// rule RL_theDebug_step
assign WILL_FIRE_RL_theDebug_step =
theDebug_curCommand$EMPTY_N &&
theDebug_debugConvert$RDY_messages_response_put &&
theDebug_state == 2'd2 ;
// rule RL_theDebug_finishExecute
assign WILL_FIRE_RL_theDebug_finishExecute =
theDebug_debugConvert$RDY_messages_response_put &&
theDebug_curCommand$EMPTY_N &&
theDebug_writebacks$EMPTY_N &&
theDebug_state == 2'd1 ;
// rule RL_theMem_l2Tomerge
assign WILL_FIRE_RL_theMem_l2Tomerge =
theMem_l2Cache$RDY_cache_response_get &&
theMem_theMemMerge_pendingReqs$EMPTY_N &&
theMem_theMemMerge_rsp_fifos$FULL_N &&
theMem_theMemMerge_rsp_fifos_1$FULL_N &&
theMem_theMemMerge_rsp_fifos_2$FULL_N ;
// rule RL_theMem_submitCapRequest
assign WILL_FIRE_RL_theMem_submitCapRequest =
theMem_capPackets$EMPTY_N && theMem_capTlbResp$EMPTY_N &&
theMem_theMemMerge_req_fifos_2$FULL_N &&
(theMem_commitCapStore$EMPTY_N ||
theMem_capPackets$D_OUT[325:324] != 2'd1) ;
// rule RL_theMem_theMemMerge_mergeInputs
assign WILL_FIRE_RL_theMem_theMemMerge_mergeInputs =
theMem_theMemMerge_pendingReqs$FULL_N &&
theMem_theMemMerge_nextReq$FULL_N ;
// rule RL_theMem_iCache_initialize
assign WILL_FIRE_RL_theMem_iCache_initialize =
theMem_iCache_tags_serverAdapterB_cnt_179_SLT_3___d1325 &&
theMem_iCache_cacheState == 2'd0 ;
// rule RL_theMem_iCache_getMemoryResponse
assign WILL_FIRE_RL_theMem_iCache_getMemoryResponse =
theMem_iCache_req_fifo$EMPTY_N &&
theMem_iCache_out_fifo_ff$FULL_N &&
theMem_theMemMerge_rsp_fifos$EMPTY_N &&
theMem_iCache_bank_serverAdapterB_cnt_293_SLT_3___d1424 &&
theMem_iCache_cacheState == 2'd2 ;
// rule RL_theMem_iCache_updateCache
assign WILL_FIRE_RL_theMem_iCache_updateCache =
theMem_iCache_bank_serverAdapterB_cnt_293_SLT_3___d1424 &&
theMem_iCache_tags_serverAdapterB_cnt_179_SLT_3___d1325 &&
theMem_iCache_cacheState == 2'd3 ;
// rule RL_theMem_iCache_respondDuringUpdate
assign WILL_FIRE_RL_theMem_iCache_respondDuringUpdate =
theCP0$RDY_tlbLookupInstruction_response_get &&
theMem_iCache_req_fifo$EMPTY_N &&
theMem_iCache_tags_serverAdapterA_outDataCore__ETC___d1473 &&
theMem_iCache_cacheState != 2'd2 &&
theMem_iCache_req_fifo_first__341_BITS_127_TO__ETC___d1372 &&
theMem_iCache_req_fifo$D_OUT[138:136] == 3'd3 &&
theMem_iCache_validFillLine ;
// rule RL_theMem_iCache_invalidateEntry
assign WILL_FIRE_RL_theMem_iCache_invalidateEntry =
theMem_iCache_tags_serverAdapterB_cnt_179_SLT_3___d1325 &&
theMem_iCache_cacheState == 2'd1 &&
theMem_iCache_invalidateFifo$EMPTY_N &&
!WILL_FIRE_RL_theMem_iCache_doCacheInstructions &&
!WILL_FIRE_RL_theMem_iCache_doRead ;
// rule RL_theMem_iCache_doCacheInstructions
assign WILL_FIRE_RL_theMem_iCache_doCacheInstructions =
theMem_iCache_req_fifo$EMPTY_N &&
theMem_iCache_tags_serverAdapterB_cnt_179_SLT_3___d1325 &&
theMem_iCache_cacheState == 2'd1 &&
theMem_iCache_req_fifo$D_OUT[138:136] != 3'd3 &&
theMem_iCache_req_fifo$D_OUT[138:136] != 3'd4 &&
!WILL_FIRE_RL_theMem_iCache_doRead ;
// rule RL_theMem_iCache_doRead
assign WILL_FIRE_RL_theMem_iCache_doRead =
theCP0$RDY_tlbLookupInstruction_response_get &&
theMem_iCache_req_fifo$EMPTY_N &&
theMem_iCache_tags_serverAdapterA_outDataCore__ETC___d1366 &&
theMem_iCache_cacheState == 2'd1 &&
(!theMem_iCache_req_fifo_first__341_BITS_127_TO__ETC___d1372 ||
theMem_iCache_req_fifo$D_OUT[138:136] != 3'd3 ||
!theMem_iCache_validFillLine) ;
// rule RL_theMem_iCacheOperation
assign WILL_FIRE_RL_theMem_iCacheOperation =
theMem_iCache_cacheState != 2'd0 &&
theMem_iCache_tags_serverAdapterA_cnt_122_SLT_3___d1914 &&
theMem_iCache_bank_serverAdapterA_cnt_236_SLT_3___d1915 &&
theMem_iCache_req_fifo$FULL_N &&
theMem_iCacheOp$EMPTY_N ;
// rule RL_theMem_iCache_tags_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_theMem_iCache_tags_serverAdapterA_outData_enqAndDeq =
theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N &&
theMem_iCache_tags_serverAdapterA_outDataCore$FULL_N &&
theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas &&
theMem_iCache_tags_serverAdapterA_outData_enqData$whas ;
// rule RL_theMem_iCache_tags_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_theMem_iCache_tags_serverAdapterB_stageReadResponseAlways =
MUX_theMem_iCache_tags_memory$b_put_1__SEL_1 ||
MUX_theMem_iCache_tags_memory$b_put_1__SEL_2 ||
MUX_theMem_iCache_cacheState$write_1__SEL_3 ||
WILL_FIRE_RL_theMem_iCache_initialize ||
WILL_FIRE_RL_theMem_iCache_invalidateEntry ;
// rule RL_theMem_iCache_bank_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_theMem_iCache_bank_serverAdapterA_outData_enqAndDeq =
theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N &&
theMem_iCache_bank_serverAdapterA_outDataCore$FULL_N &&
theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas &&
theMem_iCache_bank_serverAdapterA_outData_enqData$whas ;
// rule RL_theMem_dCache_initialize
assign WILL_FIRE_RL_theMem_dCache_initialize =
theMem_dCache_tags_serverAdapterB_cnt_576_SLT_3___d1722 &&
theMem_dCache_cacheState == 3'd0 ;
// rule RL_theMem_dCache_invalidateEntry
assign CAN_FIRE_RL_theMem_dCache_invalidateEntry =
theMem_dCache_tags_serverAdapterB_cnt_576_SLT_3___d1722 &&
theMem_dCache_req_fifo$EMPTY_N &&
theMem_dCache_cacheState == 3'd1 &&
theMem_dCache_req_fifo$D_OUT[138:136] != 3'd4 &&
theMem_dCache_invalidateFifo$EMPTY_N ;
assign WILL_FIRE_RL_theMem_dCache_invalidateEntry =
CAN_FIRE_RL_theMem_dCache_invalidateEntry &&
!WILL_FIRE_RL_theMem_dCache_doCacheInstructions ;
// rule RL_theMem_dCache_doCacheInstructions
assign WILL_FIRE_RL_theMem_dCache_doCacheInstructions =
theMem_dCache_req_fifo$EMPTY_N &&
theMem_dCache_tags_serverAdapterB_cnt_576_SLT_3___d1722 &&
theMem_dCache_cacheState == 3'd1 &&
theMem_dCache_req_fifo$D_OUT[138:136] != 3'd3 &&
theMem_dCache_req_fifo$D_OUT[138:136] != 3'd4 ;
// rule RL_theMem_dCache_getResponseUncached
assign WILL_FIRE_RL_theMem_dCache_getResponseUncached =
theMem_dCache_req_fifo$EMPTY_N &&
theMem_dCache_out_fifo_ff$FULL_N &&
theMem_theMemMerge_rsp_fifos_1$EMPTY_N &&
theMem_dCache_data_serverAdapterB_cnt_690_SLT_3___d1849 &&
theMem_dCache_tags_fifo$EMPTY_N &&
theMem_dCache_cacheState == 3'd3 ;
// rule RL_theMem_dCache_updateCache
assign WILL_FIRE_RL_theMem_dCache_updateCache =
theMem_dCache_data_serverAdapterB_cnt_690_SLT_3___d1849 &&
theMem_dCache_tags_serverAdapterB_cnt_576_SLT_3___d1722 &&
theMem_dCache_tags_fifo$EMPTY_N &&
theMem_dCache_cacheState == 3'd4 ;
// rule RL_theMem_dCache_checkTags
assign WILL_FIRE_RL_theMem_dCache_checkTags =
theCP0$RDY_tlbLookupData_response_get &&
theMem_dCache_tags_serverAdapterA_outDataCore__ETC___d1773 &&
theMem_dCache_cacheState == 3'd1 &&
theMem_dCache_req_fifo$D_OUT[138:136] == 3'd3 ;
// rule RL_theMem_dCache_wayMiss
assign WILL_FIRE_RL_theMem_dCache_wayMiss =
theMem_dCache_req_fifo_i_notEmpty__730_AND_the_ETC___d1844 &&
theMem_dCache_cacheState == 3'd2 ;
// rule RL_memAccess_doDummy
assign WILL_FIRE_RL_memAccess_doDummy =
memAccess_inQ$EMPTY_N && memAccessToWriteback$FULL_N &&
memAccess_inQ$D_OUT[14:13] == 2'd3 ;
// rule RL_theCapCop_startException
assign WILL_FIRE_RL_theCapCop_startException =
theCapCop_exception$EMPTY_N && theCapCop_fetchFifoA$FULL_N &&
theCapCop_startExp$FULL_N &&
theCapCop_capState == 3'd3 ;
// rule RL_theCapCop_finishException
assign WILL_FIRE_RL_theCapCop_finishException =
theCapCop_exception$EMPTY_N && theCapCop_fetchFifoA$EMPTY_N &&
theCapCop_startExp$EMPTY_N &&
theCapCop_capState == 3'd3 &&
!WILL_FIRE_RL_theCapCop_startException ;
// rule RL_debugInstructionFetch
assign WILL_FIRE_RL_debugInstructionFetch =
!theMem_iCacheOp$EMPTY_N && theMem_iCache_cacheState != 2'd0 &&
!theCapCop_exception$EMPTY_N &&
branch$RDY_getPc &&
theCP0$RDY_tlbLookupInstruction_request_put &&
theMem_iCache_req_fifo_i_notFull__917_AND_theM_ETC___d6580 &&
theDebug_pausePipe ;
// rule RL_writeback_doInstructionReport
assign WILL_FIRE_RL_writeback_doInstructionReport =
writeback_instructionReport$EMPTY_N &&
(!theDebug_trace_buf_tailPtr_read__1_PLUS_1_2_EQ_ETC___d8043 ||
theDebug_state != 2'd3) ;
// rule RL_theDebug_doCommands
assign WILL_FIRE_RL_theDebug_doCommands =
theDebug_debugConvert$RDY_messages_request_get &&
theDebug_debugConvert$RDY_messages_response_put &&
theDebug_instQ$FULL_N &&
theDebug_curCommand$FULL_N &&
theDebug_state == 2'd0 &&
!theDebug_bpReport$EMPTY_N &&
(!theDebug_unPipeline || theDebug_pipeCount != 3'd0) ;
// rule RL_instructionFetch
assign WILL_FIRE_RL_instructionFetch =
NOT_theDebug_bpReport_notEmpty__0_1_AND_NOT_th_ETC___d6504 &&
!theDebug_pausePipe ;
// rule RL_reportExceptionToCapabilityCoprocessor
assign WILL_FIRE_RL_reportExceptionToCapabilityCoprocessor =
writeback_exception$EMPTY_N && theCapCop_exception$FULL_N ;
// rule RL_reportExceptionReturnToCapabilityCoprocessor
assign CAN_FIRE_RL_reportExceptionReturnToCapabilityCoprocessor =
theCP0$RDY_getExceptionReturn && theCapCop_exception$FULL_N ;
// rule RL_registerFetch
assign WILL_FIRE_RL_registerFetch =
theRF_regFileState &&
theMem_iCache_out_fifo_ff_i_notEmpty__092_OR_t_ETC___d6659 &&
!initState ;
// rule RL_execute_doReadReport
assign WILL_FIRE_RL_execute_doReadReport =
!execute_pendingOps$EMPTY_N &&
!execute_loadsDone_248_EQ_execute_loadsIn_249___d3250 &&
!WILL_FIRE_RL_execute_doExecute ;
// rule RL_execute_doExecute
assign WILL_FIRE_RL_execute_doExecute =
theCapCop_nextWillWriteback_i_notEmpty__313_AN_ETC___d3340 &&
(execute_inQ$D_OUT[379:375] != 5'd19 &&
execute_inQ$D_OUT[379:375] != 5'd20 &&
execute_inQ$D_OUT[379:375] != 5'd15 &&
execute_inQ$D_OUT[379:375] != 5'd16 ||
!execute_hiLoPending$EMPTY_N) &&
!execute_pendingOps$EMPTY_N &&
(!execute_inQ$D_OUT[294] && execute_inQ$D_OUT[374:372] != 3'd5 ||
execute_loadsDone_248_EQ_execute_loadsIn_249_M_ETC___d3368) ;
// rule RL_writeback_doWriteBack
assign WILL_FIRE_RL_writeback_doWriteBack =
!theCapCop_capMemInsts$EMPTY_N && theCapCop_capState != 3'd3 &&
theCapCop_capState != 3'd0 &&
NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d2514 &&
(memAccessToWriteback$D_OUT[14:13] == 2'd3 ||
memAccessToWriteback$D_OUT[14:13] == 2'd2) &&
!initState ;
// rule RL_writeback_doWriteBackWithRead
assign WILL_FIRE_RL_writeback_doWriteBackWithRead =
NOT_theCapCop_capMemInsts_i_notEmpty__482_483__ETC___d2762 &&
memAccessToWriteback$D_OUT[14:13] == 2'd0 &&
!initState ;
// rule RL_writeback_doWriteBackWithWrite
assign WILL_FIRE_RL_writeback_doWriteBackWithWrite =
!theCapCop_capMemInsts$EMPTY_N && theCapCop_capState != 3'd3 &&
theCapCop_capState != 3'd0 &&
theMem_dCache_req_fifo$EMPTY_N &&
theMem_dCache_cacheState == 3'd1 &&
theMem_dCache_req_fifo$D_OUT[138:136] == 3'd4 &&
NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d3004 &&
memAccessToWriteback$D_OUT[14:13] == 2'd1 &&
!initState ;
// rule RL_freeRenameReg_reset
assign WILL_FIRE_RL_freeRenameReg_reset =
freeRenameReg_r_enq$whas || WILL_FIRE_RL_registerFetch ;
// rule RL_theMem_dCache_tags_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_outData_enqAndDeq =
theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N &&
theMem_dCache_tags_serverAdapterA_outDataCore$FULL_N &&
theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas &&
theMem_dCache_tags_serverAdapterA_outData_enqData$whas ;
// rule RL_theMem_dCache_tags_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_theMem_dCache_tags_serverAdapterB_stageReadResponseAlways =
MUX_theMem_dCache_tags_memory$b_put_1__SEL_1 ||
MUX_theMem_dCache_tags_memory$b_put_1__SEL_2 ||
MUX_theMem_dCache_cacheState$write_1__SEL_3 ||
WILL_FIRE_RL_theMem_dCache_initialize ||
WILL_FIRE_RL_theMem_dCache_invalidateEntry ;
// rule RL_theMem_dCache_data_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_theMem_dCache_data_serverAdapterA_outData_enqAndDeq =
theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N &&
theMem_dCache_data_serverAdapterA_outDataCore$FULL_N &&
theMem_dCache_data_serverAdapterA_outData_deqCalled$whas &&
theMem_dCache_data_serverAdapterA_outData_enqData$whas ;
// rule RL_memAccess_doMemAccess
assign CAN_FIRE_RL_memAccess_doMemAccess =
memAccess_inQ$EMPTY_N && memAccessToWriteback$FULL_N &&
theMem_dataByte$FULL_N &&
theMem_dataSize$FULL_N &&
theMem_dCache_cacheState_read__723_EQ_1_732_AN_ETC___d2049 &&
theMem_iCacheOp$FULL_N &&
memAccess_inQ$D_OUT[14:13] != 2'd3 ;
assign WILL_FIRE_RL_memAccess_doMemAccess =
CAN_FIRE_RL_memAccess_doMemAccess &&
!WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
!WILL_FIRE_RL_theMem_dCache_checkTags ;
// rule RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways
assign WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways =
WILL_FIRE_RL_memAccess_doMemAccess &&
(memAccess_inQ$D_OUT[14:13] == 2'd0 ||
memAccess_inQ$D_OUT[14:13] == 2'd1 &&
CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197 &&
(memAccess_inQ$D_OUT[374:372] != 3'd5 ||
memAccess_inQ$D_OUT[166]) ||
memAccess_inQ$D_OUT[14:13] == 2'd2 &&
memAccess_inQ$D_OUT[3:2] == 2'd1 &&
(memAccess_inQ$D_OUT[6:4] == 3'd3 ||
memAccess_inQ$D_OUT[6:4] == 3'd4)) ;
// rule RL_execute_finishMultiplyOrDivide
assign WILL_FIRE_RL_execute_finishMultiplyOrDivide =
execute_mul$RDY_muldiv_response_get &&
writeback_hiLoCommit$EMPTY_N &&
execute_hiLoPending$EMPTY_N ;
// rule RL_execute_deliverPendingOp
assign WILL_FIRE_RL_execute_deliverPendingOp =
execute_mul$RDY_muldiv_response_get &&
execute_hiLoPending$EMPTY_N &&
execute_pendingOps$EMPTY_N &&
memAccess_inQ$FULL_N ;
// inputs to muxes for submodule ports
assign MUX_execute_renameRegsVector$write_1__SEL_1 =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd0 ;
assign MUX_execute_renameRegsVector_1$write_1__SEL_1 =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd1 ;
assign MUX_execute_renameRegsVector_2$write_1__SEL_1 =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd2 ;
assign MUX_execute_renameRegsVector_3$write_1__SEL_1 =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd3 ;
assign MUX_freeRenameReg$enq_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite ||
WILL_FIRE_RL_writeback_doWriteBackWithRead ||
WILL_FIRE_RL_writeback_doWriteBack ;
assign MUX_memAccess_inQ$enq_1__SEL_1 =
WILL_FIRE_RL_execute_doExecute &&
(execute_inQ$D_OUT[379:375] != 5'd14 ||
execute_inQ$D_OUT[400:397] != 4'd9 ||
execute_inQ$D_OUT[14:13] != 2'd3) ;
assign MUX_theCP0$writeReg_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback$D_OUT[383:382] == 2'd1 ;
assign MUX_theCP0$writeReg_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback$D_OUT[383:382] == 2'd1 ;
assign MUX_theCP0$writeReg_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback$D_OUT[383:382] == 2'd1 ;
assign MUX_theCapCop_baseRegs$upd_1__SEL_1 =
WILL_FIRE_RL_theCapCop_startException &&
!theCapCop_exception$D_OUT ;
assign MUX_theCapCop_baseRegs$upd_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2714 ;
assign MUX_theCapCop_baseRegs$upd_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2980 ;
assign MUX_theCapCop_baseRegs$upd_1__SEL_4 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d3191 ;
assign MUX_theCapCop_capState$write_1__SEL_1 =
theCapCop_capState == 3'd5 && theCapCop_exception$EMPTY_N &&
!theCapCop_insts$EMPTY_N ;
assign MUX_theCapCop_capState$write_1__SEL_3 =
theCapCop_capState == 3'd0 && theCapCop_count == 5'd31 ;
assign MUX_theCapCop_capState$write_1__SEL_6 =
WILL_FIRE_RL_doDecode &&
(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd9 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd10) ;
assign MUX_theCapCop_capWriteback$write_1__SEL_1 =
WILL_FIRE_RL_execute_doExecute &&
(theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d9255 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3600) ;
assign MUX_theCapCop_capWritebackTags$enq_1__SEL_1 =
WILL_FIRE_RL_execute_doExecute &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 ;
assign MUX_theCapCop_exception$enq_1__SEL_2 =
CAN_FIRE_RL_reportExceptionReturnToCapabilityCoprocessor &&
!WILL_FIRE_RL_reportExceptionToCapabilityCoprocessor ;
assign MUX_theCapCop_pcc$write_1__SEL_1 =
WILL_FIRE_RL_execute_doExecute &&
(theCapCop_capInsts$D_OUT[99:95] == 5'd7 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd8) ;
assign MUX_theCapCop_writesCalculated$write_1__SEL_1 =
WILL_FIRE_RL_execute_doExecute &&
(theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548) ;
assign MUX_theDebug_curCommand$enq_1__SEL_1 =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd115) ;
assign MUX_theDebug_debugConvert$messages_response_put_1__SEL_1 =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd101 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd115 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd83 ;
assign MUX_theDebug_debugConvert$messages_response_put_1__SEL_2 =
WILL_FIRE_RL_theDebug_countIdleCyclesStreamTrace &&
theDebug_idleCount == 28'h000007F ;
assign MUX_theDebug_debugConvert$messages_response_put_1__SEL_3 =
WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction &&
theDebug_idleCount == 28'h000007F ;
assign MUX_theDebug_debugConvert$messages_response_put_1__SEL_4 =
WILL_FIRE_RL_theDebug_step &&
theDebug_curCommand$D_OUT[271:264] != 8'd0 ;
assign MUX_theDebug_dest$write_1__SEL_1 =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd99 ;
assign MUX_theDebug_mipsPC$write_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBack &&
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d2637 ;
assign MUX_theDebug_mipsPC$write_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d2819 ;
assign MUX_theDebug_mipsPC$write_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d3143 ;
assign MUX_theDebug_pausePipe$write_1__SEL_1 =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd112 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd114 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd117 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd115 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd83) ;
assign MUX_theDebug_pausePipe$write_1__SEL_6 =
WILL_FIRE_RL_theDebug_popTrace &&
theDebug_trace_buf_tailPtr_read__1_PLUS_1_2_EQ_ETC___d8043 ;
assign MUX_theDebug_state$write_1__SEL_1 =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd115 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd83) ;
assign MUX_theDebug_state$write_1__PSEL_2 =
WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction ||
WILL_FIRE_RL_theDebug_countIdleCyclesStreamTrace ;
assign MUX_theDebug_state$write_1__SEL_2 =
MUX_theDebug_state$write_1__PSEL_2 &&
theDebug_idleCount == 28'h000007F ;
assign MUX_theDebug_state$write_1__SEL_3 =
WILL_FIRE_RL_theDebug_finishExecute ||
WILL_FIRE_RL_theDebug_step ;
assign MUX_theDebug_unPipeline$write_1__SEL_1 =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd112 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd114 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd117 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd83) ;
assign MUX_theDebug_writebacks$enq_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback$D_OUT[1] ;
assign MUX_theDebug_writebacks$enq_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback$D_OUT[1] ;
assign MUX_theDebug_writebacks$enq_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback$D_OUT[1] ;
assign MUX_theMem_dCache_cacheState$write_1__SEL_1 =
WILL_FIRE_RL_theMem_dCache_initialize &&
theMem_dCache_count == 7'd127 ;
assign MUX_theMem_dCache_cacheState$write_1__SEL_2 =
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ||
NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d1818) ;
assign MUX_theMem_dCache_cacheState$write_1__SEL_3 =
WILL_FIRE_RL_theMem_dCache_updateCache &&
theMem_dCache_fillCount == 2'b11 ;
assign MUX_theMem_dCache_data_memory$a_put_1__SEL_1 =
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 &&
!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ;
assign MUX_theMem_dCache_data_memory$b_put_1__SEL_1 =
WILL_FIRE_RL_theMem_dCache_getResponseUncached &&
theMem_dCache_missCached ;
assign MUX_theMem_dCache_data_memory$b_put_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d3016 ;
assign MUX_theMem_dCache_out_fifo_enqw$wset_1__SEL_1 =
WILL_FIRE_RL_theMem_dCache_checkTags &&
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 &&
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ||
theCP0$tlbLookupData_response_get[13:9] != 5'd25) ;
assign MUX_theMem_dCache_tags_memory$b_put_1__SEL_1 =
WILL_FIRE_RL_theMem_dCache_doCacheInstructions &&
(theMem_dCache_req_fifo$D_OUT[138:136] == 3'd1 ||
theMem_dCache_req_fifo$D_OUT[138:136] == 3'd0) ;
assign MUX_theMem_dCache_tags_memory$b_put_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
NOT_theCP0_tlbLookupData_response_get_777_BIT__ETC___d3092 ;
assign MUX_theMem_dCache_wayTable$upd_1__SEL_1 =
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0_tlbLookupData_response_get_777_BITS_13__ETC___d1813 ;
assign MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 =
WILL_FIRE_RL_theMem_iCacheOperation &&
(theMem_iCacheOp$D_OUT[138:136] == 3'd3 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd4) ;
assign MUX_theMem_iCache_bank_memory$b_put_1__SEL_1 =
WILL_FIRE_RL_theMem_iCache_getMemoryResponse &&
theMem_iCache_missCached ;
assign MUX_theMem_iCache_bank_serverAdapterA_writeWithResp$wset_1__SEL_2 =
WILL_FIRE_RL_debugInstructionFetch ||
WILL_FIRE_RL_instructionFetch ;
assign MUX_theMem_iCache_cacheState$write_1__SEL_1 =
WILL_FIRE_RL_theMem_iCache_initialize &&
theMem_iCache_count == 9'd511 ;
assign MUX_theMem_iCache_cacheState$write_1__SEL_2 =
WILL_FIRE_RL_theMem_iCache_doRead &&
theCP0$tlbLookupInstruction_response_get[13:9] == 5'd25 &&
(!theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384 ||
!theMem_iCache_tags_serverAdapterA_outData_outData$wget[0] ||
!theCP0$tlbLookupInstruction_response_get[6]) ;
assign MUX_theMem_iCache_cacheState$write_1__SEL_3 =
WILL_FIRE_RL_theMem_iCache_updateCache &&
theMem_iCache_fillCount == 2'b11 ;
assign MUX_theMem_iCache_out_fifo_enqw$wset_1__SEL_1 =
WILL_FIRE_RL_theMem_iCache_doRead &&
(theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384 &&
theMem_iCache_tags_serverAdapterA_outData_outData$wget[0] &&
theCP0$tlbLookupInstruction_response_get[6] ||
theCP0$tlbLookupInstruction_response_get[13:9] != 5'd25) ;
assign MUX_theMem_iCache_req_fifo$enq_1__SEL_1 =
WILL_FIRE_RL_theMem_iCacheOperation &&
(theMem_iCacheOp$D_OUT[138:136] == 3'd3 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd4 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd1 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd0 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd2) ;
assign MUX_theMem_iCache_tags_memory$b_put_1__SEL_1 =
WILL_FIRE_RL_theMem_iCache_doCacheInstructions &&
(theMem_iCache_req_fifo$D_OUT[138:136] == 3'd1 ||
theMem_iCache_req_fifo$D_OUT[138:136] == 3'd0) ;
assign MUX_theMem_iCache_tags_memory$b_put_1__SEL_2 =
WILL_FIRE_RL_theMem_iCache_doRead &&
theCP0$tlbLookupInstruction_response_get[13:9] == 5'd25 &&
theCP0$tlbLookupInstruction_response_get[6] &&
(!theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384 ||
!theMem_iCache_tags_serverAdapterA_outData_outData$wget[0]) ;
assign MUX_theMem_theMemMerge_req_fifos_1$enq_1__SEL_1 =
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d1818 ;
assign MUX_theRF_regFile$upd_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBack &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2655 ;
assign MUX_theRF_regFile$upd_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2824 ;
assign MUX_theRF_regFile$upd_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d3148 ;
assign MUX_writeback_exception$enq_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBack &&
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ;
assign MUX_writeback_exception$enq_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ;
assign MUX_writeback_exception$enq_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ;
assign MUX_writeback_hiLoCommit$enq_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback$D_OUT[383:382] == 2'd2 ;
assign MUX_writeback_hiLoCommit$enq_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback$D_OUT[383:382] == 2'd2 ;
assign MUX_writeback_hiLoCommit$enq_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback$D_OUT[383:382] == 2'd2 ;
assign MUX_writeback_instCount$write_1__SEL_1 =
WILL_FIRE_RL_writeback_doWriteBack &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25 ;
assign MUX_writeback_instCount$write_1__SEL_2 =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25 ;
assign MUX_writeback_instCount$write_1__SEL_3 =
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25 ;
assign MUX_branch$pcWriteback_1__VAL_1 =
{ branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
(memAccessToWriteback$D_OUT[15] ||
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 !=
5'd25),
IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9217 } ;
assign MUX_branch$pcWriteback_1__VAL_2 =
{ branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
(memAccessToWriteback$D_OUT[15] ||
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 !=
5'd25),
IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9218 } ;
assign MUX_branch$pcWriteback_1__VAL_3 =
{ branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
(memAccessToWriteback$D_OUT[15] ||
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 !=
5'd25),
IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9219 } ;
assign MUX_branch$pcWriteback_2__VAL_1 =
(IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868 !=
5'd25 ||
memAccessToWriteback$D_OUT[0]) &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] ;
assign MUX_branch$pcWriteback_2__VAL_2 =
(IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875 !=
5'd25 ||
memAccessToWriteback$D_OUT[0]) &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] ;
assign MUX_branch$pcWriteback_2__VAL_3 =
(IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876 !=
5'd25 ||
memAccessToWriteback$D_OUT[0]) &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] ;
assign MUX_execute_renameRegsVector$write_1__VAL_1 =
{ 1'd1, execute_mul$muldiv_response_get[63:0] } ;
assign MUX_execute_renameRegsVector$write_1__VAL_2 =
{ IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 } ;
assign MUX_execute_renameRegsVector$write_1__VAL_3 =
{ IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4716,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q168 } ;
assign MUX_execute_renameRegsVector_1$write_1__VAL_2 =
{ IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 } ;
assign MUX_execute_renameRegsVector_1$write_1__VAL_3 =
{ IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4762,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q167 } ;
assign MUX_execute_renameRegsVector_2$write_1__VAL_2 =
{ IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 } ;
assign MUX_execute_renameRegsVector_2$write_1__VAL_3 =
{ IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4808,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q169 } ;
assign MUX_execute_renameRegsVector_3$write_1__VAL_2 =
{ IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045,
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 } ;
assign MUX_execute_renameRegsVector_3$write_1__VAL_3 =
{ IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4854,
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q170 } ;
assign MUX_fetchedControlToken$enq_1__VAL_1 =
{ nextId,
branch$getPc[2:0],
nextId[1:0],
42'h2AAAAAAAA48,
theDebug_bp_read__508_BIT_64_509_AND_theDebug__ETC___d7846,
21'b001010000111000000110,
branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b0_5_ETC___d8037 ?
5'd25 :
5'd22,
265'h0554554554554554554000000000000000000000000000000000000000000000000,
branch$getPc[66:3],
37'd553372,
theDebug_bp_read__508_BIT_64_509_AND_theDebug__ETC___d7846 } ;
assign MUX_fetchedControlToken$enq_1__VAL_2 =
{ nextId,
branch$getPc[2:0],
nextId[1:0],
(theDebug_instQ$D_OUT[31:26] != 6'd0 &&
theDebug_instQ$D_OUT[31:26] != 6'd28 &&
theDebug_instQ$D_OUT[31:26] != 6'd16 &&
theDebug_instQ$D_OUT[31:26] != 6'd17 &&
theDebug_instQ$D_OUT[31:26] != 6'd18 &&
theDebug_instQ$D_OUT[31:26] != 6'd19 &&
theDebug_instQ$D_OUT[31:26] != 6'd2 &&
theDebug_instQ$D_OUT[31:26] != 6'd3 &&
theDebug_instQ$D_OUT[31:26] != 6'd29) ?
2'd0 :
((theDebug_instQ$D_OUT[31:26] == 6'd2 ||
theDebug_instQ$D_OUT[31:26] == 6'd3 ||
theDebug_instQ$D_OUT[31:26] == 6'd29) ?
2'd1 :
CASE_theDebug_instQD_OUT_BITS_31_TO_26_3_0_2__ETC__q171),
theDebug_instQ$D_OUT,
402'h12050E06C9551551551551551550000000000000000000000000000000000000000000000000000000000000000000010633A } ;
assign MUX_memAccessToWriteback$enq_1__VAL_1 =
{ memAccess_inQ$D_OUT[444:436],
IF_memAccess_inQ_first__055_BITS_435_TO_434_25_ETC___d8942,
memAccess_inQ$D_OUT[433:402],
memAccess_inQ_first__055_BITS_401_TO_372_264_C_ETC___d2288 } ;
assign MUX_memAccessToWriteback$enq_1__VAL_2 =
{ memAccess_inQ$D_OUT[444:436],
IF_memAccess_inQ_first__055_BITS_435_TO_434_25_ETC___d8942,
memAccess_inQ$D_OUT[433:0] } ;
assign MUX_memAccess_inQ$enq_1__VAL_1 =
{ execute_inQ$D_OUT[444:436],
IF_execute_inQ_first__341_BITS_435_TO_434_699__ETC___d7888,
(execute_inQ$D_OUT[14:13] == 2'd3) ?
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4563 :
execute_inQ_first__341_BITS_401_TO_372_564_CON_ETC___d4659 } ;
assign MUX_memAccess_inQ$enq_1__VAL_2 =
{ execute_pendingOps$D_OUT[444:436],
CASE_execute_pendingOpsD_OUT_BITS_435_TO_434__ETC__q172,
execute_pendingOps$D_OUT[433:294],
x__h198817,
execute_pendingOps$D_OUT[229:0] } ;
assign MUX_theCP0$putException_1__VAL_1 =
{ IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868,
x__h171528,
IF_IF_IF_IF_memAccessToWriteback_first__516_BI_ETC___d7578,
memAccessToWriteback$D_OUT[401],
memAccessToWriteback$D_OUT[444:441],
!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393] } ;
assign MUX_theCP0$putException_1__VAL_2 =
{ IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875,
x__h176020,
IF_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_ETC___d7579,
memAccessToWriteback$D_OUT[401],
memAccessToWriteback$D_OUT[444:441],
!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393] } ;
assign MUX_theCP0$putException_1__VAL_3 =
{ IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876,
x__h193939,
IF_IF_IF_IF_NOT_theCP0_tlbLookupData_response__ETC___d7584,
memAccessToWriteback$D_OUT[401],
memAccessToWriteback$D_OUT[444:441],
!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393] } ;
assign MUX_theCP0$tlbLookupInstruction_request_put_1__VAL_1 =
{ put_addr__h272334, 7'd25, nextId } ;
assign MUX_theCP0$tlbLookupInstruction_request_put_1__VAL_2 =
{ put_addr__h273845, 7'd25, nextId } ;
assign MUX_theCP0$writeReg_4__VAL_1 =
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25 ;
assign MUX_theCP0$writeReg_4__VAL_2 =
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25 ;
assign MUX_theCP0$writeReg_4__VAL_3 =
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25 ;
assign MUX_theCapCop_capState$write_1__VAL_5 =
(theCapCop_capMemInsts$D_OUT[337:333] == 5'd10) ? 3'd2 : 3'd5 ;
assign MUX_theCapCop_capWriteback$write_1__VAL_1 =
{ theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548,
IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d3685 } ;
assign MUX_theCapCop_capWriteback$write_1__VAL_2 =
{ (theCapCop_pcc[244] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd28) &&
(theCapCop_pcc[243] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd29) &&
(theCapCop_pcc[242] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd30) &&
(theCapCop_pcc[241] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd31),
theMem_theMemMerge_rsp_fifos_2$D_OUT[7:0],
theMem_theMemMerge_rsp_fifos_2$D_OUT[15:8],
y_avValue_reserved__h259503,
x__h266100,
x__h266104,
theMem_theMemMerge_rsp_fifos_2$D_OUT[199:192],
theMem_theMemMerge_rsp_fifos_2$D_OUT[207:200],
theMem_theMemMerge_rsp_fifos_2$D_OUT[215:208],
theMem_theMemMerge_rsp_fifos_2$D_OUT[223:216],
theMem_theMemMerge_rsp_fifos_2$D_OUT[231:224],
theMem_theMemMerge_rsp_fifos_2$D_OUT[239:232],
theMem_theMemMerge_rsp_fifos_2$D_OUT[247:240],
theMem_theMemMerge_rsp_fifos_2$D_OUT[255:248],
theCapCop_capMemInsts$D_OUT[11:0] } ;
assign MUX_theCapCop_capWritebackTags$enq_1__VAL_1 =
{ theCapCop_capInsts$D_OUT[99:95],
theCapCop_capInsts$D_OUT[16:10],
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d9255 } ;
assign MUX_theCapCop_capWritebackTags$enq_1__VAL_2 =
{ theCapCop_capMemInsts$D_OUT[337:333],
theCapCop_capMemInsts$D_OUT[6:0],
(theCapCop_pcc[244] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd28) &&
(theCapCop_pcc[243] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd29) &&
(theCapCop_pcc[242] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd30) &&
(theCapCop_pcc[241] ||
theCapCop_capMemInsts$D_OUT[11:7] != 5'd31) } ;
assign MUX_theCapCop_fetchFifoA$enq_1__VAL_1 =
theCapCop_exception$D_OUT ? 5'd31 : 5'd29 ;
assign MUX_theCapCop_fetchFifoA$enq_1__VAL_2 =
(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd0 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd16 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd17 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd18 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd19 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd20 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd21 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd22 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd23 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd4 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd24 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd25 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd26 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd27 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd28 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd29 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd30 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd31 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd7 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd8 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd1 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd9 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd10 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd11) ?
5'd0 :
IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d7595 ;
assign MUX_theCapCop_pcc$write_1__VAL_2 =
{ theCapCop_permRegs$D_OUT_1,
theCapCop_oTypeRegs$D_OUT_1,
theCapCop_baseRegs$D_OUT_2,
theCapCop_lengthRegs$D_OUT_2 } ;
assign MUX_theCapCop_writesCalculated$write_1__VAL_1 =
theCapCop_writesCalculated + 5'd1 ;
assign MUX_theDebug_curCommand$enq_1__VAL_1 =
{ CASE_theDebug_debugConvertmessages_request_ge_ETC__q173,
theDebug_debugConvert$messages_request_get[263:0] } ;
always@(theDebug_debugConvert$messages_request_get or
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 or
theDebug_dest or theDebug_pausePipe or theDebug_unPipeline)
begin
case (theDebug_debugConvert$messages_request_get[271:264])
8'd48, 8'd49, 8'd50, 8'd51, 8'd97, 8'd98, 8'd105:
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 =
((theDebug_debugConvert$messages_request_get[271:264] ==
8'd105) ?
theDebug_debugConvert$messages_request_get[263:256] == 8'd4 :
theDebug_debugConvert$messages_request_get[263:256] ==
8'd8) ?
{ IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852,
264'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
272'h2000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
8'd67, 8'd77:
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 =
(theDebug_debugConvert$messages_request_get[263:256] == 8'd32) ?
{ IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852,
264'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
272'h2000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
8'd99, 8'd114:
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 =
{ IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852,
264'd0 };
8'd100:
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 =
{ IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852,
8'h08,
theDebug_debugConvert$messages_request_get[255:64],
theDebug_dest[7:0],
theDebug_dest[15:8],
theDebug_dest[23:16],
theDebug_dest[31:24],
theDebug_dest[39:32],
theDebug_dest[47:40],
theDebug_dest[55:48],
theDebug_dest[63:56] };
8'd112:
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 =
{ IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852,
207'h0080000000000000000000000000000000000000000000000000,
theDebug_pausePipe,
56'd0 };
8'd117:
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 =
{ IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852,
207'h0080000000000000000000000000000000000000000000000000,
theDebug_unPipeline,
56'd0 };
default: MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 =
272'h20000000000000000000000000000000000000000000000000000000000000000000;
endcase
end
assign MUX_theDebug_debugConvert$messages_response_put_1__VAL_4 =
{ CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174,
264'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_theDebug_debugConvert$messages_response_put_1__VAL_5 =
{ 16'd62496,
theDebug_trace_buf_bram$DOB[255:251],
CASE_theDebug_trace_buf_bramDOB_BITS_250_TO_2_ETC__q175,
theDebug_trace_buf_bram$DOB[245:0] } ;
assign MUX_theDebug_debugConvert$messages_response_put_1__VAL_6 =
{ CASE_theDebug_bpReportD_OUT_BITS_271_TO_264_3_ETC__q176,
theDebug_bpReport$D_OUT[263:0] } ;
assign MUX_theDebug_debugConvert$messages_response_put_1__VAL_7 =
{ CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178,
CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_0x0_ETC__q179,
251'h555555555555555555555555555555555555555555555555555555555555550,
x__h102125 } ;
assign MUX_theDebug_idleCount$write_1__VAL_1 = theDebug_idleCount + 28'd1 ;
assign MUX_theDebug_pausePipe$write_1__VAL_1 =
theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd112 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd117 ;
always@(theDebug_debugConvert$messages_request_get or theDebug_pausePipe)
begin
case (theDebug_debugConvert$messages_request_get[271:264])
8'd101: MUX_theDebug_state$write_1__VAL_1 = 2'd1;
8'd115:
MUX_theDebug_state$write_1__VAL_1 =
theDebug_pausePipe ? 2'd2 : 2'd0;
default: MUX_theDebug_state$write_1__VAL_1 = 2'd3;
endcase
end
assign MUX_theDebug_writebacks$enq_1__VAL_1 =
{ memAccessToWriteback_first__516_BITS_391_TO_38_ETC___d9252,
CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 } ;
assign MUX_theDebug_writebacks$enq_1__VAL_2 =
{ memAccessToWriteback$D_OUT[391:387] == 5'd0,
result__h176159,
CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 } ;
assign MUX_theDebug_writebacks$enq_1__VAL_3 =
{ memAccessToWriteback_first__516_BITS_391_TO_38_ETC___d9252,
CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 } ;
assign MUX_theMem_dCache_cacheState$write_1__VAL_2 =
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 ?
3'd2 :
3'd3 ;
assign MUX_theMem_dCache_cacheState$write_1__VAL_4 =
theMem_dCache_missCached ? 3'd4 : 3'd1 ;
assign MUX_theMem_dCache_data_memory$a_put_2__VAL_1 =
{ theMem_dCache_req_fifo$D_OUT[75:67],
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25] } ;
assign MUX_theMem_dCache_data_memory$a_put_2__VAL_2 =
{ memAccess_inQ$D_OUT[241:233],
theMem_dCache_wayTable$D_OUT_1 } ;
assign MUX_theMem_dCache_data_memory$b_put_2__VAL_1 =
{ theMem_dCache_addrReg[11:5],
2'd0,
~theMem_dCache_recentlyUsedWay } ;
assign MUX_theMem_dCache_data_memory$b_put_2__VAL_3 =
{ theMem_dCache_addrReg[11:5],
theMem_dCache_fillCount,
~theMem_dCache_recentlyUsedWay } ;
always@(theMem_dCache_fillCount or theMem_dCache_updateReg)
begin
case (theMem_dCache_fillCount)
2'b0:
MUX_theMem_dCache_data_memory$b_put_3__VAL_3 =
theMem_dCache_updateReg[63:0];
2'b01:
MUX_theMem_dCache_data_memory$b_put_3__VAL_3 =
theMem_dCache_updateReg[127:64];
2'b10:
MUX_theMem_dCache_data_memory$b_put_3__VAL_3 =
theMem_dCache_updateReg[191:128];
2'd3:
MUX_theMem_dCache_data_memory$b_put_3__VAL_3 =
theMem_dCache_updateReg[255:192];
endcase
end
assign MUX_theMem_dCache_fillCount$write_1__VAL_2 =
theMem_dCache_fillCount + 2'd1 ;
assign MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_1 =
{ theCP0$tlbLookupData_response_get[13:9],
(theCP0$tlbLookupData_response_get[13:9] == 5'd25) ?
v__h188873 :
64'b0 } ;
assign MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_2 =
{ 5'd25, v__h188873 } ;
assign MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_3 =
{ 5'd25, resp_data__h129680 } ;
assign MUX_theMem_dCache_tags_memory$b_put_3__VAL_2 =
{ theMem_dCache_tags_serverAdapterA_outData_outData$wget[49:26],
!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25],
theMem_dCache_tags_serverAdapterA_outData_outData$wget[24:1],
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25] &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[0] } ;
assign MUX_theMem_dCache_tags_memory$b_put_3__VAL_3 =
{ (~theMem_dCache_recentlyUsedWay) ?
theMem_dCache_addrReg[35:12] :
theMem_dCache_tags_fifo$D_OUT[49:26],
~theMem_dCache_recentlyUsedWay ||
theMem_dCache_tags_fifo$D_OUT[25],
(~theMem_dCache_recentlyUsedWay) ?
theMem_dCache_tags_fifo$D_OUT[24:1] :
theMem_dCache_addrReg[35:12],
!(~theMem_dCache_recentlyUsedWay) ||
theMem_dCache_tags_fifo$D_OUT[0] } ;
assign MUX_theMem_dCache_wayTable$upd_2__VAL_1 =
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 ?
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25] :
x__h129418 ;
assign MUX_theMem_dCache_wayTable$upd_2__VAL_2 =
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25] ;
assign MUX_theMem_iCache_bank_memory$b_put_2__VAL_1 =
{ theMem_iCache_virAddrReg[13:5], 2'd0 } ;
assign MUX_theMem_iCache_bank_memory$b_put_2__VAL_2 =
{ theMem_iCache_virAddrReg[13:5], theMem_iCache_fillCount } ;
always@(theMem_iCache_fillCount or theMem_iCache_updateReg)
begin
case (theMem_iCache_fillCount)
2'b0:
MUX_theMem_iCache_bank_memory$b_put_3__VAL_2 =
theMem_iCache_updateReg[63:0];
2'b01:
MUX_theMem_iCache_bank_memory$b_put_3__VAL_2 =
theMem_iCache_updateReg[127:64];
2'b10:
MUX_theMem_iCache_bank_memory$b_put_3__VAL_2 =
theMem_iCache_updateReg[191:128];
2'd3:
MUX_theMem_iCache_bank_memory$b_put_3__VAL_2 =
theMem_iCache_updateReg[255:192];
endcase
end
assign MUX_theMem_iCache_cacheState$write_1__VAL_4 =
theMem_iCache_missCached ? 2'd3 : 2'd1 ;
assign MUX_theMem_iCache_fillCount$write_1__VAL_2 =
theMem_iCache_fillCount + 2'd1 ;
assign MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_1 =
{ theCP0$tlbLookupInstruction_response_get[13:9],
(theCP0$tlbLookupInstruction_response_get[13:9] == 5'd25) ?
v__h112420 :
64'b0 } ;
assign MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_2 =
{ 5'd25, resp_data__h113930 } ;
assign MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_3 =
{ theCP0$tlbLookupInstruction_response_get[13:9],
x_data__h115034 } ;
assign MUX_theMem_iCache_req_fifo$enq_1__VAL_2 =
{ 11'd1023, put_addr__h272334, 64'hAAAAAAAAAAAAAAAA } ;
assign MUX_theMem_iCache_req_fifo$enq_1__VAL_3 =
{ 11'd1023, put_addr__h273845, 64'hAAAAAAAAAAAAAAAA } ;
assign MUX_theMem_iCache_tags_memory$b_put_3__VAL_3 =
{ theMem_iCache_phyAddrReg[35:12], 1'd1 } ;
assign MUX_theMem_theMemMerge_req_fifos_1$enq_1__VAL_1 =
{ 1'd0,
theCP0$tlbLookupData_response_get[45:19],
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
theCP0$tlbLookupData_response_get[6] ?
33'h1FFFFFFFF :
{ req_byteenable__h129049, 1'd0 } } ;
assign MUX_theMem_theMemMerge_req_fifos_1$enq_1__VAL_2 =
{ 1'd1,
theCP0$tlbLookupData_response_get[45:19],
IF_theCP0_tlbLookupData_response_get_777_BITS__ETC___d3085,
req_byteenable__h129049,
theCP0$tlbLookupData_response_get[6] } ;
assign MUX_writeback_instCount$write_1__VAL_1 =
writeback_instCount + 64'd1 ;
assign MUX_writeback_instructionReport$enq_1__VAL_1 =
{ memAccessToWriteback$D_OUT[444:436],
IF_memAccessToWriteback_first__516_BITS_435_TO_ETC___d7874,
memAccessToWriteback$D_OUT[401:394],
!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393],
memAccessToWriteback$D_OUT[392:372],
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712,
memAccessToWriteback$D_OUT[366:0],
memAccessToWriteback$D_OUT[293:230] } ;
assign MUX_writeback_instructionReport$enq_1__VAL_2 =
{ memAccessToWriteback$D_OUT[444:436],
IF_memAccessToWriteback_first__516_BITS_435_TO_ETC___d7874,
memAccessToWriteback$D_OUT[401:394],
!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393],
memAccessToWriteback$D_OUT[392:372],
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721,
memAccessToWriteback$D_OUT[366:0],
result__h176159 } ;
assign MUX_writeback_instructionReport$enq_1__VAL_3 =
{ memAccessToWriteback$D_OUT[444:436],
IF_memAccessToWriteback_first__516_BITS_435_TO_ETC___d7874,
memAccessToWriteback$D_OUT[401:394],
!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393],
memAccessToWriteback$D_OUT[392:372],
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733,
memAccessToWriteback$D_OUT[366:0],
memAccessToWriteback$D_OUT[293:230] } ;
// inlined wires
always@(MUX_theMem_iCache_out_fifo_enqw$wset_1__SEL_1 or
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_1 or
WILL_FIRE_RL_theMem_iCache_getMemoryResponse or
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_2 or
WILL_FIRE_RL_theMem_iCache_respondDuringUpdate or
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_iCache_out_fifo_enqw$wset_1__SEL_1:
theMem_iCache_out_fifo_enqw$wget =
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_1;
WILL_FIRE_RL_theMem_iCache_getMemoryResponse:
theMem_iCache_out_fifo_enqw$wget =
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_2;
WILL_FIRE_RL_theMem_iCache_respondDuringUpdate:
theMem_iCache_out_fifo_enqw$wget =
MUX_theMem_iCache_out_fifo_enqw$wset_1__VAL_3;
default: theMem_iCache_out_fifo_enqw$wget =
69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theMem_iCache_out_fifo_enqw$whas =
MUX_theMem_iCache_out_fifo_enqw$wset_1__SEL_1 ||
WILL_FIRE_RL_theMem_iCache_getMemoryResponse ||
WILL_FIRE_RL_theMem_iCache_respondDuringUpdate ;
assign theMem_iCache_tags_serverAdapterA_outData_enqData$whas =
theMem_iCache_tags_serverAdapterA_outDataCore$FULL_N &&
theMem_iCache_tags_serverAdapterA_s1[1] &&
theMem_iCache_tags_serverAdapterA_s1[0] ;
assign theMem_iCache_tags_serverAdapterA_outData_outData$wget =
theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N ?
theMem_iCache_tags_serverAdapterA_outDataCore$D_OUT :
theMem_iCache_tags_memory$DOA ;
assign theMem_iCache_tags_serverAdapterA_outData_outData$whas =
theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N ||
!theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N &&
theMem_iCache_tags_serverAdapterA_outData_enqData$whas ;
assign theMem_iCache_tags_serverAdapterA_cnt_1$whas =
(MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 ||
WILL_FIRE_RL_debugInstructionFetch ||
WILL_FIRE_RL_instructionFetch) &&
(!ab__h107013[1] || ab__h107013[0]) ;
assign theMem_iCache_tags_serverAdapterA_writeWithResp$whas =
MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 ||
WILL_FIRE_RL_debugInstructionFetch ||
WILL_FIRE_RL_instructionFetch ;
assign theMem_iCache_tags_serverAdapterA_s1_1$wget =
{ 1'd1, !ab__h107013[1] || ab__h107013[0] } ;
assign theMem_iCache_tags_serverAdapterB_outData_enqData$whas =
theMem_iCache_tags_serverAdapterB_outDataCore$FULL_N &&
theMem_iCache_tags_serverAdapterB_s1[1] &&
theMem_iCache_tags_serverAdapterB_s1[0] ;
assign theMem_iCache_tags_serverAdapterB_cnt_1$whas =
WILL_FIRE_RL_theMem_iCache_tags_serverAdapterB_stageReadResponseAlways &&
(!ab__h108440[1] || ab__h108440[0]) ;
assign theMem_iCache_tags_serverAdapterB_s1_1$wget =
{ 1'd1, !ab__h108440[1] || ab__h108440[0] } ;
assign theMem_iCache_bank_serverAdapterA_outData_enqData$whas =
theMem_iCache_bank_serverAdapterA_outDataCore$FULL_N &&
theMem_iCache_bank_serverAdapterA_s1[1] &&
theMem_iCache_bank_serverAdapterA_s1[0] ;
assign theMem_iCache_bank_serverAdapterA_outData_outData$whas =
theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N ||
!theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N &&
theMem_iCache_bank_serverAdapterA_outData_enqData$whas ;
assign theMem_iCache_bank_serverAdapterA_cnt_1$whas =
(MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 ||
WILL_FIRE_RL_debugInstructionFetch ||
WILL_FIRE_RL_instructionFetch) &&
(!ab__h110016[1] || ab__h110016[0]) ;
assign theMem_iCache_bank_serverAdapterA_writeWithResp$whas =
MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 ||
WILL_FIRE_RL_debugInstructionFetch ||
WILL_FIRE_RL_instructionFetch ;
assign theMem_iCache_bank_serverAdapterA_s1_1$wget =
{ 1'd1, !ab__h110016[1] || ab__h110016[0] } ;
assign theMem_iCache_bank_serverAdapterB_outData_enqData$whas =
theMem_iCache_bank_serverAdapterB_outDataCore$FULL_N &&
theMem_iCache_bank_serverAdapterB_s1[1] &&
theMem_iCache_bank_serverAdapterB_s1[0] ;
assign theMem_iCache_bank_serverAdapterB_cnt_1$whas =
(MUX_theMem_iCache_bank_memory$b_put_1__SEL_1 ||
WILL_FIRE_RL_theMem_iCache_updateCache) &&
(!ab__h111421[1] || ab__h111421[0]) ;
assign theMem_iCache_bank_serverAdapterB_writeWithResp$whas =
MUX_theMem_iCache_bank_memory$b_put_1__SEL_1 ||
WILL_FIRE_RL_theMem_iCache_updateCache ;
assign theMem_iCache_bank_serverAdapterB_s1_1$wget =
{ 1'd1, !ab__h111421[1] || ab__h111421[0] } ;
always@(MUX_theMem_dCache_out_fifo_enqw$wset_1__SEL_1 or
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_1 or
WILL_FIRE_RL_theMem_dCache_wayMiss or
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_2 or
WILL_FIRE_RL_theMem_dCache_getResponseUncached or
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_dCache_out_fifo_enqw$wset_1__SEL_1:
theMem_dCache_out_fifo_enqw$wget =
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_1;
WILL_FIRE_RL_theMem_dCache_wayMiss:
theMem_dCache_out_fifo_enqw$wget =
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_2;
WILL_FIRE_RL_theMem_dCache_getResponseUncached:
theMem_dCache_out_fifo_enqw$wget =
MUX_theMem_dCache_out_fifo_enqw$wset_1__VAL_3;
default: theMem_dCache_out_fifo_enqw$wget =
69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theMem_dCache_out_fifo_enqw$whas =
MUX_theMem_dCache_out_fifo_enqw$wset_1__SEL_1 ||
WILL_FIRE_RL_theMem_dCache_wayMiss ||
WILL_FIRE_RL_theMem_dCache_getResponseUncached ;
assign theMem_dCache_tags_serverAdapterA_outData_enqData$whas =
theMem_dCache_tags_serverAdapterA_outDataCore$FULL_N &&
theMem_dCache_tags_serverAdapterA_s1[1] &&
theMem_dCache_tags_serverAdapterA_s1[0] ;
assign theMem_dCache_tags_serverAdapterA_outData_outData$wget =
theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N ?
theMem_dCache_tags_serverAdapterA_outDataCore$D_OUT :
theMem_dCache_tags_memory$DOA ;
assign theMem_dCache_tags_serverAdapterA_outData_outData$whas =
theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N ||
!theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N &&
theMem_dCache_tags_serverAdapterA_outData_enqData$whas ;
assign theMem_dCache_tags_serverAdapterB_outData_enqData$whas =
theMem_dCache_tags_serverAdapterB_outDataCore$FULL_N &&
theMem_dCache_tags_serverAdapterB_s1[1] &&
theMem_dCache_tags_serverAdapterB_s1[0] ;
assign theMem_dCache_tags_serverAdapterB_cnt_1$whas =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterB_stageReadResponseAlways &&
(!ab__h122228[1] || ab__h122228[0]) ;
assign theMem_dCache_tags_serverAdapterB_s1_1$wget =
{ 1'd1, !ab__h122228[1] || ab__h122228[0] } ;
assign theMem_dCache_data_serverAdapterA_outData_enqData$whas =
theMem_dCache_data_serverAdapterA_outDataCore$FULL_N &&
theMem_dCache_data_serverAdapterA_s1[1] &&
theMem_dCache_data_serverAdapterA_s1[0] ;
assign theMem_dCache_data_serverAdapterA_outData_outData$whas =
theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N ||
!theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N &&
theMem_dCache_data_serverAdapterA_outData_enqData$whas ;
assign theMem_dCache_data_serverAdapterA_cnt_1$whas =
(MUX_theMem_dCache_data_memory$a_put_1__SEL_1 ||
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways) &&
(!ab__h124191[1] || ab__h124191[0]) ;
assign theMem_dCache_data_serverAdapterA_writeWithResp$whas =
MUX_theMem_dCache_data_memory$a_put_1__SEL_1 ||
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways ;
assign theMem_dCache_data_serverAdapterA_s1_1$wget =
{ 1'd1, !ab__h124191[1] || ab__h124191[0] } ;
assign theMem_dCache_data_serverAdapterB_outData_enqData$whas =
theMem_dCache_data_serverAdapterB_outDataCore$FULL_N &&
theMem_dCache_data_serverAdapterB_s1[1] &&
theMem_dCache_data_serverAdapterB_s1[0] ;
assign theMem_dCache_data_serverAdapterB_cnt_1$whas =
(MUX_theMem_dCache_data_memory$b_put_1__SEL_1 ||
MUX_theMem_dCache_data_memory$b_put_1__SEL_2 ||
WILL_FIRE_RL_theMem_dCache_updateCache) &&
(!ab__h125596[1] || ab__h125596[0]) ;
assign theMem_dCache_data_serverAdapterB_writeWithResp$whas =
MUX_theMem_dCache_data_memory$b_put_1__SEL_1 ||
MUX_theMem_dCache_data_memory$b_put_1__SEL_2 ||
WILL_FIRE_RL_theMem_dCache_updateCache ;
assign theMem_dCache_data_serverAdapterB_s1_1$wget =
{ 1'd1, !ab__h125596[1] || ab__h125596[0] } ;
assign freeRenameReg_r_enq$whas =
WILL_FIRE_RL_writeback_doWriteBackWithWrite ||
WILL_FIRE_RL_writeback_doWriteBackWithRead ||
WILL_FIRE_RL_writeback_doWriteBack ||
WILL_FIRE_RL_initialize ;
assign theDebug_trace_buf_doEnq$whas =
WILL_FIRE_RL_writeback_doInstructionReport &&
NOT_writeback_instructionReport_first__347_BIT_ETC___d2481 ;
assign theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas =
WILL_FIRE_RL_theMem_iCache_respondDuringUpdate ||
WILL_FIRE_RL_theMem_iCache_doRead ;
assign theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas =
WILL_FIRE_RL_writeback_doWriteBackWithWrite ||
WILL_FIRE_RL_theMem_dCache_checkTags ;
assign theMem_dCache_data_serverAdapterA_outData_deqCalled$whas =
WILL_FIRE_RL_writeback_doWriteBackWithWrite ||
WILL_FIRE_RL_theMem_dCache_wayMiss ||
WILL_FIRE_RL_theMem_dCache_checkTags ;
// register execute_hi
assign execute_hi$D_IN = execute_mul$muldiv_response_get[128:65] ;
assign execute_hi$EN =
WILL_FIRE_RL_execute_finishMultiplyOrDivide &&
writeback_hiLoCommit$D_OUT &&
execute_mul$muldiv_response_get[129] ;
// register execute_lo
assign execute_lo$D_IN = execute_mul$muldiv_response_get[63:0] ;
assign execute_lo$EN =
WILL_FIRE_RL_execute_finishMultiplyOrDivide &&
writeback_hiLoCommit$D_OUT &&
execute_mul$muldiv_response_get[64] ;
// register execute_loadsDone
assign execute_loadsDone$D_IN = execute_loadsDone + 4'd1 ;
assign execute_loadsDone$EN =
_dor1execute_loadsDone$EN_write &&
writeback_destRenamed$EMPTY_N ;
// register execute_loadsIn
assign execute_loadsIn$D_IN = execute_loadsIn + 4'd1 ;
assign execute_loadsIn$EN =
WILL_FIRE_RL_execute_doExecute &&
execute_inQ$D_OUT[14:13] == 2'd0 ;
// register execute_renameRegsVector
always@(MUX_execute_renameRegsVector$write_1__SEL_1 or
MUX_execute_renameRegsVector$write_1__VAL_1 or
WILL_FIRE_RL_execute_doReadReport or
MUX_execute_renameRegsVector$write_1__VAL_2 or
WILL_FIRE_RL_execute_doExecute or
MUX_execute_renameRegsVector$write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_execute_renameRegsVector$write_1__SEL_1:
execute_renameRegsVector$D_IN =
MUX_execute_renameRegsVector$write_1__VAL_1;
WILL_FIRE_RL_execute_doReadReport:
execute_renameRegsVector$D_IN =
MUX_execute_renameRegsVector$write_1__VAL_2;
WILL_FIRE_RL_execute_doExecute:
execute_renameRegsVector$D_IN =
MUX_execute_renameRegsVector$write_1__VAL_3;
default: execute_renameRegsVector$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign execute_renameRegsVector$EN =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd0 ||
WILL_FIRE_RL_execute_doReadReport ||
WILL_FIRE_RL_execute_doExecute ;
// register execute_renameRegsVector_1
always@(MUX_execute_renameRegsVector_1$write_1__SEL_1 or
MUX_execute_renameRegsVector$write_1__VAL_1 or
WILL_FIRE_RL_execute_doReadReport or
MUX_execute_renameRegsVector_1$write_1__VAL_2 or
WILL_FIRE_RL_execute_doExecute or
MUX_execute_renameRegsVector_1$write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_execute_renameRegsVector_1$write_1__SEL_1:
execute_renameRegsVector_1$D_IN =
MUX_execute_renameRegsVector$write_1__VAL_1;
WILL_FIRE_RL_execute_doReadReport:
execute_renameRegsVector_1$D_IN =
MUX_execute_renameRegsVector_1$write_1__VAL_2;
WILL_FIRE_RL_execute_doExecute:
execute_renameRegsVector_1$D_IN =
MUX_execute_renameRegsVector_1$write_1__VAL_3;
default: execute_renameRegsVector_1$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign execute_renameRegsVector_1$EN =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd1 ||
WILL_FIRE_RL_execute_doReadReport ||
WILL_FIRE_RL_execute_doExecute ;
// register execute_renameRegsVector_2
always@(MUX_execute_renameRegsVector_2$write_1__SEL_1 or
MUX_execute_renameRegsVector$write_1__VAL_1 or
WILL_FIRE_RL_execute_doReadReport or
MUX_execute_renameRegsVector_2$write_1__VAL_2 or
WILL_FIRE_RL_execute_doExecute or
MUX_execute_renameRegsVector_2$write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_execute_renameRegsVector_2$write_1__SEL_1:
execute_renameRegsVector_2$D_IN =
MUX_execute_renameRegsVector$write_1__VAL_1;
WILL_FIRE_RL_execute_doReadReport:
execute_renameRegsVector_2$D_IN =
MUX_execute_renameRegsVector_2$write_1__VAL_2;
WILL_FIRE_RL_execute_doExecute:
execute_renameRegsVector_2$D_IN =
MUX_execute_renameRegsVector_2$write_1__VAL_3;
default: execute_renameRegsVector_2$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign execute_renameRegsVector_2$EN =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd2 ||
WILL_FIRE_RL_execute_doReadReport ||
WILL_FIRE_RL_execute_doExecute ;
// register execute_renameRegsVector_3
always@(MUX_execute_renameRegsVector_3$write_1__SEL_1 or
MUX_execute_renameRegsVector$write_1__VAL_1 or
WILL_FIRE_RL_execute_doReadReport or
MUX_execute_renameRegsVector_3$write_1__VAL_2 or
WILL_FIRE_RL_execute_doExecute or
MUX_execute_renameRegsVector_3$write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_execute_renameRegsVector_3$write_1__SEL_1:
execute_renameRegsVector_3$D_IN =
MUX_execute_renameRegsVector$write_1__VAL_1;
WILL_FIRE_RL_execute_doReadReport:
execute_renameRegsVector_3$D_IN =
MUX_execute_renameRegsVector_3$write_1__VAL_2;
WILL_FIRE_RL_execute_doExecute:
execute_renameRegsVector_3$D_IN =
MUX_execute_renameRegsVector_3$write_1__VAL_3;
default: execute_renameRegsVector_3$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign execute_renameRegsVector_3$EN =
WILL_FIRE_RL_execute_deliverPendingOp &&
execute_pendingOps$D_OUT[379:375] == 5'd14 &&
execute_pendingOps$D_OUT[437:436] == 2'd3 ||
WILL_FIRE_RL_execute_doReadReport ||
WILL_FIRE_RL_execute_doExecute ;
// register freeRenameReg_countReg
assign freeRenameReg_countReg$D_IN =
freeRenameReg_r_enq$whas ?
freeRenameReg_countReg + 3'd1 :
freeRenameReg_countReg - 3'd1 ;
assign freeRenameReg_countReg$EN =
freeRenameReg_r_enq$whas != WILL_FIRE_RL_registerFetch ;
// register freeRenameReg_levelsValid
assign freeRenameReg_levelsValid$D_IN = WILL_FIRE_RL_freeRenameReg_reset ;
assign freeRenameReg_levelsValid$EN =
WILL_FIRE_RL_registerFetch ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite ||
WILL_FIRE_RL_writeback_doWriteBackWithRead ||
WILL_FIRE_RL_writeback_doWriteBack ||
WILL_FIRE_RL_initialize ||
WILL_FIRE_RL_freeRenameReg_reset ;
// register init
assign init$D_IN = init + 3'd1 ;
assign init$EN = WILL_FIRE_RL_initialize ;
// register initState
assign initState$D_IN = 1'd0 ;
assign initState$EN = WILL_FIRE_RL_initialize && init == 3'd4 ;
// register lastEpoch
assign lastEpoch$D_IN = fetchedControlToken$D_OUT[440:438] ;
assign lastEpoch$EN = WILL_FIRE_RL_registerFetch ;
// register lastWasBranch
assign lastWasBranch$D_IN =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7159 ||
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7185 ;
assign lastWasBranch$EN = WILL_FIRE_RL_registerFetch ;
// register nextId
assign nextId$D_IN = nextId + 4'd1 ;
assign nextId$EN = WILL_FIRE_RL_instructionFetch ;
// register nextInstruction_taggedReg
assign nextInstruction_taggedReg$D_IN =
70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign nextInstruction_taggedReg$EN = 1'b0 ;
// register regRenameTable
assign regRenameTable$D_IN =
(destReg__h279602 == 5'd0) ?
{ fetchedControlToken$D_OUT[437:436] != 2'd3 &&
regRenameTable[47],
regRenameTable[46:36],
fetchedControlToken$D_OUT[437:436] != 2'd2 &&
regRenameTable[35],
regRenameTable[34:24],
fetchedControlToken$D_OUT[437:436] != 2'd1 &&
regRenameTable[23],
regRenameTable[22:12],
fetchedControlToken$D_OUT[437:436] != 2'd0 &&
regRenameTable[11],
regRenameTable[10:0] } :
{ fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7032,
IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7103,
fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7107,
IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7114,
fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7119,
IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7126,
fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7131,
IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7138 } ;
assign regRenameTable$EN = WILL_FIRE_RL_registerFetch ;
// register theCapCop_capState
always@(MUX_theCapCop_capState$write_1__SEL_1 or
WILL_FIRE_RL_theCapCop_finishException or
MUX_theCapCop_capState$write_1__SEL_3 or
WILL_FIRE_RL_memToCap or
WILL_FIRE_RL_capToMem or
MUX_theCapCop_capState$write_1__VAL_5 or
MUX_theCapCop_capState$write_1__SEL_6)
case (1'b1)
MUX_theCapCop_capState$write_1__SEL_1: theCapCop_capState$D_IN = 3'd3;
WILL_FIRE_RL_theCapCop_finishException ||
MUX_theCapCop_capState$write_1__SEL_3 ||
WILL_FIRE_RL_memToCap:
theCapCop_capState$D_IN = 3'd5;
WILL_FIRE_RL_capToMem:
theCapCop_capState$D_IN = MUX_theCapCop_capState$write_1__VAL_5;
MUX_theCapCop_capState$write_1__SEL_6: theCapCop_capState$D_IN = 3'd1;
default: theCapCop_capState$D_IN = 3'b010 /* unspecified value */ ;
endcase
assign theCapCop_capState$EN =
theCapCop_capState == 3'd0 && theCapCop_count == 5'd31 ||
theCapCop_capState == 3'd5 && theCapCop_exception$EMPTY_N &&
!theCapCop_insts$EMPTY_N ||
WILL_FIRE_RL_doDecode &&
(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd9 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd10) ||
WILL_FIRE_RL_capToMem ||
WILL_FIRE_RL_memToCap ||
WILL_FIRE_RL_theCapCop_finishException ;
// register theCapCop_capWriteback
assign theCapCop_capWriteback$D_IN =
MUX_theCapCop_capWriteback$write_1__SEL_1 ?
MUX_theCapCop_capWriteback$write_1__VAL_1 :
MUX_theCapCop_capWriteback$write_1__VAL_2 ;
assign theCapCop_capWriteback$EN =
WILL_FIRE_RL_execute_doExecute &&
(theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d9255 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3600) ||
WILL_FIRE_RL_memToCap ;
// register theCapCop_commitWritebackFifo_taggedReg
assign theCapCop_commitWritebackFifo_taggedReg$D_IN =
2'b10 /* unspecified value */ ;
assign theCapCop_commitWritebackFifo_taggedReg$EN = 1'b0 ;
// register theCapCop_count
assign theCapCop_count$D_IN = theCapCop_count + 5'd1 ;
assign theCapCop_count$EN = theCapCop_capState == 3'd0 ;
// register theCapCop_pcc
assign theCapCop_pcc$D_IN =
MUX_theCapCop_pcc$write_1__SEL_1 ?
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d7882 :
MUX_theCapCop_pcc$write_1__VAL_2 ;
assign theCapCop_pcc$EN =
WILL_FIRE_RL_execute_doExecute &&
(theCapCop_capInsts$D_OUT[99:95] == 5'd7 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd8) ||
WILL_FIRE_RL_theCapCop_finishException ;
// register theCapCop_pipeEmpty
assign theCapCop_pipeEmpty$D_IN = 1'b0 ;
assign theCapCop_pipeEmpty$EN = 1'b0 ;
// register theCapCop_writesCalculated
assign theCapCop_writesCalculated$D_IN =
MUX_theCapCop_writesCalculated$write_1__SEL_1 ?
MUX_theCapCop_writesCalculated$write_1__VAL_1 :
MUX_theCapCop_writesCalculated$write_1__VAL_1 ;
assign theCapCop_writesCalculated$EN =
WILL_FIRE_RL_execute_doExecute &&
(theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548) ||
WILL_FIRE_RL_memToCap ;
// register theCapCop_writesDone
assign theCapCop_writesDone$D_IN = theCapCop_writesDone + 5'd1 ;
assign theCapCop_writesDone$EN =
MUX_freeRenameReg$enq_1__SEL_1 &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags$D_OUT[0] &&
theCapCop_capWritebackTags$D_OUT[7:4] ==
theCapCop_capWriteback[6:3] ;
// register theCapCop_writesIn
assign theCapCop_writesIn$D_IN = theCapCop_writesIn + 5'd1 ;
assign theCapCop_writesIn$EN =
WILL_FIRE_RL_doDecode &&
(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd4 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd7 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd1 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd10) ;
// register theDebug_bp
assign theDebug_bp$D_IN =
{ newVal__h6189 != 64'hFFFFFFFFFFFFFFFF,
(newVal__h6189 == 64'hFFFFFFFFFFFFFFFF) ?
{ theDebug_debugConvert$messages_request_get[7:0],
theDebug_debugConvert$messages_request_get[15:8],
theDebug_debugConvert$messages_request_get[23:16],
theDebug_debugConvert$messages_request_get[31:24],
theDebug_debugConvert$messages_request_get[39:32],
theDebug_debugConvert$messages_request_get[47:40],
theDebug_debugConvert$messages_request_get[55:48],
theDebug_debugConvert$messages_request_get[63:56] } :
newVal__h6189 } ;
assign theDebug_bp$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd48 ;
// register theDebug_bp_1
assign theDebug_bp_1$D_IN = theDebug_bp$D_IN ;
assign theDebug_bp_1$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd49 ;
// register theDebug_bp_2
assign theDebug_bp_2$D_IN = theDebug_bp$D_IN ;
assign theDebug_bp_2$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd50 ;
// register theDebug_bp_3
assign theDebug_bp_3$D_IN = theDebug_bp$D_IN ;
assign theDebug_bp_3$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd51 ;
// register theDebug_dest
assign theDebug_dest$D_IN =
MUX_theDebug_dest$write_1__SEL_1 ?
theDebug_mipsPC :
theDebug_writebacks$D_OUT[68:5] ;
assign theDebug_dest$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd99 ||
WILL_FIRE_RL_theDebug_finishExecute &&
theDebug_writebacks$D_OUT[69] ;
// register theDebug_idleCount
assign theDebug_idleCount$D_IN =
MUX_theDebug_state$write_1__PSEL_2 ?
MUX_theDebug_idleCount$write_1__VAL_1 :
28'd0 ;
assign theDebug_idleCount$EN =
WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction ||
WILL_FIRE_RL_theDebug_countIdleCyclesStreamTrace ||
WILL_FIRE_RL_theDebug_popTrace ||
WILL_FIRE_RL_theDebug_doCommands ;
// register theDebug_instDelay
assign theDebug_instDelay$D_IN = 6'h0 ;
assign theDebug_instDelay$EN = 1'b0 ;
// register theDebug_instQnotEmpty
assign theDebug_instQnotEmpty$D_IN = theDebug_instQ$EMPTY_N ;
assign theDebug_instQnotEmpty$EN = 1'd1 ;
// register theDebug_instruction
assign theDebug_instruction$D_IN =
{ theDebug_debugConvert$messages_request_get[7:0],
theDebug_debugConvert$messages_request_get[15:8],
theDebug_debugConvert$messages_request_get[23:16],
theDebug_debugConvert$messages_request_get[31:24] } ;
assign theDebug_instruction$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd105 ;
// register theDebug_mipsPC
always@(MUX_theDebug_mipsPC$write_1__SEL_1 or
_theResult_____4__h170559 or
MUX_theDebug_mipsPC$write_1__SEL_2 or
MUX_theDebug_mipsPC$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theDebug_mipsPC$write_1__SEL_1:
theDebug_mipsPC$D_IN = _theResult_____4__h170559;
MUX_theDebug_mipsPC$write_1__SEL_2:
theDebug_mipsPC$D_IN = _theResult_____4__h170559;
MUX_theDebug_mipsPC$write_1__SEL_3:
theDebug_mipsPC$D_IN = _theResult_____4__h170559;
default: theDebug_mipsPC$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theDebug_mipsPC$EN =
WILL_FIRE_RL_writeback_doWriteBack &&
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d2637 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d2819 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d3143 ;
// register theDebug_opA
assign theDebug_opA$D_IN = newVal__h6189 ;
assign theDebug_opA$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd97 ;
// register theDebug_opB
assign theDebug_opB$D_IN = newVal__h6189 ;
assign theDebug_opB$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd98 ;
// register theDebug_pauseForInst
assign theDebug_pauseForInst$D_IN = 1'b0 ;
assign theDebug_pauseForInst$EN = 1'b0 ;
// register theDebug_pausePipe
always@(MUX_theDebug_pausePipe$write_1__SEL_1 or
MUX_theDebug_pausePipe$write_1__VAL_1 or
WILL_FIRE_RL_theDebug_finishExecute or
theDebug_previousPausePipe or
WILL_FIRE_RL_theDebug_step or
WILL_FIRE_RL_theDebug_unpipelinedStep or
WILL_FIRE_RL_theDebug_reportBreakPoint or
MUX_theDebug_pausePipe$write_1__SEL_6)
case (1'b1)
MUX_theDebug_pausePipe$write_1__SEL_1:
theDebug_pausePipe$D_IN = MUX_theDebug_pausePipe$write_1__VAL_1;
WILL_FIRE_RL_theDebug_finishExecute:
theDebug_pausePipe$D_IN = theDebug_previousPausePipe;
WILL_FIRE_RL_theDebug_step: theDebug_pausePipe$D_IN = 1'd1;
WILL_FIRE_RL_theDebug_unpipelinedStep: theDebug_pausePipe$D_IN = 1'd0;
WILL_FIRE_RL_theDebug_reportBreakPoint ||
MUX_theDebug_pausePipe$write_1__SEL_6:
theDebug_pausePipe$D_IN = 1'd1;
default: theDebug_pausePipe$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign theDebug_pausePipe$EN =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd112 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd114 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd117 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd115 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd83) ||
WILL_FIRE_RL_theDebug_popTrace &&
theDebug_trace_buf_tailPtr_read__1_PLUS_1_2_EQ_ETC___d8043 ||
WILL_FIRE_RL_theDebug_finishExecute ||
WILL_FIRE_RL_theDebug_unpipelinedStep ||
WILL_FIRE_RL_theDebug_step ||
WILL_FIRE_RL_theDebug_reportBreakPoint ;
// register theDebug_pipeCount
assign theDebug_pipeCount$D_IN = theDebug_pipeCount + 3'd1 ;
assign theDebug_pipeCount$EN = 1'd1 ;
// register theDebug_pollCount
assign theDebug_pollCount$D_IN = 24'h0 ;
assign theDebug_pollCount$EN = 1'b0 ;
// register theDebug_previousPausePipe
assign theDebug_previousPausePipe$D_IN = theDebug_pausePipe ;
assign theDebug_previousPausePipe$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ;
// register theDebug_state
always@(MUX_theDebug_state$write_1__SEL_1 or
MUX_theDebug_state$write_1__VAL_1 or
MUX_theDebug_state$write_1__SEL_2 or
MUX_theDebug_state$write_1__SEL_3 or
WILL_FIRE_RL_theDebug_unpipelinedStep)
begin
case (1'b1) // synopsys parallel_case
MUX_theDebug_state$write_1__SEL_1:
theDebug_state$D_IN = MUX_theDebug_state$write_1__VAL_1;
MUX_theDebug_state$write_1__SEL_2 || MUX_theDebug_state$write_1__SEL_3:
theDebug_state$D_IN = 2'd0;
WILL_FIRE_RL_theDebug_unpipelinedStep: theDebug_state$D_IN = 2'd2;
default: theDebug_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign theDebug_state$EN =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd115 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd83) ||
(WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction ||
WILL_FIRE_RL_theDebug_countIdleCyclesStreamTrace) &&
theDebug_idleCount == 28'h000007F ||
WILL_FIRE_RL_theDebug_finishExecute ||
WILL_FIRE_RL_theDebug_step ||
WILL_FIRE_RL_theDebug_unpipelinedStep ;
// register theDebug_traceCmp
assign theDebug_traceCmp$D_IN =
{ theDebug_debugConvert$messages_request_get[7:3],
IF_theDebug_debugConvert_messages_request_get__ETC___d7855,
theDebug_debugConvert$messages_request_get[13:8],
theDebug_debugConvert$messages_request_get[23:16],
theDebug_debugConvert$messages_request_get[31:24],
theDebug_debugConvert$messages_request_get[39:32],
theDebug_debugConvert$messages_request_get[47:40],
theDebug_debugConvert$messages_request_get[55:48],
theDebug_debugConvert$messages_request_get[63:56],
theDebug_debugConvert$messages_request_get[71:64],
theDebug_debugConvert$messages_request_get[79:72],
theDebug_debugConvert$messages_request_get[87:80],
theDebug_debugConvert$messages_request_get[95:88],
theDebug_debugConvert$messages_request_get[103:96],
theDebug_debugConvert$messages_request_get[111:104],
theDebug_debugConvert$messages_request_get[119:112],
theDebug_debugConvert$messages_request_get[127:120],
theDebug_debugConvert$messages_request_get[135:128],
theDebug_debugConvert$messages_request_get[143:136],
theDebug_debugConvert$messages_request_get[151:144],
theDebug_debugConvert$messages_request_get[159:152],
theDebug_debugConvert$messages_request_get[167:160],
theDebug_debugConvert$messages_request_get[175:168],
theDebug_debugConvert$messages_request_get[183:176],
theDebug_debugConvert$messages_request_get[191:184],
theDebug_debugConvert$messages_request_get[199:192],
theDebug_debugConvert$messages_request_get[207:200],
theDebug_debugConvert$messages_request_get[215:208],
theDebug_debugConvert$messages_request_get[223:216],
theDebug_debugConvert$messages_request_get[231:224],
theDebug_debugConvert$messages_request_get[239:232],
theDebug_debugConvert$messages_request_get[247:240],
theDebug_debugConvert$messages_request_get[255:248] } ;
assign theDebug_traceCmp$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ;
// register theDebug_traceCmpMask
assign theDebug_traceCmpMask$D_IN =
{ theDebug_debugConvert$messages_request_get[7:0],
theDebug_debugConvert$messages_request_get[15:8],
theDebug_debugConvert$messages_request_get[23:16],
theDebug_debugConvert$messages_request_get[31:24],
theDebug_debugConvert$messages_request_get[39:32],
theDebug_debugConvert$messages_request_get[47:40],
theDebug_debugConvert$messages_request_get[55:48],
theDebug_debugConvert$messages_request_get[63:56],
theDebug_debugConvert$messages_request_get[71:64],
theDebug_debugConvert$messages_request_get[79:72],
theDebug_debugConvert$messages_request_get[87:80],
theDebug_debugConvert$messages_request_get[95:88],
theDebug_debugConvert$messages_request_get[103:96],
theDebug_debugConvert$messages_request_get[111:104],
theDebug_debugConvert$messages_request_get[119:112],
theDebug_debugConvert$messages_request_get[127:120],
theDebug_debugConvert$messages_request_get[135:128],
theDebug_debugConvert$messages_request_get[143:136],
theDebug_debugConvert$messages_request_get[151:144],
theDebug_debugConvert$messages_request_get[159:152],
theDebug_debugConvert$messages_request_get[167:160],
theDebug_debugConvert$messages_request_get[175:168],
theDebug_debugConvert$messages_request_get[183:176],
theDebug_debugConvert$messages_request_get[191:184],
theDebug_debugConvert$messages_request_get[199:192],
theDebug_debugConvert$messages_request_get[207:200],
theDebug_debugConvert$messages_request_get[215:208],
theDebug_debugConvert$messages_request_get[223:216],
theDebug_debugConvert$messages_request_get[231:224],
theDebug_debugConvert$messages_request_get[239:232],
theDebug_debugConvert$messages_request_get[247:240],
theDebug_debugConvert$messages_request_get[255:248] } ;
assign theDebug_traceCmpMask$EN =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd77 ;
// register theDebug_trace_buf_headPtr
assign theDebug_trace_buf_headPtr$D_IN = theDebug_trace_buf_bram$ADDRB ;
assign theDebug_trace_buf_headPtr$EN = 1'd1 ;
// register theDebug_trace_buf_readDelay
assign theDebug_trace_buf_readDelay$D_IN =
theDebug_trace_buf_tailPtr_read__1_EQ_theDebug_ETC___d40 ;
assign theDebug_trace_buf_readDelay$EN = 1'd1 ;
// register theDebug_trace_buf_tailPtr
assign theDebug_trace_buf_tailPtr$D_IN =
theDebug_trace_buf_doEnq$whas ?
theDebug_trace_buf_tailPtr_read__1_PLUS_1___d7524 :
theDebug_trace_buf_tailPtr ;
assign theDebug_trace_buf_tailPtr$EN = 1'd1 ;
// register theDebug_unPipeline
assign theDebug_unPipeline$D_IN =
MUX_theDebug_unPipeline$write_1__SEL_1 &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd117 ;
assign theDebug_unPipeline$EN =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd112 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd114 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd117 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd83) ||
WILL_FIRE_RL_theDebug_popTrace &&
theDebug_trace_buf_tailPtr_read__1_PLUS_1_2_EQ_ETC___d8043 ||
WILL_FIRE_RL_theDebug_reportBreakPoint ;
// register theMem_dCache_addrReg
assign theMem_dCache_addrReg$D_IN =
theCP0$tlbLookupData_response_get[49:14] ;
assign theMem_dCache_addrReg$EN = WILL_FIRE_RL_theMem_dCache_checkTags ;
// register theMem_dCache_byteWriteReg
assign theMem_dCache_byteWriteReg$D_IN = 8'd0 ;
assign theMem_dCache_byteWriteReg$EN =
WILL_FIRE_RL_theMem_dCache_checkTags ;
// register theMem_dCache_cacheState
always@(MUX_theMem_dCache_cacheState$write_1__SEL_2 or
MUX_theMem_dCache_cacheState$write_1__VAL_2 or
WILL_FIRE_RL_theMem_dCache_getResponseUncached or
MUX_theMem_dCache_cacheState$write_1__VAL_4 or
MUX_theMem_dCache_cacheState$write_1__SEL_1 or
MUX_theMem_dCache_cacheState$write_1__SEL_3 or
WILL_FIRE_RL_theMem_dCache_wayMiss)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_dCache_cacheState$write_1__SEL_2:
theMem_dCache_cacheState$D_IN =
MUX_theMem_dCache_cacheState$write_1__VAL_2;
WILL_FIRE_RL_theMem_dCache_getResponseUncached:
theMem_dCache_cacheState$D_IN =
MUX_theMem_dCache_cacheState$write_1__VAL_4;
MUX_theMem_dCache_cacheState$write_1__SEL_1 ||
MUX_theMem_dCache_cacheState$write_1__SEL_3 ||
WILL_FIRE_RL_theMem_dCache_wayMiss:
theMem_dCache_cacheState$D_IN = 3'd1;
default: theMem_dCache_cacheState$D_IN =
3'b010 /* unspecified value */ ;
endcase
end
assign theMem_dCache_cacheState$EN =
WILL_FIRE_RL_theMem_dCache_initialize &&
theMem_dCache_count == 7'd127 ||
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ||
NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d1818) ||
WILL_FIRE_RL_theMem_dCache_updateCache &&
theMem_dCache_fillCount == 2'b11 ||
WILL_FIRE_RL_theMem_dCache_getResponseUncached ||
WILL_FIRE_RL_theMem_dCache_wayMiss ;
// register theMem_dCache_count
assign theMem_dCache_count$D_IN = theMem_dCache_count + 7'd1 ;
assign theMem_dCache_count$EN = WILL_FIRE_RL_theMem_dCache_initialize ;
// register theMem_dCache_data_serverAdapterA_cnt
assign theMem_dCache_data_serverAdapterA_cnt$D_IN =
theMem_dCache_data_serverAdapterA_cnt_633_PLUS_ETC___d1639 ;
assign theMem_dCache_data_serverAdapterA_cnt$EN =
theMem_dCache_data_serverAdapterA_cnt_1$whas ||
theMem_dCache_data_serverAdapterA_outData_deqCalled$whas ;
// register theMem_dCache_data_serverAdapterA_s1
assign theMem_dCache_data_serverAdapterA_s1$D_IN =
{ theMem_dCache_data_serverAdapterA_writeWithResp$whas &&
theMem_dCache_data_serverAdapterA_s1_1$wget[1],
theMem_dCache_data_serverAdapterA_s1_1$wget[0] } ;
assign theMem_dCache_data_serverAdapterA_s1$EN = 1'd1 ;
// register theMem_dCache_data_serverAdapterB_cnt
assign theMem_dCache_data_serverAdapterB_cnt$D_IN =
theMem_dCache_data_serverAdapterB_cnt +
(theMem_dCache_data_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
3'd0 ;
assign theMem_dCache_data_serverAdapterB_cnt$EN =
theMem_dCache_data_serverAdapterB_cnt_1$whas ;
// register theMem_dCache_data_serverAdapterB_s1
assign theMem_dCache_data_serverAdapterB_s1$D_IN =
{ theMem_dCache_data_serverAdapterB_writeWithResp$whas &&
theMem_dCache_data_serverAdapterB_s1_1$wget[1],
theMem_dCache_data_serverAdapterB_s1_1$wget[0] } ;
assign theMem_dCache_data_serverAdapterB_s1$EN = 1'd1 ;
// register theMem_dCache_fillCount
assign theMem_dCache_fillCount$D_IN =
MUX_theMem_dCache_data_memory$b_put_1__SEL_1 ?
2'd1 :
MUX_theMem_dCache_fillCount$write_1__VAL_2 ;
assign theMem_dCache_fillCount$EN =
WILL_FIRE_RL_theMem_dCache_getResponseUncached &&
theMem_dCache_missCached ||
WILL_FIRE_RL_theMem_dCache_updateCache &&
theMem_dCache_fillCount != 2'b11 ;
// register theMem_dCache_lastKey
assign theMem_dCache_lastKey$D_IN = memAccess_inQ$D_OUT[241:235] ;
assign theMem_dCache_lastKey$EN =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways ;
// register theMem_dCache_missCached
assign theMem_dCache_missCached$D_IN =
theCP0$tlbLookupData_response_get[6] ;
assign theMem_dCache_missCached$EN = WILL_FIRE_RL_theMem_dCache_checkTags ;
// register theMem_dCache_recentlyUsedWay
assign theMem_dCache_recentlyUsedWay$D_IN =
theMem_dCache_wayPredicted$D_OUT ;
assign theMem_dCache_recentlyUsedWay$EN =
WILL_FIRE_RL_theMem_dCache_checkTags ;
// register theMem_dCache_tags_serverAdapterA_cnt
assign theMem_dCache_tags_serverAdapterA_cnt$D_IN =
theMem_dCache_tags_serverAdapterA_cnt_519_PLUS_ETC___d1525 ;
assign theMem_dCache_tags_serverAdapterA_cnt$EN =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways ||
theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas ;
// register theMem_dCache_tags_serverAdapterA_s1
assign theMem_dCache_tags_serverAdapterA_s1$D_IN =
{ WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways,
1'b1 } ;
assign theMem_dCache_tags_serverAdapterA_s1$EN = 1'd1 ;
// register theMem_dCache_tags_serverAdapterB_cnt
assign theMem_dCache_tags_serverAdapterB_cnt$D_IN =
theMem_dCache_tags_serverAdapterB_cnt +
(theMem_dCache_tags_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
3'd0 ;
assign theMem_dCache_tags_serverAdapterB_cnt$EN =
theMem_dCache_tags_serverAdapterB_cnt_1$whas ;
// register theMem_dCache_tags_serverAdapterB_s1
assign theMem_dCache_tags_serverAdapterB_s1$D_IN =
{ WILL_FIRE_RL_theMem_dCache_tags_serverAdapterB_stageReadResponseAlways &&
theMem_dCache_tags_serverAdapterB_s1_1$wget[1],
theMem_dCache_tags_serverAdapterB_s1_1$wget[0] } ;
assign theMem_dCache_tags_serverAdapterB_s1$EN = 1'd1 ;
// register theMem_dCache_updateReg
assign theMem_dCache_updateReg$D_IN = theMem_theMemMerge_rsp_fifos_1$D_OUT ;
assign theMem_dCache_updateReg$EN =
WILL_FIRE_RL_theMem_dCache_getResponseUncached ;
// register theMem_iCache_bank_serverAdapterA_cnt
assign theMem_iCache_bank_serverAdapterA_cnt$D_IN =
theMem_iCache_bank_serverAdapterA_cnt_236_PLUS_ETC___d1242 ;
assign theMem_iCache_bank_serverAdapterA_cnt$EN =
theMem_iCache_bank_serverAdapterA_cnt_1$whas ||
theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas ;
// register theMem_iCache_bank_serverAdapterA_s1
assign theMem_iCache_bank_serverAdapterA_s1$D_IN =
{ theMem_iCache_bank_serverAdapterA_writeWithResp$whas &&
theMem_iCache_bank_serverAdapterA_s1_1$wget[1],
theMem_iCache_bank_serverAdapterA_s1_1$wget[0] } ;
assign theMem_iCache_bank_serverAdapterA_s1$EN = 1'd1 ;
// register theMem_iCache_bank_serverAdapterB_cnt
assign theMem_iCache_bank_serverAdapterB_cnt$D_IN =
theMem_iCache_bank_serverAdapterB_cnt +
(theMem_iCache_bank_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
3'd0 ;
assign theMem_iCache_bank_serverAdapterB_cnt$EN =
theMem_iCache_bank_serverAdapterB_cnt_1$whas ;
// register theMem_iCache_bank_serverAdapterB_s1
assign theMem_iCache_bank_serverAdapterB_s1$D_IN =
{ theMem_iCache_bank_serverAdapterB_writeWithResp$whas &&
theMem_iCache_bank_serverAdapterB_s1_1$wget[1],
theMem_iCache_bank_serverAdapterB_s1_1$wget[0] } ;
assign theMem_iCache_bank_serverAdapterB_s1$EN = 1'd1 ;
// register theMem_iCache_byteWriteReg
assign theMem_iCache_byteWriteReg$D_IN = 8'd0 ;
assign theMem_iCache_byteWriteReg$EN =
MUX_theMem_iCache_cacheState$write_1__SEL_2 ;
// register theMem_iCache_cacheState
always@(WILL_FIRE_RL_theMem_iCache_getMemoryResponse or
MUX_theMem_iCache_cacheState$write_1__VAL_4 or
MUX_theMem_iCache_cacheState$write_1__SEL_1 or
MUX_theMem_iCache_cacheState$write_1__SEL_3 or
MUX_theMem_iCache_cacheState$write_1__SEL_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_theMem_iCache_getMemoryResponse:
theMem_iCache_cacheState$D_IN =
MUX_theMem_iCache_cacheState$write_1__VAL_4;
MUX_theMem_iCache_cacheState$write_1__SEL_1 ||
MUX_theMem_iCache_cacheState$write_1__SEL_3:
theMem_iCache_cacheState$D_IN = 2'd1;
MUX_theMem_iCache_cacheState$write_1__SEL_2:
theMem_iCache_cacheState$D_IN = 2'd2;
default: theMem_iCache_cacheState$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign theMem_iCache_cacheState$EN =
WILL_FIRE_RL_theMem_iCache_initialize &&
theMem_iCache_count == 9'd511 ||
WILL_FIRE_RL_theMem_iCache_doRead &&
theCP0$tlbLookupInstruction_response_get[13:9] == 5'd25 &&
(!theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384 ||
!theMem_iCache_tags_serverAdapterA_outData_outData$wget[0] ||
!theCP0$tlbLookupInstruction_response_get[6]) ||
WILL_FIRE_RL_theMem_iCache_updateCache &&
theMem_iCache_fillCount == 2'b11 ||
WILL_FIRE_RL_theMem_iCache_getMemoryResponse ;
// register theMem_iCache_count
assign theMem_iCache_count$D_IN = theMem_iCache_count + 9'd1 ;
assign theMem_iCache_count$EN = WILL_FIRE_RL_theMem_iCache_initialize ;
// register theMem_iCache_fillCount
assign theMem_iCache_fillCount$D_IN =
MUX_theMem_iCache_bank_memory$b_put_1__SEL_1 ?
2'd1 :
MUX_theMem_iCache_fillCount$write_1__VAL_2 ;
assign theMem_iCache_fillCount$EN =
WILL_FIRE_RL_theMem_iCache_getMemoryResponse &&
theMem_iCache_missCached ||
WILL_FIRE_RL_theMem_iCache_updateCache &&
theMem_iCache_fillCount != 2'b11 ;
// register theMem_iCache_missCached
assign theMem_iCache_missCached$D_IN =
theCP0$tlbLookupInstruction_response_get[6] ;
assign theMem_iCache_missCached$EN =
MUX_theMem_iCache_cacheState$write_1__SEL_2 ;
// register theMem_iCache_phyAddrReg
assign theMem_iCache_phyAddrReg$D_IN =
theCP0$tlbLookupInstruction_response_get[49:14] ;
assign theMem_iCache_phyAddrReg$EN =
MUX_theMem_iCache_cacheState$write_1__SEL_2 ;
// register theMem_iCache_tags_serverAdapterA_cnt
assign theMem_iCache_tags_serverAdapterA_cnt$D_IN =
theMem_iCache_tags_serverAdapterA_cnt_122_PLUS_ETC___d1128 ;
assign theMem_iCache_tags_serverAdapterA_cnt$EN =
theMem_iCache_tags_serverAdapterA_cnt_1$whas ||
theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas ;
// register theMem_iCache_tags_serverAdapterA_s1
assign theMem_iCache_tags_serverAdapterA_s1$D_IN =
{ theMem_iCache_tags_serverAdapterA_writeWithResp$whas &&
theMem_iCache_tags_serverAdapterA_s1_1$wget[1],
theMem_iCache_tags_serverAdapterA_s1_1$wget[0] } ;
assign theMem_iCache_tags_serverAdapterA_s1$EN = 1'd1 ;
// register theMem_iCache_tags_serverAdapterB_cnt
assign theMem_iCache_tags_serverAdapterB_cnt$D_IN =
theMem_iCache_tags_serverAdapterB_cnt +
(theMem_iCache_tags_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
3'd0 ;
assign theMem_iCache_tags_serverAdapterB_cnt$EN =
theMem_iCache_tags_serverAdapterB_cnt_1$whas ;
// register theMem_iCache_tags_serverAdapterB_s1
assign theMem_iCache_tags_serverAdapterB_s1$D_IN =
{ WILL_FIRE_RL_theMem_iCache_tags_serverAdapterB_stageReadResponseAlways &&
theMem_iCache_tags_serverAdapterB_s1_1$wget[1],
theMem_iCache_tags_serverAdapterB_s1_1$wget[0] } ;
assign theMem_iCache_tags_serverAdapterB_s1$EN = 1'd1 ;
// register theMem_iCache_updateReg
assign theMem_iCache_updateReg$D_IN = theMem_theMemMerge_rsp_fifos$D_OUT ;
assign theMem_iCache_updateReg$EN =
WILL_FIRE_RL_theMem_iCache_getMemoryResponse ;
// register theMem_iCache_validFillLine
assign theMem_iCache_validFillLine$D_IN =
MUX_theMem_iCache_bank_memory$b_put_1__SEL_1 ;
assign theMem_iCache_validFillLine$EN =
WILL_FIRE_RL_theMem_iCache_getMemoryResponse &&
theMem_iCache_missCached ||
WILL_FIRE_RL_theMem_iCache_doRead &&
theCP0$tlbLookupInstruction_response_get[13:9] == 5'd25 &&
(!theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384 ||
!theMem_iCache_tags_serverAdapterA_outData_outData$wget[0] ||
!theCP0$tlbLookupInstruction_response_get[6]) ;
// register theMem_iCache_virAddrReg
assign theMem_iCache_virAddrReg$D_IN =
theMem_iCache_req_fifo$D_OUT[127:64] ;
assign theMem_iCache_virAddrReg$EN =
MUX_theMem_iCache_cacheState$write_1__SEL_2 ;
// register theRF_count
assign theRF_count$D_IN = theRF_count + 5'd1 ;
assign theRF_count$EN = !theRF_regFileState ;
// register theRF_regFileState
assign theRF_regFileState$D_IN = 1'd1 ;
assign theRF_regFileState$EN = !theRF_regFileState && theRF_count == 5'd31 ;
// register writeback_cyclCount
assign writeback_cyclCount$D_IN = writeback_cyclCount + 16'd1 ;
assign writeback_cyclCount$EN = 1'd1 ;
// register writeback_instCount
always@(MUX_writeback_instCount$write_1__SEL_1 or
MUX_writeback_instCount$write_1__VAL_1 or
MUX_writeback_instCount$write_1__SEL_2 or
MUX_writeback_instCount$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_writeback_instCount$write_1__SEL_1:
writeback_instCount$D_IN = MUX_writeback_instCount$write_1__VAL_1;
MUX_writeback_instCount$write_1__SEL_2:
writeback_instCount$D_IN = MUX_writeback_instCount$write_1__VAL_1;
MUX_writeback_instCount$write_1__SEL_3:
writeback_instCount$D_IN = MUX_writeback_instCount$write_1__VAL_1;
default: writeback_instCount$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign writeback_instCount$EN =
WILL_FIRE_RL_writeback_doWriteBack &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25 ;
// register writeback_lsInCycCt
assign writeback_lsInCycCt$D_IN = writeback_cyclCount ;
assign writeback_lsInCycCt$EN =
WILL_FIRE_RL_writeback_doWriteBack &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25 ;
// submodule branch
assign branch$getPc_fromDebug = !WILL_FIRE_RL_instructionFetch ;
assign branch$getPc_id = nextId ;
always@(WILL_FIRE_RL_writeback_doWriteBack or
MUX_branch$pcWriteback_2__VAL_1 or
WILL_FIRE_RL_writeback_doWriteBackWithRead or
MUX_branch$pcWriteback_2__VAL_2 or
WILL_FIRE_RL_writeback_doWriteBackWithWrite or
MUX_branch$pcWriteback_2__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_writeback_doWriteBack:
branch$pcWriteback_exception = MUX_branch$pcWriteback_2__VAL_1;
WILL_FIRE_RL_writeback_doWriteBackWithRead:
branch$pcWriteback_exception = MUX_branch$pcWriteback_2__VAL_2;
WILL_FIRE_RL_writeback_doWriteBackWithWrite:
branch$pcWriteback_exception = MUX_branch$pcWriteback_2__VAL_3;
default: branch$pcWriteback_exception = 1'b0 /* unspecified value */ ;
endcase
end
assign branch$pcWriteback_fromDebug = memAccessToWriteback$D_OUT[1] ;
always@(WILL_FIRE_RL_writeback_doWriteBack or
MUX_branch$pcWriteback_1__VAL_1 or
WILL_FIRE_RL_writeback_doWriteBackWithRead or
MUX_branch$pcWriteback_1__VAL_2 or
WILL_FIRE_RL_writeback_doWriteBackWithWrite or
MUX_branch$pcWriteback_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_writeback_doWriteBack:
branch$pcWriteback_truePc = MUX_branch$pcWriteback_1__VAL_1;
WILL_FIRE_RL_writeback_doWriteBackWithRead:
branch$pcWriteback_truePc = MUX_branch$pcWriteback_1__VAL_2;
WILL_FIRE_RL_writeback_doWriteBackWithWrite:
branch$pcWriteback_truePc = MUX_branch$pcWriteback_1__VAL_3;
default: branch$pcWriteback_truePc =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign branch$putRegisterTarget_fromDebug = decode_inQ$D_OUT[1] ;
assign branch$putRegisterTarget_id = decode_inQ$D_OUT[444:441] ;
assign branch$putRegisterTarget_instEpoch = decode_inQ$D_OUT[440:438] ;
assign branch$putRegisterTarget_target = theRF_regFile$D_OUT_2 ;
assign branch$putTarget_branchType =
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8006 ;
assign branch$putTarget_fromDebug = fetchedControlToken$D_OUT[1] ;
assign branch$putTarget_id = fetchedControlToken$D_OUT[444:441] ;
assign branch$putTarget_instEpoch = fetchedControlToken$D_OUT[440:438] ;
assign branch$putTarget_target =
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9106) ?
branchTarget__h285642 :
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7227 ;
assign branch$EN_getPc =
WILL_FIRE_RL_instructionFetch ||
WILL_FIRE_RL_debugInstructionFetch ;
assign branch$EN_putTarget = WILL_FIRE_RL_registerFetch ;
assign branch$EN_putRegisterTarget =
WILL_FIRE_RL_doDecode && decode_inQ$D_OUT[395:394] == 2'd3 ;
assign branch$EN_pcWriteback =
WILL_FIRE_RL_writeback_doWriteBack ||
WILL_FIRE_RL_writeback_doWriteBackWithRead ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite ;
// submodule decode_inQ
assign decode_inQ$D_IN =
{ fetchedControlToken$D_OUT[444:436],
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7277,
lastWasBranch_778_AND_lastEpoch_779_EQ_fetched_ETC___d7511 } ;
assign decode_inQ$ENQ = WILL_FIRE_RL_registerFetch ;
assign decode_inQ$DEQ = WILL_FIRE_RL_doDecode ;
assign decode_inQ$CLR = 1'b0 ;
// submodule execute_hiLoPending
assign execute_hiLoPending$D_IN = 1'd1 ;
assign execute_hiLoPending$ENQ =
WILL_FIRE_RL_execute_doExecute &&
execute_inQ$D_OUT[14:13] == 2'd3 &&
execute_inQ$D_OUT[400:397] == 4'd9 &&
(execute_inQ$D_OUT[379:375] == 5'd12 ||
execute_inQ$D_OUT[379:375] == 5'd13 ||
execute_inQ$D_OUT[379:375] == 5'd14 ||
execute_inQ$D_OUT[379:375] == 5'd15 ||
execute_inQ$D_OUT[379:375] == 5'd16 ||
execute_inQ$D_OUT[379:375] == 5'd17 ||
execute_inQ$D_OUT[379:375] == 5'd18) ;
assign execute_hiLoPending$DEQ =
WILL_FIRE_RL_execute_deliverPendingOp ||
WILL_FIRE_RL_execute_finishMultiplyOrDivide ;
assign execute_hiLoPending$CLR = 1'b0 ;
// submodule execute_inQ
assign execute_inQ$D_IN =
{ decode_inQ$D_OUT[444:436],
CASE_decode_inQD_OUT_BITS_435_TO_434_3_0_deco_ETC__q202,
decode_inQ$D_OUT[433:401],
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7996,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6374 } ;
assign execute_inQ$ENQ = WILL_FIRE_RL_doDecode ;
assign execute_inQ$DEQ = WILL_FIRE_RL_execute_doExecute ;
assign execute_inQ$CLR = 1'b0 ;
// submodule execute_mul
assign execute_mul$muldiv_request_put =
{ execute_inQ$D_OUT[381:375],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828,
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829,
execute_lo,
execute_hi } ;
assign execute_mul$EN_muldiv_request_put =
WILL_FIRE_RL_execute_doExecute &&
execute_inQ$D_OUT[14:13] == 2'd3 &&
execute_inQ$D_OUT[400:397] == 4'd9 &&
(execute_inQ$D_OUT[379:375] == 5'd12 ||
execute_inQ$D_OUT[379:375] == 5'd13 ||
execute_inQ$D_OUT[379:375] == 5'd14 ||
execute_inQ$D_OUT[379:375] == 5'd15 ||
execute_inQ$D_OUT[379:375] == 5'd16 ||
execute_inQ$D_OUT[379:375] == 5'd17 ||
execute_inQ$D_OUT[379:375] == 5'd18) ;
assign execute_mul$EN_muldiv_response_get =
WILL_FIRE_RL_execute_deliverPendingOp ||
WILL_FIRE_RL_execute_finishMultiplyOrDivide ;
// submodule execute_pendingOps
assign execute_pendingOps$D_IN =
{ execute_inQ$D_OUT[444:436],
IF_execute_inQ_first__341_BITS_435_TO_434_699__ETC___d7888,
execute_inQ$D_OUT[401:393],
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597[64],
execute_inQ_first__341_BITS_391_TO_384_433_CON_ETC___d4520 } ;
assign execute_pendingOps$ENQ =
WILL_FIRE_RL_execute_doExecute &&
execute_inQ$D_OUT[14:13] == 2'd3 &&
execute_inQ$D_OUT[400:397] == 4'd9 &&
execute_inQ$D_OUT[379:375] == 5'd14 ;
assign execute_pendingOps$DEQ = WILL_FIRE_RL_execute_deliverPendingOp ;
assign execute_pendingOps$CLR = 1'b0 ;
// submodule fetchedControlToken
assign fetchedControlToken$D_IN =
WILL_FIRE_RL_instructionFetch ?
MUX_fetchedControlToken$enq_1__VAL_1 :
MUX_fetchedControlToken$enq_1__VAL_2 ;
assign fetchedControlToken$ENQ =
WILL_FIRE_RL_instructionFetch ||
WILL_FIRE_RL_debugInstructionFetch ;
assign fetchedControlToken$DEQ = WILL_FIRE_RL_registerFetch ;
assign fetchedControlToken$CLR = 1'b0 ;
// submodule freeRenameReg
assign freeRenameReg$D_IN =
MUX_freeRenameReg$enq_1__SEL_1 ?
memAccessToWriteback$D_OUT[437:436] :
2'd0 ;
assign freeRenameReg$ENQ = freeRenameReg_r_enq$whas ;
assign freeRenameReg$DEQ = WILL_FIRE_RL_registerFetch ;
assign freeRenameReg$CLR = 1'b0 ;
// submodule memAccessToWriteback
assign memAccessToWriteback$D_IN =
WILL_FIRE_RL_memAccess_doMemAccess ?
MUX_memAccessToWriteback$enq_1__VAL_1 :
MUX_memAccessToWriteback$enq_1__VAL_2 ;
assign memAccessToWriteback$ENQ =
WILL_FIRE_RL_memAccess_doMemAccess ||
WILL_FIRE_RL_memAccess_doDummy ;
assign memAccessToWriteback$DEQ = MUX_freeRenameReg$enq_1__SEL_1 ;
assign memAccessToWriteback$CLR = 1'b0 ;
// submodule memAccess_inQ
assign memAccess_inQ$D_IN =
MUX_memAccess_inQ$enq_1__SEL_1 ?
MUX_memAccess_inQ$enq_1__VAL_1 :
MUX_memAccess_inQ$enq_1__VAL_2 ;
assign memAccess_inQ$ENQ =
WILL_FIRE_RL_execute_doExecute &&
(execute_inQ$D_OUT[379:375] != 5'd14 ||
execute_inQ$D_OUT[400:397] != 4'd9 ||
execute_inQ$D_OUT[14:13] != 2'd3) ||
WILL_FIRE_RL_execute_deliverPendingOp ;
assign memAccess_inQ$DEQ =
WILL_FIRE_RL_memAccess_doDummy ||
WILL_FIRE_RL_memAccess_doMemAccess ;
assign memAccess_inQ$CLR = 1'b0 ;
// submodule theCP0
assign theCP0$getLlScReg_matchAddress =
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d9064 ;
assign theCP0$interrupts_interruptLines = putIrqs_interruptLines ;
always@(WILL_FIRE_RL_writeback_doWriteBack or
MUX_theCP0$putException_1__VAL_1 or
WILL_FIRE_RL_writeback_doWriteBackWithRead or
MUX_theCP0$putException_1__VAL_2 or
WILL_FIRE_RL_writeback_doWriteBackWithWrite or
MUX_theCP0$putException_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_writeback_doWriteBack:
theCP0$putException_exp = MUX_theCP0$putException_1__VAL_1;
WILL_FIRE_RL_writeback_doWriteBackWithRead:
theCP0$putException_exp = MUX_theCP0$putException_1__VAL_2;
WILL_FIRE_RL_writeback_doWriteBackWithWrite:
theCP0$putException_exp = MUX_theCP0$putException_1__VAL_3;
default: theCP0$putException_exp =
139'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theCP0$readGet_goingToWrite = decode_inQ$D_OUT[383:382] == 2'd1 ;
assign theCP0$readReq_rn =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
5'b0 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst__h286177 :
5'b0) ;
assign theCP0$readReq_sel =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
3'b0 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd__h286178 :
3'b0) ;
assign theCP0$tlbLookupCoprocessors_0_request_put =
{ theCapCop_capMemInsts$D_OUT[75:12],
theCapCop_capMemInsts$D_OUT[337:333] != 5'd10,
6'd25,
theCapCop_capMemInsts$D_OUT[6:3] } ;
assign theCP0$tlbLookupData_request_put =
{ memAccess_inQ$D_OUT[293:230],
(memAccess_inQ$D_OUT[14:13] == 2'd0) ?
{ 1'd0,
memAccess_inQ$D_OUT[374:372] == 3'd4,
5'd25,
memAccess_inQ$D_OUT[444:441] } :
{ 7'd89, memAccess_inQ$D_OUT[444:441] } } ;
assign theCP0$tlbLookupInstruction_request_put =
WILL_FIRE_RL_instructionFetch ?
MUX_theCP0$tlbLookupInstruction_request_put_1__VAL_1 :
MUX_theCP0$tlbLookupInstruction_request_put_1__VAL_2 ;
assign theCP0$writeReg_data =
(MUX_theCP0$writeReg_1__SEL_2 || MUX_theCP0$writeReg_1__SEL_3) ?
memAccessToWriteback$D_OUT[293:230] :
result__h176159 ;
assign theCP0$writeReg_forceKernelMode = memAccessToWriteback$D_OUT[1] ;
assign theCP0$writeReg_rn = memAccessToWriteback$D_OUT[391:387] ;
always@(MUX_theCP0$writeReg_1__SEL_1 or
MUX_theCP0$writeReg_4__VAL_1 or
MUX_theCP0$writeReg_1__SEL_2 or
MUX_theCP0$writeReg_4__VAL_2 or
MUX_theCP0$writeReg_1__SEL_3 or MUX_theCP0$writeReg_4__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theCP0$writeReg_1__SEL_1:
theCP0$writeReg_writeBack = MUX_theCP0$writeReg_4__VAL_1;
MUX_theCP0$writeReg_1__SEL_2:
theCP0$writeReg_writeBack = MUX_theCP0$writeReg_4__VAL_2;
MUX_theCP0$writeReg_1__SEL_3:
theCP0$writeReg_writeBack = MUX_theCP0$writeReg_4__VAL_3;
default: theCP0$writeReg_writeBack = 1'b0 /* unspecified value */ ;
endcase
end
assign theCP0$EN_readReq = WILL_FIRE_RL_registerFetch ;
assign theCP0$EN_readGet = WILL_FIRE_RL_doDecode ;
assign theCP0$EN_writeReg =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback$D_OUT[383:382] == 2'd1 ||
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback$D_OUT[383:382] == 2'd1 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback$D_OUT[383:382] == 2'd1 ;
assign theCP0$EN_getException = MUX_freeRenameReg$enq_1__SEL_1 ;
assign theCP0$EN_putException =
WILL_FIRE_RL_writeback_doWriteBack ||
WILL_FIRE_RL_writeback_doWriteBackWithRead ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite ;
assign theCP0$EN_interrupts = EN_putIrqs ;
assign theCP0$EN_getExceptionReturn = MUX_theCapCop_exception$enq_1__SEL_2 ;
assign theCP0$EN_tlbLookupInstruction_request_put =
WILL_FIRE_RL_instructionFetch ||
WILL_FIRE_RL_debugInstructionFetch ;
assign theCP0$EN_tlbLookupInstruction_response_get =
WILL_FIRE_RL_theMem_iCache_respondDuringUpdate ||
WILL_FIRE_RL_theMem_iCache_doRead ;
assign theCP0$EN_tlbLookupData_request_put =
WILL_FIRE_RL_memAccess_doMemAccess &&
(memAccess_inQ$D_OUT[14:13] == 2'd0 ||
memAccess_inQ$D_OUT[14:13] == 2'd1 &&
CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197 &&
(memAccess_inQ$D_OUT[374:372] != 3'd5 ||
memAccess_inQ$D_OUT[166])) ;
assign theCP0$EN_tlbLookupData_response_get =
WILL_FIRE_RL_writeback_doWriteBackWithWrite ||
WILL_FIRE_RL_theMem_dCache_checkTags ;
assign theCP0$EN_tlbLookupCoprocessors_0_request_put =
WILL_FIRE_RL_capToMem ;
assign theCP0$EN_tlbLookupCoprocessors_0_response_get =
theCP0$RDY_tlbLookupCoprocessors_0_response_get &&
theMem_capTlbResp$FULL_N &&
theMem_capExceptions$FULL_N ;
// submodule theCapCop_baseRegs
assign theCapCop_baseRegs$ADDR_1 = theCapCop_fetchFifoB$D_OUT ;
assign theCapCop_baseRegs$ADDR_2 = theCapCop_fetchFifoA$D_OUT ;
assign theCapCop_baseRegs$ADDR_3 = 5'h0 ;
assign theCapCop_baseRegs$ADDR_4 = 5'h0 ;
assign theCapCop_baseRegs$ADDR_5 = 5'h0 ;
always@(MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or
theCapCop_capState or
theCapCop_count or MUX_theCapCop_baseRegs$upd_1__SEL_1)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_baseRegs$ADDR_IN = theCapCop_capWriteback[11:7];
theCapCop_capState == 3'd0:
theCapCop_baseRegs$ADDR_IN = theCapCop_count;
MUX_theCapCop_baseRegs$upd_1__SEL_1: theCapCop_baseRegs$ADDR_IN = 5'd31;
default: theCapCop_baseRegs$ADDR_IN = 5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_theCapCop_baseRegs$upd_1__SEL_1 or
theCapCop_pcc or
MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or theCapCop_capState)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_1:
theCapCop_baseRegs$D_IN = theCapCop_pcc[127:64];
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_baseRegs$D_IN = theCapCop_capWriteback[139:76];
theCapCop_capState == 3'd0: theCapCop_baseRegs$D_IN = 64'b0;
default: theCapCop_baseRegs$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theCapCop_baseRegs$WE =
WILL_FIRE_RL_theCapCop_startException &&
!theCapCop_exception$D_OUT ||
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2714 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2980 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d3191 ||
theCapCop_capState == 3'd0 ;
// submodule theCapCop_capInsts
assign theCapCop_capInsts$D_IN =
{ IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7586,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7585,
x1_avValue_snd_snd_snd_snd_snd_snd_operand__h242915,
x1_avValue_snd_snd_snd_snd_snd_snd_select__h242916,
1'd0,
decode_inQ$D_OUT[444:438],
x__h243627,
x__h243635 } ;
assign theCapCop_capInsts$ENQ = WILL_FIRE_RL_doDecode ;
assign theCapCop_capInsts$DEQ = WILL_FIRE_RL_execute_doExecute ;
assign theCapCop_capInsts$CLR = 1'b0 ;
// submodule theCapCop_capMemInsts
assign theCapCop_capMemInsts$D_IN =
{ (theCapCop_capInsts$D_OUT[99:95] == 5'd10) ?
theCapCop_capInsts$D_OUT[99:95] :
5'd9,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d7882,
IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d3537 } ;
assign theCapCop_capMemInsts$ENQ =
WILL_FIRE_RL_execute_doExecute &&
(theCapCop_capInsts$D_OUT[99:95] == 5'd10 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd9) ;
assign theCapCop_capMemInsts$DEQ =
WILL_FIRE_RL_capToMem &&
theCapCop_capMemInsts$D_OUT[337:333] != 5'd10 ||
WILL_FIRE_RL_memToCap ;
assign theCapCop_capMemInsts$CLR = 1'b0 ;
// submodule theCapCop_capWritebackTags
assign theCapCop_capWritebackTags$D_IN =
MUX_theCapCop_capWritebackTags$enq_1__SEL_1 ?
MUX_theCapCop_capWritebackTags$enq_1__VAL_1 :
MUX_theCapCop_capWritebackTags$enq_1__VAL_2 ;
assign theCapCop_capWritebackTags$ENQ =
WILL_FIRE_RL_execute_doExecute &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 ||
WILL_FIRE_RL_memToCap ;
assign theCapCop_capWritebackTags$DEQ =
MUX_freeRenameReg$enq_1__SEL_1 &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 ;
assign theCapCop_capWritebackTags$CLR = 1'b0 ;
// submodule theCapCop_commitStore
assign theCapCop_commitStore$D_IN = 1'b0 ;
assign theCapCop_commitStore$ENQ = 1'b0 ;
assign theCapCop_commitStore$DEQ = 1'b0 ;
assign theCapCop_commitStore$CLR = 1'b0 ;
// submodule theCapCop_exception
assign theCapCop_exception$D_IN =
!WILL_FIRE_RL_reportExceptionToCapabilityCoprocessor ;
assign theCapCop_exception$ENQ =
WILL_FIRE_RL_reportExceptionToCapabilityCoprocessor ||
CAN_FIRE_RL_reportExceptionReturnToCapabilityCoprocessor &&
!WILL_FIRE_RL_reportExceptionToCapabilityCoprocessor ;
assign theCapCop_exception$DEQ = WILL_FIRE_RL_theCapCop_finishException ;
assign theCapCop_exception$CLR = 1'b0 ;
// submodule theCapCop_fetchFifoA
assign theCapCop_fetchFifoA$D_IN =
WILL_FIRE_RL_theCapCop_startException ?
MUX_theCapCop_fetchFifoA$enq_1__VAL_1 :
MUX_theCapCop_fetchFifoA$enq_1__VAL_2 ;
assign theCapCop_fetchFifoA$ENQ =
WILL_FIRE_RL_theCapCop_startException || WILL_FIRE_RL_doDecode ;
assign theCapCop_fetchFifoA$DEQ =
WILL_FIRE_RL_execute_doExecute ||
WILL_FIRE_RL_theCapCop_finishException ;
assign theCapCop_fetchFifoA$CLR = 1'b0 ;
// submodule theCapCop_fetchFifoB
assign theCapCop_fetchFifoB$D_IN =
(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd9 &&
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 !=
5'd10 ||
decode_inQ$D_OUT[435:434] == 2'd0 ||
decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2) ?
5'd0 :
IF_NOT_decode_inQ_first__909_BITS_435_TO_434_9_ETC___d7594 ;
assign theCapCop_fetchFifoB$ENQ = WILL_FIRE_RL_doDecode ;
assign theCapCop_fetchFifoB$DEQ = WILL_FIRE_RL_execute_doExecute ;
assign theCapCop_fetchFifoB$CLR = 1'b0 ;
// submodule theCapCop_insts
assign theCapCop_insts$D_IN = 1'd1 ;
assign theCapCop_insts$ENQ =
MUX_theMem_iCache_bank_serverAdapterA_writeWithResp$wset_1__SEL_2 ;
assign theCapCop_insts$DEQ = MUX_freeRenameReg$enq_1__SEL_1 ;
assign theCapCop_insts$CLR = 1'b0 ;
// submodule theCapCop_lengthRegs
assign theCapCop_lengthRegs$ADDR_1 = theCapCop_fetchFifoB$D_OUT ;
assign theCapCop_lengthRegs$ADDR_2 = theCapCop_fetchFifoA$D_OUT ;
assign theCapCop_lengthRegs$ADDR_3 = 5'h0 ;
assign theCapCop_lengthRegs$ADDR_4 = 5'h0 ;
assign theCapCop_lengthRegs$ADDR_5 = 5'h0 ;
always@(MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or
theCapCop_capState or
theCapCop_count or MUX_theCapCop_baseRegs$upd_1__SEL_1)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_lengthRegs$ADDR_IN = theCapCop_capWriteback[11:7];
theCapCop_capState == 3'd0:
theCapCop_lengthRegs$ADDR_IN = theCapCop_count;
MUX_theCapCop_baseRegs$upd_1__SEL_1:
theCapCop_lengthRegs$ADDR_IN = 5'd31;
default: theCapCop_lengthRegs$ADDR_IN =
5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_theCapCop_baseRegs$upd_1__SEL_1 or
theCapCop_pcc or
MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or theCapCop_capState)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_1:
theCapCop_lengthRegs$D_IN = theCapCop_pcc[63:0];
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_lengthRegs$D_IN = theCapCop_capWriteback[75:12];
theCapCop_capState == 3'd0:
theCapCop_lengthRegs$D_IN = 64'hFFFFFFFFFFFFFFFF;
default: theCapCop_lengthRegs$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theCapCop_lengthRegs$WE =
WILL_FIRE_RL_theCapCop_startException &&
!theCapCop_exception$D_OUT ||
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2714 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2980 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d3191 ||
theCapCop_capState == 3'd0 ;
// submodule theCapCop_memResponse
assign theCapCop_memResponse$D_IN = 256'h0 ;
assign theCapCop_memResponse$ENQ = 1'b0 ;
assign theCapCop_memResponse$DEQ = 1'b0 ;
assign theCapCop_memResponse$CLR = 1'b0 ;
// submodule theCapCop_nextCapState
assign theCapCop_nextCapState$D_IN = 3'h0 ;
assign theCapCop_nextCapState$ENQ = 1'b0 ;
assign theCapCop_nextCapState$DEQ = 1'b0 ;
assign theCapCop_nextCapState$CLR = 1'b0 ;
// submodule theCapCop_nextWillWriteback
assign theCapCop_nextWillWriteback$D_IN =
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd4 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd7 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd1 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd10 ;
assign theCapCop_nextWillWriteback$ENQ = WILL_FIRE_RL_doDecode ;
assign theCapCop_nextWillWriteback$DEQ = WILL_FIRE_RL_execute_doExecute ;
assign theCapCop_nextWillWriteback$CLR = 1'b0 ;
// submodule theCapCop_oTypeRegs
assign theCapCop_oTypeRegs$ADDR_1 = theCapCop_fetchFifoA$D_OUT ;
assign theCapCop_oTypeRegs$ADDR_2 = 5'h0 ;
assign theCapCop_oTypeRegs$ADDR_3 = 5'h0 ;
assign theCapCop_oTypeRegs$ADDR_4 = 5'h0 ;
assign theCapCop_oTypeRegs$ADDR_5 = 5'h0 ;
always@(MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or
theCapCop_capState or
theCapCop_count or MUX_theCapCop_baseRegs$upd_1__SEL_1)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_oTypeRegs$ADDR_IN = theCapCop_capWriteback[11:7];
theCapCop_capState == 3'd0:
theCapCop_oTypeRegs$ADDR_IN = theCapCop_count;
MUX_theCapCop_baseRegs$upd_1__SEL_1:
theCapCop_oTypeRegs$ADDR_IN = 5'd31;
default: theCapCop_oTypeRegs$ADDR_IN =
5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_theCapCop_baseRegs$upd_1__SEL_1 or
theCapCop_pcc or
MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or theCapCop_capState)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_1:
theCapCop_oTypeRegs$D_IN = theCapCop_pcc[191:128];
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_oTypeRegs$D_IN = theCapCop_capWriteback[203:140];
theCapCop_capState == 3'd0: theCapCop_oTypeRegs$D_IN = 64'b0;
default: theCapCop_oTypeRegs$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theCapCop_oTypeRegs$WE =
WILL_FIRE_RL_theCapCop_startException &&
!theCapCop_exception$D_OUT ||
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2714 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2980 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d3191 ||
theCapCop_capState == 3'd0 ;
// submodule theCapCop_permRegs
assign theCapCop_permRegs$ADDR_1 = theCapCop_fetchFifoA$D_OUT ;
assign theCapCop_permRegs$ADDR_2 = 5'h0 ;
assign theCapCop_permRegs$ADDR_3 = 5'h0 ;
assign theCapCop_permRegs$ADDR_4 = 5'h0 ;
assign theCapCop_permRegs$ADDR_5 = 5'h0 ;
always@(MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or
theCapCop_capState or
theCapCop_count or MUX_theCapCop_baseRegs$upd_1__SEL_1)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_permRegs$ADDR_IN = theCapCop_capWriteback[11:7];
theCapCop_capState == 3'd0:
theCapCop_permRegs$ADDR_IN = theCapCop_count;
MUX_theCapCop_baseRegs$upd_1__SEL_1: theCapCop_permRegs$ADDR_IN = 5'd31;
default: theCapCop_permRegs$ADDR_IN = 5'b01010 /* unspecified value */ ;
endcase
end
always@(MUX_theCapCop_baseRegs$upd_1__SEL_1 or
theCapCop_pcc or
MUX_theCapCop_baseRegs$upd_1__SEL_2 or
MUX_theCapCop_baseRegs$upd_1__SEL_3 or
MUX_theCapCop_baseRegs$upd_1__SEL_4 or
theCapCop_capWriteback or theCapCop_capState)
begin
case (1'b1) // synopsys parallel_case
MUX_theCapCop_baseRegs$upd_1__SEL_1:
theCapCop_permRegs$D_IN = theCapCop_pcc[255:192];
MUX_theCapCop_baseRegs$upd_1__SEL_2 ||
MUX_theCapCop_baseRegs$upd_1__SEL_3 ||
MUX_theCapCop_baseRegs$upd_1__SEL_4:
theCapCop_permRegs$D_IN = theCapCop_capWriteback[267:204];
theCapCop_capState == 3'd0:
theCapCop_permRegs$D_IN = 64'hFFFF000000000000;
default: theCapCop_permRegs$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theCapCop_permRegs$WE =
WILL_FIRE_RL_theCapCop_startException &&
!theCapCop_exception$D_OUT ||
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2714 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2980 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 &&
theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d3191 ||
theCapCop_capState == 3'd0 ;
// submodule theCapCop_startExp
assign theCapCop_startExp$D_IN = 1'd1 ;
assign theCapCop_startExp$ENQ = WILL_FIRE_RL_theCapCop_startException ;
assign theCapCop_startExp$DEQ = WILL_FIRE_RL_theCapCop_finishException ;
assign theCapCop_startExp$CLR = 1'b0 ;
// submodule theDebug_bpReport
assign theDebug_bpReport$D_IN =
{ 152'hFF08AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
branch$getPc[66:3],
branch$getPc[18:11],
branch$getPc[26:19],
branch$getPc[34:27],
branch$getPc[42:35],
branch$getPc[50:43],
branch$getPc[58:51],
branch$getPc[66:59] } ;
assign theDebug_bpReport$ENQ =
WILL_FIRE_RL_instructionFetch &&
theDebug_bp_read__508_BIT_64_509_AND_theDebug__ETC___d7846 ;
assign theDebug_bpReport$DEQ = WILL_FIRE_RL_theDebug_reportBreakPoint ;
assign theDebug_bpReport$CLR = 1'b0 ;
// submodule theDebug_curCommand
assign theDebug_curCommand$D_IN =
MUX_theDebug_curCommand$enq_1__SEL_1 ?
MUX_theDebug_curCommand$enq_1__VAL_1 :
272'd0 ;
assign theDebug_curCommand$ENQ =
WILL_FIRE_RL_theDebug_doCommands &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ||
theDebug_debugConvert$messages_request_get[271:264] ==
8'd115) ||
WILL_FIRE_RL_theDebug_unpipelinedStep ;
assign theDebug_curCommand$DEQ =
WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction &&
theDebug_idleCount == 28'h000007F ||
WILL_FIRE_RL_theDebug_finishExecute ||
WILL_FIRE_RL_theDebug_step ;
assign theDebug_curCommand$CLR = 1'b0 ;
// submodule theDebug_debugConvert
always@(MUX_theDebug_debugConvert$messages_response_put_1__SEL_1 or
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1 or
MUX_theDebug_debugConvert$messages_response_put_1__SEL_2 or
MUX_theDebug_debugConvert$messages_response_put_1__SEL_3 or
MUX_theDebug_debugConvert$messages_response_put_1__SEL_4 or
MUX_theDebug_debugConvert$messages_response_put_1__VAL_4 or
WILL_FIRE_RL_theDebug_popTrace or
MUX_theDebug_debugConvert$messages_response_put_1__VAL_5 or
WILL_FIRE_RL_theDebug_reportBreakPoint or
MUX_theDebug_debugConvert$messages_response_put_1__VAL_6 or
WILL_FIRE_RL_theDebug_finishExecute or
MUX_theDebug_debugConvert$messages_response_put_1__VAL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_theDebug_debugConvert$messages_response_put_1__SEL_1:
theDebug_debugConvert$messages_response_put =
MUX_theDebug_debugConvert$messages_response_put_1__VAL_1;
MUX_theDebug_debugConvert$messages_response_put_1__SEL_2:
theDebug_debugConvert$messages_response_put =
272'hD3000000000000000000000000000000000000000000000000000000000000000000;
MUX_theDebug_debugConvert$messages_response_put_1__SEL_3:
theDebug_debugConvert$messages_response_put =
272'hD301000000000000000000000000000000000000000000000000000000000000001F;
MUX_theDebug_debugConvert$messages_response_put_1__SEL_4:
theDebug_debugConvert$messages_response_put =
MUX_theDebug_debugConvert$messages_response_put_1__VAL_4;
WILL_FIRE_RL_theDebug_popTrace:
theDebug_debugConvert$messages_response_put =
MUX_theDebug_debugConvert$messages_response_put_1__VAL_5;
WILL_FIRE_RL_theDebug_reportBreakPoint:
theDebug_debugConvert$messages_response_put =
MUX_theDebug_debugConvert$messages_response_put_1__VAL_6;
WILL_FIRE_RL_theDebug_finishExecute:
theDebug_debugConvert$messages_response_put =
MUX_theDebug_debugConvert$messages_response_put_1__VAL_7;
default: theDebug_debugConvert$messages_response_put =
272'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theDebug_debugConvert$stream_request_put = debugStream_request_put ;
assign theDebug_debugConvert$EN_stream_request_put =
EN_debugStream_request_put ;
assign theDebug_debugConvert$EN_stream_response_get =
EN_debugStream_response_get ;
assign theDebug_debugConvert$EN_messages_request_get =
WILL_FIRE_RL_theDebug_doCommands ;
assign theDebug_debugConvert$EN_messages_response_put =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd101 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd115 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd83 ||
WILL_FIRE_RL_theDebug_countIdleCyclesStreamTrace &&
theDebug_idleCount == 28'h000007F ||
WILL_FIRE_RL_theDebug_countIdleCyclesExecuteInstruction &&
theDebug_idleCount == 28'h000007F ||
WILL_FIRE_RL_theDebug_step &&
theDebug_curCommand$D_OUT[271:264] != 8'd0 ||
WILL_FIRE_RL_theDebug_popTrace ||
WILL_FIRE_RL_theDebug_reportBreakPoint ||
WILL_FIRE_RL_theDebug_finishExecute ;
// submodule theDebug_doneInst
assign theDebug_doneInst$D_IN = 1'd1 ;
assign theDebug_doneInst$ENQ = WILL_FIRE_RL_debugInstructionFetch ;
assign theDebug_doneInst$DEQ = WILL_FIRE_RL_theDebug_finishExecute ;
assign theDebug_doneInst$CLR = 1'b0 ;
// submodule theDebug_instQ
assign theDebug_instQ$D_IN = theDebug_instruction ;
assign theDebug_instQ$ENQ =
WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd101 ;
assign theDebug_instQ$DEQ = WILL_FIRE_RL_debugInstructionFetch ;
assign theDebug_instQ$CLR = 1'b0 ;
// submodule theDebug_trace_buf_bram
assign theDebug_trace_buf_bram$ADDRA = theDebug_trace_buf_tailPtr ;
assign theDebug_trace_buf_bram$ADDRB =
(WILL_FIRE_RL_theDebug_popTrace ||
theDebug_trace_buf_doEnq$whas &&
theDebug_trace_buf_tailPtr_read__1_PLUS_1_2_EQ_ETC___d8043) ?
theDebug_trace_buf_headPtr + 12'd1 :
theDebug_trace_buf_headPtr ;
assign theDebug_trace_buf_bram$DIA = x__h168654 ;
assign theDebug_trace_buf_bram$DIB =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign theDebug_trace_buf_bram$WEA = 1'd1 ;
assign theDebug_trace_buf_bram$WEB = 1'd0 ;
assign theDebug_trace_buf_bram$ENA = theDebug_trace_buf_doEnq$whas ;
assign theDebug_trace_buf_bram$ENB = 1'd1 ;
// submodule theDebug_writebacks
always@(MUX_theDebug_writebacks$enq_1__SEL_1 or
MUX_theDebug_writebacks$enq_1__VAL_1 or
MUX_theDebug_writebacks$enq_1__SEL_2 or
MUX_theDebug_writebacks$enq_1__VAL_2 or
MUX_theDebug_writebacks$enq_1__SEL_3 or
MUX_theDebug_writebacks$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theDebug_writebacks$enq_1__SEL_1:
theDebug_writebacks$D_IN = MUX_theDebug_writebacks$enq_1__VAL_1;
MUX_theDebug_writebacks$enq_1__SEL_2:
theDebug_writebacks$D_IN = MUX_theDebug_writebacks$enq_1__VAL_2;
MUX_theDebug_writebacks$enq_1__SEL_3:
theDebug_writebacks$D_IN = MUX_theDebug_writebacks$enq_1__VAL_3;
default: theDebug_writebacks$D_IN =
70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theDebug_writebacks$ENQ =
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback$D_OUT[1] ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback$D_OUT[1] ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback$D_OUT[1] ;
assign theDebug_writebacks$DEQ = WILL_FIRE_RL_theDebug_finishExecute ;
assign theDebug_writebacks$CLR = 1'b0 ;
// submodule theMem_capExceptions
assign theMem_capExceptions$D_IN =
{ theCP0$tlbLookupCoprocessors_0_response_get[13:9],
theCP0$tlbLookupCoprocessors_0_response_get[3:0] } ;
assign theMem_capExceptions$ENQ =
theCP0$RDY_tlbLookupCoprocessors_0_response_get &&
theMem_capTlbResp$FULL_N &&
theMem_capExceptions$FULL_N ;
assign theMem_capExceptions$DEQ =
MUX_freeRenameReg$enq_1__SEL_1 && theMem_capExceptions$EMPTY_N &&
theMem_capExceptions_first__525_BITS_3_TO_0_52_ETC___d8708 ;
assign theMem_capExceptions$CLR = 1'b0 ;
// submodule theMem_capPackets
assign theMem_capPackets$D_IN =
{ (theCapCop_capMemInsts$D_OUT[337:333] == 5'd10) ? 2'd0 : 2'd1,
theCapCop_capMemInsts$D_OUT[75:12],
theCapCop_capMemInsts$D_OUT[332:77],
theCapCop_capMemInsts$D_OUT[6:3] } ;
assign theMem_capPackets$ENQ = WILL_FIRE_RL_capToMem ;
assign theMem_capPackets$DEQ = WILL_FIRE_RL_theMem_submitCapRequest ;
assign theMem_capPackets$CLR = 1'b0 ;
// submodule theMem_capTlbResp
assign theMem_capTlbResp$D_IN =
theCP0$tlbLookupCoprocessors_0_response_get ;
assign theMem_capTlbResp$ENQ =
theCP0$RDY_tlbLookupCoprocessors_0_response_get &&
theMem_capTlbResp$FULL_N &&
theMem_capExceptions$FULL_N ;
assign theMem_capTlbResp$DEQ = WILL_FIRE_RL_theMem_submitCapRequest ;
assign theMem_capTlbResp$CLR = 1'b0 ;
// submodule theMem_commitCapStore
assign theMem_commitCapStore$D_IN = MUX_theCP0$writeReg_4__VAL_2 ;
assign theMem_commitCapStore$ENQ =
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback$D_OUT[435:434] != 2'd0 &&
memAccessToWriteback$D_OUT[435:434] != 2'd1 &&
memAccessToWriteback$D_OUT[435:434] != 2'd2 &&
memAccessToWriteback$D_OUT[433:428] == 6'd18 &&
memAccessToWriteback$D_OUT[427:423] == 5'd9 ;
assign theMem_commitCapStore$DEQ =
WILL_FIRE_RL_theMem_submitCapRequest &&
theMem_capPackets$D_OUT[325:324] == 2'd1 ;
assign theMem_commitCapStore$CLR = 1'b0 ;
// submodule theMem_dCache_data_memory
assign theMem_dCache_data_memory$ADDRA =
MUX_theMem_dCache_data_memory$a_put_1__SEL_1 ?
MUX_theMem_dCache_data_memory$a_put_2__VAL_1 :
MUX_theMem_dCache_data_memory$a_put_2__VAL_2 ;
always@(MUX_theMem_dCache_data_memory$b_put_1__SEL_1 or
MUX_theMem_dCache_data_memory$b_put_2__VAL_1 or
MUX_theMem_dCache_data_memory$b_put_1__SEL_2 or
MUX_theMem_dCache_data_memory$a_put_2__VAL_1 or
WILL_FIRE_RL_theMem_dCache_updateCache or
MUX_theMem_dCache_data_memory$b_put_2__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_dCache_data_memory$b_put_1__SEL_1:
theMem_dCache_data_memory$ADDRB =
MUX_theMem_dCache_data_memory$b_put_2__VAL_1;
MUX_theMem_dCache_data_memory$b_put_1__SEL_2:
theMem_dCache_data_memory$ADDRB =
MUX_theMem_dCache_data_memory$a_put_2__VAL_1;
WILL_FIRE_RL_theMem_dCache_updateCache:
theMem_dCache_data_memory$ADDRB =
MUX_theMem_dCache_data_memory$b_put_2__VAL_3;
default: theMem_dCache_data_memory$ADDRB =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign theMem_dCache_data_memory$DIA =
MUX_theMem_dCache_data_memory$a_put_1__SEL_1 ?
64'hAAAAAAAAAAAAAAAA /* unspecified value */ :
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
always@(MUX_theMem_dCache_data_memory$b_put_1__SEL_1 or
theMem_theMemMerge_rsp_fifos_1$D_OUT or
MUX_theMem_dCache_data_memory$b_put_1__SEL_2 or
dataRead___1__h189582 or
WILL_FIRE_RL_theMem_dCache_updateCache or
MUX_theMem_dCache_data_memory$b_put_3__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_dCache_data_memory$b_put_1__SEL_1:
theMem_dCache_data_memory$DIB =
theMem_theMemMerge_rsp_fifos_1$D_OUT[63:0];
MUX_theMem_dCache_data_memory$b_put_1__SEL_2:
theMem_dCache_data_memory$DIB = dataRead___1__h189582;
WILL_FIRE_RL_theMem_dCache_updateCache:
theMem_dCache_data_memory$DIB =
MUX_theMem_dCache_data_memory$b_put_3__VAL_3;
default: theMem_dCache_data_memory$DIB =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theMem_dCache_data_memory$WEA = 1'd0 ;
assign theMem_dCache_data_memory$WEB = 1'd1 ;
assign theMem_dCache_data_memory$ENA =
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 &&
!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ||
WILL_FIRE_RL_memAccess_doMemAccess &&
(memAccess_inQ$D_OUT[14:13] == 2'd0 ||
memAccess_inQ$D_OUT[14:13] == 2'd1 &&
CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197 &&
(memAccess_inQ$D_OUT[374:372] != 3'd5 ||
memAccess_inQ$D_OUT[166]) ||
memAccess_inQ$D_OUT[14:13] == 2'd2 &&
memAccess_inQ$D_OUT[3:2] == 2'd1 &&
(memAccess_inQ$D_OUT[6:4] == 3'd3 ||
memAccess_inQ$D_OUT[6:4] == 3'd4)) ;
assign theMem_dCache_data_memory$ENB =
WILL_FIRE_RL_theMem_dCache_getResponseUncached &&
theMem_dCache_missCached ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d3016 ||
WILL_FIRE_RL_theMem_dCache_updateCache ;
// submodule theMem_dCache_data_serverAdapterA_outDataCore
assign theMem_dCache_data_serverAdapterA_outDataCore$D_IN =
theMem_dCache_data_memory$DOA ;
assign theMem_dCache_data_serverAdapterA_outDataCore$ENQ =
WILL_FIRE_RL_theMem_dCache_data_serverAdapterA_outData_enqAndDeq ||
theMem_dCache_data_serverAdapterA_outDataCore$FULL_N &&
!theMem_dCache_data_serverAdapterA_outData_deqCalled$whas &&
theMem_dCache_data_serverAdapterA_outData_enqData$whas ;
assign theMem_dCache_data_serverAdapterA_outDataCore$DEQ =
WILL_FIRE_RL_theMem_dCache_data_serverAdapterA_outData_enqAndDeq ||
theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N &&
theMem_dCache_data_serverAdapterA_outData_deqCalled$whas &&
!theMem_dCache_data_serverAdapterA_outData_enqData$whas ;
assign theMem_dCache_data_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule theMem_dCache_data_serverAdapterB_outDataCore
assign theMem_dCache_data_serverAdapterB_outDataCore$D_IN =
theMem_dCache_data_memory$DOB ;
assign theMem_dCache_data_serverAdapterB_outDataCore$ENQ =
theMem_dCache_data_serverAdapterB_outDataCore$FULL_N &&
theMem_dCache_data_serverAdapterB_outData_enqData$whas ;
assign theMem_dCache_data_serverAdapterB_outDataCore$DEQ = 1'b0 ;
assign theMem_dCache_data_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule theMem_dCache_invalidateFifo
assign theMem_dCache_invalidateFifo$D_IN =
theMem_capPackets$D_OUT[271:260] ;
assign theMem_dCache_invalidateFifo$ENQ =
WILL_FIRE_RL_theMem_submitCapRequest &&
theMem_capPackets$D_OUT[325:324] == 2'd1 &&
theMem_dCache_invalidateFifo$FULL_N ;
assign theMem_dCache_invalidateFifo$DEQ =
WILL_FIRE_RL_theMem_dCache_invalidateEntry ;
assign theMem_dCache_invalidateFifo$CLR = 1'b0 ;
// submodule theMem_dCache_out_fifo_ff
assign theMem_dCache_out_fifo_ff$D_IN = theMem_dCache_out_fifo_enqw$wget ;
assign theMem_dCache_out_fifo_ff$ENQ =
theMem_dCache_out_fifo_enqw$whas &&
(!WILL_FIRE_RL_writeback_doWriteBackWithRead ||
theMem_dCache_out_fifo_ff$EMPTY_N) ;
assign theMem_dCache_out_fifo_ff$DEQ =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
theMem_dCache_out_fifo_ff$EMPTY_N ;
assign theMem_dCache_out_fifo_ff$CLR = 1'b0 ;
// submodule theMem_dCache_out_fifo_firstValid
assign theMem_dCache_out_fifo_firstValid$D_IN = 1'd1 ;
assign theMem_dCache_out_fifo_firstValid$EN =
WILL_FIRE_RL_writeback_doWriteBackWithRead ;
// submodule theMem_dCache_req_fifo
assign theMem_dCache_req_fifo$D_IN =
{ CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q203,
CASE_memAccess_inQD_OUT_BITS_14_TO_13_0x0_0_r_ETC__q204,
x__h143650,
x__h149013 } ;
assign theMem_dCache_req_fifo$ENQ =
WILL_FIRE_RL_memAccess_doMemAccess &&
(memAccess_inQ$D_OUT[14:13] == 2'd0 ||
memAccess_inQ$D_OUT[14:13] == 2'd1 &&
CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197 &&
(memAccess_inQ$D_OUT[374:372] != 3'd5 ||
memAccess_inQ$D_OUT[166]) ||
memAccess_inQ$D_OUT[14:13] == 2'd2 &&
memAccess_inQ$D_OUT[3:2] == 2'd1 &&
(memAccess_inQ$D_OUT[6:4] == 3'd3 ||
memAccess_inQ$D_OUT[6:4] == 3'd4 ||
memAccess_inQ$D_OUT[6:4] == 3'd1 ||
memAccess_inQ$D_OUT[6:4] == 3'd0 ||
memAccess_inQ$D_OUT[6:4] == 3'd2)) ;
assign theMem_dCache_req_fifo$DEQ =
MUX_theMem_dCache_out_fifo_enqw$wset_1__SEL_1 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite ||
WILL_FIRE_RL_theMem_dCache_getResponseUncached ||
WILL_FIRE_RL_theMem_dCache_wayMiss ||
WILL_FIRE_RL_theMem_dCache_doCacheInstructions ;
assign theMem_dCache_req_fifo$CLR = 1'b0 ;
// submodule theMem_dCache_set_fifo
assign theMem_dCache_set_fifo$D_IN = 1'b0 ;
assign theMem_dCache_set_fifo$ENQ = 1'b0 ;
assign theMem_dCache_set_fifo$DEQ = 1'b0 ;
assign theMem_dCache_set_fifo$CLR = 1'b0 ;
// submodule theMem_dCache_tags_fifo
assign theMem_dCache_tags_fifo$D_IN =
theMem_dCache_tags_serverAdapterA_outData_outData$wget ;
assign theMem_dCache_tags_fifo$ENQ =
MUX_theMem_theMemMerge_req_fifos_1$enq_1__SEL_1 ;
assign theMem_dCache_tags_fifo$DEQ =
WILL_FIRE_RL_theMem_dCache_getResponseUncached &&
!theMem_dCache_missCached ||
WILL_FIRE_RL_theMem_dCache_updateCache &&
theMem_dCache_fillCount == 2'b11 ;
assign theMem_dCache_tags_fifo$CLR = 1'b0 ;
// submodule theMem_dCache_tags_memory
assign theMem_dCache_tags_memory$ADDRA = memAccess_inQ$D_OUT[241:235] ;
always@(WILL_FIRE_RL_theMem_dCache_invalidateEntry or
theMem_dCache_invalidateFifo$D_OUT or
MUX_theMem_dCache_cacheState$write_1__SEL_3 or
theMem_dCache_addrReg or
MUX_theMem_dCache_tags_memory$b_put_1__SEL_1 or
MUX_theMem_dCache_tags_memory$b_put_1__SEL_2 or
theMem_dCache_req_fifo$D_OUT or
WILL_FIRE_RL_theMem_dCache_initialize or theMem_dCache_count)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_theMem_dCache_invalidateEntry:
theMem_dCache_tags_memory$ADDRB =
theMem_dCache_invalidateFifo$D_OUT[11:5];
MUX_theMem_dCache_cacheState$write_1__SEL_3:
theMem_dCache_tags_memory$ADDRB = theMem_dCache_addrReg[11:5];
MUX_theMem_dCache_tags_memory$b_put_1__SEL_1 ||
MUX_theMem_dCache_tags_memory$b_put_1__SEL_2:
theMem_dCache_tags_memory$ADDRB =
theMem_dCache_req_fifo$D_OUT[75:69];
WILL_FIRE_RL_theMem_dCache_initialize:
theMem_dCache_tags_memory$ADDRB = theMem_dCache_count;
default: theMem_dCache_tags_memory$ADDRB =
7'b0101010 /* unspecified value */ ;
endcase
end
assign theMem_dCache_tags_memory$DIA =
50'h2AAAAAAAAAAAA /* unspecified value */ ;
always@(MUX_theMem_dCache_tags_memory$b_put_1__SEL_2 or
MUX_theMem_dCache_tags_memory$b_put_3__VAL_2 or
MUX_theMem_dCache_cacheState$write_1__SEL_3 or
MUX_theMem_dCache_tags_memory$b_put_3__VAL_3 or
MUX_theMem_dCache_tags_memory$b_put_1__SEL_1 or
WILL_FIRE_RL_theMem_dCache_initialize or
WILL_FIRE_RL_theMem_dCache_invalidateEntry)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_dCache_tags_memory$b_put_1__SEL_2:
theMem_dCache_tags_memory$DIB =
MUX_theMem_dCache_tags_memory$b_put_3__VAL_2;
MUX_theMem_dCache_cacheState$write_1__SEL_3:
theMem_dCache_tags_memory$DIB =
MUX_theMem_dCache_tags_memory$b_put_3__VAL_3;
MUX_theMem_dCache_tags_memory$b_put_1__SEL_1 ||
WILL_FIRE_RL_theMem_dCache_initialize ||
WILL_FIRE_RL_theMem_dCache_invalidateEntry:
theMem_dCache_tags_memory$DIB = 50'h2AAAAA9555554;
default: theMem_dCache_tags_memory$DIB =
50'h2AAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theMem_dCache_tags_memory$WEA = 1'd0 ;
assign theMem_dCache_tags_memory$WEB = 1'd1 ;
assign theMem_dCache_tags_memory$ENA =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways ;
assign theMem_dCache_tags_memory$ENB =
WILL_FIRE_RL_theMem_dCache_doCacheInstructions &&
(theMem_dCache_req_fifo$D_OUT[138:136] == 3'd1 ||
theMem_dCache_req_fifo$D_OUT[138:136] == 3'd0) ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
NOT_theCP0_tlbLookupData_response_get_777_BIT__ETC___d3092 ||
WILL_FIRE_RL_theMem_dCache_updateCache &&
theMem_dCache_fillCount == 2'b11 ||
WILL_FIRE_RL_theMem_dCache_initialize ||
WILL_FIRE_RL_theMem_dCache_invalidateEntry ;
// submodule theMem_dCache_tags_serverAdapterA_outDataCore
assign theMem_dCache_tags_serverAdapterA_outDataCore$D_IN =
theMem_dCache_tags_memory$DOA ;
assign theMem_dCache_tags_serverAdapterA_outDataCore$ENQ =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_outData_enqAndDeq ||
theMem_dCache_tags_serverAdapterA_outDataCore$FULL_N &&
!theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas &&
theMem_dCache_tags_serverAdapterA_outData_enqData$whas ;
assign theMem_dCache_tags_serverAdapterA_outDataCore$DEQ =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_outData_enqAndDeq ||
theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N &&
theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas &&
!theMem_dCache_tags_serverAdapterA_outData_enqData$whas ;
assign theMem_dCache_tags_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule theMem_dCache_tags_serverAdapterB_outDataCore
assign theMem_dCache_tags_serverAdapterB_outDataCore$D_IN =
theMem_dCache_tags_memory$DOB ;
assign theMem_dCache_tags_serverAdapterB_outDataCore$ENQ =
theMem_dCache_tags_serverAdapterB_outDataCore$FULL_N &&
theMem_dCache_tags_serverAdapterB_outData_enqData$whas ;
assign theMem_dCache_tags_serverAdapterB_outDataCore$DEQ = 1'b0 ;
assign theMem_dCache_tags_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule theMem_dCache_wayKey
assign theMem_dCache_wayKey$D_IN = theMem_dCache_lastKey ;
assign theMem_dCache_wayKey$ENQ =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways ;
assign theMem_dCache_wayKey$DEQ =
theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas ;
assign theMem_dCache_wayKey$CLR = 1'b0 ;
// submodule theMem_dCache_wayPredicted
assign theMem_dCache_wayPredicted$D_IN = theMem_dCache_wayTable$D_OUT_1 ;
assign theMem_dCache_wayPredicted$ENQ =
WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways ;
assign theMem_dCache_wayPredicted$DEQ =
theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas ;
assign theMem_dCache_wayPredicted$CLR = 1'b0 ;
// submodule theMem_dCache_wayTable
assign theMem_dCache_wayTable$ADDR_1 = theMem_dCache_lastKey ;
assign theMem_dCache_wayTable$ADDR_2 = 7'h0 ;
assign theMem_dCache_wayTable$ADDR_3 = 7'h0 ;
assign theMem_dCache_wayTable$ADDR_4 = 7'h0 ;
assign theMem_dCache_wayTable$ADDR_5 = 7'h0 ;
assign theMem_dCache_wayTable$ADDR_IN = theMem_dCache_wayKey$D_OUT ;
assign theMem_dCache_wayTable$D_IN =
MUX_theMem_dCache_wayTable$upd_1__SEL_1 ?
MUX_theMem_dCache_wayTable$upd_2__VAL_1 :
MUX_theMem_dCache_wayTable$upd_2__VAL_2 ;
assign theMem_dCache_wayTable$WE =
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0_tlbLookupData_response_get_777_BITS_13__ETC___d1813 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d3016 ;
// submodule theMem_dataByte
assign theMem_dataByte$D_IN = memAccess_inQ$D_OUT[232:230] ;
assign theMem_dataByte$ENQ =
WILL_FIRE_RL_memAccess_doMemAccess &&
memAccess_inQ$D_OUT[14:13] == 2'd0 ;
assign theMem_dataByte$DEQ =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
theMem_dataByte$EMPTY_N &&
theMem_dataSize$EMPTY_N ;
assign theMem_dataByte$CLR = 1'b0 ;
// submodule theMem_dataSize
assign theMem_dataSize$D_IN = memAccess_inQ$D_OUT[12:9] ;
assign theMem_dataSize$ENQ =
WILL_FIRE_RL_memAccess_doMemAccess &&
memAccess_inQ$D_OUT[14:13] == 2'd0 ;
assign theMem_dataSize$DEQ =
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
theMem_dataByte$EMPTY_N &&
theMem_dataSize$EMPTY_N ;
assign theMem_dataSize$CLR = 1'b0 ;
// submodule theMem_iCacheOp
assign theMem_iCacheOp$D_IN =
{ memAccess_inQ$D_OUT[6:4],
8'h0,
x__h143650,
64'hAAAAAAAAAAAAAAAA } ;
assign theMem_iCacheOp$ENQ =
WILL_FIRE_RL_memAccess_doMemAccess &&
memAccess_inQ$D_OUT[14:13] == 2'd2 &&
memAccess_inQ$D_OUT[3:2] == 2'd0 ;
assign theMem_iCacheOp$DEQ = WILL_FIRE_RL_theMem_iCacheOperation ;
assign theMem_iCacheOp$CLR = 1'b0 ;
// submodule theMem_iCache_bank_memory
always@(MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 or
theMem_iCacheOp$D_OUT or
WILL_FIRE_RL_instructionFetch or
IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598 or
WILL_FIRE_RL_debugInstructionFetch or
IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_iCache_bank_memory$a_put_1__SEL_1:
theMem_iCache_bank_memory$ADDRA = theMem_iCacheOp$D_OUT[77:67];
WILL_FIRE_RL_instructionFetch:
theMem_iCache_bank_memory$ADDRA =
IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598[13:3];
WILL_FIRE_RL_debugInstructionFetch:
theMem_iCache_bank_memory$ADDRA =
IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599[13:3];
default: theMem_iCache_bank_memory$ADDRA =
11'b01010101010 /* unspecified value */ ;
endcase
end
assign theMem_iCache_bank_memory$ADDRB =
MUX_theMem_iCache_bank_memory$b_put_1__SEL_1 ?
MUX_theMem_iCache_bank_memory$b_put_2__VAL_1 :
MUX_theMem_iCache_bank_memory$b_put_2__VAL_2 ;
always@(MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 or
WILL_FIRE_RL_instructionFetch or WILL_FIRE_RL_debugInstructionFetch)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_iCache_bank_memory$a_put_1__SEL_1:
theMem_iCache_bank_memory$DIA =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_instructionFetch:
theMem_iCache_bank_memory$DIA =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_debugInstructionFetch:
theMem_iCache_bank_memory$DIA =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
default: theMem_iCache_bank_memory$DIA =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theMem_iCache_bank_memory$DIB =
MUX_theMem_iCache_bank_memory$b_put_1__SEL_1 ?
theMem_theMemMerge_rsp_fifos$D_OUT[63:0] :
MUX_theMem_iCache_bank_memory$b_put_3__VAL_2 ;
assign theMem_iCache_bank_memory$WEA = 1'd0 ;
assign theMem_iCache_bank_memory$WEB = 1'd1 ;
assign theMem_iCache_bank_memory$ENA =
WILL_FIRE_RL_theMem_iCacheOperation &&
(theMem_iCacheOp$D_OUT[138:136] == 3'd3 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd4) ||
WILL_FIRE_RL_instructionFetch ||
WILL_FIRE_RL_debugInstructionFetch ;
assign theMem_iCache_bank_memory$ENB =
WILL_FIRE_RL_theMem_iCache_getMemoryResponse &&
theMem_iCache_missCached ||
WILL_FIRE_RL_theMem_iCache_updateCache ;
// submodule theMem_iCache_bank_serverAdapterA_outDataCore
assign theMem_iCache_bank_serverAdapterA_outDataCore$D_IN =
theMem_iCache_bank_memory$DOA ;
assign theMem_iCache_bank_serverAdapterA_outDataCore$ENQ =
WILL_FIRE_RL_theMem_iCache_bank_serverAdapterA_outData_enqAndDeq ||
theMem_iCache_bank_serverAdapterA_outDataCore$FULL_N &&
!theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas &&
theMem_iCache_bank_serverAdapterA_outData_enqData$whas ;
assign theMem_iCache_bank_serverAdapterA_outDataCore$DEQ =
WILL_FIRE_RL_theMem_iCache_bank_serverAdapterA_outData_enqAndDeq ||
theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N &&
theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas &&
!theMem_iCache_bank_serverAdapterA_outData_enqData$whas ;
assign theMem_iCache_bank_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule theMem_iCache_bank_serverAdapterB_outDataCore
assign theMem_iCache_bank_serverAdapterB_outDataCore$D_IN =
theMem_iCache_bank_memory$DOB ;
assign theMem_iCache_bank_serverAdapterB_outDataCore$ENQ =
theMem_iCache_bank_serverAdapterB_outDataCore$FULL_N &&
theMem_iCache_bank_serverAdapterB_outData_enqData$whas ;
assign theMem_iCache_bank_serverAdapterB_outDataCore$DEQ = 1'b0 ;
assign theMem_iCache_bank_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule theMem_iCache_delayedReq
assign theMem_iCache_delayedReq$D_IN = 139'h0 ;
assign theMem_iCache_delayedReq$ENQ = 1'b0 ;
assign theMem_iCache_delayedReq$DEQ = 1'b0 ;
assign theMem_iCache_delayedReq$CLR = 1'b0 ;
// submodule theMem_iCache_invalidateFifo
assign theMem_iCache_invalidateFifo$D_IN = 14'h0 ;
assign theMem_iCache_invalidateFifo$ENQ = 1'b0 ;
assign theMem_iCache_invalidateFifo$DEQ =
WILL_FIRE_RL_theMem_iCache_invalidateEntry ;
assign theMem_iCache_invalidateFifo$CLR = 1'b0 ;
// submodule theMem_iCache_out_fifo_ff
assign theMem_iCache_out_fifo_ff$D_IN = theMem_iCache_out_fifo_enqw$wget ;
assign theMem_iCache_out_fifo_ff$ENQ =
theMem_iCache_out_fifo_enqw$whas &&
(!WILL_FIRE_RL_registerFetch ||
theMem_iCache_out_fifo_ff$EMPTY_N) ;
assign theMem_iCache_out_fifo_ff$DEQ =
WILL_FIRE_RL_registerFetch && theMem_iCache_out_fifo_ff$EMPTY_N ;
assign theMem_iCache_out_fifo_ff$CLR = 1'b0 ;
// submodule theMem_iCache_out_fifo_firstValid
assign theMem_iCache_out_fifo_firstValid$D_IN = 1'd1 ;
assign theMem_iCache_out_fifo_firstValid$EN = WILL_FIRE_RL_registerFetch ;
// submodule theMem_iCache_req_fifo
always@(MUX_theMem_iCache_req_fifo$enq_1__SEL_1 or
theMem_iCacheOp$D_OUT or
WILL_FIRE_RL_instructionFetch or
MUX_theMem_iCache_req_fifo$enq_1__VAL_2 or
WILL_FIRE_RL_debugInstructionFetch or
MUX_theMem_iCache_req_fifo$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_iCache_req_fifo$enq_1__SEL_1:
theMem_iCache_req_fifo$D_IN = theMem_iCacheOp$D_OUT;
WILL_FIRE_RL_instructionFetch:
theMem_iCache_req_fifo$D_IN =
MUX_theMem_iCache_req_fifo$enq_1__VAL_2;
WILL_FIRE_RL_debugInstructionFetch:
theMem_iCache_req_fifo$D_IN =
MUX_theMem_iCache_req_fifo$enq_1__VAL_3;
default: theMem_iCache_req_fifo$D_IN =
139'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theMem_iCache_req_fifo$ENQ =
WILL_FIRE_RL_theMem_iCacheOperation &&
(theMem_iCacheOp$D_OUT[138:136] == 3'd3 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd4 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd1 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd0 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd2) ||
WILL_FIRE_RL_instructionFetch ||
WILL_FIRE_RL_debugInstructionFetch ;
assign theMem_iCache_req_fifo$DEQ =
MUX_theMem_iCache_out_fifo_enqw$wset_1__SEL_1 ||
WILL_FIRE_RL_theMem_iCache_respondDuringUpdate ||
WILL_FIRE_RL_theMem_iCache_getMemoryResponse ||
WILL_FIRE_RL_theMem_iCache_doCacheInstructions ;
assign theMem_iCache_req_fifo$CLR = 1'b0 ;
// submodule theMem_iCache_tags_memory
always@(MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 or
theMem_iCacheOp$D_OUT or
WILL_FIRE_RL_instructionFetch or
IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598 or
WILL_FIRE_RL_debugInstructionFetch or
IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_iCache_bank_memory$a_put_1__SEL_1:
theMem_iCache_tags_memory$ADDRA = theMem_iCacheOp$D_OUT[77:69];
WILL_FIRE_RL_instructionFetch:
theMem_iCache_tags_memory$ADDRA =
IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598[13:5];
WILL_FIRE_RL_debugInstructionFetch:
theMem_iCache_tags_memory$ADDRA =
IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599[13:5];
default: theMem_iCache_tags_memory$ADDRA =
9'b010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_theMem_iCache_invalidateEntry or
theMem_iCache_invalidateFifo$D_OUT or
MUX_theMem_iCache_cacheState$write_1__SEL_3 or
theMem_iCache_virAddrReg or
MUX_theMem_iCache_tags_memory$b_put_1__SEL_1 or
MUX_theMem_iCache_tags_memory$b_put_1__SEL_2 or
theMem_iCache_req_fifo$D_OUT or
WILL_FIRE_RL_theMem_iCache_initialize or theMem_iCache_count)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_theMem_iCache_invalidateEntry:
theMem_iCache_tags_memory$ADDRB =
theMem_iCache_invalidateFifo$D_OUT[13:5];
MUX_theMem_iCache_cacheState$write_1__SEL_3:
theMem_iCache_tags_memory$ADDRB = theMem_iCache_virAddrReg[13:5];
MUX_theMem_iCache_tags_memory$b_put_1__SEL_1 ||
MUX_theMem_iCache_tags_memory$b_put_1__SEL_2:
theMem_iCache_tags_memory$ADDRB =
theMem_iCache_req_fifo$D_OUT[77:69];
WILL_FIRE_RL_theMem_iCache_initialize:
theMem_iCache_tags_memory$ADDRB = theMem_iCache_count;
default: theMem_iCache_tags_memory$ADDRB =
9'b010101010 /* unspecified value */ ;
endcase
end
always@(MUX_theMem_iCache_bank_memory$a_put_1__SEL_1 or
WILL_FIRE_RL_instructionFetch or WILL_FIRE_RL_debugInstructionFetch)
begin
case (1'b1) // synopsys parallel_case
MUX_theMem_iCache_bank_memory$a_put_1__SEL_1:
theMem_iCache_tags_memory$DIA =
25'b0101010101010101010101010 /* unspecified value */ ;
WILL_FIRE_RL_instructionFetch:
theMem_iCache_tags_memory$DIA =
25'b0101010101010101010101010 /* unspecified value */ ;
WILL_FIRE_RL_debugInstructionFetch:
theMem_iCache_tags_memory$DIA =
25'b0101010101010101010101010 /* unspecified value */ ;
default: theMem_iCache_tags_memory$DIA =
25'b0101010101010101010101010 /* unspecified value */ ;
endcase
end
assign theMem_iCache_tags_memory$DIB =
MUX_theMem_iCache_cacheState$write_1__SEL_3 ?
MUX_theMem_iCache_tags_memory$b_put_3__VAL_3 :
25'h1555554 ;
assign theMem_iCache_tags_memory$WEA = 1'd0 ;
assign theMem_iCache_tags_memory$WEB = 1'd1 ;
assign theMem_iCache_tags_memory$ENA =
WILL_FIRE_RL_theMem_iCacheOperation &&
(theMem_iCacheOp$D_OUT[138:136] == 3'd3 ||
theMem_iCacheOp$D_OUT[138:136] == 3'd4) ||
WILL_FIRE_RL_instructionFetch ||
WILL_FIRE_RL_debugInstructionFetch ;
assign theMem_iCache_tags_memory$ENB =
WILL_FIRE_RL_theMem_iCache_doCacheInstructions &&
(theMem_iCache_req_fifo$D_OUT[138:136] == 3'd1 ||
theMem_iCache_req_fifo$D_OUT[138:136] == 3'd0) ||
WILL_FIRE_RL_theMem_iCache_doRead &&
theCP0$tlbLookupInstruction_response_get[13:9] == 5'd25 &&
theCP0$tlbLookupInstruction_response_get[6] &&
(!theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384 ||
!theMem_iCache_tags_serverAdapterA_outData_outData$wget[0]) ||
WILL_FIRE_RL_theMem_iCache_updateCache &&
theMem_iCache_fillCount == 2'b11 ||
WILL_FIRE_RL_theMem_iCache_initialize ||
WILL_FIRE_RL_theMem_iCache_invalidateEntry ;
// submodule theMem_iCache_tags_serverAdapterA_outDataCore
assign theMem_iCache_tags_serverAdapterA_outDataCore$D_IN =
theMem_iCache_tags_memory$DOA ;
assign theMem_iCache_tags_serverAdapterA_outDataCore$ENQ =
WILL_FIRE_RL_theMem_iCache_tags_serverAdapterA_outData_enqAndDeq ||
theMem_iCache_tags_serverAdapterA_outDataCore$FULL_N &&
!theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas &&
theMem_iCache_tags_serverAdapterA_outData_enqData$whas ;
assign theMem_iCache_tags_serverAdapterA_outDataCore$DEQ =
WILL_FIRE_RL_theMem_iCache_tags_serverAdapterA_outData_enqAndDeq ||
theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N &&
theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas &&
!theMem_iCache_tags_serverAdapterA_outData_enqData$whas ;
assign theMem_iCache_tags_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule theMem_iCache_tags_serverAdapterB_outDataCore
assign theMem_iCache_tags_serverAdapterB_outDataCore$D_IN =
theMem_iCache_tags_memory$DOB ;
assign theMem_iCache_tags_serverAdapterB_outDataCore$ENQ =
theMem_iCache_tags_serverAdapterB_outDataCore$FULL_N &&
theMem_iCache_tags_serverAdapterB_outData_enqData$whas ;
assign theMem_iCache_tags_serverAdapterB_outDataCore$DEQ = 1'b0 ;
assign theMem_iCache_tags_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule theMem_iCache_writeActive
assign theMem_iCache_writeActive$D_IN = 1'b0 ;
assign theMem_iCache_writeActive$ENQ = 1'b0 ;
assign theMem_iCache_writeActive$DEQ = 1'b0 ;
assign theMem_iCache_writeActive$CLR = 1'b0 ;
// submodule theMem_instructionWord
assign theMem_instructionWord$D_IN =
WILL_FIRE_RL_instructionFetch ?
IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598[2] :
IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599[2] ;
assign theMem_instructionWord$ENQ =
WILL_FIRE_RL_instructionFetch ||
WILL_FIRE_RL_debugInstructionFetch ;
assign theMem_instructionWord$DEQ = WILL_FIRE_RL_registerFetch ;
assign theMem_instructionWord$CLR = 1'b0 ;
// submodule theMem_l2Cache
assign theMem_l2Cache$cache_request_put = theMem_theMemMerge_nextReq$D_OUT ;
assign theMem_l2Cache$memory_response_put = memory_response_put ;
assign theMem_l2Cache$EN_cache_request_put =
theMem_l2Cache$RDY_cache_request_put &&
theMem_theMemMerge_nextReq$EMPTY_N ;
assign theMem_l2Cache$EN_cache_response_get =
WILL_FIRE_RL_theMem_l2Tomerge ;
assign theMem_l2Cache$EN_memory_request_get = EN_memory_request_get ;
assign theMem_l2Cache$EN_memory_response_put = EN_memory_response_put ;
// submodule theMem_pendingExcRpt
assign theMem_pendingExcRpt$D_IN = 1'd1 ;
assign theMem_pendingExcRpt$ENQ = WILL_FIRE_RL_capToMem ;
assign theMem_pendingExcRpt$DEQ =
theCP0$RDY_tlbLookupCoprocessors_0_response_get &&
theMem_capTlbResp$FULL_N &&
theMem_capExceptions$FULL_N ;
assign theMem_pendingExcRpt$CLR = 1'b0 ;
// submodule theMem_theMemMerge_nextReq
assign theMem_theMemMerge_nextReq$D_IN =
theMem_theMemMerge_req_fifos$EMPTY_N ?
theMem_theMemMerge_req_fifos$D_OUT :
_dfoo4 ;
assign theMem_theMemMerge_nextReq$ENQ =
WILL_FIRE_RL_theMem_theMemMerge_mergeInputs &&
(theMem_theMemMerge_req_fifos$EMPTY_N ||
!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_1$EMPTY_N ||
!theMem_theMemMerge_req_fifos_1$EMPTY_N &&
!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_2$EMPTY_N) ;
assign theMem_theMemMerge_nextReq$DEQ =
theMem_l2Cache$RDY_cache_request_put &&
theMem_theMemMerge_nextReq$EMPTY_N ;
assign theMem_theMemMerge_nextReq$CLR = 1'b0 ;
// submodule theMem_theMemMerge_pendingReqs
assign theMem_theMemMerge_pendingReqs$D_IN =
(theMem_theMemMerge_req_fifos$EMPTY_N &&
!theMem_theMemMerge_req_fifos$D_OUT[316]) ?
4'd0 :
((!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_1$EMPTY_N &&
!theMem_theMemMerge_req_fifos_1$D_OUT[316]) ?
4'd1 :
4'd2) ;
assign theMem_theMemMerge_pendingReqs$ENQ =
WILL_FIRE_RL_theMem_theMemMerge_mergeInputs &&
(theMem_theMemMerge_req_fifos$EMPTY_N &&
!theMem_theMemMerge_req_fifos$D_OUT[316] ||
_dfoo1) ;
assign theMem_theMemMerge_pendingReqs$DEQ = WILL_FIRE_RL_theMem_l2Tomerge ;
assign theMem_theMemMerge_pendingReqs$CLR = 1'b0 ;
// submodule theMem_theMemMerge_req_fifos
assign theMem_theMemMerge_req_fifos$D_IN =
{ 1'd0,
theCP0$tlbLookupInstruction_response_get[45:19],
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
theCP0$tlbLookupInstruction_response_get[6] ?
33'h1FFFFFFFF :
{ req_byteenable__h113255, 1'd0 } } ;
assign theMem_theMemMerge_req_fifos$ENQ =
MUX_theMem_iCache_cacheState$write_1__SEL_2 ;
assign theMem_theMemMerge_req_fifos$DEQ =
WILL_FIRE_RL_theMem_theMemMerge_mergeInputs &&
theMem_theMemMerge_req_fifos$EMPTY_N ;
assign theMem_theMemMerge_req_fifos$CLR = 1'b0 ;
// submodule theMem_theMemMerge_req_fifos_1
assign theMem_theMemMerge_req_fifos_1$D_IN =
MUX_theMem_theMemMerge_req_fifos_1$enq_1__SEL_1 ?
MUX_theMem_theMemMerge_req_fifos_1$enq_1__VAL_1 :
MUX_theMem_theMemMerge_req_fifos_1$enq_1__VAL_2 ;
assign theMem_theMemMerge_req_fifos_1$ENQ =
WILL_FIRE_RL_theMem_dCache_checkTags &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d1818 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d3016 ||
NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d3023) ;
assign theMem_theMemMerge_req_fifos_1$DEQ =
WILL_FIRE_RL_theMem_theMemMerge_mergeInputs &&
!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_1$EMPTY_N ;
assign theMem_theMemMerge_req_fifos_1$CLR = 1'b0 ;
// submodule theMem_theMemMerge_req_fifos_2
assign theMem_theMemMerge_req_fifos_2$D_IN =
{ theMem_capPackets$D_OUT[325:324] != 2'd0,
theMem_capTlbResp$D_OUT[45:19],
req_data__h133039,
32'hFFFFFFFF,
theMem_capTlbResp$D_OUT[6] } ;
assign theMem_theMemMerge_req_fifos_2$ENQ =
WILL_FIRE_RL_theMem_submitCapRequest &&
(theMem_capPackets$D_OUT[325:324] != 2'd1 ||
theMem_commitCapStore$D_OUT) ;
assign theMem_theMemMerge_req_fifos_2$DEQ =
WILL_FIRE_RL_theMem_theMemMerge_mergeInputs &&
!theMem_theMemMerge_req_fifos_1$EMPTY_N &&
!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_2$EMPTY_N ;
assign theMem_theMemMerge_req_fifos_2$CLR = 1'b0 ;
// submodule theMem_theMemMerge_rsp_fifos
assign theMem_theMemMerge_rsp_fifos$D_IN =
theMem_l2Cache$cache_response_get ;
assign theMem_theMemMerge_rsp_fifos$ENQ =
WILL_FIRE_RL_theMem_l2Tomerge &&
theMem_theMemMerge_pendingReqs$D_OUT == 4'd0 ;
assign theMem_theMemMerge_rsp_fifos$DEQ =
WILL_FIRE_RL_theMem_iCache_getMemoryResponse ;
assign theMem_theMemMerge_rsp_fifos$CLR = 1'b0 ;
// submodule theMem_theMemMerge_rsp_fifos_1
assign theMem_theMemMerge_rsp_fifos_1$D_IN =
theMem_l2Cache$cache_response_get ;
assign theMem_theMemMerge_rsp_fifos_1$ENQ =
WILL_FIRE_RL_theMem_l2Tomerge &&
theMem_theMemMerge_pendingReqs$D_OUT == 4'd1 ;
assign theMem_theMemMerge_rsp_fifos_1$DEQ =
WILL_FIRE_RL_theMem_dCache_getResponseUncached ;
assign theMem_theMemMerge_rsp_fifos_1$CLR = 1'b0 ;
// submodule theMem_theMemMerge_rsp_fifos_2
assign theMem_theMemMerge_rsp_fifos_2$D_IN =
theMem_l2Cache$cache_response_get ;
assign theMem_theMemMerge_rsp_fifos_2$ENQ =
WILL_FIRE_RL_theMem_l2Tomerge &&
theMem_theMemMerge_pendingReqs$D_OUT == 4'd2 ;
assign theMem_theMemMerge_rsp_fifos_2$DEQ = WILL_FIRE_RL_memToCap ;
assign theMem_theMemMerge_rsp_fifos_2$CLR = 1'b0 ;
// submodule theRF_idsA
assign theRF_idsA$D_IN = 4'h0 ;
assign theRF_idsA$ENQ = 1'b0 ;
assign theRF_idsA$DEQ = 1'b0 ;
assign theRF_idsA$CLR = 1'b0 ;
// submodule theRF_idsB
assign theRF_idsB$D_IN = 4'h0 ;
assign theRF_idsB$ENQ = 1'b0 ;
assign theRF_idsB$DEQ = 1'b0 ;
assign theRF_idsB$CLR = 1'b0 ;
// submodule theRF_regFile
assign theRF_regFile$ADDR_1 = theRF_reqB$D_OUT ;
assign theRF_regFile$ADDR_2 = theRF_reqA$D_OUT ;
assign theRF_regFile$ADDR_3 = 5'h0 ;
assign theRF_regFile$ADDR_4 = 5'h0 ;
assign theRF_regFile$ADDR_5 = 5'h0 ;
assign theRF_regFile$ADDR_IN =
(MUX_theRF_regFile$upd_1__SEL_1 ||
MUX_theRF_regFile$upd_1__SEL_2 ||
MUX_theRF_regFile$upd_1__SEL_3) ?
memAccessToWriteback$D_OUT[391:387] :
theRF_count ;
always@(MUX_theRF_regFile$upd_1__SEL_1 or
MUX_theRF_regFile$upd_1__SEL_3 or
memAccessToWriteback$D_OUT or
MUX_theRF_regFile$upd_1__SEL_2 or
result__h176159 or theRF_regFileState)
begin
case (1'b1) // synopsys parallel_case
MUX_theRF_regFile$upd_1__SEL_1 || MUX_theRF_regFile$upd_1__SEL_3:
theRF_regFile$D_IN = memAccessToWriteback$D_OUT[293:230];
MUX_theRF_regFile$upd_1__SEL_2: theRF_regFile$D_IN = result__h176159;
!theRF_regFileState: theRF_regFile$D_IN = 64'b0;
default: theRF_regFile$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign theRF_regFile$WE =
WILL_FIRE_RL_writeback_doWriteBack &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2655 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2824 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d3148 ||
!theRF_regFileState ;
// submodule theRF_reqA
assign theRF_reqA$D_IN =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
5'b0 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7236) ;
assign theRF_reqA$ENQ = WILL_FIRE_RL_registerFetch ;
assign theRF_reqA$DEQ = WILL_FIRE_RL_doDecode ;
assign theRF_reqA$CLR = 1'b0 ;
// submodule theRF_reqB
assign theRF_reqB$D_IN =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
v__h277714 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
5'b0 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7242) ;
assign theRF_reqB$ENQ = WILL_FIRE_RL_registerFetch ;
assign theRF_reqB$DEQ = WILL_FIRE_RL_doDecode ;
assign theRF_reqB$CLR = 1'b0 ;
// submodule writeback_destRenamed
assign writeback_destRenamed$D_IN = memAccessToWriteback$D_OUT[437:436] ;
assign writeback_destRenamed$ENQ =
WILL_FIRE_RL_writeback_doWriteBackWithRead ;
assign writeback_destRenamed$DEQ =
_dor1writeback_destRenamed$EN_deq &&
writeback_destRenamed$EMPTY_N ;
assign writeback_destRenamed$CLR = 1'b0 ;
// submodule writeback_exception
always@(MUX_writeback_exception$enq_1__SEL_1 or
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868 or
MUX_writeback_exception$enq_1__SEL_2 or
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875 or
MUX_writeback_exception$enq_1__SEL_3 or
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876)
begin
case (1'b1) // synopsys parallel_case
MUX_writeback_exception$enq_1__SEL_1:
writeback_exception$D_IN =
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868;
MUX_writeback_exception$enq_1__SEL_2:
writeback_exception$D_IN =
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875;
MUX_writeback_exception$enq_1__SEL_3:
writeback_exception$D_IN =
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876;
default: writeback_exception$D_IN = 5'b01010 /* unspecified value */ ;
endcase
end
assign writeback_exception$ENQ =
WILL_FIRE_RL_writeback_doWriteBack &&
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ;
assign writeback_exception$DEQ =
WILL_FIRE_RL_reportExceptionToCapabilityCoprocessor ;
assign writeback_exception$CLR = 1'b0 ;
// submodule writeback_hiLoCommit
always@(MUX_writeback_hiLoCommit$enq_1__SEL_1 or
MUX_theCP0$writeReg_4__VAL_2 or
MUX_writeback_hiLoCommit$enq_1__SEL_2 or
MUX_theCP0$writeReg_4__VAL_1 or
MUX_writeback_hiLoCommit$enq_1__SEL_3 or
MUX_theCP0$writeReg_4__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_writeback_hiLoCommit$enq_1__SEL_1:
writeback_hiLoCommit$D_IN = MUX_theCP0$writeReg_4__VAL_2;
MUX_writeback_hiLoCommit$enq_1__SEL_2:
writeback_hiLoCommit$D_IN = MUX_theCP0$writeReg_4__VAL_1;
MUX_writeback_hiLoCommit$enq_1__SEL_3:
writeback_hiLoCommit$D_IN = MUX_theCP0$writeReg_4__VAL_3;
default: writeback_hiLoCommit$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign writeback_hiLoCommit$ENQ =
WILL_FIRE_RL_writeback_doWriteBack &&
memAccessToWriteback$D_OUT[383:382] == 2'd2 ||
WILL_FIRE_RL_writeback_doWriteBackWithRead &&
memAccessToWriteback$D_OUT[383:382] == 2'd2 ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite &&
memAccessToWriteback$D_OUT[383:382] == 2'd2 ;
assign writeback_hiLoCommit$DEQ =
WILL_FIRE_RL_execute_finishMultiplyOrDivide ;
assign writeback_hiLoCommit$CLR = 1'b0 ;
// submodule writeback_instructionReport
always@(WILL_FIRE_RL_writeback_doWriteBack or
MUX_writeback_instructionReport$enq_1__VAL_1 or
WILL_FIRE_RL_writeback_doWriteBackWithRead or
MUX_writeback_instructionReport$enq_1__VAL_2 or
WILL_FIRE_RL_writeback_doWriteBackWithWrite or
MUX_writeback_instructionReport$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_writeback_doWriteBack:
writeback_instructionReport$D_IN =
MUX_writeback_instructionReport$enq_1__VAL_1;
WILL_FIRE_RL_writeback_doWriteBackWithRead:
writeback_instructionReport$D_IN =
MUX_writeback_instructionReport$enq_1__VAL_2;
WILL_FIRE_RL_writeback_doWriteBackWithWrite:
writeback_instructionReport$D_IN =
MUX_writeback_instructionReport$enq_1__VAL_3;
default: writeback_instructionReport$D_IN =
509'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign writeback_instructionReport$ENQ =
WILL_FIRE_RL_writeback_doWriteBack ||
WILL_FIRE_RL_writeback_doWriteBackWithRead ||
WILL_FIRE_RL_writeback_doWriteBackWithWrite ;
assign writeback_instructionReport$DEQ =
WILL_FIRE_RL_writeback_doInstructionReport ;
assign writeback_instructionReport$CLR = 1'b0 ;
// submodule writeback_results
assign writeback_results$D_IN = result__h176159 ;
assign writeback_results$ENQ = WILL_FIRE_RL_writeback_doWriteBackWithRead ;
assign writeback_results$DEQ =
_dor1writeback_results$EN_deq && writeback_destRenamed$EMPTY_N ;
assign writeback_results$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_ETC___d7579 =
(IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25) ?
64'd0 :
expWb___1_entry__h175093 ;
assign IF_IF_IF_IF_NOT_theCP0_tlbLookupData_response__ETC___d7584 =
(IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25) ?
64'd0 :
expWb___1_entry__h193005 ;
assign IF_IF_IF_IF_memAccessToWriteback_first__516_BI_ETC___d7578 =
(IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25) ?
64'd0 :
expWb___1_entry__h170521 ;
assign IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 =
(IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEm_ETC___d8720 ==
5'd25) ?
IF_theMem_capExceptions_i_notEmpty__490_THEN_I_ETC___d8802 :
IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEm_ETC___d8720 ;
assign IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 =
(IF_IF_NOT_theCP0_tlbLookupData_response_get_77_ETC___d8732 ==
5'd25) ?
IF_theMem_capExceptions_i_notEmpty__490_THEN_I_ETC___d8802 :
IF_IF_NOT_theCP0_tlbLookupData_response_get_77_ETC___d8732 ;
assign IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7227 =
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9122 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9124) ?
branchTarget__h283587 :
fetchedControlToken$D_OUT[101:38] ;
assign IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7275 =
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8261 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609) ?
{ 2'd2,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8261 ?
32'd0 :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9205 } :
{ 2'd3,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9205 } ;
assign IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7276 =
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
{ 2'd1,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9205 } :
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7275 ;
assign IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7277 =
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359) ?
{ 2'd0,
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9205 } :
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7276 ;
assign IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7502 =
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7494) ?
fetchedControlToken$D_OUT[37:18] :
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7500 ?
20'd4 :
fetchedControlToken$D_OUT[37:18]) ;
assign IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 =
(IF_IF_memAccessToWriteback_first__516_BITS_371_ETC___d8711 ==
5'd25) ?
IF_theMem_capExceptions_i_notEmpty__490_THEN_I_ETC___d8802 :
IF_IF_memAccessToWriteback_first__516_BITS_371_ETC___d8711 ;
assign IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEm_ETC___d8720 =
(IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEmpty_ETC___d8719 ==
5'd25) ?
theCP0$getException[4:0] :
IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEmpty_ETC___d8719 ;
assign IF_IF_NOT_theCP0_tlbLookupData_response_get_77_ETC___d8732 =
(IF_NOT_theCP0_tlbLookupData_response_get_777_B_ETC___d8731 ==
5'd25) ?
theCP0$getException[4:0] :
IF_NOT_theCP0_tlbLookupData_response_get_777_B_ETC___d8731 ;
assign IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d5575 =
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7997 ?
2'd0 :
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q25 ;
assign IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d6372 =
{ IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d5575,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q137,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6371 } ;
assign IF_IF_execute_inQ_first__341_BITS_316_TO_315_5_ETC___d3522 =
CASE_execute_inQD_OUT_BITS_316_TO_315_NOT_exe_ETC__q147 ?
IF_execute_inQ_first__341_BITS_316_TO_315_502__ETC___d9058 :
execute_inQ$D_OUT[229:166] ;
assign IF_IF_execute_inQ_first__341_BITS_328_TO_327_4_ETC___d3484 =
CASE_execute_inQD_OUT_BITS_328_TO_327_NOT_exe_ETC__q143 ?
IF_execute_inQ_first__341_BITS_328_TO_327_464__ETC___d9046 :
execute_inQ$D_OUT[293:230] ;
assign IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4616 =
((execute_inQ$D_OUT[379:375] == 5'd0) ?
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d4595 :
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d4614) ?
5'd25 :
5'd22 ;
assign IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4735 =
(IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd0) ?
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597[63:0] :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 ;
assign IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4781 =
(IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd1) ?
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597[63:0] :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 ;
assign IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4827 =
(IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd2) ?
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597[63:0] :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 ;
assign IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4873 =
(IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd3) ?
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597[63:0] :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4020 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] ==
6'd63) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[0] } :
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[1:0] } ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4021 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd61) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[2:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4020 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4022 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd60) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[3:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4021 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4023 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd59) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[4:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4022 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4024 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd58) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[5:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4023 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4025 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd57) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[6:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4024 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4026 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd56) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[7:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4025 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4027 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd55) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[8:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4026 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4028 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd54) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[9:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4027 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4029 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd53) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[10:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4028 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4030 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd52) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[11:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4029 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4031 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd51) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[12:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4030 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4032 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd50) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[13:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4031 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4033 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd49) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[14:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4032 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4034 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd48) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[15:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4033 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4035 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd47) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[16:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4034 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4036 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd46) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[17:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4035 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4037 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd45) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[18:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4036 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4038 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd44) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[19:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4037 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4039 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd43) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[20:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4038 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4040 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd42) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[21:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4039 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4041 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd41) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[22:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4040 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4042 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd40) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[23:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4041 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4043 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd39) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[24:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4042 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4044 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd38) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[25:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4043 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4045 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd37) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[26:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4044 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4046 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd36) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[27:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4045 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4047 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd35) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[28:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4046 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4048 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd34) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[29:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4047 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4049 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd33) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[30:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4048 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4050 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd32) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[31:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4049 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4051 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd31) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[32:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4050 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4052 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd30) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[33:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4051 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4053 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd29) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[34:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4052 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4054 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd28) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[35:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4053 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4055 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd27) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[36:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4054 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4056 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd26) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[37:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4055 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4057 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd25) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[38:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4056 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4058 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd24) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[39:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4057 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4059 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd23) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[40:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4058 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4060 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd22) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[41:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4059 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4061 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd21) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[42:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4060 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4062 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd20) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[43:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4061 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4063 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd19) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[44:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4062 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4064 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd18) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[45:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4063 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4065 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd17) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[46:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4064 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4066 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd16) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[47:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4065 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4067 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd15) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[48:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4066 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4068 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd14) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[49:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4067 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4069 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd13) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[50:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4068 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4070 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd12) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[51:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4069 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4071 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd11) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[52:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4070 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4072 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd10) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[53:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4071 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4073 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd9) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[54:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4072 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4074 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd8) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[55:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4073 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4075 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd7) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[56:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4074 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4076 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd6) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[57:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4075 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4077 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd5) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[58:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4076 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4078 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd4) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[59:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4077 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4079 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd3) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[60:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4078 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4080 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd2) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[61:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4079 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4081 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] <=
6'd1) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
result__h223714[62:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4080 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4208 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] ==
5'd31) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[0] } :
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[1:0] } ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4209 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd29) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[2:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4208 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4210 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd28) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[3:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4209 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4211 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd27) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[4:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4210 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4212 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd26) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[5:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4211 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4213 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd25) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[6:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4212 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4214 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd24) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[7:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4213 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4215 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd23) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[8:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4214 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4216 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd22) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[9:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4215 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4217 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd21) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[10:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4216 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4218 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd20) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[11:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4217 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4219 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd19) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[12:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4218 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4220 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd18) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[13:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4219 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4221 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd17) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[14:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4220 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4222 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd16) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[15:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4221 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4223 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd15) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[16:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4222 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4224 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd14) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[17:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4223 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4225 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd13) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[18:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4224 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4226 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd12) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[19:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4225 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4227 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd11) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[20:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4226 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4228 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd10) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[21:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4227 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4229 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd9) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[22:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4228 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4230 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd8) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[23:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4229 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4231 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd7) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[24:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4230 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4232 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd6) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[25:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4231 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4233 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd5) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[26:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4232 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4234 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd4) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[27:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4233 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4235 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd3) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[28:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4234 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4236 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd2) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[29:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4235 ;
assign IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4237 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] <=
5'd1) ?
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31],
result__h228964[30:0] } :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4236 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d6776 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd2 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd3 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd29 :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd0 &&
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd8 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd9) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d6946 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
y_avValue_snd_snd_snd_fst__h282689 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
y_avValue_snd_snd_snd_fst__h282691 :
5'd0) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7083 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd26 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd27 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd32 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd48 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd49 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd50 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd55 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd52 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd53 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd54 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd33 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd34 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd35 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd36 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd37 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd38 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd39 :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9127 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9117 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7081 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7159 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd1) ?
v__h277714 != 5'd12 && v__h277714 != 5'd8 &&
v__h277714 != 5'd9 &&
v__h277714 != 5'd10 &&
v__h277714 != 5'd11 &&
v__h277714 != 5'd14 &&
((v__h277714 != 5'd0 && v__h277714 != 5'd1 &&
v__h277714 != 5'd2 &&
v__h277714 != 5'd3) ?
v__h277714 != 5'd0 && v__h277714 != 5'd1 &&
v__h277714 != 5'd2 &&
v__h277714 != 5'd3 &&
v__h277714 != 5'd16 &&
v__h277714 != 5'd17 :
v__h277714 == 5'd2 || v__h277714 == 5'd3) :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd20 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd21 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd22 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd23 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd4 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
v__h277714 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7173 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd2 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd3 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd29 :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9117 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd0 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 !=
6'd8 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 !=
6'd9 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7183 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd2 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd3 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd29) &&
!fetchedControlToken$D_OUT[1] :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd0 &&
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd8 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd9) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7185 =
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120 &&
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9106 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7183) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7194 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
((IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd0) ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q184 :
2'd0) :
2'd0 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7195 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q185 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7194 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7196 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q187 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7195 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7236 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
y_avValue_snd_snd_snd_snd_snd_snd_snd_fst__h285803 :
5'b0) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7242 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
v__h277714 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_fst__h285990 :
5'b0) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7281 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q183 :
fetchedControlToken$D_OUT[400:397] ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7297 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
x1_avValue_snd_snd_fst_coProSelect__h280767 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
_theResult_____7_fst_coProSelect__h282015 :
fetchedControlToken$D_OUT[386:384]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7303 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q182 :
fetchedControlToken$D_OUT[383:382] ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7304 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
fetchedControlToken$D_OUT[383:382] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7303 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7383 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9213 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q196 :
fetchedControlToken$D_OUT[366:355]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7385 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9213 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
fetchedControlToken$D_OUT[366:355] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7383) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7410 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9214 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q195 :
fetchedControlToken$D_OUT[354:343]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7412 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9214 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
fetchedControlToken$D_OUT[354:343] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7410) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7417 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9212 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q194 :
fetchedControlToken$D_OUT[342:331]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7418 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
fetchedControlToken$D_OUT[342:331] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7417 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7433 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8841 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q192 :
fetchedControlToken$D_OUT[366]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7435 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8841 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
fetchedControlToken$D_OUT[366] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7433) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7449 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8842 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q190 :
fetchedControlToken$D_OUT[365]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7451 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8842 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
fetchedControlToken$D_OUT[365] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7449) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7460 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8845 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q193 :
fetchedControlToken$D_OUT[354]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7462 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8845 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
fetchedControlToken$D_OUT[354] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7460) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7470 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8846 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q191 :
fetchedControlToken$D_OUT[353]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7472 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8846 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
fetchedControlToken$D_OUT[353] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7470) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7479 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8849 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q189 :
fetchedControlToken$D_OUT[342]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7480 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
fetchedControlToken$D_OUT[342] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7479 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7485 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8851 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 ?
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q188 :
fetchedControlToken$D_OUT[341]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7486 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
fetchedControlToken$D_OUT[341] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7485 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7488 =
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7435 &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7451 ||
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7462 &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7472 ||
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7480 &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7486 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7498 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd2 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd3 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd29 ||
fetchedControlToken$D_OUT[1] :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9117 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd0 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 !=
6'd8 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 !=
6'd9 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7500 =
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8261 ||
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9115 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7498) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8006 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7159) ?
2'd2 :
(IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8261 ?
2'd0 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7196) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8261 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9106 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d6776) &&
(lastWasBranch &&
lastEpoch_779_EQ_fetchedControlToken_first__66_ETC___d8992 ||
fetchedControlToken$D_OUT[401]) ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9106 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd1) ?
v__h277714 != 5'd12 && v__h277714 != 5'd8 &&
v__h277714 != 5'd9 &&
v__h277714 != 5'd10 &&
v__h277714 != 5'd11 &&
v__h277714 != 5'd14 :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd4 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd5 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd6 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd7 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd20 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd21 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd22 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd23 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9115 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd1) ?
v__h277714 == 5'd12 || v__h277714 == 5'd8 ||
v__h277714 == 5'd9 ||
v__h277714 == 5'd10 ||
v__h277714 == 5'd11 ||
v__h277714 == 5'd14 :
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd4 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd5 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd6 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd7 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd20 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd21 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd22 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 !=
6'd23 ;
assign IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9120 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9115 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7173) ||
(!lastWasBranch ||
!lastEpoch_779_EQ_fetchedControlToken_first__66_ETC___d8992) &&
!fetchedControlToken$D_OUT[401] ;
assign IF_IF_memAccessToWriteback_first__516_BITS_371_ETC___d8711 =
(IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8710 ==
5'd25) ?
theCP0$getException[4:0] :
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8710 ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7094 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd3) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 :
regRenameTable[46]) :
regRenameTable[46] ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7100 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd3) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 :
regRenameTable[45:44]) :
regRenameTable[45:44] ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7109 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd2) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 :
regRenameTable[34]) :
regRenameTable[34] ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7111 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd2) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 :
regRenameTable[33:32]) :
regRenameTable[33:32] ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7121 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd1) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 :
regRenameTable[22]) :
regRenameTable[22] ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7123 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd1) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 :
regRenameTable[21:20]) :
regRenameTable[21:20] ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7133 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd0) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 :
regRenameTable[10]) :
regRenameTable[10] ;
assign IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7135 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
((IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 ==
2'd0) ?
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 :
regRenameTable[9:8]) :
regRenameTable[9:8] ;
assign IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3645 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9050 ?
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052 :
{ writeback___1_base__h207371,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 -
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 } ;
assign IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3676 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9062 ?
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052 :
{ writeback___1_base__h203941,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 -
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] } ;
assign IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d2819 =
IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875 ==
5'd25 &&
memAccessToWriteback$D_OUT[15] &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ;
assign IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875 =
(IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 !=
5'd25 &&
(!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393] ||
memAccessToWriteback$D_OUT[1])) ?
5'd25 :
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ;
assign IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d3143 =
IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876 ==
5'd25 &&
memAccessToWriteback$D_OUT[15] &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ;
assign IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876 =
(IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 !=
5'd25 &&
(!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393] ||
memAccessToWriteback$D_OUT[1])) ?
5'd25 :
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ;
assign IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d2637 =
IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868 ==
5'd25 &&
memAccessToWriteback$D_OUT[15] &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1] ;
assign IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868 =
(IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 !=
5'd25 &&
(!branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 ||
memAccessToWriteback$D_OUT[393] ||
memAccessToWriteback$D_OUT[1])) ?
5'd25 :
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ;
assign IF_NOT_IF_theMem_dCache_out_fifo_ff_i_notEmpty_ETC___d8719 =
(IF_theMem_dCache_out_fifo_ff_i_notEmpty__489_T_ETC___d8718 !=
5'd25 &&
memAccessToWriteback$D_OUT[371:367] == 5'd25) ?
IF_theMem_dCache_out_fifo_ff_i_notEmpty__489_T_ETC___d8718 :
memAccessToWriteback$D_OUT[371:367] ;
assign IF_NOT_decode_inQ_first__909_BITS_427_TO_423_9_ETC___d6153 =
(decode_inQ$D_OUT[427:423] != 5'd2 &&
decode_inQ$D_OUT[427:423] != 5'd6) ?
((decode_inQ$D_OUT[407:402] == 6'd24) ?
theCP0$readGet :
di___1_opB__h240965) :
di___1_opB__h240965 ;
assign IF_NOT_decode_inQ_first__909_BITS_435_TO_434_9_ETC___d7594 =
(decode_inQ$D_OUT[435:434] != 2'd0 &&
decode_inQ$D_OUT[435:434] != 2'd1 &&
decode_inQ$D_OUT[435:434] != 2'd2) ?
x1_avValue_snd_snd_snd_snd_rd__h242905 :
5'd0 ;
assign IF_NOT_theCP0_tlbLookupData_response_get_777_B_ETC___d8731 =
(theCP0$tlbLookupData_response_get[13:9] != 5'd25 &&
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8729 ==
5'd25) ?
theCP0$tlbLookupData_response_get[13:9] :
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8729 ;
assign IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4590 =
(theCapCop_capInsts$D_OUT[99:95] != 5'd4 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd0 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd7 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd8 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd1 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd9 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd2 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd3 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd5 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd6) ?
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d9060 :
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q153 ;
assign IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4593 =
(theCapCop_capInsts$D_OUT[99:95] != 5'd0 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd7 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd8 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd1 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd9 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd2 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd3 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd5 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd6) ?
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d9060 :
((theCapCop_capInsts$D_OUT[99:95] == 5'd0) ?
theCapCop_capInsts$D_OUT[20:18] != 3'd3 &&
theCapCop_capInsts$D_OUT[20:18] != 3'd5 :
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4587) ;
assign IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4609 =
(theCapCop_capInsts$D_OUT[99:95] != 5'd4 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd0 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd7 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd8 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd1 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd9 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd2 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd3 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd5 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd6) ?
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d9048 :
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q146 ;
assign IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4612 =
(theCapCop_capInsts$D_OUT[99:95] != 5'd0 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd7 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd8 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd1 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd9 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd2 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd3 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd5 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd6) ?
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d9048 :
((theCapCop_capInsts$D_OUT[99:95] == 5'd0) ?
theCapCop_capInsts$D_OUT[20:18] != 3'd3 &&
theCapCop_capInsts$D_OUT[20:18] != 3'd5 :
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4606) ;
assign IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4647 =
(theCapCop_capInsts$D_OUT[99:95] != 5'd4 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd0 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd7 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd8 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd1 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd9 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd2 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd3 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd5 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd6) ?
writeback___1_base__h203941 :
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q151 ;
assign IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d8815 =
(theCapCop_capInsts$D_OUT[99:95] != 5'd4 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd0 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd7 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd8 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd1 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd10 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd9 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd2 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd3 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd5 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd6) ?
writeback___1_base__h207371 :
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q158 ;
assign IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598 =
branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b0_5_ETC___d8037 ?
theCapCop_pcc[127:64] + addr__h271109 :
64'd0 ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6362 =
{ (decode_inQ$D_OUT[435:434] == 2'd0) ?
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q26 :
((decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
decode_inQ$D_OUT[8] :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
((theCP0$getCoprocessorEnables[2] ||
decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q27 :
decode_inQ$D_OUT[8]) :
decode_inQ$D_OUT[8])),
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7997,
(decode_inQ$D_OUT[435:434] == 2'd0) ?
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q29 :
decode_inQ$D_OUT[6:4],
(decode_inQ$D_OUT[435:434] == 2'd0) ?
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q31 :
decode_inQ$D_OUT[3:2],
decode_inQ$D_OUT[1],
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q34 } ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6363 =
{ CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q42,
(decode_inQ$D_OUT[435:434] == 2'd0) ?
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q45 :
((decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
decode_inQ$D_OUT[12:9] :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
((theCP0$getCoprocessorEnables[2] ||
decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q47 :
decode_inQ$D_OUT[12:9]) :
decode_inQ$D_OUT[12:9])),
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6362 } ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6364 =
{ CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q63,
NOT_decode_inQ_first__909_BIT_401_097_196_AND__ETC___d6235,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6363 } ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6368 =
{ CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q78,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q83,
decode_inQ$D_OUT[294],
x__h257310,
x__h257489,
x__h257736,
decode_inQ$D_OUT[101:38],
(decode_inQ$D_OUT[435:434] == 2'd0) ?
CASE_decode_inQD_OUT_BITS_433_TO_428_4_1_IF_N_ETC__q84 :
20'd4,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6364 } ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6370 =
{ CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q106,
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q114,
decode_inQ_first__909_BITS_366_TO_331_870_CONC_ETC___d6369 } ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6371 =
{ CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q127,
CASE_decode_inQD_OUT_BITS_435_TO_434_IF_decod_ETC__q131,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6370 } ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6374 =
{ (decode_inQ$D_OUT[435:434] == 2'd0) ?
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q138 :
decode_inQ$D_OUT[396],
decode_inQ$D_OUT[395:392],
y_avValue_dest__h253687,
y_avValue_coProSelect__h253688,
IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d6372 } ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7586 =
(decode_inQ$D_OUT[435:434] == 2'd0 ||
decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
5'd0 :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
x1_avValue_snd_rt__h242895 :
5'd0) ;
assign IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 =
(decode_inQ$D_OUT[435:434] == 2'd0 ||
decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
5'd11 :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
((theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[427:423] :
5'd11) :
5'd11) ;
assign IF_execute_inQD_OUT_BIT_381_THEN_theResult____ETC__q148 =
execute_inQ$D_OUT[381] ?
_theResult_____7__h200324 :
opA__h223616 ;
assign IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d3537 =
{ (execute_inQ$D_OUT[14:13] == 2'd3) ?
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7777 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d3532,
(theCapCop_capInsts$D_OUT[99:95] == 5'd10) ?
theCapCop_capInsts$D_OUT[94:90] :
theCapCop_capInsts$D_OUT[9:5],
theCapCop_capInsts$D_OUT[16:10] } ;
assign IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d3685 =
(execute_inQ$D_OUT[14:13] == 2'd3) ?
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9257 :
((execute_inQ$D_OUT[379:375] == 5'd0) ?
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3683 :
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9257) ;
assign IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4716 =
(execute_inQ$D_OUT[14:13] == 2'd3) ?
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4712 :
((execute_inQ$D_OUT[374:372] == 3'd5) ?
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q154 :
execute_inQ$D_OUT[437:436] != 2'd0 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042) ;
assign IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4762 =
(execute_inQ$D_OUT[14:13] == 2'd3) ?
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4758 :
((execute_inQ$D_OUT[374:372] == 3'd5) ?
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q155 :
execute_inQ$D_OUT[437:436] != 2'd1 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043) ;
assign IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4808 =
(execute_inQ$D_OUT[14:13] == 2'd3) ?
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4804 :
((execute_inQ$D_OUT[374:372] == 3'd5) ?
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q156 :
execute_inQ$D_OUT[437:436] != 2'd2 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044) ;
assign IF_execute_inQ_first__341_BITS_14_TO_13_461_EQ_ETC___d4854 =
(execute_inQ$D_OUT[14:13] == 2'd3) ?
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4850 :
((execute_inQ$D_OUT[374:372] == 3'd5) ?
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q157 :
execute_inQ$D_OUT[437:436] != 2'd3 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045) ;
assign IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4742 =
(execute_inQ$D_OUT[374:372] == 3'd5) ?
((execute_inQ$D_OUT[437:436] == 2'd0) ?
er___1_opB__h212042 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 ;
assign IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4788 =
(execute_inQ$D_OUT[374:372] == 3'd5) ?
((execute_inQ$D_OUT[437:436] == 2'd1) ?
er___1_opB__h212042 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 ;
assign IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4834 =
(execute_inQ$D_OUT[374:372] == 3'd5) ?
((execute_inQ$D_OUT[437:436] == 2'd2) ?
er___1_opB__h212042 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 ;
assign IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4880 =
(execute_inQ$D_OUT[374:372] == 3'd5) ?
((execute_inQ$D_OUT[437:436] == 2'd3) ?
er___1_opB__h212042 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d3532 =
(execute_inQ$D_OUT[379:375] == 5'd0) ?
{ _0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8034,
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7776 } :
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7777 ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4709 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4705 :
((IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd0 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 :
execute_inQ$D_OUT[437:436] != 2'd0 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042) ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4736 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4733 :
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4735 ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4755 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4752 :
((IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd1 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 :
execute_inQ$D_OUT[437:436] != 2'd1 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043) ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4782 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4779 :
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4781 ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4801 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4798 :
((IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd2 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044 :
execute_inQ$D_OUT[437:436] != 2'd2 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044) ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4828 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4825 :
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4827 ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4847 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4844 :
((IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd3 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 :
execute_inQ$D_OUT[437:436] != 2'd3 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045) ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4874 =
((execute_inQ$D_OUT[379:375] == 5'd21 ||
execute_inQ$D_OUT[379:375] == 5'd22) &&
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 ==
2'd3) ?
IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4871 :
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4873 ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d8820 =
execute_inQ$D_OUT[379:375] == 5'd22 ^
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 ==
64'd0 ;
assign IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d9064 =
(execute_inQ$D_OUT[379:375] == 5'd0) ?
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4647 :
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d8815 ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4563 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
{ execute_inQ$D_OUT[401:393],
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597[64],
execute_inQ_first__341_BITS_391_TO_384_433_CON_ETC___d4520 } :
execute_inQ_first__341_BIT_401_522_CONCAT_IF_e_ETC___d4562 ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4712 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
execute_inQ$D_OUT[437:436] != 2'd0 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4709) :
((execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd0 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042) ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4740 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4736) :
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4739 ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4758 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
execute_inQ$D_OUT[437:436] != 2'd1 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4755) :
((execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd1 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043) ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4786 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4782) :
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4785 ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4804 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
execute_inQ$D_OUT[437:436] != 2'd2 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4801) :
((execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd2 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044) ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4832 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4828) :
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4831 ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4850 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
execute_inQ$D_OUT[437:436] != 2'd3 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4847) :
((execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
execute_inQ$D_OUT[437:436] == 2'd3 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045) ;
assign IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4878 =
(execute_inQ$D_OUT[400:397] == 4'd9) ?
((execute_inQ$D_OUT[379:375] == 5'd14) ?
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 :
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d4874) :
IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4877 ;
assign IF_execute_inQ_first__341_BITS_435_TO_434_699__ETC___d7888 =
{ CASE_execute_inQD_OUT_BITS_435_TO_434_3_0_exe_ETC__q49,
execute_inQ$D_OUT[433:402] } ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4705 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd0) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042) :
execute_inQ$D_OUT[437:436] != 2'd0 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4733 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd0) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4752 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd1) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043) :
execute_inQ$D_OUT[437:436] != 2'd1 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4779 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd1) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4798 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd2) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044) :
execute_inQ$D_OUT[437:436] != 2'd2 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044 ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4825 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd2) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4844 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd3) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045) :
execute_inQ$D_OUT[437:436] != 2'd3 &&
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 ;
assign IF_execute_inQ_first__341_BIT_306_491_THEN_IF__ETC___d4871 =
execute_inQ$D_OUT[306] ?
((execute_inQ$D_OUT[437:436] == 2'd3) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 ;
assign IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 =
execute_inQ$D_OUT[318] ?
IF_IF_execute_inQ_first__341_BITS_316_TO_315_5_ETC___d3522 :
execute_inQ$D_OUT[229:166] ;
assign IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7777 =
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8036,
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7779 } ;
assign IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 =
execute_inQ$D_OUT[330] ?
IF_IF_execute_inQ_first__341_BITS_328_TO_327_4_ETC___d3484 :
execute_inQ$D_OUT[293:230] ;
assign IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7898 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 |
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 ;
assign IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8036 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 +
64'd32 <=
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d8035 ;
assign IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8039 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 <
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 ;
assign IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8138 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 ==
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 ;
assign IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d9048 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 +
_0_CONCAT_IF_IF_theCapCop_capInsts_first__372_B_ETC___d7848 <=
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 ;
assign IF_execute_inQ_first__341_BIT_380_712_THEN_IF__ETC___d4487 =
execute_inQ$D_OUT[380] ?
((_theResult_____3_fst__h222045 ==
_theResult_____3_snd__h222046) ?
execute_inQ$D_OUT[371:367] :
5'd20) :
execute_inQ$D_OUT[371:367] ;
assign IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d3754 =
execute_inQ$D_OUT[381] ?
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5] ?
calcResult___1__h223433 :
calcResult__h223403) :
calcResult__h223521 ;
assign IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597 =
execute_inQ$D_OUT[381] ?
calcResult__h221868 :
{ calcResult__h221868[64], spliced_bits__h223217 } ;
assign IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4739 =
(execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd0) ?
x__h231731 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 ;
assign IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4785 =
(execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd1) ?
x__h231731 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 ;
assign IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4831 =
(execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd2) ?
x__h231731 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 ;
assign IF_execute_inQ_first__341_BIT_7_406_OR_execute_ETC___d4877 =
(execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
((execute_inQ$D_OUT[437:436] == 2'd3) ?
x__h231731 :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550) :
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 ;
assign IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7103 =
(fetchedControlToken$D_OUT[437:436] == 2'd3) ?
{ IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7083,
fetchedControlToken$D_OUT[437:436],
destReg__h279602,
fetchedControlToken$D_OUT[440:438] } :
{ IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7094,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7100,
regRenameTable[43:36] } ;
assign IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7114 =
(fetchedControlToken$D_OUT[437:436] == 2'd2) ?
{ IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7083,
fetchedControlToken$D_OUT[437:436],
destReg__h279602,
fetchedControlToken$D_OUT[440:438] } :
{ IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7109,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7111,
regRenameTable[31:24] } ;
assign IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7126 =
(fetchedControlToken$D_OUT[437:436] == 2'd1) ?
{ IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7083,
fetchedControlToken$D_OUT[437:436],
destReg__h279602,
fetchedControlToken$D_OUT[440:438] } :
{ IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7121,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7123,
regRenameTable[19:12] } ;
assign IF_fetchedControlToken_first__662_BITS_437_TO__ETC___d7138 =
(fetchedControlToken$D_OUT[437:436] == 2'd0) ?
{ IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7083,
fetchedControlToken$D_OUT[437:436],
destReg__h279602,
fetchedControlToken$D_OUT[440:438] } :
{ IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7133,
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d7135,
regRenameTable[7:0] } ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7081 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd18 &&
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd16 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd17 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd18 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd19 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd20 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd21 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd22 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd23) ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7494 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d9106 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9122 &&
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9124 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9127 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 &&
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd0 &&
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd8 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd9)) ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7507 =
{ fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[371:367] :
((fetchedControlToken$D_OUT[371:367] == 5'd25) ?
(theMem_iCache_out_fifo_ff$EMPTY_N ?
theMem_iCache_out_fifo_ff$D_OUT[68:64] :
theMem_iCache_out_fifo_enqw$wget[68:64]) :
fetchedControlToken$D_OUT[371:367]),
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7385,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7412,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7418,
fetchedControlToken$D_OUT[330:295],
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7488 ||
fetchedControlToken$D_OUT[294],
fetchedControlToken$D_OUT[293:38],
IF_IF_IF_fetchedControlToken_first__662_BIT_1__ETC___d7502,
fetchedControlToken$D_OUT[17:0] } ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[435:434] == 2'd0 :
instruction__h274083[31:26] != 6'd0 &&
instruction__h274083[31:26] != 6'd28 &&
instruction__h274083[31:26] != 6'd16 &&
instruction__h274083[31:26] != 6'd17 &&
instruction__h274083[31:26] != 6'd18 &&
instruction__h274083[31:26] != 6'd19 &&
instruction__h274083[31:26] != 6'd2 &&
instruction__h274083[31:26] != 6'd3 &&
instruction__h274083[31:26] != 6'd29 ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[435:434] == 2'd1 :
instruction__h274083[31:26] == 6'd2 ||
instruction__h274083[31:26] == 6'd3 ||
instruction__h274083[31:26] == 6'd29 ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8609 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[435:434] == 2'd2 :
instruction__h274083[31:26] == 6'd0 ||
instruction__h274083[31:26] == 6'd28 ||
instruction__h274083[31:26] == 6'd16 ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[433:428] :
instruction__h274083[31:26] ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[427:423] :
instruction__h274083[25:21] ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[407:402] :
instruction__h274083[5:0] ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8839 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[435:434] != 2'd0 &&
fetchedControlToken$D_OUT[435:434] != 2'd1 &&
fetchedControlToken$D_OUT[435:434] != 2'd2 :
instruction__h274083[31:26] == 6'd17 ||
instruction__h274083[31:26] == 6'd18 ||
instruction__h274083[31:26] == 6'd19 ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9117 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[435:434] != 2'd2 :
instruction__h274083[31:26] != 6'd0 &&
instruction__h274083[31:26] != 6'd28 &&
instruction__h274083[31:26] != 6'd16 ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9122 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[435:434] != 2'd0 :
instruction__h274083[31:26] == 6'd0 ||
instruction__h274083[31:26] == 6'd28 ||
instruction__h274083[31:26] == 6'd16 ||
instruction__h274083[31:26] == 6'd17 ||
instruction__h274083[31:26] == 6'd18 ||
instruction__h274083[31:26] == 6'd19 ||
instruction__h274083[31:26] == 6'd2 ||
instruction__h274083[31:26] == 6'd3 ||
instruction__h274083[31:26] == 6'd29 ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9124 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 &&
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd2 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd3 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 ==
6'd29) &&
!fetchedControlToken$D_OUT[1] ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9127 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[435:434] != 2'd1 :
instruction__h274083[31:26] != 6'd2 &&
instruction__h274083[31:26] != 6'd3 &&
instruction__h274083[31:26] != 6'd29 ;
assign IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d9205 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[433:402] :
instruction__h274083 ;
assign IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8710 =
(memAccessToWriteback$D_OUT[371:367] == 5'd25) ?
(CASE_memAccessToWritebackD_OUT_BITS_374_TO_37_ETC__q115 ?
5'd21 :
memAccessToWriteback$D_OUT[371:367]) :
memAccessToWriteback$D_OUT[371:367] ;
assign IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8729 =
(memAccessToWriteback$D_OUT[371:367] == 5'd25) ?
theCP0$getException[4:0] :
memAccessToWriteback$D_OUT[371:367] ;
assign IF_memAccessToWriteback_first__516_BITS_435_TO_ETC___d7874 =
{ CASE_memAccessToWritebackD_OUT_BITS_435_TO_43_ETC__q48,
memAccessToWriteback$D_OUT[433:402] } ;
assign IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9217 =
(memAccessToWriteback$D_OUT[15] &&
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25) ?
_theResult_____4__h170559 :
IF_IF_IF_IF_memAccessToWriteback_first__516_BI_ETC___d7578 ;
assign IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9218 =
(memAccessToWriteback$D_OUT[15] &&
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25) ?
_theResult_____4__h170559 :
IF_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_ETC___d7579 ;
assign IF_memAccessToWriteback_first__516_BIT_15_536__ETC___d9219 =
(memAccessToWriteback$D_OUT[15] &&
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25) ?
_theResult_____4__h170559 :
IF_IF_IF_IF_NOT_theCP0_tlbLookupData_response__ETC___d7584 ;
assign IF_memAccess_inQD_OUT_BITS_232_TO_230_EQ_0_TH_ETC__q1 =
(memAccess_inQ$D_OUT[232:230] == 3'd0) ? 8'd1 : 8'd0 ;
assign IF_memAccess_inQD_OUT_BITS_232_TO_231_EQ_0_TH_ETC__q2 =
(memAccess_inQ$D_OUT[232:231] == 2'd0) ? 8'd3 : 8'd0 ;
assign IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_0_C_ETC__q4 =
memAccess_inQ$D_OUT[232] ? 8'd0 : { 4'd0, mask__h147921 } ;
assign IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_0_C_ETC__q8 =
memAccess_inQ$D_OUT[232] ? 8'd0 : { 4'd0, mask__h148411 } ;
assign IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_15__q3 =
memAccess_inQ$D_OUT[232] ? 8'd0 : 8'd15 ;
assign IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7334 =
(regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9102 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369) ?
regRenameTable[9:0] :
{ regRenameTable[9:3], fetchedControlToken$D_OUT[440:438] } ;
assign IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7355 =
(regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9129 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369) ?
regRenameTable[9:0] :
{ regRenameTable[9:3], fetchedControlToken$D_OUT[440:438] } ;
assign IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7375 =
(regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9130 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369) ?
regRenameTable[9:0] :
{ regRenameTable[9:3], fetchedControlToken$D_OUT[440:438] } ;
assign IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7401 =
(regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9111 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369) ?
regRenameTable[9:0] :
{ regRenameTable[9:3], fetchedControlToken$D_OUT[440:438] } ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7019 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8367 ?
regRenameTable[23] :
regRenameTable[7:3] == destReg__h279602 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11] ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7336 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8372 ?
regRenameTable[23:12] :
{ regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9102 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11],
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9134,
IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7334 } ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7357 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8376 ?
regRenameTable[23:12] :
{ regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9129 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11],
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9139,
IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7355 } ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7377 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8380 ?
regRenameTable[23:12] :
{ regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9130 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11],
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9140,
IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7375 } ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7403 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8384 ?
regRenameTable[23:12] :
{ regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9111 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11],
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9136,
IF_regRenameTable_953_BIT_11_992_AND_regRename_ETC___d7401 } ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7420 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8372 ?
regRenameTable[23] :
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9102 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11] ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7424 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8376 ?
regRenameTable[23] :
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9129 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11] ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7427 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8380 ?
regRenameTable[23] :
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9130 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11] ;
assign IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7453 =
regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8384 ?
regRenameTable[23] :
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9111 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[11] ;
assign IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7026 =
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8365 ?
regRenameTable[33:32] :
(regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8367 ?
regRenameTable[21:20] :
regRenameTable[9:8]) ;
assign IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7437 =
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8371 ?
regRenameTable[34] :
(regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8372 ?
regRenameTable[22] :
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9134) ;
assign IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7441 =
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8375 ?
regRenameTable[34] :
(regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8376 ?
regRenameTable[22] :
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9139) ;
assign IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7444 =
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8379 ?
regRenameTable[34] :
(regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8380 ?
regRenameTable[22] :
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9140) ;
assign IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7464 =
regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8383 ?
regRenameTable[34] :
(regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8384 ?
regRenameTable[22] :
regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9136) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8363 ?
regRenameTable[45:44] :
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7026 ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8841 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8370 ?
regRenameTable[47] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8371 ?
regRenameTable[35] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7420) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8842 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8370 ?
regRenameTable[46] :
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7437 ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8845 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8382 ?
regRenameTable[47] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8383 ?
regRenameTable[35] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7453) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8846 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8382 ?
regRenameTable[46] :
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7464 ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8849 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8374 ?
regRenameTable[47] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8375 ?
regRenameTable[35] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7424) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8850 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8378 ?
regRenameTable[47] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8379 ?
regRenameTable[35] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7427) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8851 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8374 ?
regRenameTable[46] :
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7441 ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8852 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8378 ?
regRenameTable[46] :
IF_regRenameTable_953_BIT_35_966_AND_regRename_ETC___d7444 ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8363 ?
regRenameTable[47] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8365 ?
regRenameTable[35] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7019) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9210 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8378 ?
regRenameTable[47:36] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8379 ?
regRenameTable[35:24] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7377) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9212 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8374 ?
regRenameTable[47:36] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8375 ?
regRenameTable[35:24] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7357) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9213 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8370 ?
regRenameTable[47:36] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8371 ?
regRenameTable[35:24] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7336) ;
assign IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9214 =
regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8382 ?
regRenameTable[47:36] :
(regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8383 ?
regRenameTable[35:24] :
IF_regRenameTable_953_BIT_23_979_AND_regRename_ETC___d7403) ;
assign IF_theCP0_tlbLookupData_response_get_777_BITS__ETC___d3085 =
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 &&
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ||
theMem_dCache_req_fifo$D_OUT[135:128] == 8'hFF)) ?
req_data__h190926 :
req_data__h191769 ;
assign IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7776 =
b__h202732 +
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] ;
assign IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7779 =
b__h202732 +
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 ;
assign IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d8035 =
(theCapCop_capInsts$D_OUT[4:0] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[75:12] :
theCapCop_lengthRegs$D_OUT_1 ;
assign IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3683 =
(theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548) ?
{ IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3681,
regNum__h203787,
theCapCop_capInsts$D_OUT[16:10] } :
{ IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9055,
regNum__h203787,
theCapCop_capInsts$D_OUT[16:10] } ;
assign IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d4595 =
(theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548) ?
theCapCop_pcc_read__315_BIT_244_550_OR_NOT_IF__ETC___d4592 :
!theCapCop_capInsts$D_OUT[17] &&
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4593 ;
assign IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d4614 =
(theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548) ?
theCapCop_pcc_read__315_BIT_244_550_OR_NOT_IF__ETC___d4611 :
!theCapCop_capInsts$D_OUT[17] &&
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4612 ;
assign IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9257 =
(theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548) ?
{ IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3656,
regNum__h203787,
theCapCop_capInsts$D_OUT[16:10] } :
{ IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886,
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9055,
regNum__h203787,
theCapCop_capInsts$D_OUT[16:10] } ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3544 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[266] :
theCapCop_permRegs$D_OUT_1[62] ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3595 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
!theCapCop_capWriteback[267] || !theCapCop_capWriteback[266] :
!theCapCop_permRegs$D_OUT_1[63] ||
!theCapCop_permRegs$D_OUT_1[62] ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3604 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
!theCapCop_capWriteback[267] :
!theCapCop_permRegs$D_OUT_1[63] ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3605 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
!theCapCop_capWriteback[266] :
!theCapCop_permRegs$D_OUT_1[62] ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3639 =
{ x1_avValue_base__h200801,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9049 ?
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 :
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 } ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3672 =
{ x1_avValue_base__h200801,
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9061 ?
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 :
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] } ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d7882 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[267:12] :
{ theCapCop_permRegs$D_OUT_1[63:48],
48'b0,
theCapCop_oTypeRegs$D_OUT_1,
theCapCop_baseRegs$D_OUT_2,
theCapCop_lengthRegs$D_OUT_2 } ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[75:12] :
theCapCop_lengthRegs$D_OUT_2 ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[266:252] :
theCapCop_permRegs$D_OUT_1[62:48] ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[267] :
theCapCop_permRegs$D_OUT_1[63] ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9049 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 <
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9050 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 <=
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[139:12] :
{ theCapCop_baseRegs$D_OUT_2, theCapCop_lengthRegs$D_OUT_2 } ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[266:12] :
{ theCapCop_permRegs$D_OUT_1[62:48],
48'b0,
theCapCop_oTypeRegs$D_OUT_1,
theCapCop_baseRegs$D_OUT_2,
theCapCop_lengthRegs$D_OUT_2 } ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9061 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 <
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] ;
assign IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9062 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 <=
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] ;
assign IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599 =
(theCapCop_pcc[63:0] < 64'd4) ? 64'd0 : theCapCop_pcc[127:64] ;
assign IF_theMem_capExceptions_i_notEmpty__490_THEN_I_ETC___d8802 =
theMem_capExceptions$EMPTY_N ?
(theMem_capExceptions_first__525_BITS_3_TO_0_52_ETC___d8708 ?
theMem_capExceptions$D_OUT[8:4] :
5'd25) :
5'd25 ;
assign IF_theMem_dCache_out_fifo_ff_i_notEmpty__489_T_ETC___d8718 =
theMem_dCache_out_fifo_ff$EMPTY_N ?
theMem_dCache_out_fifo_ff$D_OUT[68:64] :
theMem_dCache_out_fifo_enqw$wget[68:64] ;
assign IF_theMem_dCache_req_fifo_first__733_BIT_128_0_ETC___d7546 =
theMem_dCache_req_fifo$D_OUT[128] ?
{ v__h188873[63:8], theMem_dCache_req_fifo$D_OUT[7:0] } :
v__h188873 ;
assign IF_theMem_dCache_req_fifo_first__733_BIT_129_0_ETC___d7545 =
theMem_dCache_req_fifo$D_OUT[129] ?
{ IF_theMem_dCache_req_fifo_first__733_BIT_128_0_ETC___d7546[63:16],
theMem_dCache_req_fifo$D_OUT[15:8],
IF_theMem_dCache_req_fifo_first__733_BIT_128_0_ETC___d7546[7:0] } :
IF_theMem_dCache_req_fifo_first__733_BIT_128_0_ETC___d7546 ;
assign IF_theMem_dCache_req_fifo_first__733_BIT_130_0_ETC___d7544 =
theMem_dCache_req_fifo$D_OUT[130] ?
{ IF_theMem_dCache_req_fifo_first__733_BIT_129_0_ETC___d7545[63:24],
theMem_dCache_req_fifo$D_OUT[23:16],
IF_theMem_dCache_req_fifo_first__733_BIT_129_0_ETC___d7545[15:0] } :
IF_theMem_dCache_req_fifo_first__733_BIT_129_0_ETC___d7545 ;
assign IF_theMem_dCache_req_fifo_first__733_BIT_131_0_ETC___d7543 =
theMem_dCache_req_fifo$D_OUT[131] ?
{ IF_theMem_dCache_req_fifo_first__733_BIT_130_0_ETC___d7544[63:32],
theMem_dCache_req_fifo$D_OUT[31:24],
IF_theMem_dCache_req_fifo_first__733_BIT_130_0_ETC___d7544[23:0] } :
IF_theMem_dCache_req_fifo_first__733_BIT_130_0_ETC___d7544 ;
assign IF_theMem_dCache_req_fifo_first__733_BIT_132_0_ETC___d7542 =
theMem_dCache_req_fifo$D_OUT[132] ?
{ IF_theMem_dCache_req_fifo_first__733_BIT_131_0_ETC___d7543[63:40],
theMem_dCache_req_fifo$D_OUT[39:32],
IF_theMem_dCache_req_fifo_first__733_BIT_131_0_ETC___d7543[31:0] } :
IF_theMem_dCache_req_fifo_first__733_BIT_131_0_ETC___d7543 ;
assign IF_theMem_dCache_req_fifo_first__733_BIT_133_0_ETC___d7591 =
theMem_dCache_req_fifo$D_OUT[133] ?
{ IF_theMem_dCache_req_fifo_first__733_BIT_132_0_ETC___d7542[63:48],
theMem_dCache_req_fifo$D_OUT[47:40],
IF_theMem_dCache_req_fifo_first__733_BIT_132_0_ETC___d7542[39:0] } :
IF_theMem_dCache_req_fifo_first__733_BIT_132_0_ETC___d7542 ;
assign IF_theMem_dCache_req_fifo_first__733_BIT_134_0_ETC___d7590 =
theMem_dCache_req_fifo$D_OUT[134] ?
{ IF_theMem_dCache_req_fifo_first__733_BIT_133_0_ETC___d7591[63:56],
theMem_dCache_req_fifo$D_OUT[55:48],
IF_theMem_dCache_req_fifo_first__733_BIT_133_0_ETC___d7591[47:0] } :
IF_theMem_dCache_req_fifo_first__733_BIT_133_0_ETC___d7591 ;
assign IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2932 =
(theMem_dataByte$EMPTY_N && theMem_dataSize$EMPTY_N) ?
CASE_theMem_dataSizeD_OUT_temp74691_1_temp746_ETC__q198 :
temp__h174677 ;
assign IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2934 =
(theMem_dataByte$EMPTY_N && theMem_dataSize$EMPTY_N &&
(theMem_dataSize$D_OUT == 4'd4 ||
theMem_dataSize$D_OUT == 4'd5 ||
theMem_dataSize$D_OUT == 4'd6)) ?
(memAccessToWriteback$D_OUT[8] ?
{ {32{IF_theMem_dataSize_first__825_EQ_4_853_THEN_IF_ETC___d7551[31]}},
IF_theMem_dataSize_first__825_EQ_4_853_THEN_IF_ETC___d7551 } :
{ 32'd0,
IF_theMem_dataSize_first__825_EQ_4_853_THEN_IF_ETC___d7551 }) :
((!theMem_dataByte$EMPTY_N || !theMem_dataSize$EMPTY_N ||
theMem_dataSize$D_OUT != 4'd8 &&
theMem_dataSize$D_OUT != 4'd7 &&
theMem_dataSize$D_OUT != 4'd4 &&
theMem_dataSize$D_OUT != 4'd5 &&
theMem_dataSize$D_OUT != 4'd6) ?
IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2932 :
x_first_data__h174507) ;
assign IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2935 =
(theMem_dataByte$EMPTY_N && theMem_dataSize$EMPTY_N &&
theMem_dataSize$D_OUT == 4'd7) ?
(memAccessToWriteback$D_OUT[8] ?
{ {48{x76684_BITS_7_TO_0_CONCAT_x76684_BITS_15_TO_8__q199[15]}},
x76684_BITS_7_TO_0_CONCAT_x76684_BITS_15_TO_8__q199 } :
{ 48'd0, x__h176684[7:0], x__h176684[15:8] }) :
IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2934 ;
assign IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600 =
theMem_iCache_out_fifo_ff$EMPTY_N ?
theMem_iCache_out_fifo_ff$D_OUT[63:0] :
theMem_iCache_out_fifo_enqw$wget[63:0] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 =
writeback_destRenamed$EMPTY_N ?
((writeback_destRenamed$D_OUT == 2'd0) ?
writeback_results$D_OUT :
execute_renameRegsVector[63:0]) :
execute_renameRegsVector[63:0] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 =
writeback_destRenamed$EMPTY_N ?
((writeback_destRenamed$D_OUT == 2'd1) ?
writeback_results$D_OUT :
execute_renameRegsVector_1[63:0]) :
execute_renameRegsVector_1[63:0] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 =
writeback_destRenamed$EMPTY_N ?
((writeback_destRenamed$D_OUT == 2'd2) ?
writeback_results$D_OUT :
execute_renameRegsVector_2[63:0]) :
execute_renameRegsVector_2[63:0] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 =
writeback_destRenamed$EMPTY_N ?
((writeback_destRenamed$D_OUT == 2'd3) ?
writeback_results$D_OUT :
execute_renameRegsVector_3[63:0]) :
execute_renameRegsVector_3[63:0] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 =
writeback_destRenamed$EMPTY_N ?
writeback_destRenamed$D_OUT == 2'd0 ||
execute_renameRegsVector[64] :
execute_renameRegsVector[64] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 =
writeback_destRenamed$EMPTY_N ?
writeback_destRenamed$D_OUT == 2'd1 ||
execute_renameRegsVector_1[64] :
execute_renameRegsVector_1[64] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044 =
writeback_destRenamed$EMPTY_N ?
writeback_destRenamed$D_OUT == 2'd2 ||
execute_renameRegsVector_2[64] :
execute_renameRegsVector_2[64] ;
assign IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 =
writeback_destRenamed$EMPTY_N ?
writeback_destRenamed$D_OUT == 2'd3 ||
execute_renameRegsVector_3[64] :
execute_renameRegsVector_3[64] ;
assign NOT_decode_inQ_first__909_BIT_401_097_196_AND__ETC___d6235 =
!decode_inQ$D_OUT[401] &&
(!decode_inQ$D_OUT[1] ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7996 !=
4'd9) &&
((decode_inQ$D_OUT[435:434] == 2'd0) ?
((decode_inQ$D_OUT[433:428] == 6'd1) ?
decode_inQ$D_OUT[15] :
decode_inQ$D_OUT[433:428] == 6'd4 ||
decode_inQ$D_OUT[433:428] == 6'd5 ||
decode_inQ$D_OUT[433:428] == 6'd6 ||
decode_inQ$D_OUT[433:428] == 6'd7 ||
decode_inQ$D_OUT[433:428] == 6'd20 ||
decode_inQ$D_OUT[433:428] == 6'd21 ||
decode_inQ$D_OUT[433:428] == 6'd22 ||
decode_inQ$D_OUT[433:428] == 6'd23 ||
decode_inQ$D_OUT[433:428] == 6'd24 ||
decode_inQ$D_OUT[433:428] == 6'd25 ||
decode_inQ$D_OUT[433:428] == 6'd8 ||
decode_inQ$D_OUT[433:428] == 6'd9 ||
decode_inQ$D_OUT[433:428] == 6'd10 ||
decode_inQ$D_OUT[433:428] == 6'd11 ||
decode_inQ$D_OUT[433:428] == 6'd12 ||
decode_inQ$D_OUT[433:428] == 6'd13 ||
decode_inQ$D_OUT[433:428] == 6'd14 ||
decode_inQ$D_OUT[433:428] == 6'd15 ||
decode_inQ$D_OUT[433:428] == 6'd32 ||
decode_inQ$D_OUT[433:428] == 6'd33 ||
decode_inQ$D_OUT[433:428] == 6'd35 ||
decode_inQ$D_OUT[433:428] == 6'd34 ||
decode_inQ$D_OUT[433:428] == 6'd38 ||
decode_inQ$D_OUT[433:428] == 6'd48 ||
decode_inQ$D_OUT[433:428] == 6'd40 ||
decode_inQ$D_OUT[433:428] == 6'd41 ||
decode_inQ$D_OUT[433:428] == 6'd43 ||
decode_inQ$D_OUT[433:428] == 6'd42 ||
decode_inQ$D_OUT[433:428] == 6'd46 ||
decode_inQ$D_OUT[433:428] == 6'd55 ||
decode_inQ$D_OUT[433:428] == 6'd26 ||
decode_inQ$D_OUT[433:428] == 6'd27 ||
decode_inQ$D_OUT[433:428] == 6'd52 ||
decode_inQ$D_OUT[433:428] == 6'd63 ||
decode_inQ$D_OUT[433:428] == 6'd44 ||
decode_inQ$D_OUT[433:428] == 6'd45 ||
decode_inQ$D_OUT[433:428] == 6'd36 ||
decode_inQ$D_OUT[433:428] == 6'd37 ||
decode_inQ$D_OUT[433:428] == 6'd39 ||
decode_inQ$D_OUT[433:428] == 6'd56 ||
decode_inQ$D_OUT[433:428] == 6'd60 ||
decode_inQ$D_OUT[433:428] == 6'd47 ||
decode_inQ$D_OUT[15]) :
decode_inQ$D_OUT[435:434] == 2'd1 ||
((decode_inQ$D_OUT[435:434] == 2'd2) ?
((decode_inQ$D_OUT[433:428] == 6'd0) ?
decode_inQ$D_OUT[407:402] == 6'd0 ||
decode_inQ$D_OUT[407:402] == 6'd2 ||
decode_inQ$D_OUT[407:402] == 6'd3 ||
decode_inQ$D_OUT[407:402] == 6'd4 ||
decode_inQ$D_OUT[407:402] == 6'd6 ||
decode_inQ$D_OUT[407:402] == 6'd7 ||
decode_inQ$D_OUT[407:402] == 6'd32 ||
decode_inQ$D_OUT[407:402] == 6'd33 ||
decode_inQ$D_OUT[407:402] == 6'd34 ||
decode_inQ$D_OUT[407:402] == 6'd35 ||
decode_inQ$D_OUT[407:402] == 6'd24 ||
decode_inQ$D_OUT[407:402] == 6'd25 ||
decode_inQ$D_OUT[407:402] == 6'd26 ||
decode_inQ$D_OUT[407:402] == 6'd27 ||
decode_inQ$D_OUT[407:402] == 6'd16 ||
decode_inQ$D_OUT[407:402] == 6'd17 ||
decode_inQ$D_OUT[407:402] == 6'd18 ||
decode_inQ$D_OUT[407:402] == 6'd19 ||
decode_inQ$D_OUT[407:402] == 6'd36 ||
decode_inQ$D_OUT[407:402] == 6'd37 ||
decode_inQ$D_OUT[407:402] == 6'd39 ||
decode_inQ$D_OUT[407:402] == 6'd38 ||
decode_inQ$D_OUT[407:402] == 6'd20 ||
decode_inQ$D_OUT[407:402] == 6'd22 ||
decode_inQ$D_OUT[407:402] == 6'd23 ||
decode_inQ$D_OUT[407:402] == 6'd44 ||
decode_inQ$D_OUT[407:402] == 6'd45 ||
decode_inQ$D_OUT[407:402] == 6'd42 ||
decode_inQ$D_OUT[407:402] == 6'd43 ||
decode_inQ$D_OUT[407:402] == 6'd46 ||
decode_inQ$D_OUT[407:402] == 6'd47 ||
decode_inQ$D_OUT[407:402] == 6'd56 ||
decode_inQ$D_OUT[407:402] == 6'd58 ||
decode_inQ$D_OUT[407:402] == 6'd59 ||
decode_inQ$D_OUT[407:402] == 6'd60 ||
decode_inQ$D_OUT[407:402] == 6'd62 ||
decode_inQ$D_OUT[407:402] == 6'd63 ||
decode_inQ$D_OUT[407:402] == 6'd28 ||
decode_inQ$D_OUT[407:402] == 6'd29 ||
decode_inQ$D_OUT[407:402] == 6'd30 ||
decode_inQ$D_OUT[407:402] == 6'd31 ||
decode_inQ$D_OUT[407:402] == 6'd10 ||
decode_inQ$D_OUT[407:402] == 6'd11 ||
decode_inQ$D_OUT[407:402] == 6'd8 ||
decode_inQ$D_OUT[407:402] == 6'd9 ||
decode_inQ$D_OUT[407:402] == 6'd48 ||
decode_inQ$D_OUT[407:402] == 6'd49 ||
decode_inQ$D_OUT[407:402] == 6'd50 ||
decode_inQ$D_OUT[407:402] == 6'd51 ||
decode_inQ$D_OUT[407:402] == 6'd52 ||
decode_inQ$D_OUT[407:402] == 6'd54 ||
decode_inQ$D_OUT[407:402] == 6'd12 ||
decode_inQ$D_OUT[407:402] == 6'd13 ||
decode_inQ$D_OUT[407:402] == 6'd15 ||
decode_inQ$D_OUT[15] :
decode_inQ$D_OUT[433:428] != 6'd28 ||
decode_inQ$D_OUT[407:402] == 6'd2 ||
decode_inQ$D_OUT[407:402] == 6'd0 ||
decode_inQ$D_OUT[407:402] == 6'd1 ||
decode_inQ$D_OUT[407:402] == 6'd4 ||
decode_inQ$D_OUT[407:402] == 6'd5 ||
decode_inQ$D_OUT[15]) :
decode_inQ$D_OUT[433:428] != 6'd18 ||
!theCP0$getCoprocessorEnables[2] && !decode_inQ$D_OUT[1] ||
decode_inQ$D_OUT[427:423] == 5'd0 ||
decode_inQ$D_OUT[427:423] == 5'd4 ||
decode_inQ$D_OUT[427:423] == 5'd20 ||
decode_inQ$D_OUT[427:423] == 5'd21 ||
decode_inQ$D_OUT[427:423] == 5'd22 ||
decode_inQ$D_OUT[427:423] == 5'd23 ||
decode_inQ$D_OUT[427:423] == 5'd28 ||
decode_inQ$D_OUT[427:423] == 5'd29 ||
decode_inQ$D_OUT[427:423] == 5'd30 ||
decode_inQ$D_OUT[427:423] == 5'd31 ||
decode_inQ$D_OUT[427:423] == 5'd16 ||
decode_inQ$D_OUT[427:423] == 5'd17 ||
decode_inQ$D_OUT[427:423] == 5'd18 ||
decode_inQ$D_OUT[427:423] == 5'd19 ||
decode_inQ$D_OUT[427:423] == 5'd24 ||
decode_inQ$D_OUT[427:423] == 5'd25 ||
decode_inQ$D_OUT[427:423] == 5'd26 ||
decode_inQ$D_OUT[427:423] == 5'd27 ||
decode_inQ$D_OUT[427:423] == 5'd8 ||
decode_inQ$D_OUT[427:423] == 5'd7 ||
decode_inQ$D_OUT[427:423] == 5'd1 ||
decode_inQ$D_OUT[427:423] == 5'd3 ||
decode_inQ$D_OUT[427:423] == 5'd9 ||
decode_inQ$D_OUT[427:423] == 5'd10 ||
decode_inQ$D_OUT[15])) ;
assign NOT_memAccessToWriteback_first__516_BIT_393_53_ETC___d3089 =
!memAccessToWriteback$D_OUT[393] &&
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25] ||
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d9145 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[0]) ;
assign NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d1818 =
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 ||
!theMem_dCache_tags_serverAdapterA_outData_outData$wget[25]) &&
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d9145 ||
!theMem_dCache_tags_serverAdapterA_outData_outData$wget[0]) ||
!theCP0$tlbLookupData_response_get[6] ;
assign NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d3023 =
(NOT_theCP0_tlbLookupData_response_get_777_BITS_ETC___d1818 ||
!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 &&
theMem_dCache_req_fifo$D_OUT[135:128] != 8'hFF) &&
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8729 ==
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
NOT_theCP0_tlbLookupData_response_get_777_BIT__ETC___d3021 ;
assign NOT_theCP0_tlbLookupData_response_get_777_BIT__ETC___d3021 =
!theCP0$tlbLookupData_response_get[6] ||
!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 &&
theMem_dCache_req_fifo$D_OUT[135:128] != 8'hFF ||
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 ||
!theMem_dCache_tags_serverAdapterA_outData_outData$wget[25]) &&
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d9145 ||
!theMem_dCache_tags_serverAdapterA_outData_outData$wget[0]) ;
assign NOT_theCP0_tlbLookupData_response_get_777_BIT__ETC___d3092 =
(!theCP0$tlbLookupData_response_get[6] ||
!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 &&
theMem_dCache_req_fifo$D_OUT[135:128] != 8'hFF) &&
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8729 ==
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
NOT_memAccessToWriteback_first__516_BIT_393_53_ETC___d3089 ;
assign NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548 =
theCapCop_capInsts$D_OUT[99:95] == 5'd7 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd1 &&
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213 &&
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3544 ;
assign NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3600 =
theCapCop_capInsts$D_OUT[99:95] != 5'd4 &&
theCapCop_capInsts$D_OUT[99:95] != 5'd7 &&
(theCapCop_capInsts$D_OUT[99:95] != 5'd1 ||
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3595) &&
theCapCop_writesCalculated_read__320_EQ_theCap_ETC___d3321 ;
assign NOT_theCapCop_capMemInsts_i_notEmpty__482_483__ETC___d2762 =
!theCapCop_capMemInsts$EMPTY_N && theCapCop_capState != 3'd3 &&
theCapCop_capState != 3'd0 &&
(theMem_dCache_out_fifo_ff$EMPTY_N ||
theMem_dCache_out_fifo_enqw$whas) &&
NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d2760 ;
assign NOT_theDebug_bpReport_notEmpty__0_1_AND_NOT_th_ETC___d6504 =
!theDebug_bpReport$EMPTY_N && !theMem_iCacheOp$EMPTY_N &&
theMem_iCache_cacheState != 2'd0 &&
!theCapCop_exception$EMPTY_N &&
branch$RDY_getPc &&
theCP0$RDY_tlbLookupInstruction_request_put &&
theMem_iCache_req_fifo_i_notFull__917_AND_theM_ETC___d6498 ;
assign NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d2514 =
(!theMem_pendingExcRpt$EMPTY_N ||
theMem_capExceptions$EMPTY_N) &&
branch$RDY_pcWriteback &&
memAccessToWriteback$EMPTY_N &&
freeRenameReg$FULL_N &&
theCapCop_capWritebackTags$EMPTY_N &&
theCapCop_insts$EMPTY_N &&
writeback_instructionReport_i_notFull__497_AND_ETC___d2508 ;
assign NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d2760 =
(!theMem_pendingExcRpt$EMPTY_N ||
theMem_capExceptions$EMPTY_N) &&
branch$RDY_pcWriteback &&
memAccessToWriteback$EMPTY_N &&
freeRenameReg_i_notFull__494_AND_theCapCop_cap_ETC___d2757 ;
assign NOT_theMem_pendingExcRpt_i_notEmpty__488_489_O_ETC___d3004 =
(!theMem_pendingExcRpt$EMPTY_N ||
theMem_capExceptions$EMPTY_N) &&
branch$RDY_pcWriteback &&
theCP0$RDY_tlbLookupData_response_get &&
theMem_dCache_tags_serverAdapterA_outDataCore__ETC___d3001 ;
assign NOT_writeback_instructionReport_first__347_BIT_ETC___d2481 =
!writeback_instructionReport$D_OUT[65] &&
!writeback_instructionReport$D_OUT[457] &&
(x__h168654 & theDebug_traceCmpMask) ==
(x__h169227 & theDebug_traceCmpMask) ;
assign SEXT_IF_execute_inQ_first__341_BIT_330_463_THE_ETC___d8040 =
(signedA__h217100 ^ 65'h10000000000000000) <=
65'h10000000000000000 ;
assign SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041 =
{ {48{decode_inQD_OUT_BITS_417_TO_402__q64[15]}},
decode_inQD_OUT_BITS_417_TO_402__q64 } ;
assign _0_CONCAT_IF_IF_theCapCop_capInsts_first__372_B_ETC___d7848 =
{ 58'd0,
CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51 } ;
assign _0_CONCAT_IF_execute_inQ_first__341_BITS_12_TO__ETC___d7847 =
{ 58'd0,
CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52 } ;
assign _0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027 =
_theResult_____7__h200324 + _theResult_____6__h200326 ;
assign _0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8034 =
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] +
64'd32 <=
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d8035 ;
assign _0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8038 =
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] <
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 ;
assign _0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d9060 =
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] +
_0_CONCAT_IF_IF_theCapCop_capInsts_first__372_B_ETC___d7848 <=
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 ;
assign _7_MINUS_y61581__q7 = 6'd7 - y__h161581 ;
assign _dfoo1 =
!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_1$EMPTY_N &&
!theMem_theMemMerge_req_fifos_1$D_OUT[316] ||
!theMem_theMemMerge_req_fifos_1$EMPTY_N &&
!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_2$EMPTY_N &&
!theMem_theMemMerge_req_fifos_2$D_OUT[316] ;
assign _dfoo4 =
(!theMem_theMemMerge_req_fifos$EMPTY_N &&
theMem_theMemMerge_req_fifos_1$EMPTY_N) ?
theMem_theMemMerge_req_fifos_1$D_OUT :
theMem_theMemMerge_req_fifos_2$D_OUT ;
assign _dor1execute_loadsDone$EN_write =
WILL_FIRE_RL_execute_doReadReport ||
WILL_FIRE_RL_execute_doExecute ;
assign _dor1writeback_destRenamed$EN_deq =
WILL_FIRE_RL_execute_doReadReport ||
WILL_FIRE_RL_execute_doExecute ;
assign _dor1writeback_results$EN_deq =
WILL_FIRE_RL_execute_doReadReport ||
WILL_FIRE_RL_execute_doExecute ;
assign _theResult_____1_opB__h245437 =
decode_inQ$D_OUT[1] ?
_theResult___snd__h257319 :
theRF_regFile$D_OUT_1 ;
assign _theResult_____2___1_victim__h171283 =
memAccessToWriteback$D_OUT[401] ?
memAccessToWriteback$D_OUT[101:38] - 64'd4 :
memAccessToWriteback$D_OUT[101:38] ;
assign _theResult_____3_fst__h222045 =
execute_inQ$D_OUT[381] ?
carryOut1__h222151 :
carryOut1__h222047 ;
assign _theResult_____3_snd__h222037 =
execute_inQ$D_OUT[381] ? calcResult__h222022 : result__h223255 ;
assign _theResult_____3_snd__h222046 =
execute_inQ$D_OUT[381] ?
carryOut2__h222152 :
carryOut2__h222048 ;
assign _theResult_____4__h222021 =
(execute_inQ$D_OUT[379:375] == 5'd1) ?
opB__h222122 :
_theResult_____6__h200326 ;
assign _theResult_____4_snd__h222754 = _theResult_____7__h200324 ;
assign _theResult_____4_snd__h223554 =
execute_inQ$D_OUT[381] ?
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5] ?
calcResult___1__h223584 :
calcResult__h223553) :
calcResult__h223553 ;
assign _theResult_____4_snd_snd__h222026 =
execute_inQ$D_OUT[380] ?
_theResult_____3_snd__h222037 :
calcResult__h222022 ;
assign _theResult_____6__h200326 =
{ 1'b0,
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 } ;
assign _theResult_____7__h200324 =
{ 1'b0,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 } ;
assign _theResult_____8_fst_oType_eaddr__h203894 =
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8038 ?
writeback___1_base__h203941 :
x1_avValue_oType_eaddr__h200800 ;
assign _theResult_____8_fst_oType_eaddr__h207324 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8039 ?
writeback___1_base__h207371 :
x1_avValue_oType_eaddr__h200800 ;
assign _theResult___fst__h257318 =
(decode_inQ$D_OUT[427:423] == 5'd0) ?
theDebug_opA :
theRF_regFile$D_OUT_2 ;
assign _theResult___fst_coProSelect__h281892 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[404:402] :
instruction__h274083[2:0] ;
assign _theResult___snd__h257319 =
(decode_inQ$D_OUT[422:418] == 5'd0) ?
theDebug_opB :
theRF_regFile$D_OUT_1 ;
assign _theResult___snd__h280672 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd24) ?
5'd14 :
v__h278907 ;
assign ab__h107013 = 2'd0 ;
assign ab__h108440 = 2'd2 ;
assign ab__h110016 = 2'd0 ;
assign ab__h111421 = 2'd2 ;
assign ab__h122228 = 2'd2 ;
assign ab__h124191 = 2'd0 ;
assign ab__h125596 = 2'd2 ;
assign addr__h174623 = { theMem_dataByte$D_OUT, 3'b0 } ;
assign addr__h271109 = { branch$getPc[66:5], 2'b0 } ;
assign b__h202732 =
(theCapCop_capInsts$D_OUT[4:0] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[139:76] :
theCapCop_baseRegs$D_OUT_1 ;
assign branchTarget__h283587 =
{ fetchedControlToken$D_OUT[101:66], x__h285667 } ;
assign branchTarget__h285642 = x__h285659 + 64'd4 ;
assign branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2655 =
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25 &&
memAccessToWriteback$D_OUT[383:382] == 2'd0 &&
memAccessToWriteback$D_OUT[391:387] != 5'd0 ;
assign branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d2824 =
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25 &&
memAccessToWriteback$D_OUT[383:382] == 2'd0 &&
memAccessToWriteback$D_OUT[391:387] != 5'd0 ;
assign branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d3148 =
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25 &&
memAccessToWriteback$D_OUT[383:382] == 2'd0 &&
memAccessToWriteback$D_OUT[391:387] != 5'd0 ;
assign branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 =
branch$getEpoch == memAccessToWriteback$D_OUT[440:438] ;
assign branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b0_5_ETC___d8037 =
addr__h271109 + 64'd4 <= theCapCop_pcc[63:0] ;
assign byteMask__h140788 =
{ memAccess_inQ$D_OUT[232:230] == 3'd7,
memAccess_inQ$D_OUT[232:230] == 3'd6,
memAccess_inQ$D_OUT[232:230] == 3'd5,
memAccess_inQ$D_OUT[232:230] == 3'd4,
memAccess_inQ$D_OUT[232:230] == 3'd3,
memAccess_inQ$D_OUT[232:230] == 3'd2,
memAccess_inQ$D_OUT[232:230] == 3'd1,
IF_memAccess_inQD_OUT_BITS_232_TO_230_EQ_0_TH_ETC__q1[0] } ;
assign byteMask__h142387 =
{ (memAccess_inQ$D_OUT[232:231] == 2'd3) ?
memAccess_inQ$D_OUT[232:231] :
2'd0,
(memAccess_inQ$D_OUT[232:231] == 2'd2) ? 2'd3 : 2'd0,
(memAccess_inQ$D_OUT[232:231] == 2'd1) ? 2'd3 : 2'd0,
IF_memAccess_inQD_OUT_BITS_232_TO_231_EQ_0_TH_ETC__q2[1:0] } ;
assign byteMask__h143211 =
{ memAccess_inQ$D_OUT[232] ? 4'd15 : 4'd0,
IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_15__q3[3:0] } ;
assign byteMask__h147923 =
{ memAccess_inQ$D_OUT[232] ? mask__h147921 : 4'd0,
IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_0_C_ETC__q4[3:0] } ;
assign byteMask__h148413 =
{ memAccess_inQ$D_OUT[232] ? mask__h148411 : 4'd0,
IF_memAccess_inQD_OUT_BIT_232_THEN_0_ELSE_0_C_ETC__q8[3:0] } ;
assign byteMask__h148899 = 8'hFF << memAccess_inQ$D_OUT[232:230] ;
assign byteMask__h148955 = 8'hFF >> x__h148959 ;
assign calcResult21868_BITS_31_TO_0__q159 = calcResult__h221868[31:0] ;
assign calcResult23403_BITS_31_TO_0__q149 = calcResult__h223403[31:0] ;
assign calcResult___1__h223433 = { calcResult__h223403[32:0], 32'd0 } ;
assign calcResult___1__h223584 = { 33'd0, x__h223587[63:32] } ;
assign calcResult___1__h223707 = { x__h223710[63], x__h223710 } ;
assign calcResult__h221346 =
{ 1'd0,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 ^
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 } ;
assign calcResult__h221354 =
{ 1'd0,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 &
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 } ;
assign calcResult__h221414 = { execute_hi[63], execute_hi } ;
assign calcResult__h221422 = { execute_lo[63], execute_lo } ;
assign calcResult__h222022 =
_theResult_____7__h200324 + _theResult_____4__h222021 ;
assign calcResult__h223403 = { x__h223436[63], x__h223436 } ;
assign calcResult__h223521 =
{ {33{calcResult23403_BITS_31_TO_0__q149[31]}},
calcResult23403_BITS_31_TO_0__q149 } ;
assign calcResult__h223553 = { 1'd0, x__h223587 } ;
assign calcResult__h231541 =
{ IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d8815[63],
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d8815 } ;
assign carryOut1__h222047 = x__h222061 ^ calcResult__h222022[31] ;
assign carryOut1__h222151 = x__h222165 ^ calcResult__h222022[63] ;
assign carryOut2__h222048 = x__h222259 ^ calcResult__h222022[32] ;
assign carryOut2__h222152 =
_theResult_____4__h222021[64] ^ calcResult__h222022[64] ;
assign dataRead___1__h189582 =
theMem_dCache_req_fifo$D_OUT[135] ?
{ theMem_dCache_req_fifo$D_OUT[63:56],
IF_theMem_dCache_req_fifo_first__733_BIT_134_0_ETC___d7590[55:0] } :
IF_theMem_dCache_req_fifo_first__733_BIT_134_0_ETC___d7590 ;
assign decode_inQD_OUT_BITS_412_TO_402__q11 = decode_inQ$D_OUT[412:402] ;
assign decode_inQD_OUT_BITS_417_TO_402__q64 = decode_inQ$D_OUT[417:402] ;
assign decode_inQ_first__909_BITS_366_TO_331_870_CONC_ETC___d6369 =
{ decode_inQ$D_OUT[366:331],
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q99,
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d6368 } ;
assign destReg__h279602 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
y_avValue_snd_snd_snd_fst__h282686 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
_theResult_____7_snd_snd_snd_fst__h282775 :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d6946) ;
assign di___1_opB__h240965 = { 61'd0, decode_inQ$D_OUT[404:402] } ;
assign di_opA__h250012 = decode_inQ$D_OUT[101:38] + 64'd8 ;
assign di_opA__h252675 =
{ {53{decode_inQD_OUT_BITS_412_TO_402__q11[10]}},
decode_inQD_OUT_BITS_412_TO_402__q11 } ;
assign di_opB__h245718 = { 48'd0, decode_inQ$D_OUT[417:402] } ;
assign di_opB__h246406 = { 32'd0, x__h257533 } ;
assign di_opB__h248895 = { 59'd0, decode_inQ$D_OUT[412:408] } ;
assign di_opB__h249572 = di_opB__h248895 + 64'd32 ;
assign er___1_opB__h212042 = { 63'd0, theCP0$getLlScReg } ;
assign execute_inQD_OUT_BITS_417_TO_402_CONCAT_0b0__q160 =
{ execute_inQ$D_OUT[417:402], 2'b0 } ;
assign execute_inQ_first__341_BITS_379_TO_372_466_CON_ETC___d4518 =
{ execute_inQ$D_OUT[379:372],
CASE_execute_inQD_OUT_BITS_379_TO_375_execute_ETC__q161,
execute_inQ$D_OUT[366:294],
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d7597[63:0],
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829,
x__h213493,
execute_inQ$D_OUT[101:0] } ;
assign execute_inQ_first__341_BITS_391_TO_384_433_CON_ETC___d4520 =
{ execute_inQ$D_OUT[391:384],
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992,
execute_inQ$D_OUT[381],
CASE_execute_inQD_OUT_BITS_379_TO_375_NOT_exe_ETC__q162,
execute_inQ_first__341_BITS_379_TO_372_466_CON_ETC___d4518 } ;
assign execute_inQ_first__341_BITS_401_TO_372_564_CON_ETC___d4659 =
{ execute_inQ$D_OUT[401:372],
(execute_inQ$D_OUT[371:367] == 5'd25) ?
IF_IF_execute_inQ_first__341_BITS_379_TO_375_3_ETC___d4616 :
execute_inQ$D_OUT[371:367],
execute_inQ$D_OUT[366:294],
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d9064,
x__h213427,
x__h213493,
execute_inQ$D_OUT[101:0] } ;
assign execute_inQ_first__341_BIT_401_522_CONCAT_IF_e_ETC___d4562 =
{ execute_inQ$D_OUT[401],
(execute_inQ$D_OUT[435:434] == 2'd0) ?
(IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 ?
4'd6 :
4'd7) :
execute_inQ$D_OUT[400:397],
execute_inQ$D_OUT[396:294],
x__h217866,
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829,
x__h213493,
execute_inQ$D_OUT[101:38],
(execute_inQ$D_OUT[435:434] == 2'd0) ?
(IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 ?
{ {2{execute_inQD_OUT_BITS_417_TO_402_CONCAT_0b0__q160[17]}},
execute_inQD_OUT_BITS_417_TO_402_CONCAT_0b0__q160 } +
20'd4 :
20'd8) :
execute_inQ$D_OUT[37:18],
execute_inQ$D_OUT[17:1],
(execute_inQ$D_OUT[435:434] == 2'd0) ?
(IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 ?
execute_inQ$D_OUT[0] :
execute_inQ$D_OUT[396] || execute_inQ$D_OUT[0]) :
execute_inQ$D_OUT[0] } ;
assign execute_loadsDone_248_EQ_execute_loadsIn_249_M_ETC___d3368 =
execute_loadsDone == execute_loadsIn - 4'd1 &&
writeback_results$EMPTY_N ||
execute_loadsDone_248_EQ_execute_loadsIn_249___d3250 ;
assign execute_loadsDone_248_EQ_execute_loadsIn_249___d3250 =
execute_loadsDone == execute_loadsIn ;
assign expWb___1_entry__h170521 =
theCP0$getException[6] ? entry__h170816 : entry__h170934 ;
assign expWb___1_entry__h175093 =
theCP0$getException[6] ? entry__h175335 : entry__h175453 ;
assign expWb___1_entry__h193005 =
theCP0$getException[6] ? entry__h193251 : entry__h193369 ;
assign fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7032 =
fetchedControlToken$D_OUT[437:436] == 2'd3 ||
(IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 !=
2'd3 &&
regRenameTable[47] :
regRenameTable[47]) ;
assign fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7107 =
fetchedControlToken$D_OUT[437:436] == 2'd2 ||
(IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 !=
2'd2 &&
regRenameTable[35] :
regRenameTable[35]) ;
assign fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7119 =
fetchedControlToken$D_OUT[437:436] == 2'd1 ||
(IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 !=
2'd1 &&
regRenameTable[23] :
regRenameTable[23]) ;
assign fetchedControlToken_first__662_BITS_437_TO_436_ETC___d7131 =
fetchedControlToken$D_OUT[437:436] == 2'd0 ||
(IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8855 ?
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 !=
2'd0 &&
regRenameTable[11] :
regRenameTable[11]) ;
assign freeRenameReg_i_notFull__494_AND_theCapCop_cap_ETC___d2757 =
freeRenameReg$FULL_N && theCapCop_capWritebackTags$EMPTY_N &&
theCapCop_insts$EMPTY_N &&
writeback_instructionReport$FULL_N &&
theMem_dCache_out_fifo_firstValid$Q_OUT &&
writeback_exception$FULL_N &&
theRF_regFileState_4_AND_writeback_hiLoCommit__ETC___d2751 ;
assign immediate__h279604 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
y_avValue_snd_snd_snd_snd_fst__h283943 :
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608 ?
immediate__h280058 :
26'd0) ;
assign immediate__h280058 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[427:402] :
instruction__h274083[25:0] ;
assign instruction__h274083 =
theMem_instructionWord$D_OUT ?
{ IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[39:32],
IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[47:40],
IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[55:48],
IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[63:56] } :
{ IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[7:0],
IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[15:8],
IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[23:16],
IF_theMem_iCache_out_fifo_ff_i_notEmpty__092_T_ETC___d7600[31:24] } ;
assign jumpTarget__h170772 =
{ memAccessToWriteback$D_OUT[101:66],
memAccessToWriteback$D_OUT[427:402],
2'b0 } ;
assign lastEpoch_779_EQ_fetchedControlToken_first__66_ETC___d8992 =
lastEpoch == fetchedControlToken$D_OUT[440:438] ;
assign lastWasBranch_778_AND_lastEpoch_779_EQ_fetched_ETC___d7511 =
{ lastWasBranch &&
lastEpoch_779_EQ_fetchedControlToken_first__66_ETC___d8992 ||
fetchedControlToken$D_OUT[401],
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ?
fetchedControlToken$D_OUT[400:397] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7281,
fetchedControlToken$D_OUT[396],
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8006,
fetchedControlToken$D_OUT[393:387],
x_coProSelect__h290167,
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7304,
fetchedControlToken$D_OUT[381:372],
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d7507 } ;
assign mask__h147921 = 4'hF << memAccess_inQ$D_OUT[231:230] ;
assign mask__h148411 = 4'hF >> x__h148596 ;
assign mask__h174653 = 32'hFFFFFFFF << shift__h174651 ;
assign mask__h174665 = 32'hFFFFFFFF >> shift__h174663 ;
assign mask__h174680 = 64'hFFFFFFFFFFFFFFFF << addr__h174623 ;
assign mask__h174690 = 64'hFFFFFFFFFFFFFFFF >> shift__h174688 ;
assign memAccessToWritebackD_OUT_BITS_37_TO_18__q10 =
memAccessToWriteback$D_OUT[37:18] ;
assign memAccessToWriteback_first__516_BITS_391_TO_38_ETC___d9252 =
{ memAccessToWriteback$D_OUT[391:387] == 5'd0,
memAccessToWriteback$D_OUT[293:230] } ;
assign memAccessToWriteback_first__516_BITS_444_TO_44_ETC___d2705 =
memAccessToWriteback$D_OUT[444:441] ==
theCapCop_capWritebackTags$D_OUT[7:4] ;
assign memAccess_inQ_first__055_BITS_366_TO_294_275_C_ETC___d2287 =
{ memAccess_inQ$D_OUT[366:294],
x__h163529,
memAccess_inQ$D_OUT[229:15],
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q116,
memAccess_inQ$D_OUT[12:0] } ;
assign memAccess_inQ_first__055_BITS_401_TO_372_264_C_ETC___d2288 =
{ memAccess_inQ$D_OUT[401:372],
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q117,
memAccess_inQ_first__055_BITS_366_TO_294_275_C_ETC___d2287 } ;
assign newVal__h6189 =
{ theDebug_debugConvert$messages_request_get[7:0],
theDebug_debugConvert$messages_request_get[15:8],
theDebug_debugConvert$messages_request_get[23:16],
theDebug_debugConvert$messages_request_get[31:24],
theDebug_debugConvert$messages_request_get[39:32],
theDebug_debugConvert$messages_request_get[47:40],
theDebug_debugConvert$messages_request_get[55:48],
theDebug_debugConvert$messages_request_get[63:56] } ;
assign off__h176682 = { theMem_dataByte$D_OUT[2:1], 4'd0 } ;
assign off__h177367 = { theMem_dataByte$D_OUT[2], 5'd0 } ;
assign opA__h223616 =
{ 33'd0,
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31:0] } ;
assign opB__h222122 =
{ 1'd1,
~IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 } +
65'd1 ;
assign put_addr__h272334 =
{ IF_branch_getPc_511_BITS_66_TO_5_547_CONCAT_0b_ETC___d7598[63:2],
2'b0 } ;
assign put_addr__h273845 =
{ IF_theCapCop_pcc_read__315_BITS_63_TO_0_319_UL_ETC___d7599[63:2],
2'b0 } ;
assign regRenameTable_953_BITS_14_TO_12_984_EQ_fetche_ETC___d8368 =
regRenameTable[14:12] == fetchedControlToken$D_OUT[440:438] ;
assign regRenameTable_953_BITS_26_TO_24_971_EQ_fetche_ETC___d8366 =
regRenameTable[26:24] == fetchedControlToken$D_OUT[440:438] ;
assign regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 =
regRenameTable[2:0] == fetchedControlToken$D_OUT[440:438] ;
assign regRenameTable_953_BITS_38_TO_36_959_EQ_fetche_ETC___d8364 =
regRenameTable[38:36] == fetchedControlToken$D_OUT[440:438] ;
assign regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9102 =
regRenameTable[7:3] ==
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ;
assign regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9111 =
regRenameTable[7:3] == v__h277714 ;
assign regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9129 =
regRenameTable[7:3] == v__h278907 ;
assign regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9130 =
regRenameTable[7:3] == reqA__h280962 ;
assign regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9134 =
regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9102 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[10] ;
assign regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9136 =
regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9111 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[10] ;
assign regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9139 =
regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9129 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[10] ;
assign regRenameTable_953_BIT_11_992_AND_regRenameTab_ETC___d9140 =
regRenameTable[11] &&
regRenameTable_953_BITS_7_TO_3_996_EQ_IF_fetch_ETC___d9130 &&
regRenameTable_953_BITS_2_TO_0_997_EQ_fetchedC_ETC___d8369 &&
regRenameTable[10] ;
assign regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8367 =
regRenameTable[23] &&
regRenameTable[19:15] == destReg__h279602 &&
regRenameTable_953_BITS_14_TO_12_984_EQ_fetche_ETC___d8368 ;
assign regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8372 =
regRenameTable[23] &&
regRenameTable[19:15] ==
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 &&
regRenameTable_953_BITS_14_TO_12_984_EQ_fetche_ETC___d8368 ;
assign regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8376 =
regRenameTable[23] && regRenameTable[19:15] == v__h278907 &&
regRenameTable_953_BITS_14_TO_12_984_EQ_fetche_ETC___d8368 ;
assign regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8380 =
regRenameTable[23] && regRenameTable[19:15] == reqA__h280962 &&
regRenameTable_953_BITS_14_TO_12_984_EQ_fetche_ETC___d8368 ;
assign regRenameTable_953_BIT_23_979_AND_regRenameTab_ETC___d8384 =
regRenameTable[23] && regRenameTable[19:15] == v__h277714 &&
regRenameTable_953_BITS_14_TO_12_984_EQ_fetche_ETC___d8368 ;
assign regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8365 =
regRenameTable[35] &&
regRenameTable[31:27] == destReg__h279602 &&
regRenameTable_953_BITS_26_TO_24_971_EQ_fetche_ETC___d8366 ;
assign regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8371 =
regRenameTable[35] &&
regRenameTable[31:27] ==
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 &&
regRenameTable_953_BITS_26_TO_24_971_EQ_fetche_ETC___d8366 ;
assign regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8375 =
regRenameTable[35] && regRenameTable[31:27] == v__h278907 &&
regRenameTable_953_BITS_26_TO_24_971_EQ_fetche_ETC___d8366 ;
assign regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8379 =
regRenameTable[35] && regRenameTable[31:27] == reqA__h280962 &&
regRenameTable_953_BITS_26_TO_24_971_EQ_fetche_ETC___d8366 ;
assign regRenameTable_953_BIT_35_966_AND_regRenameTab_ETC___d8383 =
regRenameTable[35] && regRenameTable[31:27] == v__h277714 &&
regRenameTable_953_BITS_26_TO_24_971_EQ_fetche_ETC___d8366 ;
assign regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8363 =
regRenameTable[47] &&
regRenameTable[43:39] == destReg__h279602 &&
regRenameTable_953_BITS_38_TO_36_959_EQ_fetche_ETC___d8364 ;
assign regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8370 =
regRenameTable[47] &&
regRenameTable[43:39] ==
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 &&
regRenameTable_953_BITS_38_TO_36_959_EQ_fetche_ETC___d8364 ;
assign regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8374 =
regRenameTable[47] && regRenameTable[43:39] == v__h278907 &&
regRenameTable_953_BITS_38_TO_36_959_EQ_fetche_ETC___d8364 ;
assign regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8378 =
regRenameTable[47] && regRenameTable[43:39] == reqA__h280962 &&
regRenameTable_953_BITS_38_TO_36_959_EQ_fetche_ETC___d8364 ;
assign regRenameTable_953_BIT_47_954_AND_regRenameTab_ETC___d8382 =
regRenameTable[47] && regRenameTable[43:39] == v__h277714 &&
regRenameTable_953_BITS_38_TO_36_959_EQ_fetche_ETC___d8364 ;
assign reqA__h280962 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[412:408] :
instruction__h274083[10:6] ;
assign req_byteenable__h113255 =
{ (theMem_iCache_req_fifo$D_OUT[68:67] == 2'd3) ?
theMem_iCache_req_fifo$D_OUT[135:128] :
8'b0,
(theMem_iCache_req_fifo$D_OUT[68:67] == 2'd2) ?
theMem_iCache_req_fifo$D_OUT[135:128] :
8'b0,
(theMem_iCache_req_fifo$D_OUT[68:67] == 2'd1) ?
theMem_iCache_req_fifo$D_OUT[135:128] :
8'b0,
(theMem_iCache_req_fifo$D_OUT[68:67] == 2'd0) ?
theMem_iCache_req_fifo$D_OUT[135:128] :
8'b0 } ;
assign req_byteenable__h129049 =
{ (theMem_dCache_req_fifo$D_OUT[68:67] == 2'd3) ?
theMem_dCache_req_fifo$D_OUT[135:128] :
8'b0,
(theMem_dCache_req_fifo$D_OUT[68:67] == 2'd2) ?
theMem_dCache_req_fifo$D_OUT[135:128] :
8'b0,
(theMem_dCache_req_fifo$D_OUT[68:67] == 2'd1) ?
theMem_dCache_req_fifo$D_OUT[135:128] :
8'b0,
(theMem_dCache_req_fifo$D_OUT[68:67] == 2'd0) ?
theMem_dCache_req_fifo$D_OUT[135:128] :
8'b0 } ;
assign req_data__h133039 =
{ theMem_capPackets$D_OUT[11:4],
theMem_capPackets$D_OUT[19:12],
theMem_capPackets$D_OUT[27:20],
theMem_capPackets$D_OUT[35:28],
theMem_capPackets$D_OUT[43:36],
theMem_capPackets$D_OUT[51:44],
theMem_capPackets$D_OUT[59:52],
theMem_capPackets$D_OUT[67:60],
theMem_capPackets$D_OUT[75:68],
theMem_capPackets$D_OUT[83:76],
theMem_capPackets$D_OUT[91:84],
theMem_capPackets$D_OUT[99:92],
theMem_capPackets$D_OUT[107:100],
theMem_capPackets$D_OUT[115:108],
theMem_capPackets$D_OUT[123:116],
theMem_capPackets$D_OUT[131:124],
theMem_capPackets$D_OUT[139:132],
theMem_capPackets$D_OUT[147:140],
theMem_capPackets$D_OUT[155:148],
theMem_capPackets$D_OUT[163:156],
theMem_capPackets$D_OUT[171:164],
theMem_capPackets$D_OUT[179:172],
theMem_capPackets$D_OUT[187:180],
theMem_capPackets$D_OUT[195:188],
theMem_capPackets$D_OUT[203:196],
theMem_capPackets$D_OUT[211:204],
theMem_capPackets$D_OUT[219:212],
theMem_capPackets$D_OUT[227:220],
theMem_capPackets$D_OUT[235:228],
theMem_capPackets$D_OUT[243:236],
theMem_capPackets$D_OUT[251:244],
theMem_capPackets$D_OUT[259:252] } ;
assign req_data__h190926 =
{ CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q139,
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q140,
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q141,
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q142 } ;
assign req_data__h191769 =
{ (theMem_dCache_req_fifo$D_OUT[68:67] == 2'd3) ?
theMem_dCache_req_fifo$D_OUT[63:0] :
64'b0,
(theMem_dCache_req_fifo$D_OUT[68:67] == 2'd2) ?
theMem_dCache_req_fifo$D_OUT[63:0] :
64'b0,
(theMem_dCache_req_fifo$D_OUT[68:67] == 2'd1) ?
theMem_dCache_req_fifo$D_OUT[63:0] :
64'b0,
(theMem_dCache_req_fifo$D_OUT[68:67] == 2'd0) ?
theMem_dCache_req_fifo$D_OUT[63:0] :
64'b0 } ;
assign result__h176159 =
(theMem_dataByte$EMPTY_N && theMem_dataSize$EMPTY_N &&
theMem_dataSize$D_OUT == 4'd8) ?
(memAccessToWriteback$D_OUT[8] ?
{ {56{x76288_BITS_7_TO_0__q200[7]}},
x76288_BITS_7_TO_0__q200 } :
{ 56'd0, x__h176288[7:0] }) :
IF_theMem_dataByte_i_notEmpty__766_AND_theMem__ETC___d2935 ;
assign result__h223255 =
{ calcResult__h222022[32], calcResult__h222022[63:0] } ;
assign result__h223714 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 >>
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] ;
assign result__h228964 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31:0] >>
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] ;
assign shift__h147919 = { memAccess_inQ$D_OUT[231:230], 3'b0 } ;
assign shift__h148409 = { x__h148596, 3'b0 } ;
assign shift__h148897 = { memAccess_inQ$D_OUT[232:230], 3'd0 } ;
assign shift__h148953 = { _7_MINUS_y61581__q7[2:0], 3'd0 } ;
assign shift__h174651 = { theMem_dataByte$D_OUT[1:0], 3'b0 } ;
assign shift__h174663 = 5'd24 - shift__h174651 ;
assign shift__h174688 = 6'd56 - addr__h174623 ;
assign signedA__h217100 =
{ IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63],
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 } ;
assign signedB__h217989 =
{ IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[63],
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 } ;
assign spliced_bits__h153740 =
{ toInsert__h150906,
memAccess_inQ$D_OUT[125:118],
memAccess_inQ$D_OUT[133:126] } <<
shift__h147919 ;
assign spliced_bits__h155293 =
{ toInsert__h150906,
memAccess_inQ$D_OUT[125:118],
memAccess_inQ$D_OUT[133:126] } >>
shift__h148409 ;
assign spliced_bits__h223217 =
{ {32{calcResult21868_BITS_31_TO_0__q159[31]}},
calcResult21868_BITS_31_TO_0__q159 } ;
assign spliced_bits__h228898 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] ==
5'd0) ?
result__h228964 :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4237 ;
assign target__h170704 =
memAccessToWriteback$D_OUT[101:38] +
{ {44{memAccessToWritebackD_OUT_BITS_37_TO_18__q10[19]}},
memAccessToWritebackD_OUT_BITS_37_TO_18__q10 } ;
assign target__h170730 =
(memAccessToWriteback$D_OUT[435:434] == 2'd1) ?
jumpTarget__h170772 :
64'b0 ;
assign te_inst__h24720 =
{ theDebug_debugConvert$messages_request_get[39:32],
theDebug_debugConvert$messages_request_get[47:40],
theDebug_debugConvert$messages_request_get[55:48],
theDebug_debugConvert$messages_request_get[63:56] } ;
assign te_pc__h24721 =
{ theDebug_debugConvert$messages_request_get[71:64],
theDebug_debugConvert$messages_request_get[79:72],
theDebug_debugConvert$messages_request_get[87:80],
theDebug_debugConvert$messages_request_get[95:88],
theDebug_debugConvert$messages_request_get[103:96],
theDebug_debugConvert$messages_request_get[111:104],
theDebug_debugConvert$messages_request_get[119:112],
theDebug_debugConvert$messages_request_get[127:120] } ;
assign te_regVal1__h24722 =
{ theDebug_debugConvert$messages_request_get[135:128],
theDebug_debugConvert$messages_request_get[143:136],
theDebug_debugConvert$messages_request_get[151:144],
theDebug_debugConvert$messages_request_get[159:152],
theDebug_debugConvert$messages_request_get[167:160],
theDebug_debugConvert$messages_request_get[175:168],
theDebug_debugConvert$messages_request_get[183:176],
theDebug_debugConvert$messages_request_get[191:184] } ;
assign te_regVal2__h24723 =
{ theDebug_debugConvert$messages_request_get[199:192],
theDebug_debugConvert$messages_request_get[207:200],
theDebug_debugConvert$messages_request_get[215:208],
theDebug_debugConvert$messages_request_get[223:216],
theDebug_debugConvert$messages_request_get[231:224],
theDebug_debugConvert$messages_request_get[239:232],
theDebug_debugConvert$messages_request_get[247:240],
theDebug_debugConvert$messages_request_get[255:248] } ;
assign te_reserved__h24719 =
{ theDebug_debugConvert$messages_request_get[13:8],
theDebug_debugConvert$messages_request_get[23:16],
theDebug_debugConvert$messages_request_get[31:24] } ;
assign temp__h174650 =
{ x__h177369[7:0],
x__h177369[15:8],
x__h177369[23:16],
x__h177369[31:24] } ;
assign temp__h174652 = temp__h174650 << shift__h174651 ;
assign temp__h174654 = x__h177704 | y__h177705 ;
assign temp__h174664 = temp__h174650 >> shift__h174663 ;
assign temp__h174677 =
{ x_first_data__h174507[7:0],
x_first_data__h174507[15:8],
x_first_data__h174507[23:16],
x_first_data__h174507[31:24],
x_first_data__h174507[39:32],
x_first_data__h174507[47:40],
x_first_data__h174507[55:48],
x_first_data__h174507[63:56] } ;
assign temp__h174679 = temp__h174677 << addr__h174623 ;
assign temp__h174681 = x__h181305 | y__h181306 ;
assign temp__h174689 = temp__h174677 >> shift__h174688 ;
assign temp__h174691 = x__h183015 | y__h183016 ;
assign theCP0_tlbLookupData_response_get_777_BITS_13__ETC___d1813 =
theCP0$tlbLookupData_response_get[13:9] == 5'd25 &&
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 &&
!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ||
theCP0$tlbLookupData_response_get[6] &&
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 ||
!theMem_dCache_tags_serverAdapterA_outData_outData$wget[25]) &&
(!theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d9145 ||
!theMem_dCache_tags_serverAdapterA_outData_outData$wget[0])) ;
assign theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d3016 =
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 &&
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 ||
theMem_dCache_req_fifo$D_OUT[135:128] == 8'hFF) &&
IF_memAccessToWriteback_first__516_BITS_371_TO_ETC___d8729 ==
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] ;
assign theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 =
theCP0$tlbLookupData_response_get[49:26] ==
theMem_dCache_tags_serverAdapterA_outData_outData$wget[49:26] ;
assign theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8117 =
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25]) ==
theMem_dCache_wayPredicted$D_OUT ;
assign theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8324 =
(theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d8116 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[25] ||
theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d9145 &&
theMem_dCache_tags_serverAdapterA_outData_outData$wget[0]) &&
theCP0$tlbLookupData_response_get[6] ;
assign theCP0_tlbLookupData_response_get_777_BITS_49__ETC___d9145 =
theCP0$tlbLookupData_response_get[49:26] ==
theMem_dCache_tags_serverAdapterA_outData_outData$wget[24:1] ;
assign theCP0_tlbLookupInstruction_response_get_380_B_ETC___d1384 =
theCP0$tlbLookupInstruction_response_get[49:26] ==
theMem_iCache_tags_serverAdapterA_outData_outData$wget[24:1] ;
assign theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4587 =
theCapCop_capInsts$D_OUT[99:95] == 5'd16 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd20 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd17 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd21 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd18 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd22 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd19 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd23 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd24 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd28 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd25 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd29 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd26 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd30 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd27 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd31 ||
((theCapCop_capInsts$D_OUT[99:95] == 5'd7) ?
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] +
_0_CONCAT_IF_execute_inQ_first__341_BITS_12_TO__ETC___d7847 <=
theCapCop_pcc[63:0] :
theCapCop_capInsts$D_OUT[99:95] == 5'd8 ||
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q150) ;
assign theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4606 =
theCapCop_capInsts$D_OUT[99:95] == 5'd16 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd20 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd17 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd21 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd18 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd22 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd19 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd23 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd24 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd28 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd25 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd29 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd26 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd30 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd27 ||
theCapCop_capInsts$D_OUT[99:95] == 5'd31 ||
((theCapCop_capInsts$D_OUT[99:95] == 5'd7) ?
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 +
_0_CONCAT_IF_execute_inQ_first__341_BITS_12_TO__ETC___d7847 <=
theCapCop_pcc[63:0] :
theCapCop_capInsts$D_OUT[99:95] == 5'd8 ||
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q144) ;
assign theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d9255 =
(theCapCop_capInsts$D_OUT[99:95] == 5'd4 ||
NOT_theCapCop_capInsts_first__372_BITS_99_TO_9_ETC___d3548) &&
(theCapCop_pcc[244] || regNum__h203787 != 5'd28) &&
(theCapCop_pcc[243] || regNum__h203787 != 5'd29) &&
(theCapCop_pcc[242] || regNum__h203787 != 5'd30) &&
(theCapCop_pcc[241] || regNum__h203787 != 5'd31) ;
assign theCapCop_capInsts_i_notEmpty__326_AND_theCapC_ETC___d3337 =
theCapCop_capInsts$EMPTY_N && theCapCop_fetchFifoB$EMPTY_N &&
theCapCop_capWritebackTags$FULL_N &&
execute_mul$RDY_muldiv_request_put &&
execute_hiLoPending$FULL_N &&
execute_pendingOps$FULL_N &&
memAccess_inQ$FULL_N ;
assign theCapCop_capState_read__301_EQ_5_335_AND_theC_ETC___d4907 =
theCapCop_capState == 3'd5 &&
theCapCop_writesIn - theCapCop_writesDone <= 5'd2 &&
theCP0$RDY_readGet &&
theCapCop_fetchFifoA$FULL_N &&
decode_inQ$EMPTY_N &&
theRF_reqA_i_notEmpty__891_AND_theRF_reqB_i_no_ETC___d4903 ;
assign theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2714 =
theCapCop_capWritebackTags$D_OUT[0] &&
theCapCop_capWritebackTags$D_OUT[7:4] ==
theCapCop_capWriteback[6:3] &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712 ==
5'd25 ;
assign theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d2980 =
theCapCop_capWritebackTags$D_OUT[0] &&
theCapCop_capWritebackTags$D_OUT[7:4] ==
theCapCop_capWriteback[6:3] &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721 ==
5'd25 ;
assign theCapCop_capWritebackTags_first__703_BIT_0_70_ETC___d3191 =
theCapCop_capWritebackTags$D_OUT[0] &&
theCapCop_capWritebackTags$D_OUT[7:4] ==
theCapCop_capWriteback[6:3] &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733 ==
5'd25 ;
assign theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329 =
theCapCop_capWriteback[268] &&
theCapCop_capWriteback[2:0] == theCapCop_capInsts$D_OUT[12:10] &&
theCapCop_writesIn != theCapCop_writesDone ;
assign theCapCop_nextWillWriteback_i_notEmpty__313_AN_ETC___d3340 =
theCapCop_nextWillWriteback$EMPTY_N &&
theCapCop_capMemInsts$FULL_N &&
(theCapCop_capState == 3'd5 || theCapCop_capState == 3'd1) &&
(!theCapCop_nextWillWriteback$D_OUT ||
theCapCop_writesCalculated_read__320_EQ_theCap_ETC___d3321) &&
theCapCop_fetchFifoA$EMPTY_N &&
execute_inQ$EMPTY_N &&
theCapCop_capInsts_i_notEmpty__326_AND_theCapC_ETC___d3337 ;
assign theCapCop_pcc_read__315_BIT_244_550_OR_NOT_IF__ETC___d4592 =
(theCapCop_pcc[244] || regNum__h203787 != 5'd28) &&
(theCapCop_pcc[243] || regNum__h203787 != 5'd29) &&
(theCapCop_pcc[242] || regNum__h203787 != 5'd30) &&
(theCapCop_pcc[241] || regNum__h203787 != 5'd31) &&
!theCapCop_capInsts$D_OUT[17] &&
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4590 ;
assign theCapCop_pcc_read__315_BIT_244_550_OR_NOT_IF__ETC___d4611 =
(theCapCop_pcc[244] || regNum__h203787 != 5'd28) &&
(theCapCop_pcc[243] || regNum__h203787 != 5'd29) &&
(theCapCop_pcc[242] || regNum__h203787 != 5'd30) &&
(theCapCop_pcc[241] || regNum__h203787 != 5'd31) &&
!theCapCop_capInsts$D_OUT[17] &&
IF_NOT_theCapCop_capInsts_first__372_BITS_99_T_ETC___d4609 ;
assign theCapCop_writesCalculated_read__320_EQ_theCap_ETC___d3321 =
theCapCop_writesCalculated == theCapCop_writesDone ;
assign theDebug_bp_1_read__515_BIT_64_516_AND_theDebu_ETC___d6531 =
theDebug_bp_1[64] && theDebug_bp_1[63:0] == branch$getPc[66:3] ||
theDebug_bp_2[64] && theDebug_bp_2[63:0] == branch$getPc[66:3] ||
theDebug_bp_3[64] && theDebug_bp_3[63:0] == branch$getPc[66:3] ;
assign theDebug_bp_read__508_BIT_64_509_AND_theDebug__ETC___d7846 =
theDebug_bp[64] && theDebug_bp[63:0] == branch$getPc[66:3] ||
theDebug_bp_1_read__515_BIT_64_516_AND_theDebu_ETC___d6531 ;
assign theDebug_trace_buf_tailPtr_read__1_EQ_theDebug_ETC___d40 =
theDebug_trace_buf_tailPtr == theDebug_trace_buf_headPtr ;
assign theDebug_trace_buf_tailPtr_read__1_PLUS_1_2_EQ_ETC___d8043 =
theDebug_trace_buf_tailPtr_read__1_PLUS_1___d7524 ==
theDebug_trace_buf_headPtr ;
assign theDebug_trace_buf_tailPtr_read__1_PLUS_1___d7524 =
theDebug_trace_buf_tailPtr + 12'd1 ;
assign theMem_capExceptions_first__525_BITS_3_TO_0_52_ETC___d8708 =
theMem_capExceptions$D_OUT[3:0] ==
memAccessToWriteback$D_OUT[444:441] ;
assign theMem_dCache_cacheState_read__723_EQ_1_732_AN_ETC___d2049 =
theMem_dCache_cacheState == 3'd1 &&
theCP0$RDY_tlbLookupData_request_put &&
theMem_dCache_data_serverAdapterA_cnt_633_SLT_3___d1762 &&
(theMem_dCache_tags_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
theMem_dCache_wayKey$FULL_N &&
theMem_dCache_wayPredicted$FULL_N &&
theMem_dCache_req_fifo$FULL_N ;
assign theMem_dCache_data_serverAdapterA_cnt_633_PLUS_ETC___d1639 =
theMem_dCache_data_serverAdapterA_cnt +
(theMem_dCache_data_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) +
(theMem_dCache_data_serverAdapterA_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign theMem_dCache_data_serverAdapterA_cnt_633_SLT_3___d1762 =
(theMem_dCache_data_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign theMem_dCache_data_serverAdapterA_outData_outD_ETC___d1767 =
theMem_dCache_data_serverAdapterA_outData_outData$whas &&
theMem_dCache_out_fifo_ff$FULL_N &&
theMem_dCache_data_serverAdapterA_cnt_633_SLT_3___d1762 &&
theMem_dCache_tags_fifo$FULL_N &&
theMem_theMemMerge_req_fifos_1$FULL_N ;
assign theMem_dCache_data_serverAdapterB_cnt_690_SLT_3___d1849 =
(theMem_dCache_data_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign theMem_dCache_req_fifo_i_notEmpty__730_AND_the_ETC___d1844 =
theMem_dCache_req_fifo$EMPTY_N &&
(theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N ||
theMem_dCache_data_serverAdapterA_outData_enqData$whas) &&
theMem_dCache_data_serverAdapterA_outData_outData$whas &&
theMem_dCache_out_fifo_ff$FULL_N ;
assign theMem_dCache_tags_serverAdapterA_cnt_519_PLUS_ETC___d1525 =
theMem_dCache_tags_serverAdapterA_cnt +
(WILL_FIRE_RL_theMem_dCache_tags_serverAdapterA_stageReadResponseAlways ?
3'd1 :
3'd0) +
(theMem_dCache_tags_serverAdapterA_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign theMem_dCache_tags_serverAdapterA_outDataCore__ETC___d1773 =
(theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N ||
theMem_dCache_tags_serverAdapterA_outData_enqData$whas) &&
(theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N ||
theMem_dCache_data_serverAdapterA_outData_enqData$whas) &&
theMem_dCache_wayKey$EMPTY_N &&
theMem_dCache_wayPredicted$EMPTY_N &&
theMem_dCache_req_fifo$EMPTY_N &&
theMem_dCache_tags_serverAdapterA_outData_outData$whas &&
theMem_dCache_data_serverAdapterA_outData_outD_ETC___d1767 ;
assign theMem_dCache_tags_serverAdapterA_outDataCore__ETC___d3001 =
(theMem_dCache_tags_serverAdapterA_outDataCore$EMPTY_N ||
theMem_dCache_tags_serverAdapterA_outData_enqData$whas) &&
(theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N ||
theMem_dCache_data_serverAdapterA_outData_enqData$whas) &&
theMem_dCache_wayKey_i_notEmpty__756_AND_theMe_ETC___d2999 ;
assign theMem_dCache_tags_serverAdapterB_cnt_576_SLT_3___d1722 =
(theMem_dCache_tags_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign theMem_dCache_wayKey_i_notEmpty__756_AND_theMe_ETC___d2999 =
theMem_dCache_wayKey$EMPTY_N &&
theMem_dCache_wayPredicted$EMPTY_N &&
memAccessToWriteback$EMPTY_N &&
freeRenameReg$FULL_N &&
theCapCop_capWritebackTags$EMPTY_N &&
theCapCop_insts$EMPTY_N &&
writeback_instructionReport_i_notFull__497_AND_ETC___d2993 ;
assign theMem_iCache_bank_serverAdapterA_cnt_236_PLUS_ETC___d1242 =
theMem_iCache_bank_serverAdapterA_cnt +
(theMem_iCache_bank_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) +
(theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign theMem_iCache_bank_serverAdapterA_cnt_236_SLT_3___d1915 =
(theMem_iCache_bank_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign theMem_iCache_bank_serverAdapterB_cnt_293_SLT_3___d1424 =
(theMem_iCache_bank_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign theMem_iCache_out_fifo_ff_i_notEmpty__092_OR_t_ETC___d6659 =
(theMem_iCache_out_fifo_ff$EMPTY_N ||
theMem_iCache_out_fifo_enqw$whas) &&
branch$RDY_putTarget &&
theCP0$RDY_readReq &&
theMem_instructionWord_i_notEmpty__644_AND_fet_ETC___d6656 ;
assign theMem_iCache_req_fifo_first__341_BITS_127_TO__ETC___d1372 =
theMem_iCache_req_fifo$D_OUT[127:69] ==
theMem_iCache_virAddrReg[63:5] ;
assign theMem_iCache_req_fifo_i_notFull__917_AND_theM_ETC___d6498 =
theMem_iCache_req_fifo$FULL_N &&
theMem_iCache_tags_serverAdapterA_cnt_122_SLT_3___d1914 &&
theMem_iCache_bank_serverAdapterA_cnt_236_SLT_3___d1915 &&
theCapCop_insts$FULL_N &&
fetchedControlToken$FULL_N &&
theMem_instructionWord$FULL_N &&
theDebug_bpReport$FULL_N ;
assign theMem_iCache_req_fifo_i_notFull__917_AND_theM_ETC___d6580 =
theMem_iCache_req_fifo$FULL_N &&
theMem_iCache_tags_serverAdapterA_cnt_122_SLT_3___d1914 &&
theMem_iCache_bank_serverAdapterA_cnt_236_SLT_3___d1915 &&
theCapCop_insts$FULL_N &&
fetchedControlToken$FULL_N &&
theMem_instructionWord$FULL_N &&
theDebug_instQ$EMPTY_N ;
assign theMem_iCache_tags_serverAdapterA_cnt_122_PLUS_ETC___d1128 =
theMem_iCache_tags_serverAdapterA_cnt +
(theMem_iCache_tags_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) +
(theMem_iCache_tags_serverAdapterA_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign theMem_iCache_tags_serverAdapterA_cnt_122_SLT_3___d1914 =
(theMem_iCache_tags_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign theMem_iCache_tags_serverAdapterA_outDataCore__ETC___d1366 =
(theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N ||
theMem_iCache_tags_serverAdapterA_outData_enqData$whas) &&
(theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N ||
theMem_iCache_bank_serverAdapterA_outData_enqData$whas) &&
theMem_iCache_tags_serverAdapterA_outData_outData$whas &&
theMem_iCache_bank_serverAdapterA_outData_outData$whas &&
theMem_iCache_tags_serverAdapterB_cnt_179_SLT_3___d1325 &&
theMem_theMemMerge_req_fifos$FULL_N &&
theMem_iCache_out_fifo_ff$FULL_N ;
assign theMem_iCache_tags_serverAdapterA_outDataCore__ETC___d1473 =
(theMem_iCache_tags_serverAdapterA_outDataCore$EMPTY_N ||
theMem_iCache_tags_serverAdapterA_outData_enqData$whas) &&
(theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N ||
theMem_iCache_bank_serverAdapterA_outData_enqData$whas) &&
theMem_iCache_out_fifo_ff$FULL_N ;
assign theMem_iCache_tags_serverAdapterB_cnt_179_SLT_3___d1325 =
(theMem_iCache_tags_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign theMem_instructionWord_i_notEmpty__644_AND_fet_ETC___d6656 =
theMem_instructionWord$EMPTY_N && fetchedControlToken$EMPTY_N &&
theRF_reqA$FULL_N &&
theRF_reqB$FULL_N &&
decode_inQ$FULL_N &&
freeRenameReg$EMPTY_N &&
theMem_iCache_out_fifo_firstValid$Q_OUT ;
assign theRF_regFileState_4_AND_writeback_hiLoCommit__ETC___d2751 =
theRF_regFileState && writeback_hiLoCommit$FULL_N &&
theCP0$RDY_writeReg &&
theDebug_writebacks$FULL_N ;
assign theRF_reqA_i_notEmpty__891_AND_theRF_reqB_i_no_ETC___d4903 =
theRF_reqA$EMPTY_N && theRF_reqB$EMPTY_N &&
theCapCop_fetchFifoB$FULL_N &&
theCapCop_capInsts$FULL_N &&
theCapCop_nextWillWriteback$FULL_N &&
execute_inQ$FULL_N &&
branch$RDY_putRegisterTarget ;
assign toInsert__h150906 =
{ memAccess_inQ$D_OUT[109:102], memAccess_inQ$D_OUT[117:110] } ;
assign v__h112420 =
theMem_iCache_bank_serverAdapterA_outDataCore$EMPTY_N ?
theMem_iCache_bank_serverAdapterA_outDataCore$D_OUT :
theMem_iCache_bank_memory$DOA ;
assign v__h188873 =
theMem_dCache_data_serverAdapterA_outDataCore$EMPTY_N ?
theMem_dCache_data_serverAdapterA_outDataCore$D_OUT :
theMem_dCache_data_memory$DOA ;
assign v__h277714 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[422:418] :
instruction__h274083[20:16] ;
assign v__h278907 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[417:413] :
instruction__h274083[15:11] ;
assign writeLine__h145072 = {8{memAccess_inQ$D_OUT[109:102]}} ;
assign writeLine__h146667 =
{ (memAccess_inQ$D_OUT[232:231] == 2'd3) ?
toInsert__h150906 :
{ memAccess_inQ$D_OUT[109:102],
memAccess_inQ$D_OUT[117:110] },
(memAccess_inQ$D_OUT[232:231] == 2'd2) ?
toInsert__h150906 :
{ memAccess_inQ$D_OUT[109:102],
memAccess_inQ$D_OUT[117:110] },
(memAccess_inQ$D_OUT[232:231] == 2'd1) ?
toInsert__h150906 :
{ memAccess_inQ$D_OUT[109:102],
memAccess_inQ$D_OUT[117:110] },
(memAccess_inQ$D_OUT[232:231] == 2'd0) ?
toInsert__h150906 :
{ memAccess_inQ$D_OUT[109:102],
memAccess_inQ$D_OUT[117:110] } } ;
assign writeLine__h147487 =
memAccess_inQ$D_OUT[232] ?
{ toInsert__h150906,
memAccess_inQ$D_OUT[125:118],
memAccess_inQ$D_OUT[133:126],
memAccess_inQ$D_OUT[109:102],
memAccess_inQ$D_OUT[117:110],
memAccess_inQ$D_OUT[125:118],
memAccess_inQ$D_OUT[133:126] } :
{ memAccess_inQ$D_OUT[109:102],
memAccess_inQ$D_OUT[117:110],
memAccess_inQ$D_OUT[125:118],
memAccess_inQ$D_OUT[133:126],
toInsert__h150906,
memAccess_inQ$D_OUT[125:118],
memAccess_inQ$D_OUT[133:126] } ;
assign writeLine__h147922 = {2{spliced_bits__h153740}} ;
assign writeLine__h148412 = {2{spliced_bits__h155293}} ;
assign writeLine__h148895 =
{ toInsert__h150906,
memAccess_inQ$D_OUT[125:118],
memAccess_inQ$D_OUT[133:126],
memAccess_inQ$D_OUT[141:134],
memAccess_inQ$D_OUT[149:142],
memAccess_inQ$D_OUT[157:150],
memAccess_inQ$D_OUT[165:158] } ;
assign writeLine__h148898 = writeLine__h148895 << shift__h148897 ;
assign writeLine__h148954 = writeLine__h148895 >> shift__h148953 ;
assign writeback___1_base__h203941 =
x1_avValue_base__h200801 +
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0] ;
assign writeback___1_base__h207371 =
x1_avValue_base__h200801 +
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 ;
assign writeback_instructionReport_i_notFull__497_AND_ETC___d2508 =
writeback_instructionReport$FULL_N &&
writeback_exception$FULL_N &&
theRF_regFileState &&
writeback_hiLoCommit$FULL_N &&
theCP0$RDY_writeReg &&
theDebug_writebacks$FULL_N &&
theMem_commitCapStore$FULL_N ;
assign writeback_instructionReport_i_notFull__497_AND_ETC___d2993 =
writeback_instructionReport$FULL_N &&
theMem_dCache_tags_serverAdapterA_outData_outData$whas &&
theMem_dCache_data_serverAdapterA_outData_outData$whas &&
theMem_theMemMerge_req_fifos_1$FULL_N &&
theMem_dCache_data_serverAdapterB_cnt_690_SLT_3___d1849 &&
theMem_dCache_tags_serverAdapterB_cnt_576_SLT_3___d1722 &&
writeback_exception$FULL_N &&
theRF_regFileState_4_AND_writeback_hiLoCommit__ETC___d2751 ;
assign x1_avValue_base__h200801 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[139:76] :
theCapCop_baseRegs$D_OUT_2 ;
assign x1_avValue_dest__h241167 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
_theResult_____1_dest__h241119 :
decode_inQ$D_OUT[391:387] ;
assign x1_avValue_dest__h241851 =
(theCP0$getCoprocessorEnables[1] &&
decode_inQ$D_OUT[433:428] == 6'd17 ||
theCP0$getCoprocessorEnables[3] &&
decode_inQ$D_OUT[433:428] == 6'd19) ?
_theResult_____1_dest__h241760 :
decode_inQ$D_OUT[391:387] ;
assign x1_avValue_fst_coProSelect__h243920 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
x1_avValue_coProSelect__h242564 :
decode_inQ$D_OUT[386:384] ;
assign x1_avValue_fst_dest__h243919 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
x1_avValue_dest__h242563 :
decode_inQ$D_OUT[391:387] ;
assign x1_avValue_fst_opA__h243934 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
x1_avValue_opA__h242578 :
decode_inQ$D_OUT[293:230] ;
assign x1_avValue_fst_opB__h212082 =
(execute_inQ$D_OUT[374:372] == 3'd5) ?
er___1_opB__h212042 :
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 ;
assign x1_avValue_fst_opB__h243935 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
x1_avValue_opB__h242579 :
decode_inQ$D_OUT[229:166] ;
assign x1_avValue_fst_storeData__h243936 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
x1_avValue_storeData__h242580 :
decode_inQ$D_OUT[165:102] ;
assign x1_avValue_oType_eaddr__h200800 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[203:140] :
theCapCop_oTypeRegs$D_OUT_1 ;
assign x1_avValue_opA__h161811 =
(memAccess_inQ$D_OUT[374:372] == 3'd5) ?
memAccess_inQ$D_OUT[229:166] :
memAccess_inQ$D_OUT[293:230] ;
assign x1_avValue_opA__h237707 =
decode_inQ$D_OUT[1] ?
_theResult___fst__h257318 :
theRF_regFile$D_OUT_2 ;
assign x1_avValue_opA__h241182 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
_theResult_____1_opA__h241134 :
decode_inQ$D_OUT[293:230] ;
assign x1_avValue_opB__h237708 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
64'd0 :
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q65 ;
assign x1_avValue_opB__h241183 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
_theResult_____1_opB__h241135 :
di___1_opB__h240965 ;
assign x1_avValue_reserved__h200799 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[251:204] :
48'b0 ;
assign x1_avValue_snd_operand__h242897 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[293:230] :
64'h0 ;
assign x1_avValue_snd_rd__h242896 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[417:413] :
5'd0 ;
assign x1_avValue_snd_rt__h242895 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[422:418] :
5'd0 ;
assign x1_avValue_snd_select__h242898 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[404:402] :
3'b0 ;
assign x1_avValue_snd_snd_snd_snd_snd_snd_operand__h242915 =
(decode_inQ$D_OUT[435:434] == 2'd0 ||
decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
64'h0 :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
x1_avValue_snd_operand__h242897 :
64'h0) ;
assign x1_avValue_snd_snd_snd_snd_snd_snd_select__h242916 =
(decode_inQ$D_OUT[435:434] == 2'd0 ||
decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
3'b0 :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
x1_avValue_snd_select__h242898 :
3'b0) ;
assign x76288_BITS_7_TO_0__q200 = x__h176288[7:0] ;
assign x76684_BITS_7_TO_0_CONCAT_x76684_BITS_15_TO_8__q199 =
{ x__h176684[7:0], x__h176684[15:8] } ;
assign x__h129418 = ~theMem_dCache_wayPredicted$D_OUT ;
assign x__h143650 = { memAccess_inQ$D_OUT[293:233], 3'b0 } ;
assign x__h148596 = 2'd3 - memAccess_inQ$D_OUT[231:230] ;
assign x__h148959 = 3'd7 - memAccess_inQ$D_OUT[232:230] ;
assign x__h168654 =
{ 1'd1,
te_version__h168658,
CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5,
22'h2AAAAA,
writeback_instructionReport$D_OUT[497:466],
writeback_instructionReport$D_OUT[165:102],
CASE_writeback_instructionReportD_OUT_BITS_78_ETC__q6 } ;
assign x__h169227 =
{ theDebug_traceCmp[255:251],
CASE_theDebug_traceCmp_BITS_250_TO_246_31_0_th_ETC__q9,
theDebug_traceCmp[245:0] } ;
assign x__h171528 =
(IF_NOT_IF_IF_IF_memAccessToWriteback_first__51_ETC___d7868 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1]) ?
_theResult_____2___1_victim__h171283 :
writeback_instCount ;
assign x__h176020 =
(IF_NOT_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo__ETC___d7875 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1]) ?
_theResult_____2___1_victim__h171283 :
writeback_instCount ;
assign x__h176288 = x_first_data__h174507 >> addr__h174623 ;
assign x__h176684 = x_first_data__h174507 >> off__h176682 ;
assign x__h177369 = x_first_data__h174507 >> off__h177367 ;
assign x__h177704 = temp__h174652 & mask__h174653 ;
assign x__h178683 = temp__h174664 & mask__h174665 ;
assign x__h181305 = temp__h174679 & mask__h174680 ;
assign x__h183015 = temp__h174689 & mask__h174690 ;
assign x__h193939 =
(IF_NOT_IF_IF_IF_NOT_theCP0_tlbLookupData_respo_ETC___d7876 !=
5'd25 &&
branch_getEpoch__530_EQ_memAccessToWriteback_f_ETC___d8935 &&
!memAccessToWriteback$D_OUT[393] &&
!memAccessToWriteback$D_OUT[1]) ?
_theResult_____2___1_victim__h171283 :
writeback_instCount ;
assign x__h198817 =
(execute_pendingOps$D_OUT[379:375] == 5'd14) ?
execute_mul$muldiv_response_get[63:0] :
execute_pendingOps$D_OUT[293:230] ;
assign x__h213199 =
(theCapCop_capInsts$D_OUT[9:5] == theCapCop_capWriteback[11:7] &&
theCapCop_capWriteback_read__707_BIT_268_433_A_ETC___d8329) ?
theCapCop_capWriteback[267:252] :
theCapCop_permRegs$D_OUT_1[63:48] ;
assign x__h213493 =
(execute_inQ$D_OUT[306] &&
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065) ?
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 :
execute_inQ$D_OUT[165:102] ;
assign x__h217866 =
(execute_inQ$D_OUT[7] || execute_inQ$D_OUT[383:382] == 2'd0) ?
x__h231731 :
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 ;
assign x__h222061 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[31] ^
_theResult_____4__h222021[31] ;
assign x__h222165 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[63] ^
_theResult_____4__h222021[63] ;
assign x__h222259 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[32] ^
_theResult_____4__h222021[32] ;
assign x__h223436 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 <<
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] ;
assign x__h223587 =
IF_execute_inQD_OUT_BIT_381_THEN_theResult____ETC__q148[63:0] >>
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[4:0] ;
assign x__h223710 =
(IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829[5:0] ==
6'd0) ?
result__h223714 :
IF_IF_execute_inQ_first__341_BIT_318_501_THEN__ETC___d4081 ;
assign x__h231731 = execute_inQ$D_OUT[101:38] + 64'd8 ;
assign x__h243635 =
(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd9 ||
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 ==
5'd10) ?
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7585 :
5'd0 ;
assign x__h257533 = { decode_inQ$D_OUT[417:402], 16'b0 } ;
assign x__h257736 =
(decode_inQ$D_OUT[435:434] == 2'd0) ?
x1_avValue_storeData__h239035 :
((decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
decode_inQ$D_OUT[165:102] :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
x1_avValue_fst_storeData__h243936 :
decode_inQ$D_OUT[165:102])) ;
assign x__h266100 =
{ theMem_theMemMerge_rsp_fifos_2$D_OUT[71:64],
theMem_theMemMerge_rsp_fifos_2$D_OUT[79:72],
theMem_theMemMerge_rsp_fifos_2$D_OUT[87:80],
theMem_theMemMerge_rsp_fifos_2$D_OUT[95:88],
theMem_theMemMerge_rsp_fifos_2$D_OUT[103:96],
theMem_theMemMerge_rsp_fifos_2$D_OUT[111:104],
theMem_theMemMerge_rsp_fifos_2$D_OUT[119:112],
theMem_theMemMerge_rsp_fifos_2$D_OUT[127:120] } ;
assign x__h266104 =
{ theMem_theMemMerge_rsp_fifos_2$D_OUT[135:128],
theMem_theMemMerge_rsp_fifos_2$D_OUT[143:136],
theMem_theMemMerge_rsp_fifos_2$D_OUT[151:144],
theMem_theMemMerge_rsp_fifos_2$D_OUT[159:152],
theMem_theMemMerge_rsp_fifos_2$D_OUT[167:160],
theMem_theMemMerge_rsp_fifos_2$D_OUT[175:168],
theMem_theMemMerge_rsp_fifos_2$D_OUT[183:176],
theMem_theMemMerge_rsp_fifos_2$D_OUT[191:184] } ;
assign x__h285659 = fetchedControlToken$D_OUT[101:38] + y__h285662 ;
assign x__h285667 = { immediate__h279604, 2'b0 } ;
assign x__h285670 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[417:402] :
instruction__h274083[15:0] ;
assign x_coProSelect__h290167 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8359 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8608) ?
fetchedControlToken$D_OUT[386:384] :
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d7297 ;
assign x_first_data__h174507 =
theMem_dCache_out_fifo_ff$EMPTY_N ?
theMem_dCache_out_fifo_ff$D_OUT[63:0] :
theMem_dCache_out_fifo_enqw$wget[63:0] ;
assign y__h161581 = { 3'b0, memAccess_inQ$D_OUT[232:230] } ;
assign y__h177705 = memAccessToWriteback$D_OUT[133:102] & y__h178645 ;
assign y__h178645 = ~mask__h174653 ;
assign y__h178684 = memAccessToWriteback$D_OUT[133:102] & y__h179624 ;
assign y__h179624 = ~mask__h174665 ;
assign y__h181306 = memAccessToWriteback$D_OUT[165:102] & y__h183003 ;
assign y__h183003 = ~mask__h174680 ;
assign y__h183016 = memAccessToWriteback$D_OUT[165:102] & y__h184714 ;
assign y__h184714 = ~mask__h174690 ;
assign y__h285662 = { {36{x__h285667[27]}}, x__h285667 } ;
assign y_avValue_coProSelect__h253688 =
(decode_inQ$D_OUT[435:434] == 2'd0 ||
decode_inQ$D_OUT[435:434] == 2'd1 ||
decode_inQ$D_OUT[435:434] == 2'd2 ||
decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
decode_inQ$D_OUT[386:384] :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
x1_avValue_fst_coProSelect__h243920 :
decode_inQ$D_OUT[386:384]) ;
assign y_avValue_dest__h253687 =
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7997 ?
5'd31 :
_theResult_____2_dest__h253551 ;
assign y_avValue_reserved__h259503 =
{ theMem_theMemMerge_rsp_fifos_2$D_OUT[23:16],
theMem_theMemMerge_rsp_fifos_2$D_OUT[31:24],
theMem_theMemMerge_rsp_fifos_2$D_OUT[39:32],
theMem_theMemMerge_rsp_fifos_2$D_OUT[47:40],
theMem_theMemMerge_rsp_fifos_2$D_OUT[55:48],
theMem_theMemMerge_rsp_fifos_2$D_OUT[63:56] } ;
assign y_avValue_snd_snd_snd_fst__h282779 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770 ==
6'd8) ?
5'd0 :
v__h278907 ;
assign y_avValue_snd_snd_snd_snd_fst__h283943 =
{ {10{x__h285670[15]}}, x__h285670 } ;
always@(theMem_dCache_addrReg or theMem_theMemMerge_rsp_fifos_1$D_OUT)
begin
case (theMem_dCache_addrReg[4:3])
2'b0: resp_data__h129680 = theMem_theMemMerge_rsp_fifos_1$D_OUT[63:0];
2'b01:
resp_data__h129680 = theMem_theMemMerge_rsp_fifos_1$D_OUT[127:64];
2'b10:
resp_data__h129680 = theMem_theMemMerge_rsp_fifos_1$D_OUT[191:128];
2'd3:
resp_data__h129680 = theMem_theMemMerge_rsp_fifos_1$D_OUT[255:192];
endcase
end
always@(theMem_iCache_phyAddrReg or theMem_theMemMerge_rsp_fifos$D_OUT)
begin
case (theMem_iCache_phyAddrReg[4:3])
2'b0: resp_data__h113930 = theMem_theMemMerge_rsp_fifos$D_OUT[63:0];
2'b01: resp_data__h113930 = theMem_theMemMerge_rsp_fifos$D_OUT[127:64];
2'b10: resp_data__h113930 = theMem_theMemMerge_rsp_fifos$D_OUT[191:128];
2'd3: resp_data__h113930 = theMem_theMemMerge_rsp_fifos$D_OUT[255:192];
endcase
end
always@(theMem_iCache_req_fifo$D_OUT or theMem_iCache_updateReg)
begin
case (theMem_iCache_req_fifo$D_OUT[68:67])
2'd0: x_data__h115034 = theMem_iCache_updateReg[63:0];
2'd1: x_data__h115034 = theMem_iCache_updateReg[127:64];
2'd2: x_data__h115034 = theMem_iCache_updateReg[191:128];
2'd3: x_data__h115034 = theMem_iCache_updateReg[255:192];
endcase
end
always@(theCapCop_capInsts$D_OUT)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd4: regNum__h203787 = theCapCop_capInsts$D_OUT[94:90];
5'd7: regNum__h203787 = 5'd27;
default: regNum__h203787 = theCapCop_capInsts$D_OUT[89:85];
endcase
end
always@(memAccess_inQ$D_OUT or
byteMask__h143211 or byteMask__h142387 or byteMask__h140788)
begin
case (memAccess_inQ$D_OUT[12:9])
4'd4: req_byteWrite__h140080 = byteMask__h143211;
4'd7: req_byteWrite__h140080 = byteMask__h142387;
4'd8: req_byteWrite__h140080 = byteMask__h140788;
default: req_byteWrite__h140080 = 8'hFF;
endcase
end
always@(writeback_instructionReport$D_OUT)
begin
case (writeback_instructionReport$D_OUT[447:446])
2'd0, 2'd1, 2'd2:
val2__h168450 = writeback_instructionReport$D_OUT[63:0];
2'd3: val2__h168450 = 64'h000000000000DEAD;
endcase
end
always@(writeback_instructionReport$D_OUT)
begin
case (writeback_instructionReport$D_OUT[447:446])
2'd0, 2'd1, 2'd2: _theResult___fst__h168720 = 4'd1;
2'd3: _theResult___fst__h168720 = 4'd0;
endcase
end
always@(writeback_instructionReport$D_OUT or _theResult___fst__h168720)
begin
case (writeback_instructionReport$D_OUT[78:77])
2'd0: te_version__h168658 = 4'd2;
2'd1: te_version__h168658 = 4'd3;
default: te_version__h168658 = _theResult___fst__h168720;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1, 6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
x1_avValue_dest__h239018 = decode_inQ$D_OUT[391:387];
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
x1_avValue_dest__h239018 = decode_inQ$D_OUT[422:418];
default: x1_avValue_dest__h239018 = decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd15,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd49,
6'd50,
6'd51,
6'd52,
6'd54,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
x1_avValue_dest__h240146 = decode_inQ$D_OUT[417:413];
default: x1_avValue_dest__h240146 = decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1, 6'd2, 6'd4, 6'd5:
x1_avValue_dest__h240504 = decode_inQ$D_OUT[417:413];
default: x1_avValue_dest__h240504 = decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT or _theResult_____1_opB__h245437)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25:
x1_avValue_storeData__h239035 = decode_inQ$D_OUT[165:102];
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
x1_avValue_storeData__h239035 = _theResult_____1_opB__h245437;
default: x1_avValue_storeData__h239035 = decode_inQ$D_OUT[165:102];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1: _theResult_____1_dest__h241119 = decode_inQ$D_OUT[422:418];
5'd4, 5'd5: _theResult_____1_dest__h241119 = decode_inQ$D_OUT[417:413];
default: _theResult_____1_dest__h241119 =
(decode_inQ$D_OUT[427:423] != 5'd2 &&
decode_inQ$D_OUT[427:423] != 5'd6) ?
5'd31 :
decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_dest__h240146 or
x1_avValue_dest__h241167 or x1_avValue_dest__h240504)
begin
case (decode_inQ$D_OUT[433:428])
6'd0: x1_avValue_dest__h241267 = x1_avValue_dest__h240146;
6'd16: x1_avValue_dest__h241267 = x1_avValue_dest__h241167;
6'd28: x1_avValue_dest__h241267 = x1_avValue_dest__h240504;
default: x1_avValue_dest__h241267 = decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT or x1_avValue_snd_rd__h242896)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19: x1_avValue_snd_snd_snd_snd_rd__h242905 = 5'd0;
6'd18:
x1_avValue_snd_snd_snd_snd_rd__h242905 = x1_avValue_snd_rd__h242896;
default: x1_avValue_snd_snd_snd_snd_rd__h242905 = 5'd0;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1, 5'd4, 5'd5:
_theResult_____1_dest__h241760 = decode_inQ$D_OUT[422:418];
default: _theResult_____1_dest__h241760 = decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0,
5'd1,
5'd3,
5'd4,
5'd7,
5'd8,
5'd9,
5'd10,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
x1_avValue_dest__h242563 = decode_inQ$D_OUT[422:418];
default: x1_avValue_dest__h242563 = decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_dest__h241851 or x1_avValue_fst_dest__h243919)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19: x1_avValue_fst_dest__h243960 = x1_avValue_dest__h241851;
6'd18: x1_avValue_fst_dest__h243960 = x1_avValue_fst_dest__h243919;
default: x1_avValue_fst_dest__h243960 = decode_inQ$D_OUT[391:387];
endcase
end
always@(decode_inQ$D_OUT or theRF_regFile$D_OUT_1)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd4: x1_avValue_storeData__h242580 = decode_inQ$D_OUT[165:102];
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
x1_avValue_storeData__h242580 = theRF_regFile$D_OUT_1;
default: x1_avValue_storeData__h242580 = decode_inQ$D_OUT[165:102];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_fst_dest__h243960 or
x1_avValue_dest__h239018 or x1_avValue_dest__h241267)
begin
case (decode_inQ$D_OUT[435:434])
2'd0: _theResult_____2_dest__h253551 = x1_avValue_dest__h239018;
2'd1: _theResult_____2_dest__h253551 = decode_inQ$D_OUT[391:387];
2'd2: _theResult_____2_dest__h253551 = x1_avValue_dest__h241267;
2'd3: _theResult_____2_dest__h253551 = x1_avValue_fst_dest__h243960;
endcase
end
always@(writeback_instructionReport$D_OUT)
begin
case (writeback_instructionReport$D_OUT[435:431])
5'd0, 5'd1, 5'd23:
CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 =
writeback_instructionReport$D_OUT[435:431];
5'd2, 5'd3, 5'd4, 5'd6:
CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd2;
5'd5, 5'd7:
CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd3;
5'd8, 5'd9:
CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd4;
5'd10: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd5;
5'd11: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd6;
5'd12: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd7;
5'd13: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd8;
5'd14: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd9;
5'd15: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd10;
5'd16, 5'd17, 5'd18, 5'd19:
CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd11;
5'd20: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd12;
5'd21: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd13;
5'd22: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd18;
default: CASE_writeback_instructionReportD_OUT_BITS_43_ETC__q5 = 5'd31;
endcase
end
always@(writeback_instructionReport$D_OUT or val2__h168450)
begin
case (writeback_instructionReport$D_OUT[78:77])
2'd0:
CASE_writeback_instructionReportD_OUT_BITS_78_ETC__q6 =
{ writeback_instructionReport$D_OUT[357:294], val2__h168450 };
2'd1:
CASE_writeback_instructionReportD_OUT_BITS_78_ETC__q6 =
{ writeback_instructionReport$D_OUT[357:294],
writeback_instructionReport$D_OUT[229:166] };
default: CASE_writeback_instructionReportD_OUT_BITS_78_ETC__q6 =
{ 64'h000000000000DEAD, val2__h168450 };
endcase
end
always@(theDebug_writebacks$D_OUT)
begin
case (theDebug_writebacks$D_OUT[4:0])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
x__h102125 = theDebug_writebacks$D_OUT[4:0];
default: x__h102125 = 5'd31;
endcase
end
always@(theDebug_traceCmp)
begin
case (theDebug_traceCmp[250:246])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
CASE_theDebug_traceCmp_BITS_250_TO_246_31_0_th_ETC__q9 =
theDebug_traceCmp[250:246];
default: CASE_theDebug_traceCmp_BITS_250_TO_246_31_0_th_ETC__q9 = 5'd31;
endcase
end
always@(memAccessToWriteback$D_OUT or target__h170730 or target__h170704)
begin
case (memAccessToWriteback$D_OUT[17:16])
2'd0: _theResult_____4__h170559 = target__h170704;
2'd1: _theResult_____4__h170559 = memAccessToWriteback$D_OUT[229:166];
default: _theResult_____4__h170559 = target__h170730;
endcase
end
always@(memAccess_inQ$D_OUT or
byteMask__h148899 or
byteMask__h148955 or
byteMask__h143211 or
byteMask__h147923 or
byteMask__h148413 or byteMask__h142387 or byteMask__h140788)
begin
case (memAccess_inQ$D_OUT[12:9])
4'd1: req_byteWrite__h144298 = 8'hFF;
4'd2: req_byteWrite__h144298 = byteMask__h148899;
4'd3: req_byteWrite__h144298 = byteMask__h148955;
4'd4: req_byteWrite__h144298 = byteMask__h143211;
4'd5: req_byteWrite__h144298 = byteMask__h147923;
4'd6: req_byteWrite__h144298 = byteMask__h148413;
4'd7: req_byteWrite__h144298 = byteMask__h142387;
4'd8: req_byteWrite__h144298 = byteMask__h140788;
default: req_byteWrite__h144298 = 8'd0;
endcase
end
always@(memAccess_inQ$D_OUT or
writeLine__h148954 or
writeLine__h148895 or
writeLine__h148898 or
writeLine__h147487 or
writeLine__h147922 or
writeLine__h148412 or writeLine__h146667 or writeLine__h145072)
begin
case (memAccess_inQ$D_OUT[12:9])
4'd1: x__h149013 = writeLine__h148895;
4'd2: x__h149013 = writeLine__h148898;
4'd4: x__h149013 = writeLine__h147487;
4'd5: x__h149013 = writeLine__h147922;
4'd6: x__h149013 = writeLine__h148412;
4'd7: x__h149013 = writeLine__h146667;
4'd8: x__h149013 = writeLine__h145072;
default: x__h149013 = writeLine__h148954;
endcase
end
always@(memAccess_inQ$D_OUT or x1_avValue_opA__h161811)
begin
case (memAccess_inQ$D_OUT[14:13])
2'd0: x__h163529 = memAccess_inQ$D_OUT[293:230];
2'd1: x__h163529 = x1_avValue_opA__h161811;
default: x__h163529 = memAccess_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT or x1_avValue_opA__h237707)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
x1_avValue_opA__h239033 = x1_avValue_opA__h237707;
default: x1_avValue_opA__h239033 = decode_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT or
_theResult_____1_opB__h245437 or x1_avValue_opA__h237707)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1, 6'd4, 6'd5:
x1_avValue_opA__h240519 = _theResult_____1_opB__h245437;
6'd2: x1_avValue_opA__h240519 = x1_avValue_opA__h237707;
default: x1_avValue_opA__h240519 = decode_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_opA__h237707 or _theResult_____1_opB__h245437)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1, 6'd4, 6'd5:
x1_avValue_opB__h240520 = x1_avValue_opA__h237707;
6'd2: x1_avValue_opB__h240520 = _theResult_____1_opB__h245437;
default: x1_avValue_opB__h240520 = decode_inQ$D_OUT[229:166];
endcase
end
always@(decode_inQ$D_OUT or theCP0$readGet or _theResult_____1_opB__h245437)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1: _theResult_____1_opA__h241134 = theCP0$readGet;
5'd4, 5'd5:
_theResult_____1_opA__h241134 = _theResult_____1_opB__h245437;
default: _theResult_____1_opA__h241134 =
(decode_inQ$D_OUT[427:423] != 5'd2 &&
decode_inQ$D_OUT[427:423] != 5'd6) ?
{ 58'b0, decode_inQ$D_OUT[407:402] } :
decode_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0: x1_avValue_coProSelect__h242564 = decode_inQ$D_OUT[386:384];
5'd4: x1_avValue_coProSelect__h242564 = decode_inQ$D_OUT[404:402];
default: x1_avValue_coProSelect__h242564 = decode_inQ$D_OUT[386:384];
endcase
end
always@(decode_inQ$D_OUT or theRF_regFile$D_OUT_1)
begin
case (decode_inQ$D_OUT[427:423])
5'd0,
5'd1,
5'd3,
5'd4,
5'd7,
5'd8,
5'd9,
5'd10,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
x1_avValue_opB__h242579 = theRF_regFile$D_OUT_1;
default: x1_avValue_opB__h242579 = decode_inQ$D_OUT[229:166];
endcase
end
always@(decode_inQ$D_OUT or
theRF_regFile$D_OUT_1 or x1_avValue_fst_opB__h243935)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19: x1_avValue_fst_opB__h243976 = theRF_regFile$D_OUT_1;
6'd18: x1_avValue_fst_opB__h243976 = x1_avValue_fst_opB__h243935;
default: x1_avValue_fst_opB__h243976 = decode_inQ$D_OUT[229:166];
endcase
end
always@(decode_inQ$D_OUT or theRF_regFile$D_OUT_2 or di_opA__h252675)
begin
case (decode_inQ$D_OUT[427:423])
5'd16, 5'd17, 5'd18, 5'd19, 5'd24, 5'd25, 5'd26, 5'd27:
IF_decode_inQ_first__909_BITS_427_TO_423_928_E_ETC___d6109 =
di_opA__h252675;
default: IF_decode_inQ_first__909_BITS_427_TO_423_928_E_ETC___d6109 =
theRF_regFile$D_OUT_2;
endcase
end
always@(decode_inQ$D_OUT or
theRF_regFile$D_OUT_2 or
IF_decode_inQ_first__909_BITS_427_TO_423_928_E_ETC___d6109)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1, 5'd3, 5'd4, 5'd7, 5'd8, 5'd9, 5'd10:
x1_avValue_opA__h242578 = theRF_regFile$D_OUT_2;
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
x1_avValue_opA__h242578 =
IF_decode_inQ_first__909_BITS_427_TO_423_928_E_ETC___d6109;
default: x1_avValue_opA__h242578 = decode_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT or
theRF_regFile$D_OUT_2 or x1_avValue_fst_opA__h243934)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19: x1_avValue_fst_opA__h243975 = theRF_regFile$D_OUT_2;
6'd18: x1_avValue_fst_opA__h243975 = x1_avValue_fst_opA__h243934;
default: x1_avValue_fst_opA__h243975 = decode_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT or
_theResult_____1_opB__h245437 or
x1_avValue_opA__h237707 or di_opB__h248895 or di_opB__h249572)
begin
case (decode_inQ$D_OUT[407:402])
6'd20, 6'd22, 6'd23, 6'd28, 6'd29, 6'd30, 6'd31:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6143 =
x1_avValue_opA__h237707;
6'd56, 6'd58, 6'd59:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6143 =
di_opB__h248895;
6'd60, 6'd62, 6'd63:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6143 =
di_opB__h249572;
default: IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6143 =
_theResult_____1_opB__h245437;
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_opA__h237707 or _theResult_____1_opB__h245437)
begin
case (decode_inQ$D_OUT[407:402])
6'd20,
6'd22,
6'd23,
6'd28,
6'd29,
6'd30,
6'd31,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6081 =
_theResult_____1_opB__h245437;
default: IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6081 =
x1_avValue_opA__h237707;
endcase
end
always@(decode_inQ$D_OUT or
_theResult_____1_opB__h245437 or
di_opB__h248895 or x1_avValue_opA__h237707)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd2, 6'd3:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6139 =
di_opB__h248895;
6'd4, 6'd6, 6'd7, 6'd24, 6'd25, 6'd26, 6'd27:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6139 =
x1_avValue_opA__h237707;
6'd16, 6'd17, 6'd18, 6'd19:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6139 =
decode_inQ$D_OUT[229:166];
default: IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6139 =
_theResult_____1_opB__h245437;
endcase
end
always@(decode_inQ$D_OUT or
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6139 or
x1_avValue_opA__h237707 or
_theResult_____1_opB__h245437 or
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6143)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd16,
6'd17,
6'd18,
6'd19,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35:
x1_avValue_opB__h240162 =
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6139;
6'd8, 6'd9: x1_avValue_opB__h240162 = x1_avValue_opA__h237707;
6'd10, 6'd11, 6'd48, 6'd49, 6'd50, 6'd51, 6'd52, 6'd54:
x1_avValue_opB__h240162 = _theResult_____1_opB__h245437;
6'd20,
6'd22,
6'd23,
6'd28,
6'd29,
6'd30,
6'd31,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
x1_avValue_opB__h240162 =
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6143;
default: x1_avValue_opB__h240162 = decode_inQ$D_OUT[229:166];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_opA__h237707 or _theResult_____1_opB__h245437)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd2, 6'd3, 6'd4, 6'd6, 6'd7, 6'd24, 6'd25, 6'd26, 6'd27:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6080 =
_theResult_____1_opB__h245437;
default: IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6080 =
x1_avValue_opA__h237707;
endcase
end
always@(decode_inQ$D_OUT or
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6080 or
x1_avValue_opA__h237707 or
di_opA__h250012 or
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6081)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd16,
6'd17,
6'd18,
6'd19,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35:
x1_avValue_opA__h240161 =
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6080;
6'd8,
6'd10,
6'd11,
6'd12,
6'd13,
6'd15,
6'd48,
6'd49,
6'd50,
6'd51,
6'd52,
6'd54:
x1_avValue_opA__h240161 = x1_avValue_opA__h237707;
6'd9: x1_avValue_opA__h240161 = di_opA__h250012;
6'd20,
6'd22,
6'd23,
6'd28,
6'd29,
6'd30,
6'd31,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
x1_avValue_opA__h240161 =
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d6081;
default: x1_avValue_opA__h240161 = decode_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_opA__h240161 or
x1_avValue_opA__h241182 or x1_avValue_opA__h240519)
begin
case (decode_inQ$D_OUT[433:428])
6'd0: x1_avValue_opA__h241282 = x1_avValue_opA__h240161;
6'd16: x1_avValue_opA__h241282 = x1_avValue_opA__h241182;
6'd28: x1_avValue_opA__h241282 = x1_avValue_opA__h240519;
default: x1_avValue_opA__h241282 = decode_inQ$D_OUT[293:230];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_fst_opA__h243975 or
x1_avValue_opA__h239033 or x1_avValue_opA__h241282)
begin
case (decode_inQ$D_OUT[435:434])
2'd0: x__h257310 = x1_avValue_opA__h239033;
2'd1: x__h257310 = decode_inQ$D_OUT[293:230];
2'd2: x__h257310 = x1_avValue_opA__h241282;
2'd3: x__h257310 = x1_avValue_fst_opA__h243975;
endcase
end
always@(decode_inQ$D_OUT or
IF_NOT_decode_inQ_first__909_BITS_427_TO_423_9_ETC___d6153 or
di___1_opB__h240965)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1, 5'd4, 5'd5:
_theResult_____1_opB__h241135 = di___1_opB__h240965;
default: _theResult_____1_opB__h241135 =
IF_NOT_decode_inQ_first__909_BITS_427_TO_423_9_ETC___d6153;
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_opB__h240162 or
x1_avValue_opB__h241183 or x1_avValue_opB__h240520)
begin
case (decode_inQ$D_OUT[433:428])
6'd0: x1_avValue_opB__h241283 = x1_avValue_opB__h240162;
6'd16: x1_avValue_opB__h241283 = x1_avValue_opB__h241183;
6'd28: x1_avValue_opB__h241283 = x1_avValue_opB__h240520;
default: x1_avValue_opB__h241283 = decode_inQ$D_OUT[229:166];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd2, 6'd3:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q12 =
decode_inQ$D_OUT[433:428] == 6'd3 || decode_inQ$D_OUT[7];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q12 =
decode_inQ$D_OUT[7];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q12)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7997 =
(decode_inQ$D_OUT[433:428] == 6'd1) ?
((decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
decode_inQ$D_OUT[422:418] != 5'd0 &&
decode_inQ$D_OUT[422:418] != 5'd1 &&
decode_inQ$D_OUT[422:418] != 5'd2 &&
decode_inQ$D_OUT[422:418] != 5'd3 &&
decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14 ||
decode_inQ$D_OUT[7] :
decode_inQ$D_OUT[7]) :
decode_inQ$D_OUT[7];
2'd1:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7997 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q12;
default: IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7997 =
decode_inQ$D_OUT[7];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd16, 5'd17, 5'd18, 5'd19, 5'd20, 5'd21, 5'd22, 5'd23:
CASE_decode_inQD_OUT_BITS_427_TO_423_3_16_0_1_ETC__q13 = 2'd0;
default: CASE_decode_inQD_OUT_BITS_427_TO_423_3_16_0_1_ETC__q13 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_427_TO_423_3_16_0_1_ETC__q13)
begin
case (decode_inQ$D_OUT[427:423])
5'd0: CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_0_4__ETC__q14 = 2'd0;
5'd4: CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_0_4__ETC__q14 = 2'd3;
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_0_4__ETC__q14 =
CASE_decode_inQD_OUT_BITS_427_TO_423_3_16_0_1_ETC__q13;
default: CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_0_4__ETC__q14 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_0_4__ETC__q14)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q15 = 2'd0;
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q15 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_0_4__ETC__q14 :
decode_inQ$D_OUT[383:382];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q15 =
decode_inQ$D_OUT[383:382];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[422:418])
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q16 =
decode_inQ$D_OUT[383:382];
default: CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q16 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd48,
6'd52,
6'd55:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_26_0_2_ETC__q17 = 2'd0;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_3_26_0_2_ETC__q17 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q16 or
CASE_decode_inQD_OUT_BITS_433_TO_428_3_26_0_2_ETC__q17)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
2'd3 :
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q16;
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18 = 2'd3;
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd24,
6'd25,
6'd56,
6'd60:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18 = 2'd0;
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18 =
CASE_decode_inQD_OUT_BITS_433_TO_428_3_26_0_2_ETC__q17;
6'd47:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18 =
decode_inQ$D_OUT[383:382];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd2, 6'd3, 6'd4, 6'd6, 6'd7, 6'd16, 6'd18:
CASE_decode_inQD_OUT_BITS_407_TO_402_0_0_0_2__ETC__q19 = 2'd0;
6'd17, 6'd19, 6'd24, 6'd25, 6'd26, 6'd27:
CASE_decode_inQD_OUT_BITS_407_TO_402_0_0_0_2__ETC__q19 = 2'd2;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_0_0_0_2__ETC__q19 = 2'd0;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd28, 6'd29, 6'd30, 6'd31:
CASE_decode_inQD_OUT_BITS_407_TO_402_0_28_2_2_ETC__q20 = 2'd2;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_0_28_2_2_ETC__q20 = 2'd0;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_0_0_0_2__ETC__q19 or
CASE_decode_inQD_OUT_BITS_407_TO_402_0_28_2_2_ETC__q20)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd16,
6'd17,
6'd18,
6'd19,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35:
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21 =
CASE_decode_inQD_OUT_BITS_407_TO_402_0_0_0_2__ETC__q19;
6'd8: CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21 = 2'd3;
6'd9: CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21 = 2'd0;
6'd10, 6'd11, 6'd12, 6'd13, 6'd48, 6'd49, 6'd50, 6'd51, 6'd52, 6'd54:
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21 =
decode_inQ$D_OUT[383:382];
6'd20,
6'd22,
6'd23,
6'd28,
6'd29,
6'd30,
6'd31,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21 =
CASE_decode_inQD_OUT_BITS_407_TO_402_0_28_2_2_ETC__q20;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1:
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q22 = 2'd0;
default: CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q22 =
(decode_inQ$D_OUT[427:423] != 5'd2 &&
decode_inQ$D_OUT[427:423] != 5'd6) ?
2'd1 :
decode_inQ$D_OUT[383:382];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1, 6'd4, 6'd5:
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_2_1__ETC__q23 = 2'd2;
6'd2: CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_2_1__ETC__q23 = 2'd0;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_2_1__ETC__q23 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21 or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q22 or
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_2_1__ETC__q23)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q24 =
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_CASE_ETC__q21;
6'd16:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q24 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q22 :
decode_inQ$D_OUT[383:382];
6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q24 =
CASE_decode_inQD_OUT_BITS_407_TO_402_3_0_2_1__ETC__q23;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q24 =
decode_inQ$D_OUT[383:382];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q15 or
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q24)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q25 =
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q18;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q25 =
decode_inQ$D_OUT[383:382];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q25 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q24;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q25 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q15;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q26 =
decode_inQ$D_OUT[8];
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q26 =
decode_inQ$D_OUT[433:428] != 6'd36 &&
decode_inQ$D_OUT[433:428] != 6'd37 &&
decode_inQ$D_OUT[433:428] != 6'd39;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q26 =
decode_inQ$D_OUT[8];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd4:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q27 =
decode_inQ$D_OUT[8];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q27 =
decode_inQ$D_OUT[427:423] == 5'd20 ||
decode_inQ$D_OUT[427:423] == 5'd21 ||
decode_inQ$D_OUT[427:423] == 5'd22 ||
decode_inQ$D_OUT[427:423] == 5'd23 ||
decode_inQ$D_OUT[427:423] == 5'd28 ||
decode_inQ$D_OUT[427:423] == 5'd29 ||
decode_inQ$D_OUT[427:423] == 5'd30 ||
decode_inQ$D_OUT[427:423] == 5'd31 ||
decode_inQ$D_OUT[427:423] == 5'd16 ||
decode_inQ$D_OUT[427:423] == 5'd17 ||
decode_inQ$D_OUT[427:423] == 5'd18 ||
decode_inQ$D_OUT[427:423] == 5'd19 ||
decode_inQ$D_OUT[427:423] == 5'd24 ||
decode_inQ$D_OUT[427:423] == 5'd25 ||
decode_inQ$D_OUT[427:423] == 5'd26 ||
decode_inQ$D_OUT[427:423] == 5'd27 ||
decode_inQ$D_OUT[8];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[422:420])
3'd0:
CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28 =
decode_inQ$D_OUT[422:420];
3'd1, 3'd2:
CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28 = 3'd5;
3'd3: CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28 = 3'd2;
3'd4, 3'd5:
CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28 = 3'd1;
default: CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28 = 3'd5;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q29 =
decode_inQ$D_OUT[6:4];
6'd47:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q29 =
CASE_decode_inQD_OUT_BITS_422_TO_420_5_0_deco_ETC__q28;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q29 =
decode_inQ$D_OUT[6:4];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[419:418])
2'd0, 2'd1, 2'd2, 2'd3:
CASE_decode_inQD_OUT_BITS_419_TO_418_decode_i_ETC__q30 =
decode_inQ$D_OUT[419:418];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_419_TO_418_decode_i_ETC__q30)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q31 =
decode_inQ$D_OUT[3:2];
6'd47:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q31 =
CASE_decode_inQD_OUT_BITS_419_TO_418_decode_i_ETC__q30;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q31 =
decode_inQ$D_OUT[3:2];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1, 5'd4, 5'd5:
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q32 =
decode_inQ$D_OUT[0];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q32 =
(decode_inQ$D_OUT[427:423] != 5'd2 &&
decode_inQ$D_OUT[427:423] != 5'd6) ?
decode_inQ$D_OUT[407:402] == 6'd24 ||
decode_inQ$D_OUT[0] :
decode_inQ$D_OUT[0];
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q32)
begin
case (decode_inQ$D_OUT[433:428])
6'd0, 6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q33 =
decode_inQ$D_OUT[0];
6'd16:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q33 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q32 :
decode_inQ$D_OUT[0];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q33 =
decode_inQ$D_OUT[0];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q33)
begin
case (decode_inQ$D_OUT[435:434])
2'd0, 2'd1, 2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q34 =
decode_inQ$D_OUT[0];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q34 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q33;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd16, 5'd17, 5'd18, 5'd19, 5'd20, 5'd21, 5'd22, 5'd23:
CASE_decode_inQD_OUT_BITS_427_TO_423_1_16_0_1_ETC__q35 = 2'd0;
default: CASE_decode_inQD_OUT_BITS_427_TO_423_1_16_0_1_ETC__q35 = 2'd1;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_427_TO_423_1_16_0_1_ETC__q35)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd4:
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_3_4__ETC__q36 = 2'd3;
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_3_4__ETC__q36 =
CASE_decode_inQD_OUT_BITS_427_TO_423_1_16_0_1_ETC__q35;
default: CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_3_4__ETC__q36 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_3_4__ETC__q36)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q37 = 2'd3;
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q37 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_3_0_3_4__ETC__q36 :
decode_inQ$D_OUT[14:13];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q37 =
decode_inQ$D_OUT[14:13];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[422:418])
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q38 =
decode_inQ$D_OUT[14:13];
default: CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q38 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd48,
6'd52,
6'd55:
CASE_decode_inQD_OUT_BITS_433_TO_428_1_26_0_2_ETC__q39 = 2'd0;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_1_26_0_2_ETC__q39 = 2'd1;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q38 or
CASE_decode_inQD_OUT_BITS_433_TO_428_1_26_0_2_ETC__q39)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
2'd3 :
CASE_decode_inQD_OUT_BITS_422_TO_418_3_8_deco_ETC__q38;
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40 = 2'd3;
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40 =
CASE_decode_inQD_OUT_BITS_433_TO_428_1_26_0_2_ETC__q39;
6'd47: CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40 = 2'd2;
6'd56, 6'd60:
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40 = 2'd1;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40 = 2'd3;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd0, 6'd16, 6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q41 = 2'd3;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q41 =
decode_inQ$D_OUT[14:13];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q37 or
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q41)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q42 =
CASE_decode_inQD_OUT_BITS_433_TO_428_3_1_IF_N_ETC__q40;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q42 =
decode_inQ$D_OUT[14:13];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q42 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q41;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q42 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q37;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd26, 6'd44:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd2;
6'd27, 6'd45:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd3;
6'd32, 6'd36, 6'd40:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd8;
6'd33, 6'd37, 6'd41:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd7;
6'd34, 6'd42:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd5;
6'd35, 6'd39, 6'd43, 6'd48:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd4;
6'd38, 6'd46:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd6;
6'd52, 6'd55, 6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 = 4'd1;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 =
decode_inQ$D_OUT[12:9];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd56: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q44 = 4'd4;
6'd60: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q44 = 4'd1;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q44 =
decode_inQ$D_OUT[12:9];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q44)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q45 =
decode_inQ$D_OUT[12:9];
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q45 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q43;
6'd56, 6'd60:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q45 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q44;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q45 =
decode_inQ$D_OUT[12:9];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd16, 5'd20, 5'd24, 5'd28:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46 = 4'd8;
5'd17, 5'd21, 5'd25, 5'd29:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46 = 4'd7;
5'd18, 5'd22, 5'd26, 5'd30:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46 = 4'd4;
5'd19, 5'd23, 5'd27, 5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46 = 4'd1;
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46 =
decode_inQ$D_OUT[12:9];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd4:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q47 =
decode_inQ$D_OUT[12:9];
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q47 =
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q46;
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q47 =
decode_inQ$D_OUT[12:9];
endcase
end
always@(memAccessToWriteback$D_OUT)
begin
case (memAccessToWriteback$D_OUT[435:434])
2'd0, 2'd1, 2'd2:
CASE_memAccessToWritebackD_OUT_BITS_435_TO_43_ETC__q48 =
memAccessToWriteback$D_OUT[435:434];
2'd3: CASE_memAccessToWritebackD_OUT_BITS_435_TO_43_ETC__q48 = 2'd3;
endcase
end
always@(memAccess_inQ$D_OUT)
begin
case (memAccess_inQ$D_OUT[435:434])
2'd0, 2'd1, 2'd2:
IF_memAccess_inQ_first__055_BITS_435_TO_434_25_ETC___d8942 =
memAccess_inQ$D_OUT[435:434];
2'd3: IF_memAccess_inQ_first__055_BITS_435_TO_434_25_ETC___d8942 = 2'd3;
endcase
end
always@(execute_inQ$D_OUT)
begin
case (execute_inQ$D_OUT[435:434])
2'd0, 2'd1, 2'd2:
CASE_execute_inQD_OUT_BITS_435_TO_434_3_0_exe_ETC__q49 =
execute_inQ$D_OUT[435:434];
2'd3: CASE_execute_inQD_OUT_BITS_435_TO_434_3_0_exe_ETC__q49 = 2'd3;
endcase
end
always@(theCapCop_capInsts$D_OUT or execute_inQ$D_OUT)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0, 5'd1, 5'd4, 5'd7, 5'd8:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50 =
execute_inQ$D_OUT[12:9];
5'd9, 5'd10:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50 = 4'd0;
5'd16, 5'd20, 5'd24, 5'd28:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50 = 4'd8;
5'd17, 5'd21, 5'd25, 5'd29:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50 = 4'd7;
5'd18, 5'd22, 5'd26, 5'd30:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50 = 4'd4;
5'd19, 5'd23, 5'd27, 5'd31:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50 = 4'd1;
default: CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50 =
execute_inQ$D_OUT[12:9];
endcase
end
always@(CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50)
begin
case (CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_ex_ETC__q50)
4'd0: CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51 = 6'd32;
4'd1, 4'd2, 4'd3:
CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51 = 6'd8;
4'd4, 4'd5, 4'd6:
CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51 = 6'd4;
4'd7: CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51 = 6'd2;
4'd8: CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51 = 6'd1;
default: CASE_CASE_theCapCop_capInstsD_OUT_BITS_99_TO_9_ETC__q51 =
6'd32;
endcase
end
always@(execute_inQ$D_OUT)
begin
case (execute_inQ$D_OUT[12:9])
4'd0: CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52 = 6'd32;
4'd1, 4'd2, 4'd3:
CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52 = 6'd8;
4'd4, 4'd5, 4'd6:
CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52 = 6'd4;
4'd7: CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52 = 6'd2;
4'd8: CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52 = 6'd1;
default: CASE_execute_inQD_OUT_BITS_12_TO_9_32_0_32_1__ETC__q52 = 6'd32;
endcase
end
always@(theDebug_debugConvert$messages_request_get)
begin
case ({ theDebug_debugConvert$messages_request_get[2:0],
theDebug_debugConvert$messages_request_get[15:14] })
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
IF_theDebug_debugConvert_messages_request_get__ETC___d7855 =
{ theDebug_debugConvert$messages_request_get[2:0],
theDebug_debugConvert$messages_request_get[15:14] };
default: IF_theDebug_debugConvert_messages_request_get__ETC___d7855 =
5'd31;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[422:418])
5'd0, 5'd2, 5'd16, 5'd18:
CASE_decode_inQD_OUT_BITS_422_TO_418_IF_NOT_d_ETC__q53 = 4'd4;
default: CASE_decode_inQD_OUT_BITS_422_TO_418_IF_NOT_d_ETC__q53 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
4'd1 :
decode_inQ$D_OUT[400:397];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd4, 6'd20:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54 = 4'd0;
6'd5, 6'd21:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54 = 4'd5;
6'd6, 6'd22:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54 = 4'd3;
6'd7, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54 = 4'd2;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54 =
decode_inQ$D_OUT[400:397];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_418_IF_NOT_d_ETC__q53 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q55 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
CASE_decode_inQD_OUT_BITS_422_TO_418_IF_NOT_d_ETC__q53 :
decode_inQ$D_OUT[400:397];
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q55 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q54;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q55 =
decode_inQ$D_OUT[400:397];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd2, 6'd3:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q56 = 4'd6;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q56 =
decode_inQ$D_OUT[400:397];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd10,
6'd11,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q57 =
decode_inQ$D_OUT[400:397];
6'd8, 6'd9:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q57 = 4'd8;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q57 =
decode_inQ$D_OUT[400:397];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q55 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q56 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q57)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7996 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q55;
2'd1:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7996 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q56;
2'd2:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7996 =
(decode_inQ$D_OUT[433:428] == 6'd0) ?
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q57 :
decode_inQ$D_OUT[400:397];
2'd3:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7996 =
decode_inQ$D_OUT[400:397];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q58 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
2'd0 :
decode_inQ$D_OUT[17:16];
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q58 = 2'd0;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q58 =
decode_inQ$D_OUT[17:16];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd2, 6'd3:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q59 = 2'd2;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q59 =
decode_inQ$D_OUT[17:16];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd10,
6'd11,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q60 =
decode_inQ$D_OUT[17:16];
6'd8, 6'd9:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q60 = 2'd1;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q60 =
decode_inQ$D_OUT[17:16];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1, 5'd4, 5'd5:
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q61 =
decode_inQ$D_OUT[17:16];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q61 =
(decode_inQ$D_OUT[427:423] != 5'd2 &&
decode_inQ$D_OUT[427:423] != 5'd6) ?
((decode_inQ$D_OUT[407:402] == 6'd24) ?
2'd1 :
decode_inQ$D_OUT[17:16]) :
decode_inQ$D_OUT[17:16];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q60 or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q61)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q62 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q60;
6'd16:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q62 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_IF_NOT_d_ETC__q61 :
decode_inQ$D_OUT[17:16];
6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q62 =
decode_inQ$D_OUT[17:16];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q62 =
decode_inQ$D_OUT[17:16];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q58 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q59 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q62)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q63 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q58;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q63 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q59;
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q63 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q62;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q63 =
decode_inQ$D_OUT[17:16];
endcase
end
always@(decode_inQ$D_OUT or
SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041)
begin
case (decode_inQ$D_OUT[422:418])
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q65 =
SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041;
default: CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q65 =
decode_inQ$D_OUT[229:166];
endcase
end
always@(decode_inQ$D_OUT or
SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041 or
di_opB__h245718 or di_opB__h246406)
begin
case (decode_inQ$D_OUT[433:428])
6'd12, 6'd13, 6'd14:
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d6130 =
di_opB__h245718;
6'd15:
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d6130 =
di_opB__h246406;
default: IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d6130 =
SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041;
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_opB__h237708 or
_theResult_____1_opB__h245437 or
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d6130 or
SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041)
begin
case (decode_inQ$D_OUT[433:428])
6'd1: x1_avValue_opB__h239034 = x1_avValue_opB__h237708;
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
x1_avValue_opB__h239034 = _theResult_____1_opB__h245437;
6'd8, 6'd9, 6'd10, 6'd11, 6'd12, 6'd13, 6'd14, 6'd15, 6'd24, 6'd25:
x1_avValue_opB__h239034 =
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d6130;
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
x1_avValue_opB__h239034 =
SEXT_decode_inQ_first__909_BITS_417_TO_402_119___d8041;
default: x1_avValue_opB__h239034 = decode_inQ$D_OUT[229:166];
endcase
end
always@(decode_inQ$D_OUT or
x1_avValue_fst_opB__h243976 or
x1_avValue_opB__h239034 or x1_avValue_opB__h241283)
begin
case (decode_inQ$D_OUT[435:434])
2'd0: x__h257489 = x1_avValue_opB__h239034;
2'd1: x__h257489 = decode_inQ$D_OUT[229:166];
2'd2: x__h257489 = x1_avValue_opB__h241283;
2'd3: x__h257489 = x1_avValue_fst_opB__h243976;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0,
5'd1,
5'd3,
5'd4,
5'd7,
5'd8,
5'd9,
5'd10,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q66 =
decode_inQ$D_OUT[354:343];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q66 =
decode_inQ$D_OUT[318:307];
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q66)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q67 =
decode_inQ$D_OUT[354:343];
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q67 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q66 :
decode_inQ$D_OUT[318:307];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q67 =
decode_inQ$D_OUT[318:307];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_NOT_deco_ETC__q68 =
decode_inQ$D_OUT[354];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_NOT_deco_ETC__q68 =
decode_inQ$D_OUT[433:428] != 6'd24 &&
decode_inQ$D_OUT[433:428] != 6'd25 &&
decode_inQ$D_OUT[433:428] != 6'd8 &&
decode_inQ$D_OUT[433:428] != 6'd9 &&
decode_inQ$D_OUT[433:428] != 6'd10 &&
decode_inQ$D_OUT[433:428] != 6'd11 &&
decode_inQ$D_OUT[433:428] != 6'd12 &&
decode_inQ$D_OUT[433:428] != 6'd13 &&
decode_inQ$D_OUT[433:428] != 6'd14 &&
decode_inQ$D_OUT[433:428] != 6'd15 &&
decode_inQ$D_OUT[433:428] != 6'd32 &&
decode_inQ$D_OUT[433:428] != 6'd33 &&
decode_inQ$D_OUT[433:428] != 6'd35 &&
decode_inQ$D_OUT[433:428] != 6'd34 &&
decode_inQ$D_OUT[433:428] != 6'd38 &&
decode_inQ$D_OUT[433:428] != 6'd48 &&
decode_inQ$D_OUT[433:428] != 6'd40 &&
decode_inQ$D_OUT[433:428] != 6'd41 &&
decode_inQ$D_OUT[433:428] != 6'd43 &&
decode_inQ$D_OUT[433:428] != 6'd42 &&
decode_inQ$D_OUT[433:428] != 6'd46 &&
decode_inQ$D_OUT[433:428] != 6'd55 &&
decode_inQ$D_OUT[433:428] != 6'd26 &&
decode_inQ$D_OUT[433:428] != 6'd27 &&
decode_inQ$D_OUT[433:428] != 6'd52 &&
decode_inQ$D_OUT[433:428] != 6'd63 &&
decode_inQ$D_OUT[433:428] != 6'd44 &&
decode_inQ$D_OUT[433:428] != 6'd45 &&
decode_inQ$D_OUT[433:428] != 6'd36 &&
decode_inQ$D_OUT[433:428] != 6'd37 &&
decode_inQ$D_OUT[433:428] != 6'd39 &&
decode_inQ$D_OUT[433:428] != 6'd56 &&
decode_inQ$D_OUT[433:428] != 6'd60 &&
decode_inQ$D_OUT[433:428] != 6'd47 &&
decode_inQ$D_OUT[318];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q69 =
decode_inQ$D_OUT[317:307];
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q69 =
decode_inQ$D_OUT[353:343];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q69 =
decode_inQ$D_OUT[317:307];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd16, 6'd17, 6'd18, 6'd19:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q70 =
decode_inQ$D_OUT[318];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q70 =
decode_inQ$D_OUT[354];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd2, 6'd3, 6'd16, 6'd17, 6'd18, 6'd19:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q71 =
decode_inQ$D_OUT[317:307];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q71 =
decode_inQ$D_OUT[353:343];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q70 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q71)
begin
case (decode_inQ$D_OUT[407:402])
6'd4, 6'd6, 6'd7, 6'd24, 6'd25, 6'd26, 6'd27:
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q72 =
decode_inQ$D_OUT[366:355];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q72 =
{ decode_inQ$D_OUT[407:402] != 6'd0 &&
decode_inQ$D_OUT[407:402] != 6'd3 &&
decode_inQ$D_OUT[407:402] != 6'd2 &&
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q70,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q71 };
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd56, 6'd58, 6'd59, 6'd60, 6'd62, 6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q73 =
decode_inQ$D_OUT[317:307];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q73 =
decode_inQ$D_OUT[353:343];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q73)
begin
case (decode_inQ$D_OUT[407:402])
6'd20, 6'd22, 6'd23, 6'd28, 6'd29, 6'd30, 6'd31:
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q74 =
decode_inQ$D_OUT[366:355];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q74 =
{ decode_inQ$D_OUT[407:402] != 6'd56 &&
decode_inQ$D_OUT[407:402] != 6'd58 &&
decode_inQ$D_OUT[407:402] != 6'd59 &&
decode_inQ$D_OUT[407:402] != 6'd60 &&
decode_inQ$D_OUT[407:402] != 6'd62 &&
decode_inQ$D_OUT[407:402] != 6'd63 &&
decode_inQ$D_OUT[354],
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q73 };
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q72 or
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q74)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd16,
6'd17,
6'd18,
6'd19,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75 =
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q72;
6'd8, 6'd9:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75 =
decode_inQ$D_OUT[366:355];
6'd10, 6'd11, 6'd48, 6'd49, 6'd50, 6'd51, 6'd52, 6'd54:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75 =
decode_inQ$D_OUT[354:343];
6'd20,
6'd22,
6'd23,
6'd28,
6'd29,
6'd30,
6'd31,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75 =
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q74;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75 =
decode_inQ$D_OUT[318:307];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1, 6'd4, 6'd5:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q76 =
decode_inQ$D_OUT[366:355];
6'd2:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q76 =
decode_inQ$D_OUT[354:343];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q76 =
decode_inQ$D_OUT[318:307];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q76)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q77 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q75;
6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q77 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q76;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q77 =
decode_inQ$D_OUT[318:307];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q67 or
CASE_decode_inQD_OUT_BITS_433_TO_428_NOT_deco_ETC__q68 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q69 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q77)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q78 =
{ decode_inQ$D_OUT[433:428] != 6'd1 &&
CASE_decode_inQD_OUT_BITS_433_TO_428_NOT_deco_ETC__q68,
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q69 };
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q78 =
decode_inQ$D_OUT[318:307];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q78 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q77;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q78 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q67;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd4:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q79 =
decode_inQ$D_OUT[306:295];
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q79 =
decode_inQ$D_OUT[354:343];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q79 =
decode_inQ$D_OUT[306:295];
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q79)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q80 =
decode_inQ$D_OUT[306:295];
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q80 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q79 :
decode_inQ$D_OUT[306:295];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q80 =
decode_inQ$D_OUT[306:295];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q81 =
decode_inQ$D_OUT[306:295];
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q81 =
decode_inQ$D_OUT[354:343];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q81 =
decode_inQ$D_OUT[306:295];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q82 =
decode_inQ$D_OUT[306:295];
6'd10, 6'd11:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q82 =
decode_inQ$D_OUT[342:331];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q82 =
decode_inQ$D_OUT[306:295];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q80 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q81 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q82)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q83 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q81;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q83 =
decode_inQ$D_OUT[306:295];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q83 =
(decode_inQ$D_OUT[433:428] == 6'd0) ?
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q82 :
decode_inQ$D_OUT[306:295];
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q83 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q80;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_4_1_IF_N_ETC__q84 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
20'd8 :
20'd4;
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_4_1_IF_N_ETC__q84 = 20'd8;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_4_1_IF_N_ETC__q84 = 20'd4;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1, 5'd3, 5'd4, 5'd7, 5'd8, 5'd9, 5'd10:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q85 =
decode_inQ$D_OUT[366];
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q85 =
decode_inQ$D_OUT[427:423] != 5'd16 &&
decode_inQ$D_OUT[427:423] != 5'd17 &&
decode_inQ$D_OUT[427:423] != 5'd18 &&
decode_inQ$D_OUT[427:423] != 5'd19 &&
decode_inQ$D_OUT[427:423] != 5'd24 &&
decode_inQ$D_OUT[427:423] != 5'd25 &&
decode_inQ$D_OUT[427:423] != 5'd26 &&
decode_inQ$D_OUT[427:423] != 5'd27 &&
decode_inQ$D_OUT[366];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q85 =
decode_inQ$D_OUT[330];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0,
5'd1,
5'd3,
5'd4,
5'd7,
5'd8,
5'd9,
5'd10,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q86 =
decode_inQ$D_OUT[365:355];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q86 =
decode_inQ$D_OUT[329:319];
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q85 or
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q86)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q87 =
decode_inQ$D_OUT[366:355];
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q87 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
{ CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q85,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q86 } :
decode_inQ$D_OUT[330:319];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q87 =
decode_inQ$D_OUT[330:319];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q88 =
decode_inQ$D_OUT[366:355];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q88 =
decode_inQ$D_OUT[330:319];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd12, 6'd13, 6'd15, 6'd48, 6'd49, 6'd50, 6'd51, 6'd52, 6'd54:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q89 =
decode_inQ$D_OUT[366];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q89 =
decode_inQ$D_OUT[330];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q89)
begin
case (decode_inQ$D_OUT[407:402])
6'd8, 6'd10, 6'd11:
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q90 =
decode_inQ$D_OUT[366];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q90 =
decode_inQ$D_OUT[407:402] != 6'd9 &&
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q89;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd15,
6'd48,
6'd49,
6'd50,
6'd51,
6'd52,
6'd54:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q91 =
decode_inQ$D_OUT[365:355];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q91 =
decode_inQ$D_OUT[329:319];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd2, 6'd3, 6'd4, 6'd6, 6'd7, 6'd24, 6'd25, 6'd26, 6'd27:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q92 =
decode_inQ$D_OUT[354:343];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q92 =
decode_inQ$D_OUT[366:355];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd20,
6'd22,
6'd23,
6'd28,
6'd29,
6'd30,
6'd31,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q93 =
decode_inQ$D_OUT[354:343];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q93 =
decode_inQ$D_OUT[366:355];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q90 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q91 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q92 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q93)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd16,
6'd17,
6'd18,
6'd19,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35:
CASE_decode_inQD_OUT_BITS_407_TO_402_CASE_dec_ETC__q94 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q92;
6'd20,
6'd22,
6'd23,
6'd28,
6'd29,
6'd30,
6'd31,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_CASE_dec_ETC__q94 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q93;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_CASE_dec_ETC__q94 =
{ CASE_decode_inQD_OUT_BITS_407_TO_402_NOT_deco_ETC__q90,
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q91 };
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd4, 5'd5:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q95 =
decode_inQ$D_OUT[354];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q95 =
(decode_inQ$D_OUT[427:423] == 5'd2 ||
decode_inQ$D_OUT[427:423] == 5'd6) &&
decode_inQ$D_OUT[330];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0, 5'd1:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q96 =
decode_inQ$D_OUT[329:319];
5'd4, 5'd5:
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q96 =
decode_inQ$D_OUT[353:343];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q96 =
decode_inQ$D_OUT[329:319];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1, 6'd4, 6'd5:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q97 =
decode_inQ$D_OUT[354:343];
6'd2:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q97 =
decode_inQ$D_OUT[366:355];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q97 =
decode_inQ$D_OUT[330:319];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_CASE_dec_ETC__q94 or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q95 or
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q96 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q97)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q98 =
CASE_decode_inQD_OUT_BITS_407_TO_402_CASE_dec_ETC__q94;
6'd16:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q98 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
{ decode_inQ$D_OUT[427:423] != 5'd0 &&
decode_inQ$D_OUT[427:423] != 5'd1 &&
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q95,
CASE_decode_inQD_OUT_BITS_427_TO_423_decode_i_ETC__q96 } :
decode_inQ$D_OUT[330:319];
6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q98 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q97;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q98 =
decode_inQ$D_OUT[330:319];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q87 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q88 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q98)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q99 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q88;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q99 =
decode_inQ$D_OUT[330:319];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q99 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q98;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q99 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q87;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[422:418])
5'd8, 5'd9:
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100 = 3'd1;
5'd10, 5'd11:
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100 = 3'd2;
5'd12: CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100 = 3'd0;
5'd14: CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100 = 3'd3;
default: CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100 =
decode_inQ$D_OUT[374:372];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100)
begin
case (decode_inQ$D_OUT[422:418])
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q101 =
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q100;
default: CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q101 =
decode_inQ$D_OUT[374:372];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd36, 6'd37, 6'd39:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q102 =
decode_inQ$D_OUT[374:372];
6'd48, 6'd52:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q102 = 3'd4;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q102 =
decode_inQ$D_OUT[374:372];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q101 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q102)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
decode_inQ$D_OUT[374:372] :
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q101;
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103 =
decode_inQ$D_OUT[374:372];
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd48,
6'd52,
6'd55,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q102;
6'd56, 6'd60:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103 = 3'd5;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103 =
decode_inQ$D_OUT[374:372];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd48, 6'd49:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104 = 3'd1;
6'd50, 6'd51:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104 = 3'd2;
6'd52: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104 = 3'd0;
6'd54: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104 = 3'd3;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104 =
decode_inQ$D_OUT[374:372];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q105 =
decode_inQ$D_OUT[374:372];
6'd48, 6'd49, 6'd50, 6'd51, 6'd52, 6'd54:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q105 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q104;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q105 =
decode_inQ$D_OUT[374:372];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q105)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q106 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q103;
2'd1, 2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q106 =
decode_inQ$D_OUT[374:372];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_decode_i_ETC__q106 =
(decode_inQ$D_OUT[433:428] == 6'd0) ?
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q105 :
decode_inQ$D_OUT[374:372];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd17: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q107 = 5'd17;
6'd19: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q107 = 5'd19;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q107 =
decode_inQ$D_OUT[371:367];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[427:423])
5'd0,
5'd1,
5'd3,
5'd4,
5'd7,
5'd8,
5'd9,
5'd10,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_decode_inQD_OUT_BITS_427_TO_423_15_0_dec_ETC__q108 =
decode_inQ$D_OUT[371:367];
default: CASE_decode_inQD_OUT_BITS_427_TO_423_15_0_dec_ETC__q108 =
5'd15;
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q107 or
CASE_decode_inQD_OUT_BITS_427_TO_423_15_0_dec_ETC__q108)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q109 =
(theCP0$getCoprocessorEnables[1] &&
decode_inQ$D_OUT[433:428] == 6'd17 ||
theCP0$getCoprocessorEnables[3] &&
decode_inQ$D_OUT[433:428] == 6'd19) ?
decode_inQ$D_OUT[371:367] :
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q107;
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q109 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
CASE_decode_inQD_OUT_BITS_427_TO_423_15_0_dec_ETC__q108 :
5'd18;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q109 =
decode_inQ$D_OUT[371:367];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1,
6'd4,
6'd5,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd20,
6'd21,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_15_1_dec_ETC__q110 =
decode_inQ$D_OUT[371:367];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_15_1_dec_ETC__q110 =
5'd15;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd15,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd49,
6'd50,
6'd51,
6'd52,
6'd54,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q111 =
decode_inQ$D_OUT[371:367];
6'd12: CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q111 = 5'd13;
6'd13: CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q111 = 5'd14;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q111 =
5'd15;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1, 6'd2, 6'd4, 6'd5:
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q112 =
decode_inQ$D_OUT[371:367];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q112 =
5'd15;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q111 or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q112)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q113 =
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q111;
6'd16:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q113 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[371:367] :
5'd16;
6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q113 =
CASE_decode_inQD_OUT_BITS_407_TO_402_15_0_dec_ETC__q112;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q113 =
decode_inQ$D_OUT[371:367];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q109 or
CASE_decode_inQD_OUT_BITS_433_TO_428_15_1_dec_ETC__q110 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q113)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q114 =
CASE_decode_inQD_OUT_BITS_433_TO_428_15_1_dec_ETC__q110;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q114 =
decode_inQ$D_OUT[371:367];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q114 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q113;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q114 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q109;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3604 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3605 or
theCapCop_pcc)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0,
5'd4,
5'd8,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213;
5'd1:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886 =
(IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3604 ||
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3605) &&
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213;
5'd7:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886 =
theCapCop_pcc[255];
default: IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d7886 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044)
begin
case (execute_inQ$D_OUT[304:303])
2'd0:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042;
2'd1:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043;
2'd2:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044;
2'd3:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d9065 =
execute_inQ$D_OUT[304:303] != 2'd3 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045;
endcase
end
always@(memAccessToWriteback$D_OUT)
begin
case (memAccessToWriteback$D_OUT[374:372])
3'd0:
CASE_memAccessToWritebackD_OUT_BITS_374_TO_37_ETC__q115 =
!memAccessToWriteback$D_OUT[380] &&
memAccessToWriteback$D_OUT[293:230] == 64'd0;
3'd1:
CASE_memAccessToWritebackD_OUT_BITS_374_TO_37_ETC__q115 =
memAccessToWriteback$D_OUT[380] ?
!memAccessToWriteback$D_OUT[293] :
!memAccessToWriteback$D_OUT[392];
3'd2:
CASE_memAccessToWritebackD_OUT_BITS_374_TO_37_ETC__q115 =
memAccessToWriteback$D_OUT[380] ?
memAccessToWriteback$D_OUT[293] :
memAccessToWriteback$D_OUT[392];
default: CASE_memAccessToWritebackD_OUT_BITS_374_TO_37_ETC__q115 =
memAccessToWriteback$D_OUT[374:372] == 3'd3 &&
!memAccessToWriteback$D_OUT[380] &&
memAccessToWriteback$D_OUT[293:230] != 64'd0;
endcase
end
always@(theDebug_debugConvert$messages_request_get)
begin
case (theDebug_debugConvert$messages_request_get[271:264])
8'd48:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd22;
8'd49:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd23;
8'd50:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd24;
8'd51:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd25;
8'd67:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd26;
8'd77:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd27;
8'd83:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd37;
8'd97:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd20;
8'd98:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd21;
8'd99:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd35;
8'd100:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd30;
8'd101:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd28;
8'd105:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd19;
8'd112:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd31;
8'd114:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd32;
8'd115:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd33;
8'd117:
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 = 6'd36;
default: IF_theDebug_debugConvert_messages_request_get__ETC___d8630 =
6'd34;
endcase
end
always@(IF_theDebug_debugConvert_messages_request_get__ETC___d8630)
begin
case (IF_theDebug_debugConvert_messages_request_get__ETC___d8630)
6'd0: IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd0;
6'd1:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd105;
6'd2:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd97;
6'd3:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd98;
6'd4:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd48;
6'd5:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd49;
6'd6:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd50;
6'd7:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd51;
6'd8:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd67;
6'd9:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd77;
6'd10:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd101;
6'd11:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd100;
6'd12:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd112;
6'd13:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd114;
6'd14:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd115;
6'd15:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd99;
6'd16:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd117;
6'd17:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd116;
6'd18:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd83;
6'd19:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd233;
6'd20:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd225;
6'd21:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd226;
6'd22:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd176;
6'd23:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd177;
6'd24:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd178;
6'd25:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd179;
6'd26:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd195;
6'd27:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd205;
6'd28:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd229;
6'd29:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd197;
6'd30:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd228;
6'd31:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd240;
6'd32:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd242;
6'd33:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd243;
6'd34:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd244;
6'd35:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd227;
6'd36:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd245;
6'd37:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd211;
6'd38:
IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 = 8'd255;
default: IF_IF_theDebug_debugConvert_messages_request_g_ETC___d7852 =
8'd32;
endcase
end
always@(theDebug_curCommand$D_OUT)
begin
case (theDebug_curCommand$D_OUT[271:264])
8'd48:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd22;
8'd49:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd23;
8'd50:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd24;
8'd51:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd25;
8'd67:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd26;
8'd77:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd27;
8'd83:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd37;
8'd97:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd20;
8'd98:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd21;
8'd99:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd35;
8'd100:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd30;
8'd101:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd28;
8'd105:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd19;
8'd112:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd31;
8'd114:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd32;
8'd115:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd33;
8'd117:
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 = 6'd36;
default: IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666 =
6'd34;
endcase
end
always@(memAccess_inQ$D_OUT)
begin
case (memAccess_inQ$D_OUT[12:9])
4'd1:
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800 =
memAccess_inQ$D_OUT[232:230] != 3'd0;
4'd4:
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800 =
memAccess_inQ$D_OUT[231:230] != 2'b0;
default: IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800 =
memAccess_inQ$D_OUT[12:9] == 4'd7 &&
memAccess_inQ$D_OUT[230];
endcase
end
always@(memAccess_inQ$D_OUT or
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800)
begin
case (memAccess_inQ$D_OUT[14:13])
2'd0:
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q116 =
memAccess_inQ$D_OUT[14:13];
2'd1:
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q116 =
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800 ?
2'd3 :
((memAccess_inQ$D_OUT[374:372] != 3'd5 ||
memAccess_inQ$D_OUT[166]) ?
memAccess_inQ$D_OUT[14:13] :
2'd3);
default: CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q116 =
memAccess_inQ$D_OUT[14:13];
endcase
end
always@(memAccess_inQ$D_OUT or
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800)
begin
case (memAccess_inQ$D_OUT[14:13])
2'd0:
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q117 =
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800 ?
5'd9 :
memAccess_inQ$D_OUT[371:367];
2'd1:
CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q117 =
IF_memAccess_inQ_first__055_BITS_12_TO_9_062_E_ETC___d8800 ?
5'd10 :
memAccess_inQ$D_OUT[371:367];
default: CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q117 =
memAccess_inQ$D_OUT[371:367];
endcase
end
always@(IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712)
begin
case (IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712)
5'd0, 5'd1, 5'd3: entry__h170816 = 64'hFFFFFFFFBFC00380;
5'd2, 5'd4, 5'd5: entry__h170816 = 64'hFFFFFFFFBFC00280;
default: entry__h170816 = 64'hFFFFFFFFBFC00380;
endcase
end
always@(IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712)
begin
case (IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712)
5'd0, 5'd1, 5'd3: entry__h170934 = 64'hFFFFFFFF80000180;
5'd2, 5'd4, 5'd5: entry__h170934 = 64'hFFFFFFFF80000080;
default: entry__h170934 = 64'hFFFFFFFF80000180;
endcase
end
always@(IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733)
begin
case (IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733)
5'd0, 5'd1, 5'd3: entry__h193251 = 64'hFFFFFFFFBFC00380;
5'd2, 5'd4, 5'd5: entry__h193251 = 64'hFFFFFFFFBFC00280;
default: entry__h193251 = 64'hFFFFFFFFBFC00380;
endcase
end
always@(IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733)
begin
case (IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733)
5'd0, 5'd1, 5'd3: entry__h193369 = 64'hFFFFFFFF80000180;
5'd2, 5'd4, 5'd5: entry__h193369 = 64'hFFFFFFFF80000080;
default: entry__h193369 = 64'hFFFFFFFF80000180;
endcase
end
always@(decode_inQ$D_OUT or
IF_NOT_decode_inQ_first__909_BITS_435_TO_434_9_ETC___d7594)
begin
case (decode_inQ$D_OUT[435:434])
2'd0, 2'd1, 2'd2:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7585 = 5'd0;
2'd3:
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7585 =
IF_NOT_decode_inQ_first__909_BITS_435_TO_434_9_ETC___d7594;
endcase
end
always@(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 or
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7585 or
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7586)
begin
case (IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994)
5'd0,
5'd4,
5'd7,
5'd8,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d7595 =
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7585;
5'd1, 5'd9, 5'd10:
IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d7595 =
IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7586;
default: IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d7595 =
5'd0;
endcase
end
always@(IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994 or
IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d7595)
begin
case (IF_decode_inQ_first__909_BITS_435_TO_434_912_E_ETC___d7994)
5'd0,
5'd1,
5'd4,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
x__h243627 =
IF_IF_decode_inQ_first__909_BITS_435_TO_434_91_ETC___d7595;
default: x__h243627 = 5'd0;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd4, 6'd20, 6'd56, 6'd60:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd8;
6'd2, 6'd6, 6'd22, 6'd58, 6'd62:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd10;
6'd3, 6'd7, 6'd23, 6'd59, 6'd63:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd9;
6'd8, 6'd9, 6'd15:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd26;
6'd10:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd21;
6'd11:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd22;
6'd16:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd19;
6'd17:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd17;
6'd18:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd20;
6'd19:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd18;
6'd24, 6'd25, 6'd28, 6'd29:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd12;
6'd26, 6'd27, 6'd30, 6'd31:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd13;
6'd32, 6'd33, 6'd44, 6'd45:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd0;
6'd34, 6'd35, 6'd46, 6'd47:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd1;
6'd36:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd4;
6'd37:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd2;
6'd38:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd3;
6'd39:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd5;
6'd42:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd6;
6'd43:
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 = 5'd7;
default: IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779 =
5'd0;
endcase
end
always@(decode_inQ$D_OUT or
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd15,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q118 =
IF_decode_inQ_first__909_BITS_407_TO_402_170_E_ETC___d8779;
6'd48, 6'd49, 6'd50, 6'd51, 6'd52, 6'd54:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q118 = 5'd1;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q118 =
decode_inQ$D_OUT[379:375];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q119 = 5'd15;
6'd2: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q119 = 5'd14;
6'd4, 6'd5:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q119 = 5'd16;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q119 =
decode_inQ$D_OUT[379:375];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q118 or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q119)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d5798 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q118;
6'd16:
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d5798 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
((decode_inQ$D_OUT[427:423] != 5'd2 &&
decode_inQ$D_OUT[427:423] != 5'd6) ?
5'd26 :
decode_inQ$D_OUT[379:375]) :
decode_inQ$D_OUT[379:375];
6'd28:
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d5798 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q119;
default: IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d5798 =
decode_inQ$D_OUT[379:375];
endcase
end
always@(decode_inQ$D_OUT or theCP0$getCoprocessorEnables)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q120 =
decode_inQ$D_OUT[380];
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q120 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[427:423] != 5'd0 &&
decode_inQ$D_OUT[427:423] != 5'd4 &&
decode_inQ$D_OUT[427:423] != 5'd20 &&
decode_inQ$D_OUT[427:423] != 5'd21 &&
decode_inQ$D_OUT[427:423] != 5'd22 &&
decode_inQ$D_OUT[427:423] != 5'd23 &&
decode_inQ$D_OUT[427:423] != 5'd28 &&
decode_inQ$D_OUT[427:423] != 5'd29 &&
decode_inQ$D_OUT[427:423] != 5'd30 &&
decode_inQ$D_OUT[427:423] != 5'd31 &&
decode_inQ$D_OUT[427:423] != 5'd16 &&
decode_inQ$D_OUT[427:423] != 5'd17 &&
decode_inQ$D_OUT[427:423] != 5'd18 &&
decode_inQ$D_OUT[427:423] != 5'd19 &&
decode_inQ$D_OUT[427:423] != 5'd24 &&
decode_inQ$D_OUT[427:423] != 5'd25 &&
decode_inQ$D_OUT[427:423] != 5'd26 &&
decode_inQ$D_OUT[427:423] != 5'd27 &&
decode_inQ$D_OUT[427:423] != 5'd8 &&
decode_inQ$D_OUT[427:423] != 5'd7 &&
decode_inQ$D_OUT[427:423] != 5'd1 &&
decode_inQ$D_OUT[427:423] != 5'd3 &&
decode_inQ$D_OUT[427:423] != 5'd9 &&
decode_inQ$D_OUT[427:423] != 5'd10 &&
decode_inQ$D_OUT[380] :
decode_inQ$D_OUT[380];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q120 =
decode_inQ$D_OUT[380];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[422:418])
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q121 =
decode_inQ$D_OUT[422:418] == 5'd8 ||
decode_inQ$D_OUT[422:418] == 5'd10;
default: CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q121 =
decode_inQ$D_OUT[380];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd9, 6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q122 =
decode_inQ$D_OUT[380];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q122 =
decode_inQ$D_OUT[433:428] == 6'd10 ||
decode_inQ$D_OUT[380];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q121 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q122)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q123 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
decode_inQ$D_OUT[380] :
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q121;
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q123 =
decode_inQ$D_OUT[380];
6'd8, 6'd9, 6'd10, 6'd11, 6'd12, 6'd13, 6'd14, 6'd15, 6'd24, 6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q123 =
decode_inQ$D_OUT[433:428] == 6'd8 ||
decode_inQ$D_OUT[433:428] == 6'd24 ||
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q122;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q123 =
decode_inQ$D_OUT[380];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd15,
6'd16,
6'd17,
6'd18,
6'd19,
6'd20,
6'd22,
6'd23,
6'd24,
6'd25,
6'd26,
6'd27,
6'd28,
6'd29,
6'd30,
6'd31,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd49,
6'd50,
6'd51,
6'd52,
6'd54,
6'd56,
6'd58,
6'd59,
6'd60,
6'd62,
6'd63:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q124 =
decode_inQ$D_OUT[407:402] == 6'd32 ||
decode_inQ$D_OUT[407:402] == 6'd34 ||
decode_inQ$D_OUT[407:402] == 6'd24 ||
decode_inQ$D_OUT[407:402] == 6'd26 ||
decode_inQ$D_OUT[407:402] == 6'd44 ||
decode_inQ$D_OUT[407:402] == 6'd46 ||
decode_inQ$D_OUT[407:402] == 6'd28 ||
decode_inQ$D_OUT[407:402] == 6'd30 ||
decode_inQ$D_OUT[407:402] == 6'd48 ||
decode_inQ$D_OUT[407:402] == 6'd50 ||
decode_inQ$D_OUT[407:402] == 6'd42;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q124 =
decode_inQ$D_OUT[380];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd0, 6'd1:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q125 =
decode_inQ$D_OUT[407:402] != 6'd1;
6'd4, 6'd5:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q125 =
decode_inQ$D_OUT[407:402] != 6'd5;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q125 =
decode_inQ$D_OUT[380];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q124 or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q125)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q126 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q124;
6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q126 =
decode_inQ$D_OUT[407:402] == 6'd2 ||
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q125;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q126 =
decode_inQ$D_OUT[380];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q120 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q123 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q126)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q127 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q123;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q127 =
decode_inQ$D_OUT[380];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q127 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q126;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q127 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q120;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[422:418])
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q128 = 5'd1;
default: CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q128 =
decode_inQ$D_OUT[379:375];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd8, 6'd9, 6'd15, 6'd24, 6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129 = 5'd0;
6'd10: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129 = 5'd6;
6'd11: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129 = 5'd7;
6'd12: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129 = 5'd4;
6'd13: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129 = 5'd2;
6'd14: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129 = 5'd3;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129 =
decode_inQ$D_OUT[379:375];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q128 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
decode_inQ$D_OUT[379:375] :
CASE_decode_inQD_OUT_BITS_422_TO_418_decode_i_ETC__q128;
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130 =
decode_inQ$D_OUT[379:375];
6'd8, 6'd9, 6'd10, 6'd11, 6'd12, 6'd13, 6'd14, 6'd15, 6'd24, 6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q129;
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd47,
6'd48,
6'd52,
6'd55,
6'd56,
6'd60,
6'd63:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130 = 5'd0;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130 =
decode_inQ$D_OUT[379:375];
endcase
end
always@(decode_inQ$D_OUT or
theCP0$getCoprocessorEnables or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130 or
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d5798)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_IF_decod_ETC__q131 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q130;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_IF_decod_ETC__q131 =
decode_inQ$D_OUT[379:375];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_IF_decod_ETC__q131 =
IF_decode_inQ_first__909_BITS_433_TO_428_918_E_ETC___d5798;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_IF_decod_ETC__q131 =
(decode_inQ$D_OUT[433:428] == 6'd17 ||
decode_inQ$D_OUT[433:428] == 6'd19) ?
((theCP0$getCoprocessorEnables[1] &&
decode_inQ$D_OUT[433:428] == 6'd17 ||
theCP0$getCoprocessorEnables[3] &&
decode_inQ$D_OUT[433:428] == 6'd19) ?
((decode_inQ$D_OUT[427:423] == 5'd0 ||
decode_inQ$D_OUT[427:423] == 5'd1) ?
((decode_inQ$D_OUT[433:428] == 6'd17) ?
5'd23 :
((decode_inQ$D_OUT[433:428] == 6'd19) ?
5'd25 :
decode_inQ$D_OUT[379:375])) :
((decode_inQ$D_OUT[427:423] == 5'd4 ||
decode_inQ$D_OUT[427:423] == 5'd5) ?
5'd26 :
decode_inQ$D_OUT[379:375])) :
decode_inQ$D_OUT[379:375]) :
((decode_inQ$D_OUT[433:428] == 6'd18) ?
((theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
((decode_inQ$D_OUT[427:423] == 5'd0 ||
decode_inQ$D_OUT[427:423] == 5'd4 ||
decode_inQ$D_OUT[427:423] == 5'd20 ||
decode_inQ$D_OUT[427:423] == 5'd21 ||
decode_inQ$D_OUT[427:423] == 5'd22 ||
decode_inQ$D_OUT[427:423] == 5'd23 ||
decode_inQ$D_OUT[427:423] == 5'd28 ||
decode_inQ$D_OUT[427:423] == 5'd29 ||
decode_inQ$D_OUT[427:423] == 5'd30 ||
decode_inQ$D_OUT[427:423] == 5'd31 ||
decode_inQ$D_OUT[427:423] == 5'd16 ||
decode_inQ$D_OUT[427:423] == 5'd17 ||
decode_inQ$D_OUT[427:423] == 5'd18 ||
decode_inQ$D_OUT[427:423] == 5'd19 ||
decode_inQ$D_OUT[427:423] == 5'd24 ||
decode_inQ$D_OUT[427:423] == 5'd25 ||
decode_inQ$D_OUT[427:423] == 5'd26 ||
decode_inQ$D_OUT[427:423] == 5'd27 ||
decode_inQ$D_OUT[427:423] == 5'd8 ||
decode_inQ$D_OUT[427:423] == 5'd7 ||
decode_inQ$D_OUT[427:423] == 5'd1 ||
decode_inQ$D_OUT[427:423] == 5'd3 ||
decode_inQ$D_OUT[427:423] == 5'd9 ||
decode_inQ$D_OUT[427:423] == 5'd10) ?
5'd24 :
decode_inQ$D_OUT[379:375]) :
decode_inQ$D_OUT[379:375]) :
decode_inQ$D_OUT[379:375]);
endcase
end
always@(decode_inQ$D_OUT or theCP0$getCoprocessorEnables)
begin
case (decode_inQ$D_OUT[433:428])
6'd17, 6'd19:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q132 =
(theCP0$getCoprocessorEnables[1] &&
decode_inQ$D_OUT[433:428] == 6'd17 ||
theCP0$getCoprocessorEnables[3] &&
decode_inQ$D_OUT[433:428] == 6'd19) ?
decode_inQ$D_OUT[427:423] == 5'd1 ||
decode_inQ$D_OUT[427:423] == 5'd5 ||
decode_inQ$D_OUT[427:423] != 5'd0 &&
decode_inQ$D_OUT[427:423] != 5'd4 &&
decode_inQ$D_OUT[381] :
decode_inQ$D_OUT[381];
6'd18:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q132 =
(theCP0$getCoprocessorEnables[2] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[427:423] == 5'd0 ||
decode_inQ$D_OUT[427:423] == 5'd4 ||
decode_inQ$D_OUT[427:423] == 5'd20 ||
decode_inQ$D_OUT[427:423] == 5'd21 ||
decode_inQ$D_OUT[427:423] == 5'd22 ||
decode_inQ$D_OUT[427:423] == 5'd23 ||
decode_inQ$D_OUT[427:423] == 5'd28 ||
decode_inQ$D_OUT[427:423] == 5'd29 ||
decode_inQ$D_OUT[427:423] == 5'd30 ||
decode_inQ$D_OUT[427:423] == 5'd31 ||
decode_inQ$D_OUT[427:423] == 5'd16 ||
decode_inQ$D_OUT[427:423] == 5'd17 ||
decode_inQ$D_OUT[427:423] == 5'd18 ||
decode_inQ$D_OUT[427:423] == 5'd19 ||
decode_inQ$D_OUT[427:423] == 5'd24 ||
decode_inQ$D_OUT[427:423] == 5'd25 ||
decode_inQ$D_OUT[427:423] == 5'd26 ||
decode_inQ$D_OUT[427:423] == 5'd27 ||
decode_inQ$D_OUT[427:423] == 5'd8 ||
decode_inQ$D_OUT[427:423] == 5'd7 ||
decode_inQ$D_OUT[427:423] == 5'd1 ||
decode_inQ$D_OUT[427:423] == 5'd3 ||
decode_inQ$D_OUT[427:423] == 5'd9 ||
decode_inQ$D_OUT[427:423] == 5'd10 ||
decode_inQ$D_OUT[381] :
decode_inQ$D_OUT[381];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q132 =
decode_inQ$D_OUT[381];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q133 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
decode_inQ$D_OUT[381] :
decode_inQ$D_OUT[422:418] == 5'd12 ||
decode_inQ$D_OUT[422:418] == 5'd8 ||
decode_inQ$D_OUT[422:418] == 5'd9 ||
decode_inQ$D_OUT[422:418] == 5'd10 ||
decode_inQ$D_OUT[422:418] == 5'd11 ||
decode_inQ$D_OUT[422:418] == 5'd14 ||
decode_inQ$D_OUT[381];
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q133 =
decode_inQ$D_OUT[381];
6'd8, 6'd9, 6'd10, 6'd11, 6'd12, 6'd13, 6'd14, 6'd15, 6'd24, 6'd25:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q133 =
decode_inQ$D_OUT[433:428] == 6'd24 ||
decode_inQ$D_OUT[433:428] == 6'd25 ||
decode_inQ$D_OUT[433:428] == 6'd13 ||
decode_inQ$D_OUT[433:428] == 6'd12 ||
decode_inQ$D_OUT[433:428] == 6'd14 ||
decode_inQ$D_OUT[433:428] == 6'd10 ||
decode_inQ$D_OUT[433:428] == 6'd11;
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q133 =
decode_inQ$D_OUT[433:428] == 6'd32 ||
decode_inQ$D_OUT[433:428] == 6'd33 ||
decode_inQ$D_OUT[433:428] == 6'd35 ||
decode_inQ$D_OUT[433:428] == 6'd34 ||
decode_inQ$D_OUT[433:428] == 6'd38 ||
decode_inQ$D_OUT[433:428] == 6'd48 ||
decode_inQ$D_OUT[433:428] == 6'd40 ||
decode_inQ$D_OUT[433:428] == 6'd41 ||
decode_inQ$D_OUT[433:428] == 6'd43 ||
decode_inQ$D_OUT[433:428] == 6'd42 ||
decode_inQ$D_OUT[433:428] == 6'd46 ||
decode_inQ$D_OUT[433:428] == 6'd55 ||
decode_inQ$D_OUT[433:428] == 6'd26 ||
decode_inQ$D_OUT[433:428] == 6'd27 ||
decode_inQ$D_OUT[433:428] == 6'd52 ||
decode_inQ$D_OUT[433:428] == 6'd63 ||
decode_inQ$D_OUT[433:428] == 6'd44 ||
decode_inQ$D_OUT[433:428] == 6'd45 ||
decode_inQ$D_OUT[433:428] == 6'd36 ||
decode_inQ$D_OUT[433:428] == 6'd37 ||
decode_inQ$D_OUT[433:428] == 6'd39 ||
decode_inQ$D_OUT[433:428] == 6'd56 ||
decode_inQ$D_OUT[433:428] == 6'd60 ||
decode_inQ$D_OUT[433:428] == 6'd47 ||
decode_inQ$D_OUT[381];
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[407:402])
6'd8, 6'd9:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q134 =
decode_inQ$D_OUT[381];
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q134 =
decode_inQ$D_OUT[407:402] == 6'd48 ||
decode_inQ$D_OUT[407:402] == 6'd49 ||
decode_inQ$D_OUT[407:402] == 6'd50 ||
decode_inQ$D_OUT[407:402] == 6'd51 ||
decode_inQ$D_OUT[407:402] == 6'd52 ||
decode_inQ$D_OUT[407:402] == 6'd54 ||
decode_inQ$D_OUT[381];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q134)
begin
case (decode_inQ$D_OUT[407:402])
6'd0,
6'd2,
6'd3,
6'd4,
6'd6,
6'd7,
6'd16,
6'd17,
6'd18,
6'd19,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35:
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q135 =
decode_inQ$D_OUT[407:402] == 6'd16 ||
decode_inQ$D_OUT[407:402] == 6'd18 ||
decode_inQ$D_OUT[407:402] == 6'd17 ||
decode_inQ$D_OUT[407:402] == 6'd19;
default: CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q135 =
decode_inQ$D_OUT[407:402] == 6'd36 ||
decode_inQ$D_OUT[407:402] == 6'd37 ||
decode_inQ$D_OUT[407:402] == 6'd39 ||
decode_inQ$D_OUT[407:402] == 6'd38 ||
decode_inQ$D_OUT[407:402] == 6'd20 ||
decode_inQ$D_OUT[407:402] == 6'd22 ||
decode_inQ$D_OUT[407:402] == 6'd23 ||
decode_inQ$D_OUT[407:402] == 6'd44 ||
decode_inQ$D_OUT[407:402] == 6'd45 ||
decode_inQ$D_OUT[407:402] == 6'd42 ||
decode_inQ$D_OUT[407:402] == 6'd43 ||
decode_inQ$D_OUT[407:402] == 6'd46 ||
decode_inQ$D_OUT[407:402] == 6'd47 ||
decode_inQ$D_OUT[407:402] == 6'd56 ||
decode_inQ$D_OUT[407:402] == 6'd58 ||
decode_inQ$D_OUT[407:402] == 6'd59 ||
decode_inQ$D_OUT[407:402] == 6'd60 ||
decode_inQ$D_OUT[407:402] == 6'd62 ||
decode_inQ$D_OUT[407:402] == 6'd63 ||
decode_inQ$D_OUT[407:402] == 6'd28 ||
decode_inQ$D_OUT[407:402] == 6'd29 ||
decode_inQ$D_OUT[407:402] == 6'd30 ||
decode_inQ$D_OUT[407:402] == 6'd31 ||
decode_inQ$D_OUT[407:402] == 6'd10 ||
decode_inQ$D_OUT[407:402] == 6'd11 ||
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q134;
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q135 or
theCP0$getCoprocessorEnables)
begin
case (decode_inQ$D_OUT[433:428])
6'd0:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q136 =
CASE_decode_inQD_OUT_BITS_407_TO_402_decode_i_ETC__q135;
6'd16:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q136 =
(theCP0$getCoprocessorEnables[0] || decode_inQ$D_OUT[1]) ?
decode_inQ$D_OUT[427:423] == 5'd1 ||
decode_inQ$D_OUT[427:423] == 5'd5 ||
decode_inQ$D_OUT[427:423] != 5'd0 &&
decode_inQ$D_OUT[427:423] != 5'd4 &&
decode_inQ$D_OUT[381] :
decode_inQ$D_OUT[381];
6'd28:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q136 =
decode_inQ$D_OUT[407:402] != 6'd2 &&
decode_inQ$D_OUT[407:402] != 6'd0 &&
decode_inQ$D_OUT[407:402] != 6'd1 &&
decode_inQ$D_OUT[407:402] != 6'd4 &&
decode_inQ$D_OUT[407:402] != 6'd5 &&
decode_inQ$D_OUT[381];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q136 =
decode_inQ$D_OUT[381];
endcase
end
always@(decode_inQ$D_OUT or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q132 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q133 or
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q136)
begin
case (decode_inQ$D_OUT[435:434])
2'd0:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q137 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q133;
2'd1:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q137 =
decode_inQ$D_OUT[381];
2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q137 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q136;
2'd3:
CASE_decode_inQD_OUT_BITS_435_TO_434_CASE_dec_ETC__q137 =
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q132;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[433:428])
6'd1:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q138 =
(decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14) ?
decode_inQ$D_OUT[422:418] != 5'd0 &&
decode_inQ$D_OUT[422:418] != 5'd1 &&
decode_inQ$D_OUT[422:418] != 5'd12 &&
decode_inQ$D_OUT[422:418] != 5'd8 &&
decode_inQ$D_OUT[422:418] != 5'd9 &&
decode_inQ$D_OUT[422:418] != 5'd10 &&
decode_inQ$D_OUT[422:418] != 5'd11 &&
decode_inQ$D_OUT[422:418] != 5'd14 &&
decode_inQ$D_OUT[422:418] != 5'd16 &&
decode_inQ$D_OUT[422:418] != 5'd17 ||
decode_inQ$D_OUT[396] :
decode_inQ$D_OUT[396];
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q138 =
decode_inQ$D_OUT[433:428] == 6'd20 ||
decode_inQ$D_OUT[433:428] == 6'd21 ||
decode_inQ$D_OUT[433:428] == 6'd22 ||
decode_inQ$D_OUT[433:428] == 6'd23 ||
decode_inQ$D_OUT[396];
default: CASE_decode_inQD_OUT_BITS_433_TO_428_decode_i_ETC__q138 =
decode_inQ$D_OUT[396];
endcase
end
always@(theMem_dCache_req_fifo$D_OUT or dataRead___1__h189582)
begin
case (theMem_dCache_req_fifo$D_OUT[68:67])
2'd3:
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q139 =
dataRead___1__h189582;
default: CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q139 =
64'b0;
endcase
end
always@(theMem_dCache_req_fifo$D_OUT or dataRead___1__h189582)
begin
case (theMem_dCache_req_fifo$D_OUT[68:67])
2'd2:
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q140 =
dataRead___1__h189582;
default: CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q140 =
64'b0;
endcase
end
always@(theMem_dCache_req_fifo$D_OUT or dataRead___1__h189582)
begin
case (theMem_dCache_req_fifo$D_OUT[68:67])
2'd1:
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q141 =
dataRead___1__h189582;
default: CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q141 =
64'b0;
endcase
end
always@(theMem_dCache_req_fifo$D_OUT or dataRead___1__h189582)
begin
case (theMem_dCache_req_fifo$D_OUT[68:67])
2'd0:
CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q142 =
dataRead___1__h189582;
default: CASE_theMem_dCache_req_fifoD_OUT_BITS_68_TO_6_ETC__q142 =
64'b0;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029 or
x1_avValue_base__h200801 or
x1_avValue_oType_eaddr__h200800 or x__h213199)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0:
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8029;
3'd1:
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 =
x1_avValue_base__h200801;
3'd2:
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 =
x1_avValue_oType_eaddr__h200800;
3'd4:
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 = 64'd0;
3'd6:
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 =
{ 48'd0, x__h213199 };
default: IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 =
64'h0;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549)
begin
case (execute_inQ$D_OUT[328:327])
2'd0:
IF_execute_inQ_first__341_BITS_328_TO_327_464__ETC___d9046 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547;
2'd1:
IF_execute_inQ_first__341_BITS_328_TO_327_464__ETC___d9046 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548;
2'd2:
IF_execute_inQ_first__341_BITS_328_TO_327_464__ETC___d9046 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549;
2'd3:
IF_execute_inQ_first__341_BITS_328_TO_327_464__ETC___d9046 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044)
begin
case (execute_inQ$D_OUT[328:327])
2'd0:
CASE_execute_inQD_OUT_BITS_328_TO_327_NOT_exe_ETC__q143 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042;
2'd1:
CASE_execute_inQD_OUT_BITS_328_TO_327_NOT_exe_ETC__q143 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043;
2'd2:
CASE_execute_inQD_OUT_BITS_328_TO_327_NOT_exe_ETC__q143 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044;
2'd3:
CASE_execute_inQD_OUT_BITS_328_TO_327_NOT_exe_ETC__q143 =
execute_inQ$D_OUT[328:327] != 2'd3 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8036 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3544)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd1:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q144 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213 &&
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3544;
5'd10:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q144 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8036;
default: CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q144 =
theCapCop_capInsts$D_OUT[99:95] != 5'd9 ||
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8036;
endcase
end
always@(theCapCop_capInsts$D_OUT or
x1_avValue_oType_eaddr__h200800 or
_theResult_____8_fst_oType_eaddr__h207324)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0, 3'd1:
_theResult_____8_fst_oType_eaddr__h207334 =
x1_avValue_oType_eaddr__h200800;
3'd2:
_theResult_____8_fst_oType_eaddr__h207334 =
_theResult_____8_fst_oType_eaddr__h207324;
default: _theResult_____8_fst_oType_eaddr__h207334 =
x1_avValue_oType_eaddr__h200800;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8039 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9049 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9050)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q145 =
!IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9049;
3'd1:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q145 =
!IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9050;
default: CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q145 =
theCapCop_capInsts$D_OUT[20:18] != 3'd2 ||
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8039;
endcase
end
always@(theCapCop_capInsts$D_OUT or
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4606 or
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q145)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q146 =
theCapCop_capInsts$D_OUT[20:18] != 3'd3 &&
theCapCop_capInsts$D_OUT[20:18] != 3'd5;
5'd4:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q146 =
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q145;
default: CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q146 =
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4606;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549)
begin
case (execute_inQ$D_OUT[316:315])
2'd0:
IF_execute_inQ_first__341_BITS_316_TO_315_502__ETC___d9058 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547;
2'd1:
IF_execute_inQ_first__341_BITS_316_TO_315_502__ETC___d9058 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548;
2'd2:
IF_execute_inQ_first__341_BITS_316_TO_315_502__ETC___d9058 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549;
2'd3:
IF_execute_inQ_first__341_BITS_316_TO_315_502__ETC___d9058 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044)
begin
case (execute_inQ$D_OUT[316:315])
2'd0:
CASE_execute_inQD_OUT_BITS_316_TO_315_NOT_exe_ETC__q147 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042;
2'd1:
CASE_execute_inQD_OUT_BITS_316_TO_315_NOT_exe_ETC__q147 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043;
2'd2:
CASE_execute_inQD_OUT_BITS_316_TO_315_NOT_exe_ETC__q147 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044;
2'd3:
CASE_execute_inQD_OUT_BITS_316_TO_315_NOT_exe_ETC__q147 =
execute_inQ$D_OUT[316:315] != 2'd3 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045;
endcase
end
always@(execute_inQ$D_OUT or
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829 or
x1_avValue_fst_opB__h212082)
begin
case (execute_inQ$D_OUT[14:13])
2'd0:
x__h213427 =
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829;
2'd1: x__h213427 = x1_avValue_fst_opB__h212082;
default: x__h213427 =
IF_execute_inQ_first__341_BIT_318_501_THEN_IF__ETC___d7829;
endcase
end
always@(theCapCop_capInsts$D_OUT or
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8034 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3544)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd1:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q150 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8213 &&
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3544;
5'd10:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q150 =
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8034;
default: CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_NO_ETC__q150 =
theCapCop_capInsts$D_OUT[99:95] != 5'd9 ||
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8034;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 or
theCapCop_pcc or
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027 or
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7776)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q151 =
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812;
5'd1,
5'd4,
5'd8,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q151 = 64'b0;
5'd7:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q151 =
theCapCop_pcc[127:64] +
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[63:0];
5'd9, 5'd10:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q151 =
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7776;
default: CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q151 =
64'h0;
endcase
end
always@(theCapCop_capInsts$D_OUT or
x1_avValue_oType_eaddr__h200800 or
_theResult_____8_fst_oType_eaddr__h203894)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0, 3'd1:
_theResult_____8_fst_oType_eaddr__h203904 =
x1_avValue_oType_eaddr__h200800;
3'd2:
_theResult_____8_fst_oType_eaddr__h203904 =
_theResult_____8_fst_oType_eaddr__h203894;
default: _theResult_____8_fst_oType_eaddr__h203904 =
x1_avValue_oType_eaddr__h200800;
endcase
end
always@(theCapCop_capInsts$D_OUT or
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8038 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9061 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9062)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q152 =
!IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9061;
3'd1:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q152 =
!IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9062;
default: CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q152 =
theCapCop_capInsts$D_OUT[20:18] != 3'd2 ||
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8038;
endcase
end
always@(theCapCop_capInsts$D_OUT or
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4587 or
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q152)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q153 =
theCapCop_capInsts$D_OUT[20:18] != 3'd3 &&
theCapCop_capInsts$D_OUT[20:18] != 3'd5;
5'd4:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q153 =
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_NO_ETC__q152;
default: CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_th_ETC__q153 =
theCapCop_capInsts_first__372_BITS_99_TO_95_37_ETC___d4587;
endcase
end
always@(execute_inQ$D_OUT or
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d8820)
begin
case (execute_inQ$D_OUT[379:375])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd12,
5'd13,
5'd14,
5'd15,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20:
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 =
execute_inQ$D_OUT[383:382];
5'd21, 5'd22:
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 =
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d8820 ?
2'd0 :
2'd3;
5'd23, 5'd25:
IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 = 2'd3;
default: IF_execute_inQ_first__341_BITS_379_TO_375_342__ETC___d7992 =
execute_inQ$D_OUT[383:382];
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042)
begin
case (execute_inQ$D_OUT[14:13])
2'd0:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q154 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q154 =
execute_inQ$D_OUT[437:436] == 2'd0 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042;
default: CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q154 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9042;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043)
begin
case (execute_inQ$D_OUT[14:13])
2'd0:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q155 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q155 =
execute_inQ$D_OUT[437:436] == 2'd1 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043;
default: CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q155 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9043;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044)
begin
case (execute_inQ$D_OUT[14:13])
2'd0:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q156 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q156 =
execute_inQ$D_OUT[437:436] == 2'd2 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044;
default: CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q156 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9044;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045)
begin
case (execute_inQ$D_OUT[14:13])
2'd0:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q157 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q157 =
execute_inQ$D_OUT[437:436] == 2'd3 ||
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045;
default: CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q157 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d9045;
endcase
end
always@(execute_inQ$D_OUT or
signedA__h217100 or
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8138 or
SEXT_IF_execute_inQ_first__341_BIT_330_463_THE_ETC___d8040)
begin
case (execute_inQ$D_OUT[400:397])
4'd0:
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 =
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8138;
4'd2:
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 =
!SEXT_IF_execute_inQ_first__341_BIT_330_463_THE_ETC___d8040;
4'd3:
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 =
SEXT_IF_execute_inQ_first__341_BIT_330_463_THE_ETC___d8040;
4'd4:
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 =
signedA__h217100[64];
4'd5:
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 =
!IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d8138;
default: IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d8818 =
!signedA__h217100[64];
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812 or
theCapCop_pcc or
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 or
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7779)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q158 =
IF_theCapCop_capInsts_first__372_BITS_20_TO_18_ETC___d8812;
5'd1,
5'd4,
5'd8,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q158 = 64'b0;
5'd7:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q158 =
theCapCop_pcc[127:64] +
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828;
5'd9, 5'd10:
CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q158 =
IF_theCapCop_capInsts_first__372_BITS_4_TO_0_4_ETC___d7779;
default: CASE_theCapCop_capInstsD_OUT_BITS_99_TO_95_0x_ETC__q158 =
64'h0;
endcase
end
always@(execute_inQ$D_OUT or
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 or
x__h231731 or
_theResult_____4_snd_snd__h222026 or
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7898 or
calcResult__h221346 or
calcResult__h221354 or
signedA__h217100 or
signedB__h217989 or
_theResult_____7__h200324 or
_theResult_____6__h200326 or
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d3754 or
calcResult___1__h223707 or
spliced_bits__h228898 or
_theResult_____4_snd__h223554 or
calcResult__h221414 or
calcResult__h221422 or
_theResult_____4_snd__h222754 or calcResult__h231541)
begin
case (execute_inQ$D_OUT[379:375])
5'd0, 5'd1: calcResult__h221868 = _theResult_____4_snd_snd__h222026;
5'd2, 5'd5:
calcResult__h221868 =
{ execute_inQ$D_OUT[379:375] == 5'd5,
(execute_inQ$D_OUT[379:375] == 5'd5) ?
~IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7898 :
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7898 };
5'd3: calcResult__h221868 = calcResult__h221346;
5'd4: calcResult__h221868 = calcResult__h221354;
5'd6:
calcResult__h221868 =
((signedA__h217100 ^ 65'h10000000000000000) <
(signedB__h217989 ^ 65'h10000000000000000)) ?
65'd1 :
65'd0;
5'd7:
calcResult__h221868 =
(_theResult_____7__h200324 < _theResult_____6__h200326) ?
65'd1 :
65'd0;
5'd8:
calcResult__h221868 =
IF_execute_inQ_first__341_BIT_381_709_THEN_IF__ETC___d3754;
5'd9:
calcResult__h221868 =
execute_inQ$D_OUT[381] ?
calcResult___1__h223707 :
{ 33'h0AAAAAAAA, spliced_bits__h228898 };
5'd10: calcResult__h221868 = _theResult_____4_snd__h223554;
5'd12, 5'd13, 5'd14, 5'd15, 5'd16, 5'd17, 5'd18:
calcResult__h221868 = _theResult_____7__h200324;
5'd19: calcResult__h221868 = calcResult__h221414;
5'd20: calcResult__h221868 = calcResult__h221422;
5'd21, 5'd22: calcResult__h221868 = _theResult_____4_snd__h222754;
5'd24: calcResult__h221868 = calcResult__h231541;
default: calcResult__h221868 =
{ 1'b0,
(execute_inQ$D_OUT[379:375] == 5'd26) ?
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828 :
x__h231731 };
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549)
begin
case (execute_inQ$D_OUT[304:303])
2'd0:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547;
2'd1:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548;
2'd2:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549;
2'd3:
IF_execute_inQ_first__341_BITS_304_TO_303_492__ETC___d7593 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550;
endcase
end
always@(execute_inQ$D_OUT or
IF_execute_inQ_first__341_BIT_380_712_THEN_IF__ETC___d4487)
begin
case (execute_inQ$D_OUT[379:375])
5'd0, 5'd1:
CASE_execute_inQD_OUT_BITS_379_TO_375_execute_ETC__q161 =
IF_execute_inQ_first__341_BIT_380_712_THEN_IF__ETC___d4487;
default: CASE_execute_inQD_OUT_BITS_379_TO_375_execute_ETC__q161 =
execute_inQ$D_OUT[371:367];
endcase
end
always@(execute_inQ$D_OUT)
begin
case (execute_inQ$D_OUT[379:375])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd19,
5'd20,
5'd23,
5'd25:
CASE_execute_inQD_OUT_BITS_379_TO_375_NOT_exe_ETC__q162 =
execute_inQ$D_OUT[380];
default: CASE_execute_inQD_OUT_BITS_379_TO_375_NOT_exe_ETC__q162 =
execute_inQ$D_OUT[379:375] != 5'd12 &&
execute_inQ$D_OUT[379:375] != 5'd13 &&
execute_inQ$D_OUT[379:375] != 5'd14 &&
execute_inQ$D_OUT[379:375] != 5'd15 &&
execute_inQ$D_OUT[379:375] != 5'd16 &&
execute_inQ$D_OUT[379:375] != 5'd17 &&
execute_inQ$D_OUT[379:375] != 5'd18 &&
execute_inQ$D_OUT[380];
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054 or
theCapCop_pcc)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9055 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054;
5'd7:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9055 =
theCapCop_pcc[254:0];
default: IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d9055 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031 or
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0, 3'd1, 3'd2:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q163 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031;
3'd6:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q163 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031 &
_0b0_CONCAT_IF_execute_inQ_first__341_BIT_330_4_ETC___d8027[14:0];
default: CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q163 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3672 or
IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3676)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q164 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3672;
3'd1:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q164 =
IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3676;
default: CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q164 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054 or
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q163 or
x1_avValue_reserved__h200799 or
_theResult_____8_fst_oType_eaddr__h203904 or
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q164 or
theCapCop_pcc)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3681 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054;
5'd4:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3681 =
{ CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q163,
x1_avValue_reserved__h200799,
_theResult_____8_fst_oType_eaddr__h203904,
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q164 };
5'd7:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3681 =
theCapCop_pcc[254:0];
default: IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3681 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031 or
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0, 3'd1, 3'd2:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q165 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031;
3'd6:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q165 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031 &
IF_execute_inQ_first__341_BIT_330_463_THEN_IF__ETC___d7828[14:0];
default: CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q165 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d8031;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052 or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3639 or
IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3645)
begin
case (theCapCop_capInsts$D_OUT[20:18])
3'd0:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q166 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d3639;
3'd1:
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q166 =
IF_IF_theCapCop_capInsts_first__372_BITS_9_TO__ETC___d3645;
default: CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q166 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9052;
endcase
end
always@(theCapCop_capInsts$D_OUT or
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054 or
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q165 or
x1_avValue_reserved__h200799 or
_theResult_____8_fst_oType_eaddr__h207334 or
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q166 or
theCapCop_pcc)
begin
case (theCapCop_capInsts$D_OUT[99:95])
5'd0,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd27,
5'd28,
5'd29,
5'd30,
5'd31:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3656 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054;
5'd4:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3656 =
{ CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q165,
x1_avValue_reserved__h200799,
_theResult_____8_fst_oType_eaddr__h207334,
CASE_theCapCop_capInstsD_OUT_BITS_20_TO_18_IF_ETC__q166 };
5'd7:
IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3656 =
theCapCop_pcc[254:0];
default: IF_theCapCop_capInsts_first__372_BITS_99_TO_95_ETC___d3656 =
IF_theCapCop_capInsts_first__372_BITS_9_TO_5_4_ETC___d9054;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548 or
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4788 or
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4786)
begin
case (execute_inQ$D_OUT[14:13])
2'd0, 2'd2:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q167 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7548;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q167 =
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4788;
2'd3:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q167 =
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4786;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547 or
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4742 or
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4740)
begin
case (execute_inQ$D_OUT[14:13])
2'd0, 2'd2:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q168 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7547;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q168 =
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4742;
2'd3:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q168 =
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4740;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549 or
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4834 or
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4832)
begin
case (execute_inQ$D_OUT[14:13])
2'd0, 2'd2:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q169 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7549;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q169 =
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4834;
2'd3:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q169 =
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4832;
endcase
end
always@(execute_inQ$D_OUT or
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550 or
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4880 or
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4878)
begin
case (execute_inQ$D_OUT[14:13])
2'd0, 2'd2:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q170 =
IF_writeback_destRenamed_i_notEmpty__253_THEN__ETC___d7550;
2'd1:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q170 =
IF_execute_inQ_first__341_BITS_374_TO_372_360__ETC___d4880;
2'd3:
CASE_execute_inQD_OUT_BITS_14_TO_13_IF_writeb_ETC__q170 =
IF_execute_inQ_first__341_BITS_400_TO_397_692__ETC___d4878;
endcase
end
always@(theDebug_instQ$D_OUT)
begin
case (theDebug_instQ$D_OUT[31:26])
6'd0, 6'd16, 6'd28:
CASE_theDebug_instQD_OUT_BITS_31_TO_26_3_0_2__ETC__q171 = 2'd2;
default: CASE_theDebug_instQD_OUT_BITS_31_TO_26_3_0_2__ETC__q171 = 2'd3;
endcase
end
always@(execute_pendingOps$D_OUT)
begin
case (execute_pendingOps$D_OUT[435:434])
2'd0, 2'd1, 2'd2:
CASE_execute_pendingOpsD_OUT_BITS_435_TO_434__ETC__q172 =
execute_pendingOps$D_OUT[435:434];
2'd3: CASE_execute_pendingOpsD_OUT_BITS_435_TO_434__ETC__q172 = 2'd3;
endcase
end
always@(theDebug_debugConvert$messages_request_get)
begin
case (theDebug_debugConvert$messages_request_get[271:264])
8'd0,
8'd48,
8'd49,
8'd50,
8'd51,
8'd67,
8'd77,
8'd83,
8'd97,
8'd98,
8'd99,
8'd100,
8'd101,
8'd105,
8'd112,
8'd114,
8'd115,
8'd116,
8'd117,
8'd176,
8'd177,
8'd178,
8'd179,
8'd195,
8'd197,
8'd205,
8'd211,
8'd225,
8'd226,
8'd227,
8'd228,
8'd229,
8'd233,
8'd240,
8'd242,
8'd243,
8'd244,
8'd245,
8'd255:
CASE_theDebug_debugConvertmessages_request_ge_ETC__q173 =
theDebug_debugConvert$messages_request_get[271:264];
default: CASE_theDebug_debugConvertmessages_request_ge_ETC__q173 =
8'd32;
endcase
end
always@(IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666)
begin
case (IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666)
6'd0: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd0;
6'd1: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd105;
6'd2: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd97;
6'd3: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd98;
6'd4: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd48;
6'd5: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd49;
6'd6: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd50;
6'd7: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd51;
6'd8: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd67;
6'd9: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd77;
6'd10:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd101;
6'd11:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd100;
6'd12:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd112;
6'd13:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd114;
6'd14:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd115;
6'd15: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd99;
6'd16:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd117;
6'd17:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd116;
6'd18: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd83;
6'd19:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd233;
6'd20:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd225;
6'd21:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd226;
6'd22:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd176;
6'd23:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd177;
6'd24:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd178;
6'd25:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd179;
6'd26:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd195;
6'd27:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd205;
6'd28:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd229;
6'd29:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd197;
6'd30:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd228;
6'd31:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd240;
6'd32:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd242;
6'd33:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd243;
6'd34:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd244;
6'd35:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd227;
6'd36:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd245;
6'd37:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd211;
6'd38:
CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 = 8'd255;
default: CASE_IF_theDebug_curCommand_first__06_BITS_271_ETC__q174 =
8'd32;
endcase
end
always@(theDebug_trace_buf_bram$DOB)
begin
case (theDebug_trace_buf_bram$DOB[250:246])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
CASE_theDebug_trace_buf_bramDOB_BITS_250_TO_2_ETC__q175 =
theDebug_trace_buf_bram$DOB[250:246];
default: CASE_theDebug_trace_buf_bramDOB_BITS_250_TO_2_ETC__q175 =
5'd31;
endcase
end
always@(theDebug_bpReport$D_OUT)
begin
case (theDebug_bpReport$D_OUT[271:264])
8'd0,
8'd48,
8'd49,
8'd50,
8'd51,
8'd67,
8'd77,
8'd83,
8'd97,
8'd98,
8'd99,
8'd100,
8'd101,
8'd105,
8'd112,
8'd114,
8'd115,
8'd116,
8'd117,
8'd176,
8'd177,
8'd178,
8'd179,
8'd195,
8'd197,
8'd205,
8'd211,
8'd225,
8'd226,
8'd227,
8'd228,
8'd229,
8'd233,
8'd240,
8'd242,
8'd243,
8'd244,
8'd245,
8'd255:
CASE_theDebug_bpReportD_OUT_BITS_271_TO_264_3_ETC__q176 =
theDebug_bpReport$D_OUT[271:264];
default: CASE_theDebug_bpReportD_OUT_BITS_271_TO_264_3_ETC__q176 =
8'd32;
endcase
end
always@(theDebug_writebacks$D_OUT or
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666)
begin
case (theDebug_writebacks$D_OUT[4:0])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_IF__ETC__q177 = 6'd29;
default: CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_IF__ETC__q177 =
IF_theDebug_curCommand_first__06_BITS_271_TO_2_ETC___d8666;
endcase
end
always@(CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_IF__ETC__q177)
begin
case (CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_IF__ETC__q177)
6'd0: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd0;
6'd1: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd105;
6'd2: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd97;
6'd3: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd98;
6'd4: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd48;
6'd5: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd49;
6'd6: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd50;
6'd7: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd51;
6'd8: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd67;
6'd9: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd77;
6'd10:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd101;
6'd11:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd100;
6'd12:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd112;
6'd13:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd114;
6'd14:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd115;
6'd15: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd99;
6'd16:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd117;
6'd17:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd116;
6'd18: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd83;
6'd19:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd233;
6'd20:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd225;
6'd21:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd226;
6'd22:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd176;
6'd23:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd177;
6'd24:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd178;
6'd25:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd179;
6'd26:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd195;
6'd27:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd205;
6'd28:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd229;
6'd29:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd197;
6'd30:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd228;
6'd31:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd240;
6'd32:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd242;
6'd33:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd243;
6'd34:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd244;
6'd35:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd227;
6'd36:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd245;
6'd37:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd211;
6'd38:
CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 = 8'd255;
default: CASE_CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_ETC__q178 =
8'd32;
endcase
end
always@(theDebug_writebacks$D_OUT)
begin
case (theDebug_writebacks$D_OUT[4:0])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd12,
5'd13,
5'd15,
5'd18,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26,
5'd30:
CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_0x0_ETC__q179 = 8'h01;
default: CASE_theDebug_writebacksD_OUT_BITS_4_TO_0_0x0_ETC__q179 = 8'h0;
endcase
end
always@(IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712)
begin
case (IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712)
5'd0, 5'd1, 5'd23:
CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 =
IF_IF_IF_memAccessToWriteback_first__516_BITS__ETC___d8712;
5'd2, 5'd3, 5'd4, 5'd6:
CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd2;
5'd5, 5'd7:
CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd3;
5'd8, 5'd9:
CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd4;
5'd10: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd5;
5'd11: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd6;
5'd12: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd7;
5'd13: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd8;
5'd14: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd9;
5'd15: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd10;
5'd16, 5'd17, 5'd18, 5'd19:
CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd11;
5'd20: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd12;
5'd21: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd13;
5'd22: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 = 5'd18;
default: CASE_IF_IF_IF_memAccessToWriteback_first__516__ETC__q180 =
5'd31;
endcase
end
always@(IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733)
begin
case (IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733)
5'd0, 5'd1, 5'd23:
CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 =
IF_IF_IF_NOT_theCP0_tlbLookupData_response_get_ETC___d8733;
5'd2, 5'd3, 5'd4, 5'd6:
CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd2;
5'd5, 5'd7:
CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd3;
5'd8, 5'd9:
CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd4;
5'd10: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd5;
5'd11: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd6;
5'd12: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd7;
5'd13: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd8;
5'd14: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd9;
5'd15: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd10;
5'd16, 5'd17, 5'd18, 5'd19:
CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd11;
5'd20: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd12;
5'd21: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd13;
5'd22: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 = 5'd18;
default: CASE_IF_IF_IF_NOT_theCP0_tlbLookupData_respons_ETC__q181 =
5'd31;
endcase
end
always@(v__h277714)
begin
case (v__h277714)
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
y_avValue_snd_snd_fst__h282717 = 5'd0;
default: y_avValue_snd_snd_fst__h282717 =
(v__h277714 != 5'd0 && v__h277714 != 5'd1 &&
v__h277714 != 5'd2 &&
v__h277714 != 5'd3) ?
5'd31 :
5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 or
v__h277714)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764)
5'd0, 5'd1, 5'd2: y_avValue_snd_snd_snd_fst__h282782 = v__h277714;
default: y_avValue_snd_snd_snd_fst__h282782 = 5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 or
v__h277714)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764)
5'd0, 5'd1: _theResult_____7_snd_fst__h282877 = v__h277714;
default: _theResult_____7_snd_fst__h282877 = 5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 or
v__h277714)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764)
5'd0, 5'd16, 5'd17, 5'd18, 5'd19, 5'd20, 5'd21, 5'd22, 5'd23:
_theResult_____7_snd_fst__h282960 = v__h277714;
5'd4: _theResult_____7_snd_fst__h282960 = 5'd0;
default: _theResult_____7_snd_fst__h282960 = 5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 or
fetchedControlToken$D_OUT or _theResult___fst_coProSelect__h281892)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764)
5'd0, 5'd4:
_theResult___fst_coProSelect__h281974 =
_theResult___fst_coProSelect__h281892;
default: _theResult___fst_coProSelect__h281974 =
fetchedControlToken$D_OUT[386:384];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
y_avValue_snd_snd_fst__h282717 or v__h277714)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd1:
y_avValue_snd_snd_snd_fst__h282686 = y_avValue_snd_snd_fst__h282717;
6'd4,
6'd5,
6'd6,
6'd7,
6'd20,
6'd21,
6'd22,
6'd23,
6'd40,
6'd41,
6'd42,
6'd43,
6'd44,
6'd45,
6'd46,
6'd61,
6'd62,
6'd63:
y_avValue_snd_snd_snd_fst__h282686 = 5'd0;
6'd8,
6'd9,
6'd10,
6'd11,
6'd12,
6'd13,
6'd14,
6'd15,
6'd24,
6'd25,
6'd26,
6'd27,
6'd32,
6'd33,
6'd34,
6'd35,
6'd36,
6'd37,
6'd38,
6'd39,
6'd48,
6'd49,
6'd50,
6'd52,
6'd53,
6'd54,
6'd55,
6'd56,
6'd60:
y_avValue_snd_snd_snd_fst__h282686 = v__h277714;
default: y_avValue_snd_snd_snd_fst__h282686 = 5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd2: _theResult_____7_snd_snd_snd_fst__h282775 = 5'd0;
6'd3, 6'd29: _theResult_____7_snd_snd_snd_fst__h282775 = 5'd31;
default: _theResult_____7_snd_snd_snd_fst__h282775 = 5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
_theResult_____7_snd_fst__h282877 or
_theResult_____7_snd_fst__h282960)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
y_avValue_snd_snd_snd_fst__h282691 =
_theResult_____7_snd_fst__h282877;
6'd18:
y_avValue_snd_snd_snd_fst__h282691 =
_theResult_____7_snd_fst__h282960;
default: y_avValue_snd_snd_snd_fst__h282691 = 5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
v__h278907 or reqA__h280962)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
y_avValue_snd_snd_snd_snd_snd_snd_snd_fst__h285803 = v__h278907;
6'd18:
y_avValue_snd_snd_snd_snd_snd_snd_snd_fst__h285803 = reqA__h280962;
default: y_avValue_snd_snd_snd_snd_snd_snd_snd_fst__h285803 = 5'b0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
reqA__h280962 or v__h277714)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_fst__h285990 =
reqA__h280962;
6'd18:
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_fst__h285990 = v__h277714;
default: y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_fst__h285990 = 5'b0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or _theResult___fst_coProSelect__h281974)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
_theResult_____7_fst_coProSelect__h282015 =
fetchedControlToken$D_OUT[386:384];
6'd18:
_theResult_____7_fst_coProSelect__h282015 =
_theResult___fst_coProSelect__h281974;
default: _theResult_____7_fst_coProSelect__h282015 =
fetchedControlToken$D_OUT[386:384];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd0, 6'd28:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q182 =
fetchedControlToken$D_OUT[383:382];
6'd16:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q182 =
(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd0 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd1 ||
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 ==
5'd2) ?
fetchedControlToken$D_OUT[383:382] :
2'd1;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q182 =
fetchedControlToken$D_OUT[383:382];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd2, 6'd3, 6'd29:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q183 =
fetchedControlToken$D_OUT[1] ?
fetchedControlToken$D_OUT[400:397] :
4'd6;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q183 =
fetchedControlToken$D_OUT[400:397];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd0, 6'd28:
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd__h286178 = 3'b0;
6'd16:
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd__h286178 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770[2:0];
default: y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_snd__h286178 =
3'b0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
y_avValue_snd_snd_snd_fst__h282779 or
y_avValue_snd_snd_snd_fst__h282782 or v__h278907)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd0:
y_avValue_snd_snd_snd_fst__h282689 =
y_avValue_snd_snd_snd_fst__h282779;
6'd16:
y_avValue_snd_snd_snd_fst__h282689 =
y_avValue_snd_snd_snd_fst__h282782;
6'd28: y_avValue_snd_snd_snd_fst__h282689 = v__h278907;
default: y_avValue_snd_snd_snd_fst__h282689 = 5'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 or
_theResult___snd__h280672 or v__h278907)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764)
5'd0, 5'd1, 5'd2, 5'd4, 5'd5, 5'd6:
y_avValue_snd_snd_snd_snd_fst__h286189 = v__h278907;
default: y_avValue_snd_snd_snd_snd_fst__h286189 =
_theResult___snd__h280672;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
v__h278907 or y_avValue_snd_snd_snd_snd_fst__h286189)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd0, 6'd28:
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst__h286177 =
v__h278907;
6'd16:
y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst__h286177 =
y_avValue_snd_snd_snd_snd_fst__h286189;
default: y_avValue_snd_snd_snd_snd_snd_snd_snd_snd_snd_fst__h286177 =
v__h278907;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764 or
fetchedControlToken$D_OUT or
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8764)
5'd0, 5'd1, 5'd2, 5'd4, 5'd5, 5'd6:
x1_avValue_fst_coProSelect__h280726 =
IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770[2:0];
default: x1_avValue_fst_coProSelect__h280726 =
fetchedControlToken$D_OUT[386:384];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or x1_avValue_fst_coProSelect__h280726)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd0, 6'd28:
x1_avValue_snd_snd_fst_coProSelect__h280767 =
fetchedControlToken$D_OUT[386:384];
6'd16:
x1_avValue_snd_snd_fst_coProSelect__h280767 =
x1_avValue_fst_coProSelect__h280726;
default: x1_avValue_snd_snd_fst_coProSelect__h280767 =
fetchedControlToken$D_OUT[386:384];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8770)
6'd8, 6'd9:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q184 = 2'd3;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q184 =
2'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd2, 6'd3, 6'd29:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q185 =
fetchedControlToken$D_OUT[1] ? 2'd0 : 2'd2;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q185 =
2'd0;
endcase
end
always@(v__h277714)
begin
case (v__h277714)
5'd8, 5'd9, 5'd10, 5'd11, 5'd12, 5'd14:
CASE_v77714_1_8_0_9_0_10_0_11_0_12_0_14_0__q186 = 2'd0;
default: CASE_v77714_1_8_0_9_0_10_0_11_0_12_0_14_0__q186 = 2'd1;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
CASE_v77714_1_8_0_9_0_10_0_11_0_12_0_14_0__q186)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd1:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q187 =
CASE_v77714_1_8_0_9_0_10_0_11_0_12_0_14_0__q186;
6'd4, 6'd5, 6'd6, 6'd7, 6'd20, 6'd21, 6'd22, 6'd23:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q187 = 2'd1;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q187 =
2'd0;
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8851)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q188 =
fetchedControlToken$D_OUT[341];
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q188 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8851;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q188 =
fetchedControlToken$D_OUT[341];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8849)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q189 =
fetchedControlToken$D_OUT[342];
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q189 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8849;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q189 =
fetchedControlToken$D_OUT[342];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8851 or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8852)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q190 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8851;
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q190 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8852;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q190 =
fetchedControlToken$D_OUT[365];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8852 or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8846)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q191 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8852;
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q191 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8846;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q191 =
fetchedControlToken$D_OUT[353];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8849 or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8850)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q192 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8849;
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q192 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8850;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q192 =
fetchedControlToken$D_OUT[366];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8850 or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8845)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q193 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8850;
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q193 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8845;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q193 =
fetchedControlToken$D_OUT[354];
endcase
end
always@(IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 or
regRenameTable)
begin
case (IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769)
2'd0:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 =
regRenameTable[10];
2'd1:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 =
regRenameTable[22];
2'd2:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 =
regRenameTable[34];
2'd3:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8861 =
regRenameTable[46];
endcase
end
always@(IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769 or
regRenameTable)
begin
case (IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d8769)
2'd0:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 =
regRenameTable[9:8];
2'd1:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 =
regRenameTable[21:20];
2'd2:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 =
regRenameTable[33:32];
2'd3:
IF_IF_regRenameTable_953_BIT_47_954_AND_regRen_ETC___d8862 =
regRenameTable[45:44];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9212)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q194 =
fetchedControlToken$D_OUT[342:331];
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q194 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9212;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q194 =
fetchedControlToken$D_OUT[342:331];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9210 or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9214)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q195 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9210;
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q195 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9214;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q195 =
fetchedControlToken$D_OUT[354:343];
endcase
end
always@(IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761 or
fetchedControlToken$D_OUT or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9212 or
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9210)
begin
case (IF_fetchedControlToken_first__662_BIT_1_663_TH_ETC___d8761)
6'd17, 6'd19:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q196 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9212;
6'd18:
CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q196 =
IF_regRenameTable_953_BIT_47_954_AND_regRename_ETC___d9210;
default: CASE_IF_fetchedControlToken_first__662_BIT_1_6_ETC__q196 =
fetchedControlToken$D_OUT[366:355];
endcase
end
always@(memAccess_inQ$D_OUT)
begin
case (memAccess_inQ$D_OUT[12:9])
4'd1:
CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197 =
memAccess_inQ$D_OUT[232:230] == 3'd0;
4'd4:
CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197 =
memAccess_inQ$D_OUT[231:230] == 2'b0;
default: CASE_memAccess_inQD_OUT_BITS_12_TO_9_NOT_memA_ETC__q197 =
memAccess_inQ$D_OUT[12:9] != 4'd7 ||
!memAccess_inQ$D_OUT[230];
endcase
end
always@(theMem_dataSize$D_OUT or
temp__h174691 or temp__h174677 or temp__h174681)
begin
case (theMem_dataSize$D_OUT)
4'd1:
CASE_theMem_dataSizeD_OUT_temp74691_1_temp746_ETC__q198 =
temp__h174677;
4'd2:
CASE_theMem_dataSizeD_OUT_temp74691_1_temp746_ETC__q198 =
temp__h174681;
default: CASE_theMem_dataSizeD_OUT_temp74691_1_temp746_ETC__q198 =
temp__h174691;
endcase
end
always@(theMem_dataSize$D_OUT or
x__h178683 or y__h178684 or temp__h174650 or temp__h174654)
begin
case (theMem_dataSize$D_OUT)
4'd4:
IF_theMem_dataSize_first__825_EQ_4_853_THEN_IF_ETC___d7551 =
temp__h174650;
4'd5:
IF_theMem_dataSize_first__825_EQ_4_853_THEN_IF_ETC___d7551 =
temp__h174654;
default: IF_theMem_dataSize_first__825_EQ_4_853_THEN_IF_ETC___d7551 =
x__h178683 | y__h178684;
endcase
end
always@(IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721)
begin
case (IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721)
5'd0, 5'd1, 5'd3: entry__h175335 = 64'hFFFFFFFFBFC00380;
5'd2, 5'd4, 5'd5: entry__h175335 = 64'hFFFFFFFFBFC00280;
default: entry__h175335 = 64'hFFFFFFFFBFC00380;
endcase
end
always@(IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721)
begin
case (IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721)
5'd0, 5'd1, 5'd3: entry__h175453 = 64'hFFFFFFFF80000180;
5'd2, 5'd4, 5'd5: entry__h175453 = 64'hFFFFFFFF80000080;
default: entry__h175453 = 64'hFFFFFFFF80000180;
endcase
end
always@(IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721)
begin
case (IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721)
5'd0, 5'd1, 5'd23:
CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 =
IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_i_no_ETC___d8721;
5'd2, 5'd3, 5'd4, 5'd6:
CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd2;
5'd5, 5'd7:
CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd3;
5'd8, 5'd9:
CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd4;
5'd10: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd5;
5'd11: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd6;
5'd12: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd7;
5'd13: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd8;
5'd14: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd9;
5'd15: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd10;
5'd16, 5'd17, 5'd18, 5'd19:
CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd11;
5'd20: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd12;
5'd21: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd13;
5'd22: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 = 5'd18;
default: CASE_IF_IF_IF_NOT_IF_theMem_dCache_out_fifo_ff_ETC__q201 =
5'd31;
endcase
end
always@(decode_inQ$D_OUT)
begin
case (decode_inQ$D_OUT[435:434])
2'd0, 2'd1, 2'd2:
CASE_decode_inQD_OUT_BITS_435_TO_434_3_0_deco_ETC__q202 =
decode_inQ$D_OUT[435:434];
2'd3: CASE_decode_inQD_OUT_BITS_435_TO_434_3_0_deco_ETC__q202 = 2'd3;
endcase
end
always@(memAccess_inQ$D_OUT)
begin
case (memAccess_inQ$D_OUT[14:13])
2'd0: CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q203 = 3'd3;
2'd1: CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q203 = 3'd4;
default: CASE_memAccess_inQD_OUT_BITS_14_TO_13_memAcce_ETC__q203 =
memAccess_inQ$D_OUT[6:4];
endcase
end
always@(memAccess_inQ$D_OUT or
req_byteWrite__h140080 or req_byteWrite__h144298)
begin
case (memAccess_inQ$D_OUT[14:13])
2'd0:
CASE_memAccess_inQD_OUT_BITS_14_TO_13_0x0_0_r_ETC__q204 =
req_byteWrite__h140080;
2'd1:
CASE_memAccess_inQD_OUT_BITS_14_TO_13_0x0_0_r_ETC__q204 =
req_byteWrite__h144298;
default: CASE_memAccess_inQD_OUT_BITS_14_TO_13_0x0_0_r_ETC__q204 = 8'h0;
endcase
end
// handling of inlined registers
always@(posedge csi_c0_clk)
begin
if (!csi_c0_reset_n)
begin
execute_hi <= `BSV_ASSIGNMENT_DELAY 64'b0;
execute_lo <= `BSV_ASSIGNMENT_DELAY 64'b0;
execute_loadsDone <= `BSV_ASSIGNMENT_DELAY 4'd0;
execute_loadsIn <= `BSV_ASSIGNMENT_DELAY 4'd0;
execute_renameRegsVector <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
execute_renameRegsVector_1 <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
execute_renameRegsVector_2 <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
execute_renameRegsVector_3 <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
freeRenameReg_countReg <= `BSV_ASSIGNMENT_DELAY 3'd0;
freeRenameReg_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
init <= `BSV_ASSIGNMENT_DELAY 3'd0;
initState <= `BSV_ASSIGNMENT_DELAY 1'd1;
lastEpoch <= `BSV_ASSIGNMENT_DELAY 3'd0;
lastWasBranch <= `BSV_ASSIGNMENT_DELAY 1'd0;
nextId <= `BSV_ASSIGNMENT_DELAY 4'd0;
nextInstruction_taggedReg <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
regRenameTable <= `BSV_ASSIGNMENT_DELAY 48'h2AA2AA2AA2AA;
theCapCop_capState <= `BSV_ASSIGNMENT_DELAY 3'd0;
theCapCop_capWriteback <= `BSV_ASSIGNMENT_DELAY
269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAF82;
theCapCop_commitWritebackFifo_taggedReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
theCapCop_count <= `BSV_ASSIGNMENT_DELAY 5'd0;
theCapCop_pcc <= `BSV_ASSIGNMENT_DELAY
256'hFFFF00000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF;
theCapCop_pipeEmpty <= `BSV_ASSIGNMENT_DELAY 1'd0;
theCapCop_writesCalculated <= `BSV_ASSIGNMENT_DELAY 5'd0;
theCapCop_writesDone <= `BSV_ASSIGNMENT_DELAY 5'd0;
theCapCop_writesIn <= `BSV_ASSIGNMENT_DELAY 5'd0;
theDebug_bp <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA;
theDebug_bp_1 <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA;
theDebug_bp_2 <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA;
theDebug_bp_3 <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA;
theDebug_dest <= `BSV_ASSIGNMENT_DELAY 64'd0;
theDebug_idleCount <= `BSV_ASSIGNMENT_DELAY 28'd0;
theDebug_instDelay <= `BSV_ASSIGNMENT_DELAY 6'd0;
theDebug_instQnotEmpty <= `BSV_ASSIGNMENT_DELAY 1'd0;
theDebug_instruction <= `BSV_ASSIGNMENT_DELAY 32'd0;
theDebug_mipsPC <= `BSV_ASSIGNMENT_DELAY 64'd0;
theDebug_opA <= `BSV_ASSIGNMENT_DELAY 64'd0;
theDebug_opB <= `BSV_ASSIGNMENT_DELAY 64'd0;
theDebug_pauseForInst <= `BSV_ASSIGNMENT_DELAY 1'd0;
theDebug_pausePipe <= `BSV_ASSIGNMENT_DELAY 1'd0;
theDebug_pipeCount <= `BSV_ASSIGNMENT_DELAY 3'd0;
theDebug_pollCount <= `BSV_ASSIGNMENT_DELAY 24'd0;
theDebug_previousPausePipe <= `BSV_ASSIGNMENT_DELAY 1'd0;
theDebug_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
theDebug_traceCmp <= `BSV_ASSIGNMENT_DELAY
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
theDebug_traceCmpMask <= `BSV_ASSIGNMENT_DELAY 256'd0;
theDebug_trace_buf_headPtr <= `BSV_ASSIGNMENT_DELAY 12'd0;
theDebug_trace_buf_readDelay <= `BSV_ASSIGNMENT_DELAY 1'd0;
theDebug_trace_buf_tailPtr <= `BSV_ASSIGNMENT_DELAY 12'd0;
theDebug_unPipeline <= `BSV_ASSIGNMENT_DELAY 1'd0;
theMem_dCache_cacheState <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_dCache_count <= `BSV_ASSIGNMENT_DELAY 7'd0;
theMem_dCache_data_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_dCache_data_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_dCache_data_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_dCache_data_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_dCache_fillCount <= `BSV_ASSIGNMENT_DELAY 2'd2;
theMem_dCache_missCached <= `BSV_ASSIGNMENT_DELAY 1'd0;
theMem_dCache_tags_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_dCache_tags_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_dCache_tags_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_dCache_tags_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_iCache_bank_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_iCache_bank_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_iCache_bank_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_iCache_bank_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_iCache_byteWriteReg <= `BSV_ASSIGNMENT_DELAY 8'd0;
theMem_iCache_cacheState <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_iCache_count <= `BSV_ASSIGNMENT_DELAY 9'd0;
theMem_iCache_fillCount <= `BSV_ASSIGNMENT_DELAY 2'd2;
theMem_iCache_missCached <= `BSV_ASSIGNMENT_DELAY 1'd0;
theMem_iCache_tags_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_iCache_tags_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_iCache_tags_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
theMem_iCache_tags_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
theMem_iCache_updateReg <= `BSV_ASSIGNMENT_DELAY 256'd0;
theMem_iCache_validFillLine <= `BSV_ASSIGNMENT_DELAY 1'd0;
theRF_count <= `BSV_ASSIGNMENT_DELAY 5'd0;
theRF_regFileState <= `BSV_ASSIGNMENT_DELAY 1'd0;
writeback_cyclCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
writeback_instCount <= `BSV_ASSIGNMENT_DELAY 64'd0;
writeback_lsInCycCt <= `BSV_ASSIGNMENT_DELAY 16'd0;
end
else
begin
if (execute_hi$EN)
execute_hi <= `BSV_ASSIGNMENT_DELAY execute_hi$D_IN;
if (execute_lo$EN)
execute_lo <= `BSV_ASSIGNMENT_DELAY execute_lo$D_IN;
if (execute_loadsDone$EN)
execute_loadsDone <= `BSV_ASSIGNMENT_DELAY execute_loadsDone$D_IN;
if (execute_loadsIn$EN)
execute_loadsIn <= `BSV_ASSIGNMENT_DELAY execute_loadsIn$D_IN;
if (execute_renameRegsVector$EN)
execute_renameRegsVector <= `BSV_ASSIGNMENT_DELAY
execute_renameRegsVector$D_IN;
if (execute_renameRegsVector_1$EN)
execute_renameRegsVector_1 <= `BSV_ASSIGNMENT_DELAY
execute_renameRegsVector_1$D_IN;
if (execute_renameRegsVector_2$EN)
execute_renameRegsVector_2 <= `BSV_ASSIGNMENT_DELAY
execute_renameRegsVector_2$D_IN;
if (execute_renameRegsVector_3$EN)
execute_renameRegsVector_3 <= `BSV_ASSIGNMENT_DELAY
execute_renameRegsVector_3$D_IN;
if (freeRenameReg_countReg$EN)
freeRenameReg_countReg <= `BSV_ASSIGNMENT_DELAY
freeRenameReg_countReg$D_IN;
if (freeRenameReg_levelsValid$EN)
freeRenameReg_levelsValid <= `BSV_ASSIGNMENT_DELAY
freeRenameReg_levelsValid$D_IN;
if (init$EN) init <= `BSV_ASSIGNMENT_DELAY init$D_IN;
if (initState$EN) initState <= `BSV_ASSIGNMENT_DELAY initState$D_IN;
if (lastEpoch$EN) lastEpoch <= `BSV_ASSIGNMENT_DELAY lastEpoch$D_IN;
if (lastWasBranch$EN)
lastWasBranch <= `BSV_ASSIGNMENT_DELAY lastWasBranch$D_IN;
if (nextId$EN) nextId <= `BSV_ASSIGNMENT_DELAY nextId$D_IN;
if (nextInstruction_taggedReg$EN)
nextInstruction_taggedReg <= `BSV_ASSIGNMENT_DELAY
nextInstruction_taggedReg$D_IN;
if (regRenameTable$EN)
regRenameTable <= `BSV_ASSIGNMENT_DELAY regRenameTable$D_IN;
if (theCapCop_capState$EN)
theCapCop_capState <= `BSV_ASSIGNMENT_DELAY theCapCop_capState$D_IN;
if (theCapCop_capWriteback$EN)
theCapCop_capWriteback <= `BSV_ASSIGNMENT_DELAY
theCapCop_capWriteback$D_IN;
if (theCapCop_commitWritebackFifo_taggedReg$EN)
theCapCop_commitWritebackFifo_taggedReg <= `BSV_ASSIGNMENT_DELAY
theCapCop_commitWritebackFifo_taggedReg$D_IN;
if (theCapCop_count$EN)
theCapCop_count <= `BSV_ASSIGNMENT_DELAY theCapCop_count$D_IN;
if (theCapCop_pcc$EN)
theCapCop_pcc <= `BSV_ASSIGNMENT_DELAY theCapCop_pcc$D_IN;
if (theCapCop_pipeEmpty$EN)
theCapCop_pipeEmpty <= `BSV_ASSIGNMENT_DELAY
theCapCop_pipeEmpty$D_IN;
if (theCapCop_writesCalculated$EN)
theCapCop_writesCalculated <= `BSV_ASSIGNMENT_DELAY
theCapCop_writesCalculated$D_IN;
if (theCapCop_writesDone$EN)
theCapCop_writesDone <= `BSV_ASSIGNMENT_DELAY
theCapCop_writesDone$D_IN;
if (theCapCop_writesIn$EN)
theCapCop_writesIn <= `BSV_ASSIGNMENT_DELAY theCapCop_writesIn$D_IN;
if (theDebug_bp$EN)
theDebug_bp <= `BSV_ASSIGNMENT_DELAY theDebug_bp$D_IN;
if (theDebug_bp_1$EN)
theDebug_bp_1 <= `BSV_ASSIGNMENT_DELAY theDebug_bp_1$D_IN;
if (theDebug_bp_2$EN)
theDebug_bp_2 <= `BSV_ASSIGNMENT_DELAY theDebug_bp_2$D_IN;
if (theDebug_bp_3$EN)
theDebug_bp_3 <= `BSV_ASSIGNMENT_DELAY theDebug_bp_3$D_IN;
if (theDebug_dest$EN)
theDebug_dest <= `BSV_ASSIGNMENT_DELAY theDebug_dest$D_IN;
if (theDebug_idleCount$EN)
theDebug_idleCount <= `BSV_ASSIGNMENT_DELAY theDebug_idleCount$D_IN;
if (theDebug_instDelay$EN)
theDebug_instDelay <= `BSV_ASSIGNMENT_DELAY theDebug_instDelay$D_IN;
if (theDebug_instQnotEmpty$EN)
theDebug_instQnotEmpty <= `BSV_ASSIGNMENT_DELAY
theDebug_instQnotEmpty$D_IN;
if (theDebug_instruction$EN)
theDebug_instruction <= `BSV_ASSIGNMENT_DELAY
theDebug_instruction$D_IN;
if (theDebug_mipsPC$EN)
theDebug_mipsPC <= `BSV_ASSIGNMENT_DELAY theDebug_mipsPC$D_IN;
if (theDebug_opA$EN)
theDebug_opA <= `BSV_ASSIGNMENT_DELAY theDebug_opA$D_IN;
if (theDebug_opB$EN)
theDebug_opB <= `BSV_ASSIGNMENT_DELAY theDebug_opB$D_IN;
if (theDebug_pauseForInst$EN)
theDebug_pauseForInst <= `BSV_ASSIGNMENT_DELAY
theDebug_pauseForInst$D_IN;
if (theDebug_pausePipe$EN)
theDebug_pausePipe <= `BSV_ASSIGNMENT_DELAY theDebug_pausePipe$D_IN;
if (theDebug_pipeCount$EN)
theDebug_pipeCount <= `BSV_ASSIGNMENT_DELAY theDebug_pipeCount$D_IN;
if (theDebug_pollCount$EN)
theDebug_pollCount <= `BSV_ASSIGNMENT_DELAY theDebug_pollCount$D_IN;
if (theDebug_previousPausePipe$EN)
theDebug_previousPausePipe <= `BSV_ASSIGNMENT_DELAY
theDebug_previousPausePipe$D_IN;
if (theDebug_state$EN)
theDebug_state <= `BSV_ASSIGNMENT_DELAY theDebug_state$D_IN;
if (theDebug_traceCmp$EN)
theDebug_traceCmp <= `BSV_ASSIGNMENT_DELAY theDebug_traceCmp$D_IN;
if (theDebug_traceCmpMask$EN)
theDebug_traceCmpMask <= `BSV_ASSIGNMENT_DELAY
theDebug_traceCmpMask$D_IN;
if (theDebug_trace_buf_headPtr$EN)
theDebug_trace_buf_headPtr <= `BSV_ASSIGNMENT_DELAY
theDebug_trace_buf_headPtr$D_IN;
if (theDebug_trace_buf_readDelay$EN)
theDebug_trace_buf_readDelay <= `BSV_ASSIGNMENT_DELAY
theDebug_trace_buf_readDelay$D_IN;
if (theDebug_trace_buf_tailPtr$EN)
theDebug_trace_buf_tailPtr <= `BSV_ASSIGNMENT_DELAY
theDebug_trace_buf_tailPtr$D_IN;
if (theDebug_unPipeline$EN)
theDebug_unPipeline <= `BSV_ASSIGNMENT_DELAY
theDebug_unPipeline$D_IN;
if (theMem_dCache_cacheState$EN)
theMem_dCache_cacheState <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_cacheState$D_IN;
if (theMem_dCache_count$EN)
theMem_dCache_count <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_count$D_IN;
if (theMem_dCache_data_serverAdapterA_cnt$EN)
theMem_dCache_data_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_data_serverAdapterA_cnt$D_IN;
if (theMem_dCache_data_serverAdapterA_s1$EN)
theMem_dCache_data_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_data_serverAdapterA_s1$D_IN;
if (theMem_dCache_data_serverAdapterB_cnt$EN)
theMem_dCache_data_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_data_serverAdapterB_cnt$D_IN;
if (theMem_dCache_data_serverAdapterB_s1$EN)
theMem_dCache_data_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_data_serverAdapterB_s1$D_IN;
if (theMem_dCache_fillCount$EN)
theMem_dCache_fillCount <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_fillCount$D_IN;
if (theMem_dCache_missCached$EN)
theMem_dCache_missCached <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_missCached$D_IN;
if (theMem_dCache_tags_serverAdapterA_cnt$EN)
theMem_dCache_tags_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_tags_serverAdapterA_cnt$D_IN;
if (theMem_dCache_tags_serverAdapterA_s1$EN)
theMem_dCache_tags_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_tags_serverAdapterA_s1$D_IN;
if (theMem_dCache_tags_serverAdapterB_cnt$EN)
theMem_dCache_tags_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_tags_serverAdapterB_cnt$D_IN;
if (theMem_dCache_tags_serverAdapterB_s1$EN)
theMem_dCache_tags_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_tags_serverAdapterB_s1$D_IN;
if (theMem_iCache_bank_serverAdapterA_cnt$EN)
theMem_iCache_bank_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_bank_serverAdapterA_cnt$D_IN;
if (theMem_iCache_bank_serverAdapterA_s1$EN)
theMem_iCache_bank_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_bank_serverAdapterA_s1$D_IN;
if (theMem_iCache_bank_serverAdapterB_cnt$EN)
theMem_iCache_bank_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_bank_serverAdapterB_cnt$D_IN;
if (theMem_iCache_bank_serverAdapterB_s1$EN)
theMem_iCache_bank_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_bank_serverAdapterB_s1$D_IN;
if (theMem_iCache_byteWriteReg$EN)
theMem_iCache_byteWriteReg <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_byteWriteReg$D_IN;
if (theMem_iCache_cacheState$EN)
theMem_iCache_cacheState <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_cacheState$D_IN;
if (theMem_iCache_count$EN)
theMem_iCache_count <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_count$D_IN;
if (theMem_iCache_fillCount$EN)
theMem_iCache_fillCount <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_fillCount$D_IN;
if (theMem_iCache_missCached$EN)
theMem_iCache_missCached <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_missCached$D_IN;
if (theMem_iCache_tags_serverAdapterA_cnt$EN)
theMem_iCache_tags_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_tags_serverAdapterA_cnt$D_IN;
if (theMem_iCache_tags_serverAdapterA_s1$EN)
theMem_iCache_tags_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_tags_serverAdapterA_s1$D_IN;
if (theMem_iCache_tags_serverAdapterB_cnt$EN)
theMem_iCache_tags_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_tags_serverAdapterB_cnt$D_IN;
if (theMem_iCache_tags_serverAdapterB_s1$EN)
theMem_iCache_tags_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_tags_serverAdapterB_s1$D_IN;
if (theMem_iCache_updateReg$EN)
theMem_iCache_updateReg <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_updateReg$D_IN;
if (theMem_iCache_validFillLine$EN)
theMem_iCache_validFillLine <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_validFillLine$D_IN;
if (theRF_count$EN)
theRF_count <= `BSV_ASSIGNMENT_DELAY theRF_count$D_IN;
if (theRF_regFileState$EN)
theRF_regFileState <= `BSV_ASSIGNMENT_DELAY theRF_regFileState$D_IN;
if (writeback_cyclCount$EN)
writeback_cyclCount <= `BSV_ASSIGNMENT_DELAY
writeback_cyclCount$D_IN;
if (writeback_instCount$EN)
writeback_instCount <= `BSV_ASSIGNMENT_DELAY
writeback_instCount$D_IN;
if (writeback_lsInCycCt$EN)
writeback_lsInCycCt <= `BSV_ASSIGNMENT_DELAY
writeback_lsInCycCt$D_IN;
end
if (theMem_dCache_addrReg$EN)
theMem_dCache_addrReg <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_addrReg$D_IN;
if (theMem_dCache_byteWriteReg$EN)
theMem_dCache_byteWriteReg <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_byteWriteReg$D_IN;
if (theMem_dCache_lastKey$EN)
theMem_dCache_lastKey <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_lastKey$D_IN;
if (theMem_dCache_recentlyUsedWay$EN)
theMem_dCache_recentlyUsedWay <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_recentlyUsedWay$D_IN;
if (theMem_dCache_updateReg$EN)
theMem_dCache_updateReg <= `BSV_ASSIGNMENT_DELAY
theMem_dCache_updateReg$D_IN;
if (theMem_iCache_phyAddrReg$EN)
theMem_iCache_phyAddrReg <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_phyAddrReg$D_IN;
if (theMem_iCache_virAddrReg$EN)
theMem_iCache_virAddrReg <= `BSV_ASSIGNMENT_DELAY
theMem_iCache_virAddrReg$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
execute_hi = 64'hAAAAAAAAAAAAAAAA;
execute_lo = 64'hAAAAAAAAAAAAAAAA;
execute_loadsDone = 4'hA;
execute_loadsIn = 4'hA;
execute_renameRegsVector = 65'h0AAAAAAAAAAAAAAAA;
execute_renameRegsVector_1 = 65'h0AAAAAAAAAAAAAAAA;
execute_renameRegsVector_2 = 65'h0AAAAAAAAAAAAAAAA;
execute_renameRegsVector_3 = 65'h0AAAAAAAAAAAAAAAA;
freeRenameReg_countReg = 3'h2;
freeRenameReg_levelsValid = 1'h0;
init = 3'h2;
initState = 1'h0;
lastEpoch = 3'h2;
lastWasBranch = 1'h0;
nextId = 4'hA;
nextInstruction_taggedReg = 70'h2AAAAAAAAAAAAAAAAA;
regRenameTable = 48'hAAAAAAAAAAAA;
theCapCop_capState = 3'h2;
theCapCop_capWriteback =
269'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
theCapCop_commitWritebackFifo_taggedReg = 2'h2;
theCapCop_count = 5'h0A;
theCapCop_pcc =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
theCapCop_pipeEmpty = 1'h0;
theCapCop_writesCalculated = 5'h0A;
theCapCop_writesDone = 5'h0A;
theCapCop_writesIn = 5'h0A;
theDebug_bp = 65'h0AAAAAAAAAAAAAAAA;
theDebug_bp_1 = 65'h0AAAAAAAAAAAAAAAA;
theDebug_bp_2 = 65'h0AAAAAAAAAAAAAAAA;
theDebug_bp_3 = 65'h0AAAAAAAAAAAAAAAA;
theDebug_dest = 64'hAAAAAAAAAAAAAAAA;
theDebug_idleCount = 28'hAAAAAAA;
theDebug_instDelay = 6'h2A;
theDebug_instQnotEmpty = 1'h0;
theDebug_instruction = 32'hAAAAAAAA;
theDebug_mipsPC = 64'hAAAAAAAAAAAAAAAA;
theDebug_opA = 64'hAAAAAAAAAAAAAAAA;
theDebug_opB = 64'hAAAAAAAAAAAAAAAA;
theDebug_pauseForInst = 1'h0;
theDebug_pausePipe = 1'h0;
theDebug_pipeCount = 3'h2;
theDebug_pollCount = 24'hAAAAAA;
theDebug_previousPausePipe = 1'h0;
theDebug_state = 2'h2;
theDebug_traceCmp =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
theDebug_traceCmpMask =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
theDebug_trace_buf_headPtr = 12'hAAA;
theDebug_trace_buf_readDelay = 1'h0;
theDebug_trace_buf_tailPtr = 12'hAAA;
theDebug_unPipeline = 1'h0;
theMem_dCache_addrReg = 36'hAAAAAAAAA;
theMem_dCache_byteWriteReg = 8'hAA;
theMem_dCache_cacheState = 3'h2;
theMem_dCache_count = 7'h2A;
theMem_dCache_data_serverAdapterA_cnt = 3'h2;
theMem_dCache_data_serverAdapterA_s1 = 2'h2;
theMem_dCache_data_serverAdapterB_cnt = 3'h2;
theMem_dCache_data_serverAdapterB_s1 = 2'h2;
theMem_dCache_fillCount = 2'h2;
theMem_dCache_lastKey = 7'h2A;
theMem_dCache_missCached = 1'h0;
theMem_dCache_recentlyUsedWay = 1'h0;
theMem_dCache_tags_serverAdapterA_cnt = 3'h2;
theMem_dCache_tags_serverAdapterA_s1 = 2'h2;
theMem_dCache_tags_serverAdapterB_cnt = 3'h2;
theMem_dCache_tags_serverAdapterB_s1 = 2'h2;
theMem_dCache_updateReg =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
theMem_iCache_bank_serverAdapterA_cnt = 3'h2;
theMem_iCache_bank_serverAdapterA_s1 = 2'h2;
theMem_iCache_bank_serverAdapterB_cnt = 3'h2;
theMem_iCache_bank_serverAdapterB_s1 = 2'h2;
theMem_iCache_byteWriteReg = 8'hAA;
theMem_iCache_cacheState = 2'h2;
theMem_iCache_count = 9'h0AA;
theMem_iCache_fillCount = 2'h2;
theMem_iCache_missCached = 1'h0;
theMem_iCache_phyAddrReg = 36'hAAAAAAAAA;
theMem_iCache_tags_serverAdapterA_cnt = 3'h2;
theMem_iCache_tags_serverAdapterA_s1 = 2'h2;
theMem_iCache_tags_serverAdapterB_cnt = 3'h2;
theMem_iCache_tags_serverAdapterB_s1 = 2'h2;
theMem_iCache_updateReg =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
theMem_iCache_validFillLine = 1'h0;
theMem_iCache_virAddrReg = 64'hAAAAAAAAAAAAAAAA;
theRF_count = 5'h0A;
theRF_regFileState = 1'h0;
writeback_cyclCount = 16'hAAAA;
writeback_instCount = 64'hAAAAAAAAAAAAAAAA;
writeback_lsInCycCt = 16'hAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge csi_c0_clk)
begin
#0;
if (csi_c0_reset_n)
if (theMem_iCache_tags_serverAdapterA_s1[1] &&
!theMem_iCache_tags_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (theMem_iCache_tags_serverAdapterB_s1[1] &&
!theMem_iCache_tags_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (theMem_iCache_bank_serverAdapterA_s1[1] &&
!theMem_iCache_bank_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (theMem_iCache_bank_serverAdapterB_s1[1] &&
!theMem_iCache_bank_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (theMem_dCache_tags_serverAdapterA_s1[1] &&
!theMem_dCache_tags_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (theMem_dCache_tags_serverAdapterB_s1[1] &&
!theMem_dCache_tags_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (theMem_dCache_data_serverAdapterA_s1[1] &&
!theMem_dCache_data_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (theMem_dCache_data_serverAdapterB_s1[1] &&
!theMem_dCache_data_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("DEBUG PACKET: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("MessagePacket{op: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd67)
$write("LoadTraceFilter");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] == 8'd77)
$write("LoadTraceFilterMask");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write(" length: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("%d",
$unsigned(theDebug_debugConvert$messages_request_get[263:256]));
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write(" data: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("<V ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", theDebug_debugConvert$messages_request_get[7:0], " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", theDebug_debugConvert$messages_request_get[15:8], " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[23:16],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[31:24],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[39:32],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[47:40],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[55:48],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[63:56],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[71:64],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[79:72],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[87:80],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[95:88],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[103:96],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[111:104],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[119:112],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[127:120],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[135:128],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[143:136],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[151:144],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[159:152],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[167:160],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[175:168],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[183:176],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[191:184],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[199:192],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[207:200],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[215:208],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[223:216],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[231:224],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[239:232],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[247:240],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h",
theDebug_debugConvert$messages_request_get[255:248],
" ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write(" >");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("}");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("\n");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$display("valid=%d, version=%d, ex=%d, reserved=%x, inst=%x, pc=%x, regVal1=%x, regVal2=%x",
theDebug_debugConvert$messages_request_get[7],
theDebug_debugConvert$messages_request_get[6:3],
IF_theDebug_debugConvert_messages_request_get__ETC___d7855,
te_reserved__h24719,
te_inst__h24720,
te_pc__h24721,
te_regVal1__h24722,
te_regVal2__h24723);
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("DEBUG RESPONSE: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("MessagePacket{op: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd0)
$write("Null");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd1)
$write("LoadInstruction");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd2)
$write("LoadOpA");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd3)
$write("LoadOpB");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd4)
$write("LoadBreakPoint0");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd5)
$write("LoadBreakPoint1");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd6)
$write("LoadBreakPoint2");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd7)
$write("LoadBreakPoint3");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd8)
$write("LoadTraceFilter");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd9)
$write("LoadTraceFilterMask");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd10)
$write("ExecuteInstruction");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd11)
$write("ReportDest");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd12)
$write("PauseExecution");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd13)
$write("ResumeExecution");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd14)
$write("StepExecution");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd17)
$write("PopTrace");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd15)
$write("MovePCtoDest");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd16)
$write("ResumeUnpipelined");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd18)
$write("StreamTrace");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd19)
$write("LoadInstructionResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd20)
$write("LoadOpAResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd21)
$write("LoadOpBResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd22)
$write("LoadBreakPoint0Response");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd23)
$write("LoadBreakPoint1Response");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd24)
$write("LoadBreakPoint2Response");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd25)
$write("LoadBreakPoint3Response");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd26)
$write("LoadTraceFilterResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd27)
$write("LoadTraceFilterMaskResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd28)
$write("ExecuteInstructionResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd30)
$write("ReportDestResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd31)
$write("PauseExecutionResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd32)
$write("ResumeExecutionResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd33)
$write("StepExecutionResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd34)
$write("PopTraceResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd35)
$write("MovePCtoDestResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd36)
$write("ResumeUnpipelinedResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd37)
$write("StreamTraceResponse");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 == 6'd38)
$write("BreakpointFired");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77) &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd0 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd1 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd2 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd3 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd4 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd5 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd6 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd7 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd8 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd9 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd10 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd11 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd12 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd13 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd14 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd17 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd15 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd16 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd18 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd19 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd20 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd21 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd22 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd23 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd24 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd25 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd26 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd27 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd28 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd30 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd31 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd32 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd33 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd34 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd35 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd36 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 !=
6'd37 &&
IF_theDebug_debugConvert_messages_request_get__ETC___d8630 != 6'd38)
$write("InvalidInstruction");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write(" length: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("%d", $unsigned(8'b0));
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write(" data: ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("<V ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("'h%h", 8'hAA, " ");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write(" >");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("}");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_theDebug_doCommands &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd105 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd97 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd98 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd48 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd49 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd50 &&
theDebug_debugConvert$messages_request_get[271:264] != 8'd51 &&
(theDebug_debugConvert$messages_request_get[271:264] == 8'd67 ||
theDebug_debugConvert$messages_request_get[271:264] == 8'd77))
$write("\n");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_registerFetch &&
IF_IF_fetchedControlToken_first__662_BIT_1_663_ETC___d8261)
$display("killing branch in branch delay slot!");
if (csi_c0_reset_n)
if (WILL_FIRE_RL_execute_finishMultiplyOrDivide &&
WILL_FIRE_RL_execute_deliverPendingOp)
$display("Error: \"Execute.bsv\", line 95, column 28: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_execute_finishMultiplyOrDivide] and [RL_execute_deliverPendingOp] )\n fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkMIPSTop
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Thu Aug 16 15:00:30 BST 2012
//
// Method conflict info:
// Method: avs_s0
// Conflict-free: avs_s0_readdata,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced before (restricted): avs_s0_waitrequest
// Conflicts: avs_s0
//
// Method: avs_s0_readdata
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: avs_s0_waitrequest
// Conflict-free: avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): avs_s0
//
// Method: aso_stream_out_data
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out_valid
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced before (restricted): aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket
// Conflicts: aso_stream_out
//
// Method: aso_stream_out_startofpacket
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out_endofpacket
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: coe_ssram_adv
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_ssram_bwa_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_bwb_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_ce_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_cke_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_ssram_oe_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_we_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_a
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_d_out
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_d
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_cke_n,
// coe_flash_clk,
// coe_touch
// Sequenced before (restricted): coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_oe_n,
// coe_flash_we_n
// Conflicts: coe_fsm_d
//
// Method: coe_fsm_dout_req
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_adv_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_ce_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_clk
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_flash_oe_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_we_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_touch
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n
// Conflicts: coe_touch
//
//
// Ports:
// Name I/O size props
// avs_s0_readdata O 32
// avs_s0_waitrequest O 1
// aso_stream_out_data O 24
// aso_stream_out_valid O 1
// aso_stream_out_startofpacket O 1
// aso_stream_out_endofpacket O 1
// coe_ssram_adv O 1 const
// coe_ssram_bwa_n O 1
// coe_ssram_bwb_n O 1
// coe_ssram_ce_n O 1
// coe_ssram_cke_n O 1 const
// coe_ssram_oe_n O 1
// coe_ssram_we_n O 1
// coe_fsm_a O 25
// coe_fsm_d_out O 16
// coe_fsm_dout_req O 1
// coe_flash_adv_n O 1
// coe_flash_ce_n O 1
// coe_flash_clk O 1 const
// coe_flash_oe_n O 1
// coe_flash_we_n O 1
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// avs_s0_address I 25 reg
// avs_s0_writedata I 32 reg
// avs_s0_write I 1
// avs_s0_read I 1
// avs_s0_byteenable I 4 reg
// aso_stream_out_ready I 1
// coe_fsm_d_in I 16
// coe_touch_x1 I 10
// coe_touch_y1 I 9
// coe_touch_x2 I 10
// coe_touch_y2 I 9
// coe_touch_count_gesture I 10
// coe_touch_touch_valid I 1
//
// Combinational paths from inputs to outputs:
// (avs_s0_write, avs_s0_read) -> avs_s0_waitrequest
// aso_stream_out_ready -> aso_stream_out_data
// aso_stream_out_ready -> aso_stream_out_valid
// aso_stream_out_ready -> aso_stream_out_startofpacket
// aso_stream_out_ready -> aso_stream_out_endofpacket
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkMTL_Framebuffer_Flash(csi_clockreset_clk,
csi_clockreset_reset_n,
avs_s0_address,
avs_s0_writedata,
avs_s0_write,
avs_s0_read,
avs_s0_byteenable,
avs_s0_readdata,
avs_s0_waitrequest,
aso_stream_out_data,
aso_stream_out_valid,
aso_stream_out_ready,
aso_stream_out_startofpacket,
aso_stream_out_endofpacket,
coe_ssram_adv,
coe_ssram_bwa_n,
coe_ssram_bwb_n,
coe_ssram_ce_n,
coe_ssram_cke_n,
coe_ssram_oe_n,
coe_ssram_we_n,
coe_fsm_a,
coe_fsm_d_out,
coe_fsm_d_in,
coe_fsm_dout_req,
coe_flash_adv_n,
coe_flash_ce_n,
coe_flash_clk,
coe_flash_oe_n,
coe_flash_we_n,
coe_touch_x1,
coe_touch_y1,
coe_touch_x2,
coe_touch_y2,
coe_touch_count_gesture,
coe_touch_touch_valid);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method avs_s0
input [24 : 0] avs_s0_address;
input [31 : 0] avs_s0_writedata;
input avs_s0_write;
input avs_s0_read;
input [3 : 0] avs_s0_byteenable;
// value method avs_s0_readdata
output [31 : 0] avs_s0_readdata;
// value method avs_s0_waitrequest
output avs_s0_waitrequest;
// value method aso_stream_out_data
output [23 : 0] aso_stream_out_data;
// value method aso_stream_out_valid
output aso_stream_out_valid;
// action method aso_stream_out
input aso_stream_out_ready;
// value method aso_stream_out_startofpacket
output aso_stream_out_startofpacket;
// value method aso_stream_out_endofpacket
output aso_stream_out_endofpacket;
// value method coe_ssram_adv
output coe_ssram_adv;
// value method coe_ssram_bwa_n
output coe_ssram_bwa_n;
// value method coe_ssram_bwb_n
output coe_ssram_bwb_n;
// value method coe_ssram_ce_n
output coe_ssram_ce_n;
// value method coe_ssram_cke_n
output coe_ssram_cke_n;
// value method coe_ssram_oe_n
output coe_ssram_oe_n;
// value method coe_ssram_we_n
output coe_ssram_we_n;
// value method coe_fsm_a
output [24 : 0] coe_fsm_a;
// value method coe_fsm_d_out
output [15 : 0] coe_fsm_d_out;
// action method coe_fsm_d
input [15 : 0] coe_fsm_d_in;
// value method coe_fsm_dout_req
output coe_fsm_dout_req;
// value method coe_flash_adv_n
output coe_flash_adv_n;
// value method coe_flash_ce_n
output coe_flash_ce_n;
// value method coe_flash_clk
output coe_flash_clk;
// value method coe_flash_oe_n
output coe_flash_oe_n;
// value method coe_flash_we_n
output coe_flash_we_n;
// action method coe_touch
input [9 : 0] coe_touch_x1;
input [8 : 0] coe_touch_y1;
input [9 : 0] coe_touch_x2;
input [8 : 0] coe_touch_y2;
input [9 : 0] coe_touch_count_gesture;
input coe_touch_touch_valid;
// signals for module outputs
wire [31 : 0] avs_s0_readdata;
wire [24 : 0] coe_fsm_a;
wire [23 : 0] aso_stream_out_data;
wire [15 : 0] coe_fsm_d_out;
wire aso_stream_out_endofpacket,
aso_stream_out_startofpacket,
aso_stream_out_valid,
avs_s0_waitrequest,
coe_flash_adv_n,
coe_flash_ce_n,
coe_flash_clk,
coe_flash_oe_n,
coe_flash_we_n,
coe_fsm_dout_req,
coe_ssram_adv,
coe_ssram_bwa_n,
coe_ssram_bwb_n,
coe_ssram_ce_n,
coe_ssram_cke_n,
coe_ssram_oe_n,
coe_ssram_we_n;
// inlined wires
wire [24 : 0] pixel_engine_lcd_stream_data_dw$wget;
wire [15 : 0] mem_fsm_dout_dw$wget;
wire avalon_slave_avalonwait$wget,
avalon_slave_avalonwait_end_read$whas,
avalon_slave_avalonwait_end_write$whas,
mem_flash_ce_n_dw$wget,
mem_flash_we_n_dw$wget,
mem_fsm_a_w$whas,
mem_fsm_dout_dw$whas,
mem_fsm_dout_req_dw$wget,
mem_ssram_ce_pw$whas;
// register avalon_slave_ignore_further_requests
reg avalon_slave_ignore_further_requests;
wire avalon_slave_ignore_further_requests$D_IN,
avalon_slave_ignore_further_requests$EN;
// register mem_flash_timer
reg [3 : 0] mem_flash_timer;
wire [3 : 0] mem_flash_timer$D_IN;
wire mem_flash_timer$EN;
// register pixel_engine_addr
reg [24 : 0] pixel_engine_addr;
wire [24 : 0] pixel_engine_addr$D_IN;
wire pixel_engine_addr$EN;
// register pixel_engine_char_addr
reg [24 : 0] pixel_engine_char_addr;
wire [24 : 0] pixel_engine_char_addr$D_IN;
wire pixel_engine_char_addr$EN;
// register pixel_engine_char_base
reg [24 : 0] pixel_engine_char_base;
wire [24 : 0] pixel_engine_char_base$D_IN;
wire pixel_engine_char_base$EN;
// register pixel_engine_char_ctr
reg pixel_engine_char_ctr;
wire pixel_engine_char_ctr$D_IN, pixel_engine_char_ctr$EN;
// register pixel_engine_char_end
reg [24 : 0] pixel_engine_char_end;
wire [24 : 0] pixel_engine_char_end$D_IN;
wire pixel_engine_char_end$EN;
// register pixel_engine_char_x_pos
reg [2 : 0] pixel_engine_char_x_pos;
wire [2 : 0] pixel_engine_char_x_pos$D_IN;
wire pixel_engine_char_x_pos$EN;
// register pixel_engine_char_x_two_char
reg [5 : 0] pixel_engine_char_x_two_char;
wire [5 : 0] pixel_engine_char_x_two_char$D_IN;
wire pixel_engine_char_x_two_char$EN;
// register pixel_engine_char_y
reg [24 : 0] pixel_engine_char_y;
wire [24 : 0] pixel_engine_char_y$D_IN;
wire pixel_engine_char_y$EN;
// register pixel_engine_cursor_pos
reg [15 : 0] pixel_engine_cursor_pos;
wire [15 : 0] pixel_engine_cursor_pos$D_IN;
wire pixel_engine_cursor_pos$EN;
// register pixel_engine_fb_blend
reg [31 : 0] pixel_engine_fb_blend;
wire [31 : 0] pixel_engine_fb_blend$D_IN;
wire pixel_engine_fb_blend$EN;
// register pixel_engine_flash_col
reg [5 : 0] pixel_engine_flash_col;
wire [5 : 0] pixel_engine_flash_col$D_IN;
wire pixel_engine_flash_col$EN;
// register pixel_engine_font_y
reg [3 : 0] pixel_engine_font_y;
wire [3 : 0] pixel_engine_font_y$D_IN;
wire pixel_engine_font_y$EN;
// register prev_touch_info
reg [47 : 0] prev_touch_info;
wire [47 : 0] prev_touch_info$D_IN;
wire prev_touch_info$EN;
// ports of submodule avalon_control_reg_resp
wire [32 : 0] avalon_control_reg_resp$D_IN, avalon_control_reg_resp$D_OUT;
wire avalon_control_reg_resp$CLR,
avalon_control_reg_resp$DEQ,
avalon_control_reg_resp$EMPTY_N,
avalon_control_reg_resp$ENQ,
avalon_control_reg_resp$FULL_N;
// ports of submodule avalon_mem_resp
wire [32 : 0] avalon_mem_resp$D_IN, avalon_mem_resp$D_OUT;
wire avalon_mem_resp$CLR,
avalon_mem_resp$DEQ,
avalon_mem_resp$EMPTY_N,
avalon_mem_resp$ENQ,
avalon_mem_resp$FULL_N;
// ports of submodule avalon_req
wire [61 : 0] avalon_req$D_IN, avalon_req$D_OUT;
wire avalon_req$CLR,
avalon_req$DEQ,
avalon_req$EMPTY_N,
avalon_req$ENQ,
avalon_req$FULL_N;
// ports of submodule avalon_slave_outbuf
wire [62 : 0] avalon_slave_outbuf$D_IN, avalon_slave_outbuf$D_OUT;
wire avalon_slave_outbuf$CLR,
avalon_slave_outbuf$DEQ,
avalon_slave_outbuf$EMPTY_N,
avalon_slave_outbuf$ENQ,
avalon_slave_outbuf$FULL_N;
// ports of submodule lower_16b_returned
wire [16 : 0] lower_16b_returned$D_IN, lower_16b_returned$D_OUT;
wire lower_16b_returned$CLR,
lower_16b_returned$DEQ,
lower_16b_returned$EMPTY_N,
lower_16b_returned$ENQ;
// ports of submodule mem_pipe0
wire [16 : 0] mem_pipe0$D_IN, mem_pipe0$D_OUT;
wire mem_pipe0$CLR,
mem_pipe0$DEQ,
mem_pipe0$EMPTY_N,
mem_pipe0$ENQ,
mem_pipe0$FULL_N;
// ports of submodule mem_pipe1
wire [16 : 0] mem_pipe1$D_IN, mem_pipe1$D_OUT;
wire mem_pipe1$CLR,
mem_pipe1$DEQ,
mem_pipe1$EMPTY_N,
mem_pipe1$ENQ,
mem_pipe1$FULL_N;
// ports of submodule mem_pipe2
wire [16 : 0] mem_pipe2$D_IN, mem_pipe2$D_OUT;
wire mem_pipe2$CLR,
mem_pipe2$DEQ,
mem_pipe2$EMPTY_N,
mem_pipe2$ENQ,
mem_pipe2$FULL_N;
// ports of submodule mem_req
wire [44 : 0] mem_req$D_IN, mem_req$D_OUT;
wire mem_req$CLR, mem_req$DEQ, mem_req$EMPTY_N, mem_req$ENQ, mem_req$FULL_N;
// ports of submodule mem_resp
wire [16 : 0] mem_resp$D_IN, mem_resp$D_OUT;
wire mem_resp$CLR,
mem_resp$DEQ,
mem_resp$EMPTY_N,
mem_resp$ENQ,
mem_resp$FULL_N;
// ports of submodule mem_upper_16b_request
wire [44 : 0] mem_upper_16b_request$D_IN, mem_upper_16b_request$D_OUT;
wire mem_upper_16b_request$CLR,
mem_upper_16b_request$DEQ,
mem_upper_16b_request$EMPTY_N,
mem_upper_16b_request$ENQ;
// ports of submodule pixel_engine_char_colour
wire [9 : 0] pixel_engine_char_colour$D_IN, pixel_engine_char_colour$D_OUT;
wire pixel_engine_char_colour$CLR,
pixel_engine_char_colour$DEQ,
pixel_engine_char_colour$EMPTY_N,
pixel_engine_char_colour$ENQ,
pixel_engine_char_colour$FULL_N;
// ports of submodule pixel_engine_char_pixel
wire [9 : 0] pixel_engine_char_pixel$D_IN, pixel_engine_char_pixel$D_OUT;
wire pixel_engine_char_pixel$CLR,
pixel_engine_char_pixel$DEQ,
pixel_engine_char_pixel$EMPTY_N,
pixel_engine_char_pixel$ENQ,
pixel_engine_char_pixel$FULL_N;
// ports of submodule pixel_engine_char_pos
wire [15 : 0] pixel_engine_char_pos$D_IN, pixel_engine_char_pos$D_OUT;
wire pixel_engine_char_pos$CLR,
pixel_engine_char_pos$DEQ,
pixel_engine_char_pos$EMPTY_N,
pixel_engine_char_pos$ENQ,
pixel_engine_char_pos$FULL_N;
// ports of submodule pixel_engine_chars_read
wire pixel_engine_chars_read$CLR,
pixel_engine_chars_read$DEQ,
pixel_engine_chars_read$D_IN,
pixel_engine_chars_read$D_OUT,
pixel_engine_chars_read$EMPTY_N,
pixel_engine_chars_read$ENQ,
pixel_engine_chars_read$FULL_N;
// ports of submodule pixel_engine_font_y_pos
wire [3 : 0] pixel_engine_font_y_pos$D_IN, pixel_engine_font_y_pos$D_OUT;
wire pixel_engine_font_y_pos$CLR,
pixel_engine_font_y_pos$DEQ,
pixel_engine_font_y_pos$EMPTY_N,
pixel_engine_font_y_pos$ENQ,
pixel_engine_font_y_pos$FULL_N;
// ports of submodule pixel_engine_fontbits
wire [7 : 0] pixel_engine_fontbits$D_IN, pixel_engine_fontbits$D_OUT;
wire pixel_engine_fontbits$CLR,
pixel_engine_fontbits$DEQ,
pixel_engine_fontbits$EMPTY_N,
pixel_engine_fontbits$ENQ,
pixel_engine_fontbits$FULL_N;
// ports of submodule pixel_engine_fontrom_rom
wire [11 : 0] pixel_engine_fontrom_rom$v_addr;
wire [7 : 0] pixel_engine_fontrom_rom$v_data;
wire pixel_engine_fontrom_rom$v_en;
// ports of submodule pixel_engine_fontrom_seq_fifo
wire pixel_engine_fontrom_seq_fifo$CLR,
pixel_engine_fontrom_seq_fifo$DEQ,
pixel_engine_fontrom_seq_fifo$D_IN,
pixel_engine_fontrom_seq_fifo$EMPTY_N,
pixel_engine_fontrom_seq_fifo$ENQ,
pixel_engine_fontrom_seq_fifo$FULL_N;
// ports of submodule pixel_engine_pixpos
wire [1 : 0] pixel_engine_pixpos$D_IN, pixel_engine_pixpos$D_OUT;
wire pixel_engine_pixpos$CLR,
pixel_engine_pixpos$DEQ,
pixel_engine_pixpos$EMPTY_N,
pixel_engine_pixpos$ENQ,
pixel_engine_pixpos$FULL_N;
// ports of submodule pixel_engine_req
wire [61 : 0] pixel_engine_req$D_IN, pixel_engine_req$D_OUT;
wire pixel_engine_req$CLR,
pixel_engine_req$DEQ,
pixel_engine_req$EMPTY_N,
pixel_engine_req$ENQ,
pixel_engine_req$FULL_N;
// ports of submodule pixel_engine_ssram_req
wire [61 : 0] pixel_engine_ssram_req$D_IN, pixel_engine_ssram_req$D_OUT;
wire pixel_engine_ssram_req$CLR,
pixel_engine_ssram_req$DEQ,
pixel_engine_ssram_req$EMPTY_N,
pixel_engine_ssram_req$ENQ,
pixel_engine_ssram_req$FULL_N;
// ports of submodule pixel_engine_ssram_resp
wire [31 : 0] pixel_engine_ssram_resp$D_IN, pixel_engine_ssram_resp$D_OUT;
wire pixel_engine_ssram_resp$CLR,
pixel_engine_ssram_resp$DEQ,
pixel_engine_ssram_resp$EMPTY_N,
pixel_engine_ssram_resp$ENQ,
pixel_engine_ssram_resp$FULL_N;
// ports of submodule pixel_engine_two_chars
wire [31 : 0] pixel_engine_two_chars$D_IN, pixel_engine_two_chars$D_OUT;
wire pixel_engine_two_chars$CLR,
pixel_engine_two_chars$DEQ,
pixel_engine_two_chars$EMPTY_N,
pixel_engine_two_chars$ENQ,
pixel_engine_two_chars$FULL_N;
// ports of submodule response_for_avalon
wire response_for_avalon$CLR,
response_for_avalon$DEQ,
response_for_avalon$D_IN,
response_for_avalon$D_OUT,
response_for_avalon$EMPTY_N,
response_for_avalon$ENQ,
response_for_avalon$FULL_N;
// ports of submodule touch
wire [47 : 0] touch$D_IN, touch$D_OUT;
wire touch$CLR, touch$DEQ, touch$EMPTY_N, touch$ENQ, touch$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_arbitrate_requests,
CAN_FIRE_RL_avalon_request_splitter,
CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests,
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests,
CAN_FIRE_RL_avalon_slave_wire_up_avalonwait,
CAN_FIRE_RL_forward_upper_bytes,
CAN_FIRE_RL_mem_forward_requests_flash,
CAN_FIRE_RL_mem_forward_requests_ssram,
CAN_FIRE_RL_mem_pipe_stage_0,
CAN_FIRE_RL_mem_pipe_stage_1,
CAN_FIRE_RL_mem_pipe_stage_2,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_pixel_engine_buffer_characters_read,
CAN_FIRE_RL_pixel_engine_char_pixels,
CAN_FIRE_RL_pixel_engine_demux_two_chars,
CAN_FIRE_RL_pixel_engine_forward_pixel_values,
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut,
CAN_FIRE_RL_pixel_engine_request_char_values,
CAN_FIRE_RL_pixel_engine_request_pixel_values,
CAN_FIRE_RL_receive_mem_responses,
CAN_FIRE_RL_return_control_register_response,
CAN_FIRE_RL_return_mem_response,
CAN_FIRE_aso_stream_out,
CAN_FIRE_avs_s0,
CAN_FIRE_coe_fsm_d,
CAN_FIRE_coe_touch,
WILL_FIRE_RL_arbitrate_requests,
WILL_FIRE_RL_avalon_request_splitter,
WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests,
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests,
WILL_FIRE_RL_avalon_slave_wire_up_avalonwait,
WILL_FIRE_RL_forward_upper_bytes,
WILL_FIRE_RL_mem_forward_requests_flash,
WILL_FIRE_RL_mem_forward_requests_ssram,
WILL_FIRE_RL_mem_pipe_stage_0,
WILL_FIRE_RL_mem_pipe_stage_1,
WILL_FIRE_RL_mem_pipe_stage_2,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_pixel_engine_buffer_characters_read,
WILL_FIRE_RL_pixel_engine_char_pixels,
WILL_FIRE_RL_pixel_engine_demux_two_chars,
WILL_FIRE_RL_pixel_engine_forward_pixel_values,
WILL_FIRE_RL_pixel_engine_mkConnectionGetPut,
WILL_FIRE_RL_pixel_engine_request_char_values,
WILL_FIRE_RL_pixel_engine_request_pixel_values,
WILL_FIRE_RL_receive_mem_responses,
WILL_FIRE_RL_return_control_register_response,
WILL_FIRE_RL_return_mem_response,
WILL_FIRE_aso_stream_out,
WILL_FIRE_avs_s0,
WILL_FIRE_coe_fsm_d,
WILL_FIRE_coe_touch;
// inputs to muxes for submodule ports
wire [61 : 0] MUX_pixel_engine_ssram_req$enq_1__VAL_1,
MUX_pixel_engine_ssram_req$enq_1__VAL_2;
wire [44 : 0] MUX_mem_req$enq_1__VAL_1;
wire [16 : 0] MUX_mem_resp$enq_1__VAL_1, MUX_mem_resp$enq_1__VAL_2;
wire [15 : 0] MUX_mem_fsm_dout_dw$wset_1__VAL_2;
wire MUX_avalon_slave_datareturned$wset_1__SEL_1,
MUX_mem_fsm_a_w$wset_1__SEL_1,
MUX_mem_resp$enq_1__SEL_1;
// remaining internal signals
reg [23 : 0] IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654,
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652;
wire [49 : 0] IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55;
wire [31 : 0] IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669,
b__h14135;
wire [25 : 0] x__h13071, x_addr__h13123;
wire [24 : 0] IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645,
next_addr__h3065,
next_char_y___2__h3016,
next_char_y__h2903,
x1_avValue_addr__h12990,
x__h3050,
y__h3053;
wire [8 : 0] minus__h3867,
minus__h4723,
minus__h5121,
minus__h5335,
minus__h5712,
minus__h5926,
sum__h3311,
sum__h3767,
sum__h4866,
sum__h5021,
sum__h5457,
sum__h5612;
wire [7 : 0] a__h3765,
a__h3866,
a__h5019,
a__h5120,
a__h5610,
a__h5711,
b__h3310,
b__h3766,
b__h4865,
b__h5020,
b__h5456,
b__h5611,
bitmap_col_chan_b__h3300,
bitmap_col_chan_g__h3299,
bitmap_col_chan_r__h3298,
char__h6798,
char_alpha__h3227,
x__h2840,
x__h7183;
wire [5 : 0] next_x_two_char_addr__h2897, next_x_two_char_addr__h2901;
wire [3 : 0] IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668,
next_font_y___2__h2969;
wire [2 : 0] x__h7767;
wire [1 : 0] IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710;
wire IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611,
mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345,
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706,
response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529,
x__h7731;
// action method avs_s0
assign CAN_FIRE_avs_s0 = 1'd1 ;
assign WILL_FIRE_avs_s0 = 1'd1 ;
// value method avs_s0_readdata
assign avs_s0_readdata =
avalon_slave_avalonwait_end_read$whas ?
b__h14135 :
32'hDEADDEAD ;
// value method avs_s0_waitrequest
assign avs_s0_waitrequest =
avs_s0_read && !avalon_slave_avalonwait_end_read$whas ||
avs_s0_write && !avalon_slave_avalonwait_end_write$whas ;
// value method aso_stream_out_data
assign aso_stream_out_data =
(!CAN_FIRE_RL_pixel_engine_forward_pixel_values ||
!pixel_engine_lcd_stream_data_dw$wget[24]) ?
24'd0 :
pixel_engine_lcd_stream_data_dw$wget[23:0] ;
// value method aso_stream_out_valid
assign aso_stream_out_valid =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_lcd_stream_data_dw$wget[24] ;
// action method aso_stream_out
assign CAN_FIRE_aso_stream_out = 1'd1 ;
assign WILL_FIRE_aso_stream_out = 1'd1 ;
// value method aso_stream_out_startofpacket
assign aso_stream_out_startofpacket =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[1] ;
// value method aso_stream_out_endofpacket
assign aso_stream_out_endofpacket =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[0] ;
// value method coe_ssram_adv
assign coe_ssram_adv = 1'd0 ;
// value method coe_ssram_bwa_n
assign coe_ssram_bwa_n =
!IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710[0] ;
// value method coe_ssram_bwb_n
assign coe_ssram_bwb_n =
!IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710[1] ;
// value method coe_ssram_ce_n
assign coe_ssram_ce_n = !mem_ssram_ce_pw$whas ;
// value method coe_ssram_cke_n
assign coe_ssram_cke_n = 1'd0 ;
// value method coe_ssram_oe_n
assign coe_ssram_oe_n = mem_fsm_dout_dw$whas && mem_fsm_dout_req_dw$wget ;
// value method coe_ssram_we_n
assign coe_ssram_we_n =
!CAN_FIRE_RL_mem_forward_requests_ssram || !mem_req$D_OUT[44] ;
// value method coe_fsm_a
assign coe_fsm_a = mem_fsm_a_w$whas ? mem_req$D_OUT[40:16] : 25'd0 ;
// value method coe_fsm_d_out
assign coe_fsm_d_out =
mem_fsm_dout_dw$whas ? mem_fsm_dout_dw$wget : 16'hDEAD ;
// action method coe_fsm_d
assign CAN_FIRE_coe_fsm_d = 1'd1 ;
assign WILL_FIRE_coe_fsm_d = 1'd1 ;
// value method coe_fsm_dout_req
assign coe_fsm_dout_req = mem_fsm_dout_dw$whas && mem_fsm_dout_req_dw$wget ;
// value method coe_flash_adv_n
assign coe_flash_adv_n = !MUX_mem_fsm_a_w$wset_1__SEL_1 ;
// value method coe_flash_ce_n
assign coe_flash_ce_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_flash_ce_n_dw$wget ;
// value method coe_flash_clk
assign coe_flash_clk = 1'd0 ;
// value method coe_flash_oe_n
assign coe_flash_oe_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_req$D_OUT[44] ;
// value method coe_flash_we_n
assign coe_flash_we_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_flash_we_n_dw$wget ;
// action method coe_touch
assign CAN_FIRE_coe_touch = 1'd1 ;
assign WILL_FIRE_coe_touch = 1'd1 ;
// submodule avalon_control_reg_resp
FIFO1 #(.width(32'd33),
.guarded(32'd1)) avalon_control_reg_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_control_reg_resp$D_IN),
.ENQ(avalon_control_reg_resp$ENQ),
.DEQ(avalon_control_reg_resp$DEQ),
.CLR(avalon_control_reg_resp$CLR),
.D_OUT(avalon_control_reg_resp$D_OUT),
.FULL_N(avalon_control_reg_resp$FULL_N),
.EMPTY_N(avalon_control_reg_resp$EMPTY_N));
// submodule avalon_mem_resp
FIFO1 #(.width(32'd33),
.guarded(32'd1)) avalon_mem_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_mem_resp$D_IN),
.ENQ(avalon_mem_resp$ENQ),
.DEQ(avalon_mem_resp$DEQ),
.CLR(avalon_mem_resp$CLR),
.D_OUT(avalon_mem_resp$D_OUT),
.FULL_N(avalon_mem_resp$FULL_N),
.EMPTY_N(avalon_mem_resp$EMPTY_N));
// submodule avalon_req
FIFO2 #(.width(32'd62),
.guarded(32'd1)) avalon_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_req$D_IN),
.ENQ(avalon_req$ENQ),
.DEQ(avalon_req$DEQ),
.CLR(avalon_req$CLR),
.D_OUT(avalon_req$D_OUT),
.FULL_N(avalon_req$FULL_N),
.EMPTY_N(avalon_req$EMPTY_N));
// submodule avalon_slave_outbuf
FIFO2 #(.width(32'd63),
.guarded(32'd1)) avalon_slave_outbuf(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_slave_outbuf$D_IN),
.ENQ(avalon_slave_outbuf$ENQ),
.DEQ(avalon_slave_outbuf$DEQ),
.CLR(avalon_slave_outbuf$CLR),
.D_OUT(avalon_slave_outbuf$D_OUT),
.FULL_N(avalon_slave_outbuf$FULL_N),
.EMPTY_N(avalon_slave_outbuf$EMPTY_N));
// submodule lower_16b_returned
FIFO2 #(.width(32'd17),
.guarded(32'd0)) lower_16b_returned(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(lower_16b_returned$D_IN),
.ENQ(lower_16b_returned$ENQ),
.DEQ(lower_16b_returned$DEQ),
.CLR(lower_16b_returned$CLR),
.D_OUT(lower_16b_returned$D_OUT),
.FULL_N(),
.EMPTY_N(lower_16b_returned$EMPTY_N));
// submodule mem_pipe0
FIFOL1 #(.width(32'd17)) mem_pipe0(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe0$D_IN),
.ENQ(mem_pipe0$ENQ),
.DEQ(mem_pipe0$DEQ),
.CLR(mem_pipe0$CLR),
.D_OUT(mem_pipe0$D_OUT),
.FULL_N(mem_pipe0$FULL_N),
.EMPTY_N(mem_pipe0$EMPTY_N));
// submodule mem_pipe1
FIFOL1 #(.width(32'd17)) mem_pipe1(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe1$D_IN),
.ENQ(mem_pipe1$ENQ),
.DEQ(mem_pipe1$DEQ),
.CLR(mem_pipe1$CLR),
.D_OUT(mem_pipe1$D_OUT),
.FULL_N(mem_pipe1$FULL_N),
.EMPTY_N(mem_pipe1$EMPTY_N));
// submodule mem_pipe2
FIFOL1 #(.width(32'd17)) mem_pipe2(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe2$D_IN),
.ENQ(mem_pipe2$ENQ),
.DEQ(mem_pipe2$DEQ),
.CLR(mem_pipe2$CLR),
.D_OUT(mem_pipe2$D_OUT),
.FULL_N(mem_pipe2$FULL_N),
.EMPTY_N(mem_pipe2$EMPTY_N));
// submodule mem_req
FIFOL1 #(.width(32'd45)) mem_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_req$D_IN),
.ENQ(mem_req$ENQ),
.DEQ(mem_req$DEQ),
.CLR(mem_req$CLR),
.D_OUT(mem_req$D_OUT),
.FULL_N(mem_req$FULL_N),
.EMPTY_N(mem_req$EMPTY_N));
// submodule mem_resp
FIFOL1 #(.width(32'd17)) mem_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_resp$D_IN),
.ENQ(mem_resp$ENQ),
.DEQ(mem_resp$DEQ),
.CLR(mem_resp$CLR),
.D_OUT(mem_resp$D_OUT),
.FULL_N(mem_resp$FULL_N),
.EMPTY_N(mem_resp$EMPTY_N));
// submodule mem_upper_16b_request
FIFO2 #(.width(32'd45),
.guarded(32'd0)) mem_upper_16b_request(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_upper_16b_request$D_IN),
.ENQ(mem_upper_16b_request$ENQ),
.DEQ(mem_upper_16b_request$DEQ),
.CLR(mem_upper_16b_request$CLR),
.D_OUT(mem_upper_16b_request$D_OUT),
.FULL_N(),
.EMPTY_N(mem_upper_16b_request$EMPTY_N));
// submodule pixel_engine_char_colour
FIFO2 #(.width(32'd10),
.guarded(32'd1)) pixel_engine_char_colour(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_colour$D_IN),
.ENQ(pixel_engine_char_colour$ENQ),
.DEQ(pixel_engine_char_colour$DEQ),
.CLR(pixel_engine_char_colour$CLR),
.D_OUT(pixel_engine_char_colour$D_OUT),
.FULL_N(pixel_engine_char_colour$FULL_N),
.EMPTY_N(pixel_engine_char_colour$EMPTY_N));
// submodule pixel_engine_char_pixel
FIFO2 #(.width(32'd10),
.guarded(32'd1)) pixel_engine_char_pixel(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_pixel$D_IN),
.ENQ(pixel_engine_char_pixel$ENQ),
.DEQ(pixel_engine_char_pixel$DEQ),
.CLR(pixel_engine_char_pixel$CLR),
.D_OUT(pixel_engine_char_pixel$D_OUT),
.FULL_N(pixel_engine_char_pixel$FULL_N),
.EMPTY_N(pixel_engine_char_pixel$EMPTY_N));
// submodule pixel_engine_char_pos
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) pixel_engine_char_pos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_pos$D_IN),
.ENQ(pixel_engine_char_pos$ENQ),
.DEQ(pixel_engine_char_pos$DEQ),
.CLR(pixel_engine_char_pos$CLR),
.D_OUT(pixel_engine_char_pos$D_OUT),
.FULL_N(pixel_engine_char_pos$FULL_N),
.EMPTY_N(pixel_engine_char_pos$EMPTY_N));
// submodule pixel_engine_chars_read
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_chars_read(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_chars_read$D_IN),
.ENQ(pixel_engine_chars_read$ENQ),
.DEQ(pixel_engine_chars_read$DEQ),
.CLR(pixel_engine_chars_read$CLR),
.D_OUT(pixel_engine_chars_read$D_OUT),
.FULL_N(pixel_engine_chars_read$FULL_N),
.EMPTY_N(pixel_engine_chars_read$EMPTY_N));
// submodule pixel_engine_font_y_pos
FIFO2 #(.width(32'd4),
.guarded(32'd1)) pixel_engine_font_y_pos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_font_y_pos$D_IN),
.ENQ(pixel_engine_font_y_pos$ENQ),
.DEQ(pixel_engine_font_y_pos$DEQ),
.CLR(pixel_engine_font_y_pos$CLR),
.D_OUT(pixel_engine_font_y_pos$D_OUT),
.FULL_N(pixel_engine_font_y_pos$FULL_N),
.EMPTY_N(pixel_engine_font_y_pos$EMPTY_N));
// submodule pixel_engine_fontbits
FIFO2 #(.width(32'd8),
.guarded(32'd1)) pixel_engine_fontbits(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_fontbits$D_IN),
.ENQ(pixel_engine_fontbits$ENQ),
.DEQ(pixel_engine_fontbits$DEQ),
.CLR(pixel_engine_fontbits$CLR),
.D_OUT(pixel_engine_fontbits$D_OUT),
.FULL_N(pixel_engine_fontbits$FULL_N),
.EMPTY_N(pixel_engine_fontbits$EMPTY_N));
// submodule pixel_engine_fontrom_rom
VerilogAlteraROM #(.FILENAME("hdl/vgafontrom.mif"),
.ADDRESS_WIDTH(32'd12),
.DATA_WIDTH(32'd8)) pixel_engine_fontrom_rom(.clk(csi_clockreset_clk),
.v_addr(pixel_engine_fontrom_rom$v_addr),
.v_en(pixel_engine_fontrom_rom$v_en),
.v_data(pixel_engine_fontrom_rom$v_data));
// submodule pixel_engine_fontrom_seq_fifo
FIFO1 #(.width(32'd1),
.guarded(32'd1)) pixel_engine_fontrom_seq_fifo(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_fontrom_seq_fifo$D_IN),
.ENQ(pixel_engine_fontrom_seq_fifo$ENQ),
.DEQ(pixel_engine_fontrom_seq_fifo$DEQ),
.CLR(pixel_engine_fontrom_seq_fifo$CLR),
.D_OUT(),
.FULL_N(pixel_engine_fontrom_seq_fifo$FULL_N),
.EMPTY_N(pixel_engine_fontrom_seq_fifo$EMPTY_N));
// submodule pixel_engine_pixpos
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_pixpos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_pixpos$D_IN),
.ENQ(pixel_engine_pixpos$ENQ),
.DEQ(pixel_engine_pixpos$DEQ),
.CLR(pixel_engine_pixpos$CLR),
.D_OUT(pixel_engine_pixpos$D_OUT),
.FULL_N(pixel_engine_pixpos$FULL_N),
.EMPTY_N(pixel_engine_pixpos$EMPTY_N));
// submodule pixel_engine_req
FIFO2 #(.width(32'd62),
.guarded(32'd1)) pixel_engine_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_req$D_IN),
.ENQ(pixel_engine_req$ENQ),
.DEQ(pixel_engine_req$DEQ),
.CLR(pixel_engine_req$CLR),
.D_OUT(pixel_engine_req$D_OUT),
.FULL_N(pixel_engine_req$FULL_N),
.EMPTY_N(pixel_engine_req$EMPTY_N));
// submodule pixel_engine_ssram_req
FIFOL1 #(.width(32'd62)) pixel_engine_ssram_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_ssram_req$D_IN),
.ENQ(pixel_engine_ssram_req$ENQ),
.DEQ(pixel_engine_ssram_req$DEQ),
.CLR(pixel_engine_ssram_req$CLR),
.D_OUT(pixel_engine_ssram_req$D_OUT),
.FULL_N(pixel_engine_ssram_req$FULL_N),
.EMPTY_N(pixel_engine_ssram_req$EMPTY_N));
// submodule pixel_engine_ssram_resp
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_ssram_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_ssram_resp$D_IN),
.ENQ(pixel_engine_ssram_resp$ENQ),
.DEQ(pixel_engine_ssram_resp$DEQ),
.CLR(pixel_engine_ssram_resp$CLR),
.D_OUT(pixel_engine_ssram_resp$D_OUT),
.FULL_N(pixel_engine_ssram_resp$FULL_N),
.EMPTY_N(pixel_engine_ssram_resp$EMPTY_N));
// submodule pixel_engine_two_chars
FIFO2 #(.width(32'd32),
.guarded(32'd1)) pixel_engine_two_chars(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_two_chars$D_IN),
.ENQ(pixel_engine_two_chars$ENQ),
.DEQ(pixel_engine_two_chars$DEQ),
.CLR(pixel_engine_two_chars$CLR),
.D_OUT(pixel_engine_two_chars$D_OUT),
.FULL_N(pixel_engine_two_chars$FULL_N),
.EMPTY_N(pixel_engine_two_chars$EMPTY_N));
// submodule response_for_avalon
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) response_for_avalon(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(response_for_avalon$D_IN),
.ENQ(response_for_avalon$ENQ),
.DEQ(response_for_avalon$DEQ),
.CLR(response_for_avalon$CLR),
.D_OUT(response_for_avalon$D_OUT),
.FULL_N(response_for_avalon$FULL_N),
.EMPTY_N(response_for_avalon$EMPTY_N));
// submodule touch
FIFO2 #(.width(32'd48),
.guarded(32'd0)) touch(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(touch$D_IN),
.ENQ(touch$ENQ),
.DEQ(touch$DEQ),
.CLR(touch$CLR),
.D_OUT(touch$D_OUT),
.FULL_N(touch$FULL_N),
.EMPTY_N(touch$EMPTY_N));
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
pixel_engine_ssram_req$EMPTY_N && pixel_engine_req$FULL_N ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_return_control_register_response
assign CAN_FIRE_RL_return_control_register_response =
avalon_control_reg_resp$EMPTY_N && !avalon_mem_resp$EMPTY_N ;
assign WILL_FIRE_RL_return_control_register_response =
CAN_FIRE_RL_return_control_register_response ;
// rule RL_return_mem_response
assign CAN_FIRE_RL_return_mem_response = avalon_mem_resp$EMPTY_N ;
assign WILL_FIRE_RL_return_mem_response = avalon_mem_resp$EMPTY_N ;
// rule RL_receive_mem_responses
assign CAN_FIRE_RL_receive_mem_responses =
mem_resp$EMPTY_N &&
(!lower_16b_returned$EMPTY_N ||
response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529) ;
assign WILL_FIRE_RL_receive_mem_responses =
CAN_FIRE_RL_receive_mem_responses ;
// rule RL_avalon_slave_hanlde_bus_requests
assign CAN_FIRE_RL_avalon_slave_hanlde_bus_requests =
avalon_slave_outbuf$FULL_N && (avs_s0_read || avs_s0_write) &&
!avalon_slave_ignore_further_requests ;
assign WILL_FIRE_RL_avalon_slave_hanlde_bus_requests =
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests ;
// rule RL_avalon_slave_wire_up_avalonwait
assign CAN_FIRE_RL_avalon_slave_wire_up_avalonwait = 1'd1 ;
assign WILL_FIRE_RL_avalon_slave_wire_up_avalonwait = 1'd1 ;
// rule RL_avalon_slave_cancel_ingore_further_requests
assign CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests =
!avalon_slave_avalonwait$wget &&
avalon_slave_ignore_further_requests ;
assign WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests =
CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests ;
// rule RL_pixel_engine_request_char_values
assign CAN_FIRE_RL_pixel_engine_request_char_values =
pixel_engine_ssram_req$FULL_N &&
pixel_engine_font_y_pos$FULL_N &&
pixel_engine_char_pos$FULL_N &&
pixel_engine_chars_read$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_request_char_values =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// rule RL_pixel_engine_request_pixel_values
assign CAN_FIRE_RL_pixel_engine_request_pixel_values =
pixel_engine_ssram_req$FULL_N &&
pixel_engine_chars_read$FULL_N &&
pixel_engine_pixpos$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_request_pixel_values =
CAN_FIRE_RL_pixel_engine_request_pixel_values &&
!WILL_FIRE_RL_pixel_engine_request_char_values ;
// rule RL_pixel_engine_forward_pixel_values
assign CAN_FIRE_RL_pixel_engine_forward_pixel_values =
pixel_engine_chars_read$EMPTY_N && aso_stream_out_ready &&
pixel_engine_char_pixel$EMPTY_N &&
pixel_engine_ssram_resp$EMPTY_N &&
pixel_engine_pixpos$EMPTY_N &&
!pixel_engine_chars_read$D_OUT ;
assign WILL_FIRE_RL_pixel_engine_forward_pixel_values =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
// rule RL_pixel_engine_buffer_characters_read
assign CAN_FIRE_RL_pixel_engine_buffer_characters_read =
pixel_engine_chars_read$EMPTY_N &&
pixel_engine_ssram_resp$EMPTY_N &&
pixel_engine_two_chars$FULL_N &&
pixel_engine_chars_read$D_OUT ;
assign WILL_FIRE_RL_pixel_engine_buffer_characters_read =
CAN_FIRE_RL_pixel_engine_buffer_characters_read ;
// rule RL_pixel_engine_mkConnectionGetPut
assign CAN_FIRE_RL_pixel_engine_mkConnectionGetPut =
pixel_engine_fontrom_seq_fifo$EMPTY_N &&
pixel_engine_fontbits$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_mkConnectionGetPut =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
// rule RL_pixel_engine_demux_two_chars
assign CAN_FIRE_RL_pixel_engine_demux_two_chars =
pixel_engine_two_chars$EMPTY_N &&
pixel_engine_font_y_pos$EMPTY_N &&
pixel_engine_fontrom_seq_fifo$FULL_N &&
pixel_engine_char_colour$FULL_N &&
pixel_engine_char_pos$EMPTY_N ;
assign WILL_FIRE_RL_pixel_engine_demux_two_chars =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// rule RL_avalon_request_splitter
assign CAN_FIRE_RL_avalon_request_splitter =
avalon_slave_outbuf$EMPTY_N &&
((avalon_slave_outbuf$D_OUT[60:54] == 7'd4) ?
avalon_control_reg_resp$FULL_N :
avalon_req$FULL_N) ;
assign WILL_FIRE_RL_avalon_request_splitter =
CAN_FIRE_RL_avalon_request_splitter ;
// rule RL_pixel_engine_char_pixels
assign CAN_FIRE_RL_pixel_engine_char_pixels =
pixel_engine_char_pixel$FULL_N &&
pixel_engine_char_colour$EMPTY_N &&
pixel_engine_fontbits$EMPTY_N ;
assign WILL_FIRE_RL_pixel_engine_char_pixels =
CAN_FIRE_RL_pixel_engine_char_pixels ;
// rule RL_mem_pipe_stage_2
assign CAN_FIRE_RL_mem_pipe_stage_2 = mem_resp$FULL_N && mem_pipe2$EMPTY_N ;
assign WILL_FIRE_RL_mem_pipe_stage_2 = CAN_FIRE_RL_mem_pipe_stage_2 ;
// rule RL_mem_pipe_stage_1
assign CAN_FIRE_RL_mem_pipe_stage_1 =
mem_pipe1$EMPTY_N && mem_pipe2$FULL_N ;
assign WILL_FIRE_RL_mem_pipe_stage_1 = CAN_FIRE_RL_mem_pipe_stage_1 ;
// rule RL_mem_pipe_stage_0
assign CAN_FIRE_RL_mem_pipe_stage_0 =
mem_pipe1$FULL_N && mem_pipe0$EMPTY_N ;
assign WILL_FIRE_RL_mem_pipe_stage_0 = CAN_FIRE_RL_mem_pipe_stage_0 ;
// rule RL_mem_forward_requests_ssram
assign CAN_FIRE_RL_mem_forward_requests_ssram =
mem_req$EMPTY_N && mem_pipe0$FULL_N && !mem_req$D_OUT[41] ;
assign WILL_FIRE_RL_mem_forward_requests_ssram =
CAN_FIRE_RL_mem_forward_requests_ssram ;
// rule RL_mem_forward_requests_flash
assign CAN_FIRE_RL_mem_forward_requests_flash =
mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345 &&
mem_req$D_OUT[41] &&
!mem_ssram_ce_pw$whas ;
assign WILL_FIRE_RL_mem_forward_requests_flash =
CAN_FIRE_RL_mem_forward_requests_flash &&
!WILL_FIRE_RL_mem_pipe_stage_1 &&
!WILL_FIRE_RL_mem_pipe_stage_2 ;
// rule RL_arbitrate_requests
assign CAN_FIRE_RL_arbitrate_requests =
response_for_avalon$FULL_N && mem_req$FULL_N &&
!mem_upper_16b_request$EMPTY_N &&
(pixel_engine_req$EMPTY_N || avalon_req$EMPTY_N) ;
assign WILL_FIRE_RL_arbitrate_requests = CAN_FIRE_RL_arbitrate_requests ;
// rule RL_forward_upper_bytes
assign CAN_FIRE_RL_forward_upper_bytes =
mem_req$FULL_N && mem_upper_16b_request$EMPTY_N ;
assign WILL_FIRE_RL_forward_upper_bytes = CAN_FIRE_RL_forward_upper_bytes ;
// inputs to muxes for submodule ports
assign MUX_avalon_slave_datareturned$wset_1__SEL_1 =
avalon_mem_resp$EMPTY_N && avalon_mem_resp$D_OUT[32] ;
assign MUX_mem_fsm_a_w$wset_1__SEL_1 =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ;
assign MUX_mem_resp$enq_1__SEL_1 =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ;
assign MUX_mem_fsm_dout_dw$wset_1__VAL_2 =
mem_pipe1$D_OUT[16] ? mem_pipe1$D_OUT[15:0] : 16'hEEEE ;
assign MUX_mem_req$enq_1__VAL_1 =
{ IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668[1:0],
x__h13071,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669[15:0] } ;
assign MUX_mem_resp$enq_1__VAL_1 =
(mem_req$D_OUT[43:42] == 2'b0) ?
(mem_req$D_OUT[44] ? 17'd43690 : 17'd65536) :
{ !mem_req$D_OUT[44], coe_fsm_d_in } ;
assign MUX_mem_resp$enq_1__VAL_2 = { !mem_pipe2$D_OUT[16], coe_fsm_d_in } ;
assign MUX_pixel_engine_ssram_req$enq_1__VAL_1 =
{ 5'd15, pixel_engine_char_addr, 32'd0 } ;
assign MUX_pixel_engine_ssram_req$enq_1__VAL_2 =
{ 5'd15, pixel_engine_addr, 32'd0 } ;
// inlined wires
assign pixel_engine_lcd_stream_data_dw$wget =
{ 1'd1,
bitmap_col_chan_r__h3298,
bitmap_col_chan_g__h3299,
bitmap_col_chan_b__h3300 } ;
assign mem_fsm_a_w$whas =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign mem_fsm_dout_dw$wget =
MUX_mem_fsm_a_w$wset_1__SEL_1 ?
mem_req$D_OUT[15:0] :
MUX_mem_fsm_dout_dw$wset_1__VAL_2 ;
assign mem_fsm_dout_dw$whas =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ||
WILL_FIRE_RL_mem_pipe_stage_1 ;
assign mem_fsm_dout_req_dw$wget =
MUX_mem_fsm_a_w$wset_1__SEL_1 ?
mem_req$D_OUT[44] :
mem_pipe1$D_OUT[16] ;
assign mem_flash_ce_n_dw$wget =
mem_req$D_OUT[44] && mem_flash_timer == 4'd10 ;
assign mem_flash_we_n_dw$wget =
!mem_req$D_OUT[44] || mem_flash_timer == 4'd10 ||
mem_flash_timer == 4'd9 ;
assign avalon_slave_avalonwait_end_read$whas =
avalon_mem_resp$EMPTY_N && avalon_mem_resp$D_OUT[32] ||
WILL_FIRE_RL_return_control_register_response &&
avalon_control_reg_resp$D_OUT[32] ;
assign avalon_slave_avalonwait_end_write$whas =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests && avs_s0_write ;
assign mem_ssram_ce_pw$whas =
WILL_FIRE_RL_mem_pipe_stage_2 || WILL_FIRE_RL_mem_pipe_stage_1 ||
WILL_FIRE_RL_mem_pipe_stage_0 ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign avalon_slave_avalonwait$wget =
avs_s0_read && !avalon_slave_avalonwait_end_read$whas ||
avs_s0_write && !avalon_slave_avalonwait_end_write$whas ;
// register avalon_slave_ignore_further_requests
assign avalon_slave_ignore_further_requests$D_IN =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests && avs_s0_read ;
assign avalon_slave_ignore_further_requests$EN =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests ||
WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests ;
// register mem_flash_timer
assign mem_flash_timer$D_IN =
(mem_flash_timer == 4'd10) ? 4'd0 : mem_flash_timer + 4'd1 ;
assign mem_flash_timer$EN = MUX_mem_fsm_a_w$wset_1__SEL_1 ;
// register pixel_engine_addr
assign pixel_engine_addr$D_IN =
(pixel_engine_addr == 25'd383999) ? 25'd0 : next_addr__h3065 ;
assign pixel_engine_addr$EN =
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
// register pixel_engine_char_addr
assign pixel_engine_char_addr$D_IN =
x__h3050 +
IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55[24:0] ;
assign pixel_engine_char_addr$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_char_base
assign pixel_engine_char_base$D_IN = avalon_slave_outbuf$D_OUT[30:6] ;
assign pixel_engine_char_base$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_char_ctr
assign pixel_engine_char_ctr$D_IN = pixel_engine_char_ctr + 1'd1 ;
assign pixel_engine_char_ctr$EN = CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// register pixel_engine_char_end
assign pixel_engine_char_end$D_IN =
avalon_slave_outbuf$D_OUT[30:6] + 25'd6000 ;
assign pixel_engine_char_end$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_char_x_pos
assign pixel_engine_char_x_pos$D_IN = pixel_engine_char_x_pos + 3'd1 ;
assign pixel_engine_char_x_pos$EN = CAN_FIRE_RL_pixel_engine_char_pixels ;
// register pixel_engine_char_x_two_char
assign pixel_engine_char_x_two_char$D_IN = next_x_two_char_addr__h2901 ;
assign pixel_engine_char_x_two_char$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_char_y
assign pixel_engine_char_y$D_IN = next_char_y__h2903 ;
assign pixel_engine_char_y$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_cursor_pos
assign pixel_engine_cursor_pos$D_IN = avalon_slave_outbuf$D_OUT[19:4] ;
assign pixel_engine_cursor_pos$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd1 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_fb_blend
assign pixel_engine_fb_blend$D_IN = avalon_slave_outbuf$D_OUT[35:4] ;
assign pixel_engine_fb_blend$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd0 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_flash_col
assign pixel_engine_flash_col$D_IN = pixel_engine_flash_col + 6'd1 ;
assign pixel_engine_flash_col$EN =
WILL_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[0] ;
// register pixel_engine_font_y
assign pixel_engine_font_y$D_IN =
(pixel_engine_char_x_two_char == 6'd49) ?
((pixel_engine_font_y == 4'd11) ?
4'd0 :
next_font_y___2__h2969) :
pixel_engine_font_y ;
assign pixel_engine_font_y$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register prev_touch_info
assign prev_touch_info$D_IN =
{ coe_touch_x1,
coe_touch_y1,
coe_touch_x2,
coe_touch_y2,
coe_touch_count_gesture } ;
assign prev_touch_info$EN =
coe_touch_touch_valid &&
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 &&
touch$FULL_N ;
// submodule avalon_control_reg_resp
assign avalon_control_reg_resp$D_IN =
{ avalon_slave_outbuf$D_OUT[62:61] == 2'd0,
(avalon_slave_outbuf$D_OUT[53:36] == 18'd0 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
pixel_engine_fb_blend :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458 } ;
assign avalon_control_reg_resp$ENQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 ;
assign avalon_control_reg_resp$DEQ =
CAN_FIRE_RL_return_control_register_response ;
assign avalon_control_reg_resp$CLR = 1'b0 ;
// submodule avalon_mem_resp
assign avalon_mem_resp$D_IN =
{ mem_resp$D_OUT[16] && lower_16b_returned$D_OUT[16],
mem_resp$D_OUT[15:0],
lower_16b_returned$D_OUT[15:0] } ;
assign avalon_mem_resp$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N &&
response_for_avalon$D_OUT ;
assign avalon_mem_resp$DEQ = avalon_mem_resp$EMPTY_N ;
assign avalon_mem_resp$CLR = 1'b0 ;
// submodule avalon_req
assign avalon_req$D_IN =
{ avalon_slave_outbuf$D_OUT[62:61] == 2'd1,
avalon_slave_outbuf$D_OUT[3:0],
avalon_slave_outbuf$D_OUT[60:4] } ;
assign avalon_req$ENQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] != 7'd4 ;
assign avalon_req$DEQ =
WILL_FIRE_RL_arbitrate_requests && !pixel_engine_req$EMPTY_N ;
assign avalon_req$CLR = 1'b0 ;
// submodule avalon_slave_outbuf
assign avalon_slave_outbuf$D_IN =
{ avs_s0_read ? 2'd0 : 2'd1,
avs_s0_address,
avs_s0_writedata,
avs_s0_byteenable } ;
assign avalon_slave_outbuf$ENQ =
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests ;
assign avalon_slave_outbuf$DEQ = CAN_FIRE_RL_avalon_request_splitter ;
assign avalon_slave_outbuf$CLR = 1'b0 ;
// submodule lower_16b_returned
assign lower_16b_returned$D_IN = mem_resp$D_OUT ;
assign lower_16b_returned$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
!lower_16b_returned$EMPTY_N ;
assign lower_16b_returned$DEQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N ;
assign lower_16b_returned$CLR = 1'b0 ;
// submodule mem_pipe0
assign mem_pipe0$D_IN = { mem_req$D_OUT[44], mem_req$D_OUT[15:0] } ;
assign mem_pipe0$ENQ = CAN_FIRE_RL_mem_forward_requests_ssram ;
assign mem_pipe0$DEQ = CAN_FIRE_RL_mem_pipe_stage_0 ;
assign mem_pipe0$CLR = 1'b0 ;
// submodule mem_pipe1
assign mem_pipe1$D_IN = mem_pipe0$D_OUT ;
assign mem_pipe1$ENQ = CAN_FIRE_RL_mem_pipe_stage_0 ;
assign mem_pipe1$DEQ = CAN_FIRE_RL_mem_pipe_stage_1 ;
assign mem_pipe1$CLR = 1'b0 ;
// submodule mem_pipe2
assign mem_pipe2$D_IN = mem_pipe1$D_OUT ;
assign mem_pipe2$ENQ = CAN_FIRE_RL_mem_pipe_stage_1 ;
assign mem_pipe2$DEQ = CAN_FIRE_RL_mem_pipe_stage_2 ;
assign mem_pipe2$CLR = 1'b0 ;
// submodule mem_req
assign mem_req$D_IN =
WILL_FIRE_RL_arbitrate_requests ?
MUX_mem_req$enq_1__VAL_1 :
mem_upper_16b_request$D_OUT ;
assign mem_req$ENQ =
WILL_FIRE_RL_arbitrate_requests ||
WILL_FIRE_RL_forward_upper_bytes ;
assign mem_req$DEQ =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign mem_req$CLR = 1'b0 ;
// submodule mem_resp
assign mem_resp$D_IN =
MUX_mem_resp$enq_1__SEL_1 ?
MUX_mem_resp$enq_1__VAL_1 :
MUX_mem_resp$enq_1__VAL_2 ;
assign mem_resp$ENQ =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ||
WILL_FIRE_RL_mem_pipe_stage_2 ;
assign mem_resp$DEQ = CAN_FIRE_RL_receive_mem_responses ;
assign mem_resp$CLR = 1'b0 ;
// submodule mem_upper_16b_request
assign mem_upper_16b_request$D_IN =
{ IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668[3:2],
x_addr__h13123,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669[31:16] } ;
assign mem_upper_16b_request$ENQ = CAN_FIRE_RL_arbitrate_requests ;
assign mem_upper_16b_request$DEQ = CAN_FIRE_RL_forward_upper_bytes ;
assign mem_upper_16b_request$CLR = 1'b0 ;
// submodule pixel_engine_char_colour
assign pixel_engine_char_colour$D_IN =
{ x__h7183 == pixel_engine_cursor_pos[15:8] &&
pixel_engine_char_pos$D_OUT[7:0] ==
pixel_engine_cursor_pos[7:0],
pixel_engine_char_ctr ?
pixel_engine_two_chars$D_OUT[31:24] :
pixel_engine_two_chars$D_OUT[15:8],
1'd0 } ;
assign pixel_engine_char_colour$ENQ =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
assign pixel_engine_char_colour$DEQ =
WILL_FIRE_RL_pixel_engine_char_pixels &&
pixel_engine_char_x_pos == 3'd7 ;
assign pixel_engine_char_colour$CLR = 1'b0 ;
// submodule pixel_engine_char_pixel
assign pixel_engine_char_pixel$D_IN =
{ pixel_engine_char_colour$D_OUT[9:1], x__h7731 } ;
assign pixel_engine_char_pixel$ENQ = CAN_FIRE_RL_pixel_engine_char_pixels ;
assign pixel_engine_char_pixel$DEQ =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_char_pixel$CLR = 1'b0 ;
// submodule pixel_engine_char_pos
assign pixel_engine_char_pos$D_IN = { x__h2840, pixel_engine_char_y[7:0] } ;
assign pixel_engine_char_pos$ENQ =
CAN_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_char_pos$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_char_pos$CLR = 1'b0 ;
// submodule pixel_engine_chars_read
assign pixel_engine_chars_read$D_IN =
!WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_chars_read$ENQ =
WILL_FIRE_RL_pixel_engine_request_pixel_values ||
WILL_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_chars_read$DEQ =
WILL_FIRE_RL_pixel_engine_buffer_characters_read ||
WILL_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_chars_read$CLR = 1'b0 ;
// submodule pixel_engine_font_y_pos
assign pixel_engine_font_y_pos$D_IN = pixel_engine_font_y ;
assign pixel_engine_font_y_pos$ENQ =
CAN_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_font_y_pos$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_font_y_pos$CLR = 1'b0 ;
// submodule pixel_engine_fontbits
assign pixel_engine_fontbits$D_IN = pixel_engine_fontrom_rom$v_data ;
assign pixel_engine_fontbits$ENQ =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
assign pixel_engine_fontbits$DEQ =
WILL_FIRE_RL_pixel_engine_char_pixels &&
pixel_engine_char_x_pos == 3'd7 ;
assign pixel_engine_fontbits$CLR = 1'b0 ;
// submodule pixel_engine_fontrom_rom
assign pixel_engine_fontrom_rom$v_addr =
{ char__h6798, pixel_engine_font_y_pos$D_OUT } ;
assign pixel_engine_fontrom_rom$v_en =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// submodule pixel_engine_fontrom_seq_fifo
assign pixel_engine_fontrom_seq_fifo$D_IN = 1'd1 ;
assign pixel_engine_fontrom_seq_fifo$ENQ =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
assign pixel_engine_fontrom_seq_fifo$DEQ =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
assign pixel_engine_fontrom_seq_fifo$CLR = 1'b0 ;
// submodule pixel_engine_pixpos
assign pixel_engine_pixpos$D_IN =
{ pixel_engine_addr == 25'd0, pixel_engine_addr == 25'd383999 } ;
assign pixel_engine_pixpos$ENQ =
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_pixpos$DEQ =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_pixpos$CLR = 1'b0 ;
// submodule pixel_engine_req
assign pixel_engine_req$D_IN = pixel_engine_ssram_req$D_OUT ;
assign pixel_engine_req$ENQ = CAN_FIRE_RL_mkConnectionGetPut ;
assign pixel_engine_req$DEQ =
WILL_FIRE_RL_arbitrate_requests && pixel_engine_req$EMPTY_N ;
assign pixel_engine_req$CLR = 1'b0 ;
// submodule pixel_engine_ssram_req
assign pixel_engine_ssram_req$D_IN =
WILL_FIRE_RL_pixel_engine_request_char_values ?
MUX_pixel_engine_ssram_req$enq_1__VAL_1 :
MUX_pixel_engine_ssram_req$enq_1__VAL_2 ;
assign pixel_engine_ssram_req$ENQ =
WILL_FIRE_RL_pixel_engine_request_char_values ||
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_ssram_req$DEQ = CAN_FIRE_RL_mkConnectionGetPut ;
assign pixel_engine_ssram_req$CLR = 1'b0 ;
// submodule pixel_engine_ssram_resp
assign pixel_engine_ssram_resp$D_IN =
{ mem_resp$D_OUT[15:0], lower_16b_returned$D_OUT[15:0] } ;
assign pixel_engine_ssram_resp$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N &&
!response_for_avalon$D_OUT ;
assign pixel_engine_ssram_resp$DEQ =
WILL_FIRE_RL_pixel_engine_buffer_characters_read ||
WILL_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_ssram_resp$CLR = 1'b0 ;
// submodule pixel_engine_two_chars
assign pixel_engine_two_chars$D_IN = pixel_engine_ssram_resp$D_OUT ;
assign pixel_engine_two_chars$ENQ =
CAN_FIRE_RL_pixel_engine_buffer_characters_read ;
assign pixel_engine_two_chars$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_two_chars$CLR = 1'b0 ;
// submodule response_for_avalon
assign response_for_avalon$D_IN = !pixel_engine_req$EMPTY_N ;
assign response_for_avalon$ENQ = CAN_FIRE_RL_arbitrate_requests ;
assign response_for_avalon$DEQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N ;
assign response_for_avalon$CLR = 1'b0 ;
// submodule touch
assign touch$D_IN = prev_touch_info$D_IN ;
assign touch$ENQ =
coe_touch_touch_valid &&
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 &&
touch$FULL_N ;
assign touch$DEQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd7 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0 ;
assign touch$CLR = 1'b0 ;
// remaining internal signals
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd7 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ? { 22'd0, touch$D_OUT[9:0] } : 32'hFFFFFFFF) :
32'hFFFFFFFF ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd6 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 23'd0, touch$D_OUT[18:10] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd5 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 22'd0, touch$D_OUT[28:19] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd4 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 23'd0, touch$D_OUT[37:29] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd3 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 22'd0, touch$D_OUT[47:38] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd1 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
{ 16'd0, pixel_engine_cursor_pos } :
((avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
{ 7'd0, pixel_engine_char_base[22:0], 2'd0 } :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456) ;
assign IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710 =
CAN_FIRE_RL_mem_forward_requests_ssram ?
mem_req$D_OUT[43:42] :
2'b0 ;
assign IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55 =
next_char_y__h2903 * 25'd50 ;
assign IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645 =
(pixel_engine_font_y == 4'd11) ?
((pixel_engine_char_y == 25'd39) ?
25'd0 :
next_char_y___2__h3016) :
pixel_engine_char_y ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[61] :
avalon_req$D_OUT[61] ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[60:57] :
avalon_req$D_OUT[60:57] ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[31:0] :
avalon_req$D_OUT[31:0] ;
assign NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 =
coe_touch_x1 != prev_touch_info[47:38] ||
coe_touch_y1 != prev_touch_info[37:29] ||
coe_touch_x2 != prev_touch_info[28:19] ||
coe_touch_y2 != prev_touch_info[18:10] ||
coe_touch_count_gesture != prev_touch_info[9:0] ;
assign a__h3765 = minus__h3867[8] ? 8'd0 : minus__h3867[7:0] ;
assign a__h3866 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[23:16] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[23:16] ;
assign a__h5019 = minus__h5121[8] ? 8'd0 : minus__h5121[7:0] ;
assign a__h5120 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[15:8] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[15:8] ;
assign a__h5610 = minus__h5712[8] ? 8'd0 : minus__h5712[7:0] ;
assign a__h5711 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[7:0] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[7:0] ;
assign b__h14135 =
MUX_avalon_slave_datareturned$wset_1__SEL_1 ?
avalon_mem_resp$D_OUT[31:0] :
avalon_control_reg_resp$D_OUT[31:0] ;
assign b__h3310 = sum__h3767[8] ? 8'hFF : sum__h3767[7:0] ;
assign b__h3766 = minus__h4723[8] ? 8'd0 : minus__h4723[7:0] ;
assign b__h4865 = sum__h5021[8] ? 8'hFF : sum__h5021[7:0] ;
assign b__h5020 = minus__h5335[8] ? 8'd0 : minus__h5335[7:0] ;
assign b__h5456 = sum__h5612[8] ? 8'hFF : sum__h5612[7:0] ;
assign b__h5611 = minus__h5926[8] ? 8'd0 : minus__h5926[7:0] ;
assign bitmap_col_chan_b__h3300 = sum__h5457[8] ? 8'hFF : sum__h5457[7:0] ;
assign bitmap_col_chan_g__h3299 = sum__h4866[8] ? 8'hFF : sum__h4866[7:0] ;
assign bitmap_col_chan_r__h3298 = sum__h3311[8] ? 8'hFF : sum__h3311[7:0] ;
assign char__h6798 =
pixel_engine_char_ctr ?
pixel_engine_two_chars$D_OUT[23:16] :
pixel_engine_two_chars$D_OUT[7:0] ;
assign char_alpha__h3227 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
pixel_engine_fb_blend[7:0] :
pixel_engine_fb_blend[15:8] ;
assign mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345 =
mem_req$EMPTY_N &&
((mem_req$D_OUT[43:42] == 2'b0) ?
mem_resp$FULL_N :
mem_flash_timer != 4'd10 || mem_resp$FULL_N) ;
assign minus__h3867 =
{ 1'd0, a__h3866 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h4723 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[23:16] } -
{ 1'd0, char_alpha__h3227 } ;
assign minus__h5121 =
{ 1'd0, a__h5120 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h5335 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[15:8] } -
{ 1'd0, char_alpha__h3227 } ;
assign minus__h5712 =
{ 1'd0, a__h5711 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h5926 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[7:0] } -
{ 1'd0, char_alpha__h3227 } ;
assign next_addr__h3065 = pixel_engine_addr + 25'd1 ;
assign next_char_y___2__h3016 = pixel_engine_char_y + 25'd1 ;
assign next_char_y__h2903 =
(pixel_engine_char_x_two_char == 6'd49) ?
IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645 :
pixel_engine_char_y ;
assign next_font_y___2__h2969 = pixel_engine_font_y + 4'd1 ;
assign next_x_two_char_addr__h2897 = pixel_engine_char_x_two_char + 6'd1 ;
assign next_x_two_char_addr__h2901 =
(pixel_engine_char_x_two_char == 6'd49) ?
6'd0 :
next_x_two_char_addr__h2897 ;
assign pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 =
(pixel_engine_char_pixel$D_OUT[9] &&
pixel_engine_flash_col[5]) ==
(pixel_engine_char_pixel$D_OUT[0] &&
(!pixel_engine_char_pixel$D_OUT[8] ||
pixel_engine_flash_col[4])) ;
assign response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529 =
response_for_avalon$EMPTY_N &&
(response_for_avalon$D_OUT ?
avalon_mem_resp$FULL_N :
pixel_engine_ssram_resp$FULL_N) ;
assign sum__h3311 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[23:16] } +
{ 1'd0, b__h3310 } ;
assign sum__h3767 = { 1'd0, a__h3765 } + { 1'd0, b__h3766 } ;
assign sum__h4866 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[15:8] } +
{ 1'd0, b__h4865 } ;
assign sum__h5021 = { 1'd0, a__h5019 } + { 1'd0, b__h5020 } ;
assign sum__h5457 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[7:0] } +
{ 1'd0, b__h5456 } ;
assign sum__h5612 = { 1'd0, a__h5610 } + { 1'd0, b__h5611 } ;
assign x1_avValue_addr__h12990 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[56:32] :
avalon_req$D_OUT[56:32] ;
assign x__h13071 = { x1_avValue_addr__h12990, 1'b0 } ;
assign x__h2840 = { 1'd0, pixel_engine_char_x_two_char, 1'd0 } ;
assign x__h3050 = pixel_engine_char_base + y__h3053 ;
assign x__h7183 =
pixel_engine_char_pos$D_OUT[15:8] +
{ 7'd0, pixel_engine_char_ctr } ;
assign x__h7731 = pixel_engine_fontbits$D_OUT[x__h7767] ;
assign x__h7767 = 3'd7 - pixel_engine_char_x_pos ;
assign x_addr__h13123 = { x1_avValue_addr__h12990, 1'b1 } ;
assign y__h3053 = { 19'd0, next_x_two_char_addr__h2901 } ;
always@(pixel_engine_fb_blend)
begin
case (pixel_engine_fb_blend[27:24])
4'd0: IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 = 24'h0;
4'd1:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h0000AA;
4'd2:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h00AA00;
4'd3:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h00AAAA;
4'd4:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA0000;
4'd5:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA00AA;
4'd6:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA5500;
4'd7:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAAAAAA;
4'd8:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h555555;
4'd9:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h5555FF;
4'd10:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h55FF55;
4'd11:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h55FFFF;
4'd12:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFF5555;
4'd13:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFF55FF;
4'd14:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFFFF55;
4'd15:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFFFFFF;
endcase
end
always@(pixel_engine_char_pixel$D_OUT)
begin
case (pixel_engine_char_pixel$D_OUT[7:5])
3'd0: IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 = 24'h0;
3'd1:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h0000AA;
3'd2:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h00AA00;
3'd3:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h00AAAA;
3'd4:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA0000;
3'd5:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA00AA;
3'd6:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA5500;
3'd7:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAAAAAA;
endcase
end
always@(pixel_engine_char_pixel$D_OUT)
begin
case (pixel_engine_char_pixel$D_OUT[4:1])
4'd0: IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 = 24'h0;
4'd1:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h0000AA;
4'd2:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h00AA00;
4'd3:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h00AAAA;
4'd4:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA0000;
4'd5:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA00AA;
4'd6:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA5500;
4'd7:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAAAAAA;
4'd8:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h555555;
4'd9:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h5555FF;
4'd10:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h55FF55;
4'd11:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h55FFFF;
4'd12:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFF5555;
4'd13:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFF55FF;
4'd14:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFFFF55;
4'd15:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFFFFFF;
endcase
end
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
avalon_slave_ignore_further_requests <= `BSV_ASSIGNMENT_DELAY 1'd0;
mem_flash_timer <= `BSV_ASSIGNMENT_DELAY 4'd0;
pixel_engine_addr <= `BSV_ASSIGNMENT_DELAY 25'd0;
pixel_engine_char_addr <= `BSV_ASSIGNMENT_DELAY 25'd384000;
pixel_engine_char_base <= `BSV_ASSIGNMENT_DELAY 25'd384000;
pixel_engine_char_ctr <= `BSV_ASSIGNMENT_DELAY 1'd0;
pixel_engine_char_end <= `BSV_ASSIGNMENT_DELAY 25'd390000;
pixel_engine_char_x_pos <= `BSV_ASSIGNMENT_DELAY 3'd0;
pixel_engine_char_x_two_char <= `BSV_ASSIGNMENT_DELAY 6'd0;
pixel_engine_char_y <= `BSV_ASSIGNMENT_DELAY 25'd0;
pixel_engine_cursor_pos <= `BSV_ASSIGNMENT_DELAY 16'd65535;
pixel_engine_fb_blend <= `BSV_ASSIGNMENT_DELAY 32'd50331647;
pixel_engine_flash_col <= `BSV_ASSIGNMENT_DELAY 6'd0;
pixel_engine_font_y <= `BSV_ASSIGNMENT_DELAY 4'd0;
prev_touch_info <= `BSV_ASSIGNMENT_DELAY 48'hAAAAAAAAAAAA;
end
else
begin
if (avalon_slave_ignore_further_requests$EN)
avalon_slave_ignore_further_requests <= `BSV_ASSIGNMENT_DELAY
avalon_slave_ignore_further_requests$D_IN;
if (mem_flash_timer$EN)
mem_flash_timer <= `BSV_ASSIGNMENT_DELAY mem_flash_timer$D_IN;
if (pixel_engine_addr$EN)
pixel_engine_addr <= `BSV_ASSIGNMENT_DELAY pixel_engine_addr$D_IN;
if (pixel_engine_char_addr$EN)
pixel_engine_char_addr <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_addr$D_IN;
if (pixel_engine_char_base$EN)
pixel_engine_char_base <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_base$D_IN;
if (pixel_engine_char_ctr$EN)
pixel_engine_char_ctr <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_ctr$D_IN;
if (pixel_engine_char_end$EN)
pixel_engine_char_end <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_end$D_IN;
if (pixel_engine_char_x_pos$EN)
pixel_engine_char_x_pos <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_x_pos$D_IN;
if (pixel_engine_char_x_two_char$EN)
pixel_engine_char_x_two_char <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_x_two_char$D_IN;
if (pixel_engine_char_y$EN)
pixel_engine_char_y <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_y$D_IN;
if (pixel_engine_cursor_pos$EN)
pixel_engine_cursor_pos <= `BSV_ASSIGNMENT_DELAY
pixel_engine_cursor_pos$D_IN;
if (pixel_engine_fb_blend$EN)
pixel_engine_fb_blend <= `BSV_ASSIGNMENT_DELAY
pixel_engine_fb_blend$D_IN;
if (pixel_engine_flash_col$EN)
pixel_engine_flash_col <= `BSV_ASSIGNMENT_DELAY
pixel_engine_flash_col$D_IN;
if (pixel_engine_font_y$EN)
pixel_engine_font_y <= `BSV_ASSIGNMENT_DELAY
pixel_engine_font_y$D_IN;
if (prev_touch_info$EN)
prev_touch_info <= `BSV_ASSIGNMENT_DELAY prev_touch_info$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
avalon_slave_ignore_further_requests = 1'h0;
mem_flash_timer = 4'hA;
pixel_engine_addr = 25'h0AAAAAA;
pixel_engine_char_addr = 25'h0AAAAAA;
pixel_engine_char_base = 25'h0AAAAAA;
pixel_engine_char_ctr = 1'h0;
pixel_engine_char_end = 25'h0AAAAAA;
pixel_engine_char_x_pos = 3'h2;
pixel_engine_char_x_two_char = 6'h2A;
pixel_engine_char_y = 25'h0AAAAAA;
pixel_engine_cursor_pos = 16'hAAAA;
pixel_engine_fb_blend = 32'hAAAAAAAA;
pixel_engine_flash_col = 6'h2A;
pixel_engine_font_y = 4'hA;
prev_touch_info = 48'hAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkMTL_Framebuffer_Flash
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:44:45 BST 2012
//
// Method conflict info:
// Method: muldiv_request_put
// Sequenced before (restricted): muldiv_response_get
// Conflicts: muldiv_request_put
//
// Method: muldiv_response_get
// Sequenced after (restricted): muldiv_request_put
// Conflicts: muldiv_response_get
//
//
// Ports:
// Name I/O size props
// RDY_muldiv_request_put O 1
// muldiv_response_get O 130
// RDY_muldiv_response_get O 1
// CLK I 1 clock
// RST_N I 1 reset
// muldiv_request_put I 263
// EN_muldiv_request_put I 1
// EN_muldiv_response_get I 1
//
// Combinational paths from inputs to outputs:
// (muldiv_request_put, EN_muldiv_request_put) -> RDY_muldiv_response_get
// (muldiv_request_put, EN_muldiv_request_put) -> muldiv_response_get
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkMulDiv(CLK,
RST_N,
muldiv_request_put,
EN_muldiv_request_put,
RDY_muldiv_request_put,
EN_muldiv_response_get,
muldiv_response_get,
RDY_muldiv_response_get);
input CLK;
input RST_N;
// action method muldiv_request_put
input [262 : 0] muldiv_request_put;
input EN_muldiv_request_put;
output RDY_muldiv_request_put;
// actionvalue method muldiv_response_get
input EN_muldiv_response_get;
output [129 : 0] muldiv_response_get;
output RDY_muldiv_response_get;
// signals for module outputs
wire [129 : 0] muldiv_response_get;
wire RDY_muldiv_request_put, RDY_muldiv_response_get;
// inlined wires
reg [64 : 0] hi_fifo_rw_enq$wget, lo_fifo_rw_enq$wget;
wire lo_fifo_rw_enq$whas;
// register divint
reg [265 : 0] divint;
wire [265 : 0] divint$D_IN;
wire divint$EN;
// register hi_fifo_taggedReg
reg [65 : 0] hi_fifo_taggedReg;
wire [65 : 0] hi_fifo_taggedReg$D_IN;
wire hi_fifo_taggedReg$EN;
// register lo_fifo_taggedReg
reg [65 : 0] lo_fifo_taggedReg;
wire [65 : 0] lo_fifo_taggedReg$D_IN;
wire lo_fifo_taggedReg$EN;
// register mulIntReg
reg [257 : 0] mulIntReg;
wire [257 : 0] mulIntReg$D_IN;
wire mulIntReg$EN;
// register state
reg [2 : 0] state;
reg [2 : 0] state$D_IN;
wire state$EN;
// ports of submodule request_fifo
wire [262 : 0] request_fifo$D_IN, request_fifo$D_OUT;
wire request_fifo$CLR,
request_fifo$DEQ,
request_fifo$EMPTY_N,
request_fifo$ENQ,
request_fifo$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_doDivide,
WILL_FIRE_RL_finishDivide,
WILL_FIRE_RL_hi_fifo_rule_enq,
WILL_FIRE_RL_lo_fifo_rule_enq,
WILL_FIRE_RL_mulPipe4;
// inputs to muxes for submodule ports
reg [2 : 0] MUX_state$write_1__VAL_2;
wire [265 : 0] MUX_divint$write_1__VAL_1, MUX_divint$write_1__VAL_2;
wire [257 : 0] MUX_mulIntReg$write_1__VAL_1, MUX_mulIntReg$write_1__VAL_2;
wire [65 : 0] MUX_hi_fifo_taggedReg$write_1__VAL_1,
MUX_lo_fifo_taggedReg$write_1__VAL_1;
wire [64 : 0] MUX_hi_fifo_rw_enq$wset_1__VAL_1,
MUX_hi_fifo_rw_enq$wset_1__VAL_2,
MUX_hi_fifo_rw_enq$wset_1__VAL_3,
MUX_lo_fifo_rw_enq$wset_1__VAL_1,
MUX_lo_fifo_rw_enq$wset_1__VAL_2,
MUX_lo_fifo_rw_enq$wset_1__VAL_3;
wire MUX_divint$write_1__SEL_1,
MUX_hi_fifo_rw_enq$wset_1__SEL_1,
MUX_mulIntReg$write_1__SEL_1,
MUX_state$write_1__SEL_1,
MUX_state$write_1__SEL_2,
MUX_state$write_1__SEL_3;
// remaining internal signals
reg [127 : 0] IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC___d271;
wire [127 : 0] IF_request_fifo_first__4_BIT_262_5_THEN_IF_NOT_ETC___d272,
_0_CONCAT_mulIntReg_BITS_129_TO_66_PLUS_0_CONCA_ETC__q3,
_0_CONCAT_mulIntReg_read__2_BITS_161_TO_130_4_5_ETC___d36,
_0_CONCAT_mulIntReg_read__2_BITS_161_TO_130_4_5_ETC___d38,
_0_CONCAT_mulIntReg_read__2_BITS_225_TO_194_3_4_ETC___d27,
_0_CONCAT_mulIntReg_read__2_BITS_225_TO_194_3_4_ETC___d31,
_theResult_____1_dividend__h4791,
_theResult____h3766,
_theResult___dividend__h4720,
mydiv___1_dividend__h4726,
mydiv_dividend__h4663,
product___1__h4098,
product__h3765,
product__h3952,
product__h3995,
product__h4310,
x_dividend__h7213;
wire [63 : 0] IF_muldiv_request_put_BIT_261_75_THEN_IF_IF_mu_ETC___d270,
_theResult_____2__h5132,
_theResult_____2_fst__h6340,
_theResult_____2_snd_fst__h6342,
_theResult___fst__h6377,
_theResult___quotient__h4721,
_theResult___quotient__h5201,
_theResult___snd__h6378,
a___1__h6385,
a___1__h6896,
a___2__h6419,
a__h5584,
b___1__h6386,
b___1__h6451,
b___2__h6420,
b__h5585,
b__h5616,
mydiv_quotient__h4664,
mydiv_quotient__h4798,
newHi__h3951,
newLo__h3950,
remainder___1__h5390,
spliced_bits__h4887,
x__h3998,
x__h4313,
x__h4960,
y__h5243,
y__h5385;
wire [31 : 0] IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q6,
IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q7,
muldiv_request_put_BITS_159_TO_128__q2,
muldiv_request_put_BITS_223_TO_192__q1,
theResult_____2132_BITS_31_TO_0__q5,
theResult___quotient201_BITS_31_TO_0__q4;
wire [7 : 0] _theResult_____1_count__h4793,
mydiv___1_count__h4728,
mydiv_count__h4665;
wire IF_divint_read__01_BITS_200_TO_129_03_EQ_0x0_0_ETC___d260;
// action method muldiv_request_put
assign RDY_muldiv_request_put =
state == 3'd0 && request_fifo$FULL_N && !lo_fifo_taggedReg[65] &&
!hi_fifo_taggedReg[65] ;
// actionvalue method muldiv_response_get
assign muldiv_response_get =
{ lo_fifo_rw_enq$whas ?
hi_fifo_rw_enq$wget[64] :
!hi_fifo_taggedReg[65] || hi_fifo_taggedReg[64],
lo_fifo_rw_enq$whas ?
hi_fifo_rw_enq$wget[63:0] :
hi_fifo_taggedReg[63:0],
lo_fifo_rw_enq$whas ?
lo_fifo_rw_enq$wget[64] :
!lo_fifo_taggedReg[65] || lo_fifo_taggedReg[64],
lo_fifo_rw_enq$whas ?
lo_fifo_rw_enq$wget[63:0] :
lo_fifo_taggedReg[63:0] } ;
assign RDY_muldiv_response_get =
(lo_fifo_taggedReg[65] || lo_fifo_rw_enq$whas) &&
(hi_fifo_taggedReg[65] || lo_fifo_rw_enq$whas) ;
// submodule request_fifo
FIFO1 #(.width(32'd263), .guarded(32'd1)) request_fifo(.RST_N(RST_N),
.CLK(CLK),
.D_IN(request_fifo$D_IN),
.ENQ(request_fifo$ENQ),
.DEQ(request_fifo$DEQ),
.CLR(request_fifo$CLR),
.D_OUT(request_fifo$D_OUT),
.FULL_N(request_fifo$FULL_N),
.EMPTY_N(request_fifo$EMPTY_N));
// rule RL_mulPipe4
assign WILL_FIRE_RL_mulPipe4 =
request_fifo$EMPTY_N && !lo_fifo_taggedReg[65] &&
!hi_fifo_taggedReg[65] &&
state == 3'd4 ;
// rule RL_doDivide
assign WILL_FIRE_RL_doDivide = request_fifo$EMPTY_N && state == 3'd5 ;
// rule RL_finishDivide
assign WILL_FIRE_RL_finishDivide =
request_fifo$EMPTY_N && !lo_fifo_taggedReg[65] &&
!hi_fifo_taggedReg[65] &&
state == 3'd6 ;
// rule RL_lo_fifo_rule_enq
assign WILL_FIRE_RL_lo_fifo_rule_enq =
lo_fifo_rw_enq$whas && !EN_muldiv_response_get ;
// rule RL_hi_fifo_rule_enq
assign WILL_FIRE_RL_hi_fifo_rule_enq =
lo_fifo_rw_enq$whas && !EN_muldiv_response_get ;
// inputs to muxes for submodule ports
assign MUX_divint$write_1__SEL_1 =
EN_muldiv_request_put && muldiv_request_put[260:256] == 5'd13 ;
assign MUX_hi_fifo_rw_enq$wset_1__SEL_1 =
EN_muldiv_request_put &&
(muldiv_request_put[260:256] == 5'd17 ||
muldiv_request_put[260:256] == 5'd18) ;
assign MUX_mulIntReg$write_1__SEL_1 =
EN_muldiv_request_put &&
(muldiv_request_put[260:256] == 5'd12 ||
muldiv_request_put[260:256] == 5'd14 ||
muldiv_request_put[260:256] == 5'd15 ||
muldiv_request_put[260:256] == 5'd16) ;
assign MUX_state$write_1__SEL_1 =
WILL_FIRE_RL_doDivide && _theResult_____1_count__h4793 == 8'd0 ;
assign MUX_state$write_1__SEL_2 =
EN_muldiv_request_put &&
(muldiv_request_put[260:256] == 5'd12 ||
muldiv_request_put[260:256] == 5'd14 ||
muldiv_request_put[260:256] == 5'd15 ||
muldiv_request_put[260:256] == 5'd16 ||
muldiv_request_put[260:256] == 5'd13) ;
assign MUX_state$write_1__SEL_3 =
WILL_FIRE_RL_finishDivide || WILL_FIRE_RL_mulPipe4 ;
assign MUX_divint$write_1__VAL_1 =
{ IF_muldiv_request_put_BIT_261_75_THEN_IF_IF_mu_ETC___d270,
x_dividend__h7213,
72'd64,
muldiv_request_put[261] && a__h5584[63],
muldiv_request_put[261] && b__h5585[63] } ;
assign MUX_divint$write_1__VAL_2 =
{ divint[265:202],
_theResult_____1_dividend__h4791,
x__h4960,
_theResult_____1_count__h4793,
divint[1:0] } ;
assign MUX_hi_fifo_rw_enq$wset_1__VAL_1 =
{ muldiv_request_put[260:256] == 5'd17,
IF_muldiv_request_put_BIT_261_75_THEN_IF_IF_mu_ETC___d270 } ;
assign MUX_hi_fifo_rw_enq$wset_1__VAL_2 =
{ 1'd1,
IF_request_fifo_first__4_BIT_262_5_THEN_IF_NOT_ETC___d272[127:64] } ;
assign MUX_hi_fifo_rw_enq$wset_1__VAL_3 =
{ 1'd1,
request_fifo$D_OUT[262] ?
_theResult_____2__h5132 :
y__h5385 } ;
assign MUX_hi_fifo_taggedReg$write_1__VAL_1 =
{ 1'd1, hi_fifo_rw_enq$wget } ;
assign MUX_lo_fifo_rw_enq$wset_1__VAL_1 =
{ muldiv_request_put[260:256] != 5'd17,
IF_muldiv_request_put_BIT_261_75_THEN_IF_IF_mu_ETC___d270 } ;
assign MUX_lo_fifo_rw_enq$wset_1__VAL_2 =
{ 1'd1,
IF_request_fifo_first__4_BIT_262_5_THEN_IF_NOT_ETC___d272[63:0] } ;
assign MUX_lo_fifo_rw_enq$wset_1__VAL_3 =
{ 1'd1,
request_fifo$D_OUT[262] ?
_theResult___quotient__h5201 :
y__h5243 } ;
assign MUX_lo_fifo_taggedReg$write_1__VAL_1 =
{ 1'd1, lo_fifo_rw_enq$wget } ;
assign MUX_mulIntReg$write_1__VAL_1 =
{ 32'd0,
b__h5616[63:32],
32'd0,
b__h5616[31:0],
32'd0,
IF_muldiv_request_put_BIT_261_75_THEN_IF_IF_mu_ETC___d270[63:32],
32'd0,
IF_muldiv_request_put_BIT_261_75_THEN_IF_IF_mu_ETC___d270[31:0],
muldiv_request_put[261] && a__h5584[63],
muldiv_request_put[261] && b__h5585[63] } ;
assign MUX_mulIntReg$write_1__VAL_2 =
{ _0_CONCAT_mulIntReg_read__2_BITS_225_TO_194_3_4_ETC___d27[63:0],
_0_CONCAT_mulIntReg_read__2_BITS_225_TO_194_3_4_ETC___d31[63:0],
_0_CONCAT_mulIntReg_read__2_BITS_161_TO_130_4_5_ETC___d36[63:0],
_0_CONCAT_mulIntReg_read__2_BITS_161_TO_130_4_5_ETC___d38[63:0],
mulIntReg[1:0] } ;
always@(muldiv_request_put)
begin
case (muldiv_request_put[260:256])
5'd12, 5'd14, 5'd15, 5'd16: MUX_state$write_1__VAL_2 = 3'd1;
default: MUX_state$write_1__VAL_2 = 3'd5;
endcase
end
// inlined wires
always@(MUX_hi_fifo_rw_enq$wset_1__SEL_1 or
MUX_lo_fifo_rw_enq$wset_1__VAL_1 or
WILL_FIRE_RL_mulPipe4 or
MUX_lo_fifo_rw_enq$wset_1__VAL_2 or
WILL_FIRE_RL_finishDivide or MUX_lo_fifo_rw_enq$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_hi_fifo_rw_enq$wset_1__SEL_1:
lo_fifo_rw_enq$wget = MUX_lo_fifo_rw_enq$wset_1__VAL_1;
WILL_FIRE_RL_mulPipe4:
lo_fifo_rw_enq$wget = MUX_lo_fifo_rw_enq$wset_1__VAL_2;
WILL_FIRE_RL_finishDivide:
lo_fifo_rw_enq$wget = MUX_lo_fifo_rw_enq$wset_1__VAL_3;
default: lo_fifo_rw_enq$wget =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign lo_fifo_rw_enq$whas =
EN_muldiv_request_put &&
(muldiv_request_put[260:256] == 5'd17 ||
muldiv_request_put[260:256] == 5'd18) ||
WILL_FIRE_RL_mulPipe4 ||
WILL_FIRE_RL_finishDivide ;
always@(MUX_hi_fifo_rw_enq$wset_1__SEL_1 or
MUX_hi_fifo_rw_enq$wset_1__VAL_1 or
WILL_FIRE_RL_mulPipe4 or
MUX_hi_fifo_rw_enq$wset_1__VAL_2 or
WILL_FIRE_RL_finishDivide or MUX_hi_fifo_rw_enq$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_hi_fifo_rw_enq$wset_1__SEL_1:
hi_fifo_rw_enq$wget = MUX_hi_fifo_rw_enq$wset_1__VAL_1;
WILL_FIRE_RL_mulPipe4:
hi_fifo_rw_enq$wget = MUX_hi_fifo_rw_enq$wset_1__VAL_2;
WILL_FIRE_RL_finishDivide:
hi_fifo_rw_enq$wget = MUX_hi_fifo_rw_enq$wset_1__VAL_3;
default: hi_fifo_rw_enq$wget =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// register divint
assign divint$D_IN =
MUX_divint$write_1__SEL_1 ?
MUX_divint$write_1__VAL_1 :
MUX_divint$write_1__VAL_2 ;
assign divint$EN =
EN_muldiv_request_put && muldiv_request_put[260:256] == 5'd13 ||
WILL_FIRE_RL_doDivide ;
// register hi_fifo_taggedReg
assign hi_fifo_taggedReg$D_IN =
WILL_FIRE_RL_hi_fifo_rule_enq ?
MUX_hi_fifo_taggedReg$write_1__VAL_1 :
66'h0AAAAAAAAAAAAAAAA ;
assign hi_fifo_taggedReg$EN =
WILL_FIRE_RL_hi_fifo_rule_enq || EN_muldiv_response_get ;
// register lo_fifo_taggedReg
assign lo_fifo_taggedReg$D_IN =
WILL_FIRE_RL_lo_fifo_rule_enq ?
MUX_lo_fifo_taggedReg$write_1__VAL_1 :
66'h0AAAAAAAAAAAAAAAA ;
assign lo_fifo_taggedReg$EN =
WILL_FIRE_RL_lo_fifo_rule_enq || EN_muldiv_response_get ;
// register mulIntReg
assign mulIntReg$D_IN =
MUX_mulIntReg$write_1__SEL_1 ?
MUX_mulIntReg$write_1__VAL_1 :
MUX_mulIntReg$write_1__VAL_2 ;
assign mulIntReg$EN =
EN_muldiv_request_put &&
(muldiv_request_put[260:256] == 5'd12 ||
muldiv_request_put[260:256] == 5'd14 ||
muldiv_request_put[260:256] == 5'd15 ||
muldiv_request_put[260:256] == 5'd16) ||
state == 3'd1 ;
// register state
always@(MUX_state$write_1__SEL_1 or
MUX_state$write_1__SEL_2 or
MUX_state$write_1__VAL_2 or MUX_state$write_1__SEL_3 or state)
begin
case (1'b1) // synopsys parallel_case
MUX_state$write_1__SEL_1: state$D_IN = 3'd6;
MUX_state$write_1__SEL_2: state$D_IN = MUX_state$write_1__VAL_2;
MUX_state$write_1__SEL_3: state$D_IN = 3'd0;
state == 3'd1: state$D_IN = 3'd4;
default: state$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign state$EN =
WILL_FIRE_RL_doDivide && _theResult_____1_count__h4793 == 8'd0 ||
EN_muldiv_request_put &&
(muldiv_request_put[260:256] == 5'd12 ||
muldiv_request_put[260:256] == 5'd14 ||
muldiv_request_put[260:256] == 5'd15 ||
muldiv_request_put[260:256] == 5'd16 ||
muldiv_request_put[260:256] == 5'd13) ||
WILL_FIRE_RL_finishDivide ||
WILL_FIRE_RL_mulPipe4 ||
state == 3'd1 ;
// submodule request_fifo
assign request_fifo$D_IN = muldiv_request_put ;
assign request_fifo$ENQ = MUX_state$write_1__SEL_2 ;
assign request_fifo$DEQ = MUX_state$write_1__SEL_3 ;
assign request_fifo$CLR = 1'b0 ;
// remaining internal signals
assign IF_divint_read__01_BITS_200_TO_129_03_EQ_0x0_0_ETC___d260 =
_theResult___dividend__h4720[127:64] < divint[265:202] ;
assign IF_muldiv_request_put_BIT_261_75_THEN_IF_IF_mu_ETC___d270 =
muldiv_request_put[261] ?
_theResult_____2_fst__h6340 :
a__h5584 ;
assign IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q6 =
IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC___d271[63:32] ;
assign IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q7 =
IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC___d271[31:0] ;
assign IF_request_fifo_first__4_BIT_262_5_THEN_IF_NOT_ETC___d272 =
request_fifo$D_OUT[262] ? _theResult____h3766 : product__h3952 ;
assign _0_CONCAT_mulIntReg_BITS_129_TO_66_PLUS_0_CONCA_ETC__q3 =
{ 64'd0, mulIntReg[129:66] } + { 64'd0, mulIntReg[193:130] } ;
assign _0_CONCAT_mulIntReg_read__2_BITS_161_TO_130_4_5_ETC___d36 =
{ 32'd0, mulIntReg[161:130] } * { 32'd0, mulIntReg[97:66] } ;
assign _0_CONCAT_mulIntReg_read__2_BITS_161_TO_130_4_5_ETC___d38 =
{ 32'd0, mulIntReg[161:130] } * { 32'd0, mulIntReg[33:2] } ;
assign _0_CONCAT_mulIntReg_read__2_BITS_225_TO_194_3_4_ETC___d27 =
{ 32'd0, mulIntReg[225:194] } * { 32'd0, mulIntReg[97:66] } ;
assign _0_CONCAT_mulIntReg_read__2_BITS_225_TO_194_3_4_ETC___d31 =
{ 32'd0, mulIntReg[225:194] } * { 32'd0, mulIntReg[33:2] } ;
assign _theResult_____1_count__h4793 =
(divint[200:129] == 72'h0 && mydiv_count__h4665 > 8'd9) ?
mydiv___1_count__h4728 :
mydiv_count__h4665 ;
assign _theResult_____1_dividend__h4791 =
request_fifo$D_OUT[261] ?
(spliced_bits__h4887[63] ?
_theResult___dividend__h4720 :
{ spliced_bits__h4887,
_theResult___dividend__h4720[63:0] }) :
(IF_divint_read__01_BITS_200_TO_129_03_EQ_0x0_0_ETC___d260 ?
_theResult___dividend__h4720 :
{ spliced_bits__h4887,
_theResult___dividend__h4720[63:0] }) ;
assign _theResult_____2__h5132 =
(divint[0] && request_fifo$D_OUT[261]) ?
remainder___1__h5390 :
divint[201:138] ;
assign _theResult_____2_fst__h6340 =
a__h5584[63] ? a___1__h6896 : a__h5584 ;
assign _theResult_____2_snd_fst__h6342 =
b__h5585[63] ? b___1__h6451 : b__h5585 ;
assign _theResult____h3766 =
(mulIntReg[1] != mulIntReg[0] && request_fifo$D_OUT[261]) ?
product___1__h4098 :
product__h3765 ;
assign _theResult___dividend__h4720 =
(divint[200:129] == 72'h0 && mydiv_count__h4665 > 8'd9) ?
mydiv___1_dividend__h4726 :
mydiv_dividend__h4663 ;
assign _theResult___fst__h6377 =
muldiv_request_put[261] ? a___1__h6385 : a___2__h6419 ;
assign _theResult___quotient__h4721 =
(divint[200:129] == 72'h0 && mydiv_count__h4665 > 8'd9) ?
{ divint[64:10], 9'd0 } :
mydiv_quotient__h4664 ;
assign _theResult___quotient__h5201 =
(divint[1] != divint[0] && request_fifo$D_OUT[261]) ?
~divint[73:10] + 64'd1 :
divint[73:10] ;
assign _theResult___snd__h6378 =
muldiv_request_put[261] ? b___1__h6386 : b___2__h6420 ;
assign a___1__h6385 =
{ {32{muldiv_request_put_BITS_223_TO_192__q1[31]}},
muldiv_request_put_BITS_223_TO_192__q1 } ;
assign a___1__h6896 = ~(a__h5584 - 64'd1) ;
assign a___2__h6419 = { 32'd0, muldiv_request_put[223:192] } ;
assign a__h5584 =
muldiv_request_put[262] ?
muldiv_request_put[255:192] :
_theResult___fst__h6377 ;
assign b___1__h6386 =
{ {32{muldiv_request_put_BITS_159_TO_128__q2[31]}},
muldiv_request_put_BITS_159_TO_128__q2 } ;
assign b___1__h6451 = ~(b__h5585 - 64'd1) ;
assign b___2__h6420 = { 32'd0, muldiv_request_put[159:128] } ;
assign b__h5585 =
muldiv_request_put[262] ?
muldiv_request_put[191:128] :
_theResult___snd__h6378 ;
assign b__h5616 =
muldiv_request_put[261] ?
_theResult_____2_snd_fst__h6342 :
b__h5585 ;
assign muldiv_request_put_BITS_159_TO_128__q2 =
muldiv_request_put[159:128] ;
assign muldiv_request_put_BITS_223_TO_192__q1 =
muldiv_request_put[223:192] ;
assign mydiv___1_count__h4728 = mydiv_count__h4665 - 8'd8 ;
assign mydiv___1_dividend__h4726 = { divint[192:74], 9'd0 } ;
assign mydiv_count__h4665 = divint[9:2] - 8'd1 ;
assign mydiv_dividend__h4663 = { divint[200:74], 1'd0 } ;
assign mydiv_quotient__h4664 = { divint[72:10], 1'd0 } ;
assign mydiv_quotient__h4798 =
{ _theResult___quotient__h4721[63:1], 1'd1 } ;
assign newHi__h3951 =
{ {32{IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q6[31]}},
IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q6 } ;
assign newLo__h3950 =
{ {32{IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q7[31]}},
IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC__q7 } ;
assign product___1__h4098 = ~product__h3765 + 128'd1 ;
assign product__h3765 =
{ mulIntReg[257:194], mulIntReg[65:2] } +
{ _0_CONCAT_mulIntReg_BITS_129_TO_66_PLUS_0_CONCA_ETC__q3[95:0],
32'd0 } ;
assign product__h3952 = { newHi__h3951, newLo__h3950 } ;
assign product__h3995 = { {64{x__h3998[63]}}, x__h3998 } ;
assign product__h4310 = { {64{x__h4313[63]}}, x__h4313 } ;
assign remainder___1__h5390 = ~divint[201:138] + 64'd1 ;
assign spliced_bits__h4887 =
_theResult___dividend__h4720[127:64] - divint[265:202] ;
assign theResult_____2132_BITS_31_TO_0__q5 = _theResult_____2__h5132[31:0] ;
assign theResult___quotient201_BITS_31_TO_0__q4 =
_theResult___quotient__h5201[31:0] ;
assign x__h3998 =
{ request_fifo$D_OUT[31:0], request_fifo$D_OUT[95:64] } +
_theResult____h3766[63:0] ;
assign x__h4313 =
{ request_fifo$D_OUT[31:0], request_fifo$D_OUT[95:64] } -
_theResult____h3766[63:0] ;
assign x__h4960 =
request_fifo$D_OUT[261] ?
(spliced_bits__h4887[63] ?
_theResult___quotient__h4721 :
mydiv_quotient__h4798) :
(IF_divint_read__01_BITS_200_TO_129_03_EQ_0x0_0_ETC___d260 ?
_theResult___quotient__h4721 :
mydiv_quotient__h4798) ;
assign x_dividend__h7213 = { 64'h0, b__h5616 } ;
assign y__h5243 =
{ {32{theResult___quotient201_BITS_31_TO_0__q4[31]}},
theResult___quotient201_BITS_31_TO_0__q4 } ;
assign y__h5385 =
{ {32{theResult_____2132_BITS_31_TO_0__q5[31]}},
theResult_____2132_BITS_31_TO_0__q5 } ;
always@(request_fifo$D_OUT or
_theResult____h3766 or product__h3995 or product__h4310)
begin
case (request_fifo$D_OUT[260:256])
5'd15:
IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC___d271 =
product__h3995;
5'd16:
IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC___d271 =
product__h4310;
default: IF_request_fifo_first__4_BITS_260_TO_256_6_EQ__ETC___d271 =
_theResult____h3766;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
divint <= `BSV_ASSIGNMENT_DELAY 266'd0;
hi_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
lo_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
mulIntReg <= `BSV_ASSIGNMENT_DELAY
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
state <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (divint$EN) divint <= `BSV_ASSIGNMENT_DELAY divint$D_IN;
if (hi_fifo_taggedReg$EN)
hi_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY hi_fifo_taggedReg$D_IN;
if (lo_fifo_taggedReg$EN)
lo_fifo_taggedReg <= `BSV_ASSIGNMENT_DELAY lo_fifo_taggedReg$D_IN;
if (mulIntReg$EN) mulIntReg <= `BSV_ASSIGNMENT_DELAY mulIntReg$D_IN;
if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
divint =
266'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
hi_fifo_taggedReg = 66'h2AAAAAAAAAAAAAAAA;
lo_fifo_taggedReg = 66'h2AAAAAAAAAAAAAAAA;
mulIntReg =
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
state = 3'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkMulDiv
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:45:36 BST 2012
//
// Method conflict info:
// Method: avm_m0
// Conflict-free: avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Conflicts: avm_m0
//
// Method: avm_irq
// Conflict-free: avm_m0,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Sequenced before (restricted): avm_irq
//
// Method: avm_writedata
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_address
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_read
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_write
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_byteenable
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: debugStreamSink_stream_in
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Conflicts: debugStreamSink_stream_in
//
// Method: debugStreamSink_stream_in_ready
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out_data
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Sequenced after (restricted): debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out_valid
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Sequenced after (restricted): debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready
// Sequenced before (restricted): debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Conflicts: debugStreamSource_stream_out
//
//
// Ports:
// Name I/O size props
// avm_writedata O 256 reg
// avm_address O 32
// avm_read O 1 reg
// avm_write O 1 reg
// avm_byteenable O 32 reg
// debugStreamSink_stream_in_ready O 1
// debugStreamSource_stream_out_data O 8
// debugStreamSource_stream_out_valid O 1
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// avm_readdata I 256
// avm_readdatavalid I 1
// avm_waitrequest I 1
// avm_irq_irqs I 5 reg
// debugStreamSink_stream_in_data I 8
// debugStreamSink_stream_in_valid I 1
// debugStreamSource_stream_out_ready I 1
//
// Combinational paths from inputs to outputs:
// debugStreamSource_stream_out_ready -> debugStreamSource_stream_out_data
// debugStreamSource_stream_out_ready -> debugStreamSource_stream_out_valid
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkTopAvalonPhy(csi_clockreset_clk,
csi_clockreset_reset_n,
avm_readdata,
avm_readdatavalid,
avm_waitrequest,
avm_irq_irqs,
avm_writedata,
avm_address,
avm_read,
avm_write,
avm_byteenable,
debugStreamSink_stream_in_data,
debugStreamSink_stream_in_valid,
debugStreamSink_stream_in_ready,
debugStreamSource_stream_out_data,
debugStreamSource_stream_out_valid,
debugStreamSource_stream_out_ready);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method avm_m0
input [255 : 0] avm_readdata;
input avm_readdatavalid;
input avm_waitrequest;
// action method avm_irq
input [4 : 0] avm_irq_irqs;
// value method avm_writedata
output [255 : 0] avm_writedata;
// value method avm_address
output [31 : 0] avm_address;
// value method avm_read
output avm_read;
// value method avm_write
output avm_write;
// value method avm_byteenable
output [31 : 0] avm_byteenable;
// action method debugStreamSink_stream_in
input [7 : 0] debugStreamSink_stream_in_data;
input debugStreamSink_stream_in_valid;
// value method debugStreamSink_stream_in_ready
output debugStreamSink_stream_in_ready;
// value method debugStreamSource_stream_out_data
output [7 : 0] debugStreamSource_stream_out_data;
// value method debugStreamSource_stream_out_valid
output debugStreamSource_stream_out_valid;
// action method debugStreamSource_stream_out
input debugStreamSource_stream_out_ready;
// signals for module outputs
wire [255 : 0] avm_writedata;
wire [31 : 0] avm_address, avm_byteenable;
wire [7 : 0] debugStreamSource_stream_out_data;
wire avm_read,
avm_write,
debugStreamSink_stream_in_ready,
debugStreamSource_stream_out_valid;
// inlined wires
wire [256 : 0] datareturnbuf_rw_enq$wget;
wire [8 : 0] streamIn_d_dw$wget, streamOut_data_dw$wget;
wire signal_read$whas, signal_write$whas, streamOut_data_dw$whas;
// register address_r
reg [26 : 0] address_r;
wire [26 : 0] address_r$D_IN;
wire address_r$EN;
// register byteenable_r
reg [31 : 0] byteenable_r;
wire [31 : 0] byteenable_r$D_IN;
wire byteenable_r$EN;
// register count
reg [15 : 0] count;
wire [15 : 0] count$D_IN;
wire count$EN;
// register datareturnbuf_taggedReg
reg [257 : 0] datareturnbuf_taggedReg;
wire [257 : 0] datareturnbuf_taggedReg$D_IN;
wire datareturnbuf_taggedReg$EN;
// register interrupts
reg [4 : 0] interrupts;
wire [4 : 0] interrupts$D_IN;
wire interrupts$EN;
// register read_r
reg read_r;
wire read_r$D_IN, read_r$EN;
// register write_r
reg write_r;
wire write_r$D_IN, write_r$EN;
// register writedata_r
reg [255 : 0] writedata_r;
wire [255 : 0] writedata_r$D_IN;
wire writedata_r$EN;
// ports of submodule beri
wire [316 : 0] beri$memory_request_get;
wire [255 : 0] beri$memory_response_put;
wire [7 : 0] beri$debugStream_request_put, beri$debugStream_response_get;
wire [4 : 0] beri$putIrqs_interruptLines;
wire beri$EN_debugStream_request_put,
beri$EN_debugStream_response_get,
beri$EN_memory_request_get,
beri$EN_memory_response_put,
beri$EN_putIrqs,
beri$RDY_debugStream_request_put,
beri$RDY_debugStream_response_get,
beri$RDY_memory_request_get,
beri$RDY_memory_response_put;
// ports of submodule pending_acks
wire pending_acks$CLR,
pending_acks$DEQ,
pending_acks$D_IN,
pending_acks$EMPTY_N,
pending_acks$ENQ,
pending_acks$FULL_N;
// ports of submodule perif_reads
wire [2 : 0] perif_reads$D_IN, perif_reads$D_OUT;
wire perif_reads$CLR, perif_reads$DEQ, perif_reads$EMPTY_N, perif_reads$ENQ;
// ports of submodule streamIn_f
wire [7 : 0] streamIn_f$D_IN, streamIn_f$D_OUT;
wire streamIn_f$CLR,
streamIn_f$DEQ,
streamIn_f$EMPTY_N,
streamIn_f$ENQ,
streamIn_f$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_buffer_data_read,
WILL_FIRE_RL_datareturnbuf_rule_enq,
WILL_FIRE_RL_getRequest;
// inputs to muxes for submodule ports
wire [257 : 0] MUX_datareturnbuf_taggedReg$write_1__VAL_1;
wire MUX_datareturnbuf_taggedReg$write_1__SEL_2;
// remaining internal signals
wire [255 : 0] v__h1794, v__h1820;
// value method avm_writedata
assign avm_writedata = writedata_r ;
// value method avm_address
assign avm_address = { address_r, 5'b0 } ;
// value method avm_read
assign avm_read = read_r ;
// value method avm_write
assign avm_write = write_r ;
// value method avm_byteenable
assign avm_byteenable = byteenable_r ;
// value method debugStreamSink_stream_in_ready
assign debugStreamSink_stream_in_ready = streamIn_f$FULL_N ;
// value method debugStreamSource_stream_out_data
assign debugStreamSource_stream_out_data = streamOut_data_dw$wget[7:0] ;
// value method debugStreamSource_stream_out_valid
assign debugStreamSource_stream_out_valid =
streamOut_data_dw$whas && streamOut_data_dw$wget[8] ;
// submodule beri
mkMIPSTop beri(.csi_c0_clk(csi_clockreset_clk),
.csi_c0_reset_n(csi_clockreset_reset_n),
.debugStream_request_put(beri$debugStream_request_put),
.memory_response_put(beri$memory_response_put),
.putIrqs_interruptLines(beri$putIrqs_interruptLines),
.EN_memory_request_get(beri$EN_memory_request_get),
.EN_memory_response_put(beri$EN_memory_response_put),
.EN_putIrqs(beri$EN_putIrqs),
.EN_debugStream_request_put(beri$EN_debugStream_request_put),
.EN_debugStream_response_get(beri$EN_debugStream_response_get),
.memory_request_get(beri$memory_request_get),
.RDY_memory_request_get(beri$RDY_memory_request_get),
.RDY_memory_response_put(beri$RDY_memory_response_put),
.RDY_putIrqs(),
.RDY_debugStream_request_put(beri$RDY_debugStream_request_put),
.debugStream_response_get(beri$debugStream_response_get),
.RDY_debugStream_response_get(beri$RDY_debugStream_response_get));
// submodule pending_acks
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) pending_acks(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pending_acks$D_IN),
.ENQ(pending_acks$ENQ),
.DEQ(pending_acks$DEQ),
.CLR(pending_acks$CLR),
.D_OUT(),
.FULL_N(pending_acks$FULL_N),
.EMPTY_N(pending_acks$EMPTY_N));
// submodule perif_reads
FIFO2 #(.width(32'd3),
.guarded(32'd0)) perif_reads(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(perif_reads$D_IN),
.ENQ(perif_reads$ENQ),
.DEQ(perif_reads$DEQ),
.CLR(perif_reads$CLR),
.D_OUT(perif_reads$D_OUT),
.FULL_N(),
.EMPTY_N(perif_reads$EMPTY_N));
// submodule streamIn_f
FIFOL1 #(.width(32'd8)) streamIn_f(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(streamIn_f$D_IN),
.ENQ(streamIn_f$ENQ),
.DEQ(streamIn_f$DEQ),
.CLR(streamIn_f$CLR),
.D_OUT(streamIn_f$D_OUT),
.FULL_N(streamIn_f$FULL_N),
.EMPTY_N(streamIn_f$EMPTY_N));
// rule RL_buffer_data_read
assign WILL_FIRE_RL_buffer_data_read =
!datareturnbuf_taggedReg[257] && avm_readdatavalid ;
// rule RL_getRequest
assign WILL_FIRE_RL_getRequest =
beri$RDY_memory_request_get && pending_acks$FULL_N &&
(!avm_waitrequest || !read_r && !write_r) ;
// rule RL_datareturnbuf_rule_enq
assign WILL_FIRE_RL_datareturnbuf_rule_enq =
WILL_FIRE_RL_buffer_data_read &&
!MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_datareturnbuf_taggedReg$write_1__SEL_2 =
beri$RDY_memory_response_put &&
(datareturnbuf_taggedReg[257] ||
WILL_FIRE_RL_buffer_data_read) &&
pending_acks$EMPTY_N ;
assign MUX_datareturnbuf_taggedReg$write_1__VAL_1 =
{ 1'd1, datareturnbuf_rw_enq$wget } ;
// inlined wires
assign datareturnbuf_rw_enq$wget =
{ 1'd1, perif_reads$EMPTY_N ? v__h1794 : avm_readdata } ;
assign streamIn_d_dw$wget = { 1'd1, debugStreamSink_stream_in_data } ;
assign streamOut_data_dw$wget = { 1'd1, beri$debugStream_response_get } ;
assign streamOut_data_dw$whas =
beri$RDY_debugStream_response_get &&
debugStreamSource_stream_out_ready ;
assign signal_read$whas =
WILL_FIRE_RL_getRequest && !beri$memory_request_get[316] ;
assign signal_write$whas =
WILL_FIRE_RL_getRequest && beri$memory_request_get[316] ;
// register address_r
assign address_r$D_IN = beri$memory_request_get[315:289] ;
assign address_r$EN = WILL_FIRE_RL_getRequest ;
// register byteenable_r
assign byteenable_r$D_IN = beri$memory_request_get[32:1] ;
assign byteenable_r$EN = WILL_FIRE_RL_getRequest ;
// register count
assign count$D_IN = count + 16'd1 ;
assign count$EN =
WILL_FIRE_RL_buffer_data_read && perif_reads$EMPTY_N &&
perif_reads$D_OUT == 3'd2 ;
// register datareturnbuf_taggedReg
assign datareturnbuf_taggedReg$D_IN =
WILL_FIRE_RL_datareturnbuf_rule_enq ?
MUX_datareturnbuf_taggedReg$write_1__VAL_1 :
258'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign datareturnbuf_taggedReg$EN =
WILL_FIRE_RL_datareturnbuf_rule_enq ||
beri$RDY_memory_response_put &&
(datareturnbuf_taggedReg[257] ||
WILL_FIRE_RL_buffer_data_read) &&
pending_acks$EMPTY_N ;
// register interrupts
assign interrupts$D_IN = avm_irq_irqs ;
assign interrupts$EN = 1'd1 ;
// register read_r
assign read_r$D_IN = signal_read$whas ;
assign read_r$EN = signal_read$whas || !avm_waitrequest ;
// register write_r
assign write_r$D_IN = signal_write$whas ;
assign write_r$EN = signal_write$whas || !avm_waitrequest ;
// register writedata_r
assign writedata_r$D_IN = beri$memory_request_get[288:33] ;
assign writedata_r$EN = WILL_FIRE_RL_getRequest ;
// submodule beri
assign beri$debugStream_request_put = streamIn_f$D_OUT ;
assign beri$memory_response_put =
(WILL_FIRE_RL_buffer_data_read ?
!datareturnbuf_rw_enq$wget[256] :
datareturnbuf_taggedReg[257] &&
!datareturnbuf_taggedReg[256]) ?
256'b0 :
(WILL_FIRE_RL_buffer_data_read ?
datareturnbuf_rw_enq$wget[255:0] :
datareturnbuf_taggedReg[255:0]) ;
assign beri$putIrqs_interruptLines = interrupts ;
assign beri$EN_memory_request_get = WILL_FIRE_RL_getRequest ;
assign beri$EN_memory_response_put =
MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
assign beri$EN_putIrqs = 1'd1 ;
assign beri$EN_debugStream_request_put =
beri$RDY_debugStream_request_put && streamIn_f$EMPTY_N ;
assign beri$EN_debugStream_response_get =
beri$RDY_debugStream_response_get &&
debugStreamSource_stream_out_ready ;
// submodule pending_acks
assign pending_acks$D_IN = 1'd0 ;
assign pending_acks$ENQ = signal_read$whas ;
assign pending_acks$DEQ = MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
assign pending_acks$CLR = 1'b0 ;
// submodule perif_reads
assign perif_reads$D_IN =
(beri$memory_request_get[315:289] == 27'h3F80200) ? 3'd2 : 3'd5 ;
assign perif_reads$ENQ = signal_read$whas ;
assign perif_reads$DEQ =
WILL_FIRE_RL_buffer_data_read && perif_reads$EMPTY_N ;
assign perif_reads$CLR = 1'b0 ;
// submodule streamIn_f
assign streamIn_f$D_IN = streamIn_d_dw$wget[7:0] ;
assign streamIn_f$ENQ =
streamIn_f$FULL_N && debugStreamSink_stream_in_valid &&
streamIn_d_dw$wget[8] ;
assign streamIn_f$DEQ =
beri$RDY_debugStream_request_put && streamIn_f$EMPTY_N ;
assign streamIn_f$CLR = 1'b0 ;
// remaining internal signals
assign v__h1794 = (perif_reads$D_OUT == 3'd2) ? v__h1820 : avm_readdata ;
assign v__h1820 = { avm_readdata[255:16], count } ;
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
address_r <= `BSV_ASSIGNMENT_DELAY 27'd0;
byteenable_r <= `BSV_ASSIGNMENT_DELAY 32'hAAAAAAAA;
count <= `BSV_ASSIGNMENT_DELAY 16'd0;
datareturnbuf_taggedReg <= `BSV_ASSIGNMENT_DELAY
258'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
interrupts <= `BSV_ASSIGNMENT_DELAY 5'b0;
read_r <= `BSV_ASSIGNMENT_DELAY 1'd0;
write_r <= `BSV_ASSIGNMENT_DELAY 1'd0;
writedata_r <= `BSV_ASSIGNMENT_DELAY 256'd0;
end
else
begin
if (address_r$EN) address_r <= `BSV_ASSIGNMENT_DELAY address_r$D_IN;
if (byteenable_r$EN)
byteenable_r <= `BSV_ASSIGNMENT_DELAY byteenable_r$D_IN;
if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (datareturnbuf_taggedReg$EN)
datareturnbuf_taggedReg <= `BSV_ASSIGNMENT_DELAY
datareturnbuf_taggedReg$D_IN;
if (interrupts$EN)
interrupts <= `BSV_ASSIGNMENT_DELAY interrupts$D_IN;
if (read_r$EN) read_r <= `BSV_ASSIGNMENT_DELAY read_r$D_IN;
if (write_r$EN) write_r <= `BSV_ASSIGNMENT_DELAY write_r$D_IN;
if (writedata_r$EN)
writedata_r <= `BSV_ASSIGNMENT_DELAY writedata_r$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
address_r = 27'h2AAAAAA;
byteenable_r = 32'hAAAAAAAA;
count = 16'hAAAA;
datareturnbuf_taggedReg =
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
interrupts = 5'h0A;
read_r = 1'h0;
write_r = 1'h0;
writedata_r =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkTopAvalonPhy
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_125.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_125 (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [9:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 5,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_125",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_125.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_125.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll_125 (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_125.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 20802 $
// $Date: 2010-06-03 15:31:55 +0000 (Thu, 03 Jun 2010) $
`define BSV_WARN_REGFILE_ADDR_RANGE 0
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Multi-ported Register File
module RegFile(CLK,
ADDR_IN, D_IN, WE,
ADDR_1, D_OUT_1,
ADDR_2, D_OUT_2,
ADDR_3, D_OUT_3,
ADDR_4, D_OUT_4,
ADDR_5, D_OUT_5
);
// synopsys template
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input CLK;
input [addr_width - 1 : 0] ADDR_IN;
input [data_width - 1 : 0] D_IN;
input WE;
input [addr_width - 1 : 0] ADDR_1;
output [data_width - 1 : 0] D_OUT_1;
input [addr_width - 1 : 0] ADDR_2;
output [data_width - 1 : 0] D_OUT_2;
input [addr_width - 1 : 0] ADDR_3;
output [data_width - 1 : 0] D_OUT_3;
input [addr_width - 1 : 0] ADDR_4;
output [data_width - 1 : 0] D_OUT_4;
input [addr_width - 1 : 0] ADDR_5;
output [data_width - 1 : 0] D_OUT_5;
reg [data_width - 1 : 0] arr[lo:hi];
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : init_block
integer i; // temporary for generate reset value
for (i = lo; i <= hi; i = i + 1) begin
arr[i] = {((data_width + 1)/2){2'b10}} ;
end
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK)
begin
if (WE)
arr[ADDR_IN] <= `BSV_ASSIGNMENT_DELAY D_IN;
end // always@ (posedge CLK)
assign D_OUT_1 = arr[ADDR_1];
assign D_OUT_2 = arr[ADDR_2];
assign D_OUT_3 = arr[ADDR_3];
assign D_OUT_4 = arr[ADDR_4];
assign D_OUT_5 = arr[ADDR_5];
// synopsys translate_off
always@(posedge CLK)
begin : runtime_check
reg enable_check;
enable_check = `BSV_WARN_REGFILE_ADDR_RANGE ;
if ( enable_check )
begin
if (( ADDR_1 < lo ) || (ADDR_1 > hi) )
$display( "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", ADDR_1 ) ;
if (( ADDR_2 < lo ) || (ADDR_2 > hi) )
$display( "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", ADDR_2 ) ;
if (( ADDR_3 < lo ) || (ADDR_3 > hi) )
$display( "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", ADDR_3 ) ;
if (( ADDR_4 < lo ) || (ADDR_4 > hi) )
$display( "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", ADDR_4 ) ;
if (( ADDR_5 < lo ) || (ADDR_5 > hi) )
$display( "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", ADDR_5 ) ;
if ( WE && ( ADDR_IN < lo ) || (ADDR_IN > hi) )
$display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ;
end
end
// synopsys translate_on
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 18220 $
// $Date: 2009-10-27 15:19:11 +0000 (Tue, 27 Oct 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module RevertReg(CLK, Q_OUT, D_IN, EN);
// synopsys template
parameter width = 1;
parameter init = { width {1'b0} } ;
input CLK;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
assign Q_OUT = init;
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
// synopsys template
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1;
input CLK;
input RST_N;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: ((p2depth >= 2) ? (p2depth-2) : 0)];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth - 'd2 ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2[p3cntr_width-1:0] ) ? 'b0 : incr_head ;
assign next_tail = (tail == depthLess2[p3cntr_width-1:0] ) ? 'b0 : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
integer i;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth - 2 && p2depth > 2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK /* or negedge RST_N */ )
begin
if (!RST_N)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
for (i = 0; i <= p2depth - 2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
*/
end // if (RST_N == 0)
else
begin
// Update arr[tail] once, since some FPGA synthesis tools are unable
// to infer good RAM placement when there are multiple separate
// writes of arr[tail] <= D_IN
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
if (CLR)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (DEQ && ENQ )
begin
if (ring_empty)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end
else
begin
// moved into combined write above
// arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head];
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
end // if (DEQ && ENQ )
else if ( DEQ )
begin
if (ring_empty)
begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head];
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
end // if ( DEQ )
else if (ENQ)
begin
if (! hasodata)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
// moved into combined write above
// arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN; // drop the old element
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end // if (ENQ)
end // else: !if(RST_N == 0)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( RST_N )
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 2 )
begin
ok = 0;
$display ( "ERROR SizedFIFO.v: depth parameter must be greater than 2" ) ;
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO.v: width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
|
// megafunction wizard: %ALTTEMP_SENSE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTTEMP_SENSE
// ============================================================
// File Name: temp_sense.v
// Megafunction Name(s):
// ALTTEMP_SENSE
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alttemp_sense CBX_AUTO_BLACKBOX="ALL" CLK_FREQUENCY="50.0" CLOCK_DIVIDER_ENABLE="on" CLOCK_DIVIDER_VALUE=80 DEVICE_FAMILY="Stratix IV" NUMBER_OF_SAMPLES=128 POI_CAL_TEMPERATURE=85 SIM_TSDCALO=0 USE_WYS="on" USER_OFFSET_ENABLE="off" ce clk clr tsdcaldone tsdcalo ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 11.1 cbx_alttemp_sense 2011:10:31:21:13:15:SJ cbx_cycloneii 2011:10:31:21:13:15:SJ cbx_lpm_add_sub 2011:10:31:21:13:15:SJ cbx_lpm_compare 2011:10:31:21:13:15:SJ cbx_lpm_counter 2011:10:31:21:13:15:SJ cbx_lpm_decode 2011:10:31:21:13:15:SJ cbx_mgl 2011:10:31:21:14:05:SJ cbx_stratix 2011:10:31:21:13:15:SJ cbx_stratixii 2011:10:31:21:13:15:SJ cbx_stratixiii 2011:10:31:21:13:15:SJ cbx_stratixv 2011:10:31:21:13:15:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixiv_tsdblock 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module temp_sense_alttemp_sense_8ct
(
ce,
clk,
clr,
tsdcaldone,
tsdcalo) /* synthesis synthesis_clearbox=2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ce;
tri0 clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_tsdcaldone;
wire [7:0] wire_sd1_tsdcalo;
stratixiv_tsdblock sd1
(
.ce(ce),
.clk(clk),
.clr(clr),
.offsetout(),
.tsdcaldone(wire_sd1_tsdcaldone),
.tsdcalo(wire_sd1_tsdcalo),
.tsdcompout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.compouttest(1'b0),
.fdbkctrlfromcore(1'b0),
.offset({6{1'b0}}),
.testin({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
sd1.clock_divider_enable = "on",
sd1.clock_divider_value = 80,
sd1.sim_tsdcalo = 0,
sd1.lpm_type = "stratixiv_tsdblock";
assign
tsdcaldone = wire_sd1_tsdcaldone,
tsdcalo = wire_sd1_tsdcalo;
endmodule //temp_sense_alttemp_sense_8ct
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module temp_sense (
ce,
clk,
clr,
tsdcaldone,
tsdcalo)/* synthesis synthesis_clearbox = 2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [7:0] tsdcalo = sub_wire0[7:0];
wire tsdcaldone = sub_wire1;
temp_sense_alttemp_sense_8ct temp_sense_alttemp_sense_8ct_component (
.ce (ce),
.clk (clk),
.clr (clr),
.tsdcalo (sub_wire0),
.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = ALTTEMP_SENSE
clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix IV;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: CLK_FREQUENCY STRING "50.0"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_ENABLE STRING "ON"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_VALUE NUMERIC "80"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alttemp_sense"
// Retrieval info: CONSTANT: NUMBER_OF_SAMPLES NUMERIC "128"
// Retrieval info: CONSTANT: POI_CAL_TEMPERATURE NUMERIC "85"
// Retrieval info: CONSTANT: SIM_TSDCALO NUMERIC "0"
// Retrieval info: CONSTANT: USER_OFFSET_ENABLE STRING "off"
// Retrieval info: CONSTANT: USE_WYS STRING "on"
// Retrieval info: USED_PORT: ce 0 0 0 0 INPUT NODEFVAL "ce"
// Retrieval info: CONNECT: @ce 0 0 0 0 ce 0 0 0 0
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: USED_PORT: clr 0 0 0 0 INPUT NODEFVAL "clr"
// Retrieval info: CONNECT: @clr 0 0 0 0 clr 0 0 0 0
// Retrieval info: USED_PORT: tsdcaldone 0 0 0 0 OUTPUT NODEFVAL "tsdcaldone"
// Retrieval info: CONNECT: tsdcaldone 0 0 0 0 @tsdcaldone 0 0 0 0
// Retrieval info: USED_PORT: tsdcalo 0 0 8 0 OUTPUT NODEFVAL "tsdcalo[7..0]"
// Retrieval info: CONNECT: tsdcalo 0 0 8 0 @tsdcalo 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.cmp TRUE TRUE
|
/*****************************************************************************
Copyright (c) 2012 Simon William Moore <[email protected]>
All rights reserved.
This software was previously released by the author to students at
the University of Cambridge and made freely available on the web. It
has been included for this project under the following license.
This software was developed by SRI International and the University of
Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
("CTSRD"), as part of the DARPA CRASH research programme.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
*****************************************************************************
Paramererised Verilog Altera ROM
================================
Verilog stub for Altera's Quartus tools to provide a generic ROM interface
for AlteraROM.bsv
*****************************************************************************/
module VerilogAlteraROM(clk, v_addr, v_data, v_en, v_rdy);
parameter ADDRESS_WIDTH=11;
parameter MEM_SIZE=(1<<ADDRESS_WIDTH);
parameter DATA_WIDTH=8;
parameter FILENAME="your_rom_data.mif";
input clk;
input [ADDRESS_WIDTH-1:0] v_addr;
output reg [DATA_WIDTH-1:0] v_data;
input v_en;
output reg v_rdy;
(* ram_init_file = FILENAME *) reg [DATA_WIDTH-1:0] rom [0:MEM_SIZE-1];
always @(posedge clk) begin
v_rdy <= v_en;
if(v_en)
v_data <= rom[v_addr];
end
endmodule // Verilog_AlteraROM
|
// DE4_SOPC.v
// Generated using ACDS version 12.1 177 at 2013.01.18.12:06:11
`timescale 1 ps / 1 ps
module DE4_SOPC (
output wire sram_clk_clk, // sram_clk.clk
input wire [15:0] switches_export, // switches.export
input wire clk_50, // clk_50_clk_in.clk
input wire [9:0] touch_x1, // touch.x1
input wire [8:0] touch_y1, // .y1
input wire [9:0] touch_x2, // .x2
input wire [8:0] touch_y2, // .y2
input wire [9:0] touch_count_gesture, // .count_gesture
input wire touch_touch_valid, // .touch_valid
output wire mem_ssram_adv, // mem.ssram_adv
output wire mem_ssram_bwa_n, // .ssram_bwa_n
output wire mem_ssram_bwb_n, // .ssram_bwb_n
output wire mem_ssram_ce_n, // .ssram_ce_n
output wire mem_ssram_cke_n, // .ssram_cke_n
output wire mem_ssram_oe_n, // .ssram_oe_n
output wire mem_ssram_we_n, // .ssram_we_n
output wire [24:0] mem_fsm_a, // .fsm_a
output wire [15:0] mem_fsm_d_out, // .fsm_d_out
input wire [15:0] mem_fsm_d_in, // .fsm_d_in
output wire mem_fsm_dout_req, // .fsm_dout_req
output wire mem_flash_adv_n, // .flash_adv_n
output wire mem_flash_ce_n, // .flash_ce_n
output wire mem_flash_clk, // .flash_clk
output wire mem_flash_oe_n, // .flash_oe_n
output wire mem_flash_we_n, // .flash_we_n
inout wire sd_b_SD_cmd, // sd.b_SD_cmd
inout wire sd_b_SD_dat, // .b_SD_dat
inout wire sd_b_SD_dat3, // .b_SD_dat3
output wire sd_o_SD_clock, // .o_SD_clock
input wire reset_reset_n, // reset.reset_n
output wire [7:0] leds_external_connection_export, // leds_external_connection.export
output wire [7:0] mtl_lcd_r, // mtl_lcd.r
output wire [7:0] mtl_lcd_g, // .g
output wire [7:0] mtl_lcd_b, // .b
output wire mtl_lcd_hsd, // .hsd
output wire mtl_lcd_vsd // .vsd
);
wire timing_adapter_1_out_endofpacket; // timing_adapter_1:out_endofpacket -> receive_fifo:avalonst_sink_endofpacket
wire timing_adapter_1_out_valid; // timing_adapter_1:out_valid -> receive_fifo:avalonst_sink_valid
wire timing_adapter_1_out_startofpacket; // timing_adapter_1:out_startofpacket -> receive_fifo:avalonst_sink_startofpacket
wire [5:0] timing_adapter_1_out_error; // timing_adapter_1:out_error -> receive_fifo:avalonst_sink_error
wire [1:0] timing_adapter_1_out_empty; // timing_adapter_1:out_empty -> receive_fifo:avalonst_sink_empty
wire [31:0] timing_adapter_1_out_data; // timing_adapter_1:out_data -> receive_fifo:avalonst_sink_data
wire timing_adapter_1_out_ready; // receive_fifo:avalonst_sink_ready -> timing_adapter_1:out_ready
wire dc_fifo_0_out_endofpacket; // dc_fifo_0:out_endofpacket -> AvalonStream2MTL_LCD24bit_0:asi_stream_in_endofpacket
wire dc_fifo_0_out_valid; // dc_fifo_0:out_valid -> AvalonStream2MTL_LCD24bit_0:asi_stream_in_valid
wire dc_fifo_0_out_startofpacket; // dc_fifo_0:out_startofpacket -> AvalonStream2MTL_LCD24bit_0:asi_stream_in_startofpacket
wire [23:0] dc_fifo_0_out_data; // dc_fifo_0:out_data -> AvalonStream2MTL_LCD24bit_0:asi_stream_in_data
wire dc_fifo_0_out_ready; // AvalonStream2MTL_LCD24bit_0:asi_stream_in_ready -> dc_fifo_0:out_ready
wire mkmtl_framebuffer_flash_0_stream_out_endofpacket; // mkMTL_Framebuffer_Flash_0:aso_stream_out_endofpacket -> dc_fifo_0:in_endofpacket
wire mkmtl_framebuffer_flash_0_stream_out_valid; // mkMTL_Framebuffer_Flash_0:aso_stream_out_valid -> dc_fifo_0:in_valid
wire mkmtl_framebuffer_flash_0_stream_out_startofpacket; // mkMTL_Framebuffer_Flash_0:aso_stream_out_startofpacket -> dc_fifo_0:in_startofpacket
wire [23:0] mkmtl_framebuffer_flash_0_stream_out_data; // mkMTL_Framebuffer_Flash_0:aso_stream_out_data -> dc_fifo_0:in_data
wire mkmtl_framebuffer_flash_0_stream_out_ready; // dc_fifo_0:in_ready -> mkMTL_Framebuffer_Flash_0:aso_stream_out_ready
wire transmit_fifo_out_endofpacket; // transmit_fifo:avalonst_source_endofpacket -> timing_adapter:in_endofpacket
wire transmit_fifo_out_valid; // transmit_fifo:avalonst_source_valid -> timing_adapter:in_valid
wire transmit_fifo_out_startofpacket; // transmit_fifo:avalonst_source_startofpacket -> timing_adapter:in_startofpacket
wire transmit_fifo_out_error; // transmit_fifo:avalonst_source_error -> timing_adapter:in_error
wire [1:0] transmit_fifo_out_empty; // transmit_fifo:avalonst_source_empty -> timing_adapter:in_empty
wire [31:0] transmit_fifo_out_data; // transmit_fifo:avalonst_source_data -> timing_adapter:in_data
wire transmit_fifo_out_ready; // timing_adapter:in_ready -> transmit_fifo:avalonst_source_ready
wire [0:0] peripheral_bridge_m0_burstcount; // peripheral_bridge:m0_burstcount -> peripheral_bridge_m0_translator:av_burstcount
wire peripheral_bridge_m0_waitrequest; // peripheral_bridge_m0_translator:av_waitrequest -> peripheral_bridge:m0_waitrequest
wire [29:0] peripheral_bridge_m0_address; // peripheral_bridge:m0_address -> peripheral_bridge_m0_translator:av_address
wire [31:0] peripheral_bridge_m0_writedata; // peripheral_bridge:m0_writedata -> peripheral_bridge_m0_translator:av_writedata
wire peripheral_bridge_m0_write; // peripheral_bridge:m0_write -> peripheral_bridge_m0_translator:av_write
wire peripheral_bridge_m0_read; // peripheral_bridge:m0_read -> peripheral_bridge_m0_translator:av_read
wire [31:0] peripheral_bridge_m0_readdata; // peripheral_bridge_m0_translator:av_readdata -> peripheral_bridge:m0_readdata
wire peripheral_bridge_m0_debugaccess; // peripheral_bridge:m0_debugaccess -> peripheral_bridge_m0_translator:av_debugaccess
wire [3:0] peripheral_bridge_m0_byteenable; // peripheral_bridge:m0_byteenable -> peripheral_bridge_m0_translator:av_byteenable
wire peripheral_bridge_m0_readdatavalid; // peripheral_bridge_m0_translator:av_readdatavalid -> peripheral_bridge:m0_readdatavalid
wire mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_waitrequest; // mm_clock_crossing_bridge_0:s0_waitrequest -> mm_clock_crossing_bridge_0_s0_translator:av_waitrequest
wire [0:0] mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_burstcount; // mm_clock_crossing_bridge_0_s0_translator:av_burstcount -> mm_clock_crossing_bridge_0:s0_burstcount
wire [31:0] mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_writedata; // mm_clock_crossing_bridge_0_s0_translator:av_writedata -> mm_clock_crossing_bridge_0:s0_writedata
wire [17:0] mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_address; // mm_clock_crossing_bridge_0_s0_translator:av_address -> mm_clock_crossing_bridge_0:s0_address
wire mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_write; // mm_clock_crossing_bridge_0_s0_translator:av_write -> mm_clock_crossing_bridge_0:s0_write
wire mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_read; // mm_clock_crossing_bridge_0_s0_translator:av_read -> mm_clock_crossing_bridge_0:s0_read
wire [31:0] mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_readdata; // mm_clock_crossing_bridge_0:s0_readdata -> mm_clock_crossing_bridge_0_s0_translator:av_readdata
wire mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_debugaccess; // mm_clock_crossing_bridge_0_s0_translator:av_debugaccess -> mm_clock_crossing_bridge_0:s0_debugaccess
wire mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_readdatavalid; // mm_clock_crossing_bridge_0:s0_readdatavalid -> mm_clock_crossing_bridge_0_s0_translator:av_readdatavalid
wire [3:0] mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_byteenable; // mm_clock_crossing_bridge_0_s0_translator:av_byteenable -> mm_clock_crossing_bridge_0:s0_byteenable
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_waitrequest; // mkMTL_Framebuffer_Flash_0:avs_s0_waitrequest -> mkMTL_Framebuffer_Flash_0_s0_translator:av_waitrequest
wire [31:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_writedata; // mkMTL_Framebuffer_Flash_0_s0_translator:av_writedata -> mkMTL_Framebuffer_Flash_0:avs_s0_writedata
wire [24:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_address; // mkMTL_Framebuffer_Flash_0_s0_translator:av_address -> mkMTL_Framebuffer_Flash_0:avs_s0_address
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_write; // mkMTL_Framebuffer_Flash_0_s0_translator:av_write -> mkMTL_Framebuffer_Flash_0:avs_s0_write
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_read; // mkMTL_Framebuffer_Flash_0_s0_translator:av_read -> mkMTL_Framebuffer_Flash_0:avs_s0_read
wire [31:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_readdata; // mkMTL_Framebuffer_Flash_0:avs_s0_readdata -> mkMTL_Framebuffer_Flash_0_s0_translator:av_readdata
wire [3:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_byteenable; // mkMTL_Framebuffer_Flash_0_s0_translator:av_byteenable -> mkMTL_Framebuffer_Flash_0:avs_s0_byteenable
wire [31:0] onchip_memory_mips_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_MIPS_s1_translator:av_writedata -> onchip_memory_MIPS:writedata
wire [12:0] onchip_memory_mips_s1_translator_avalon_anti_slave_0_address; // onchip_memory_MIPS_s1_translator:av_address -> onchip_memory_MIPS:address
wire onchip_memory_mips_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_MIPS_s1_translator:av_chipselect -> onchip_memory_MIPS:chipselect
wire onchip_memory_mips_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_MIPS_s1_translator:av_clken -> onchip_memory_MIPS:clken
wire onchip_memory_mips_s1_translator_avalon_anti_slave_0_write; // onchip_memory_MIPS_s1_translator:av_write -> onchip_memory_MIPS:write
wire [31:0] onchip_memory_mips_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory_MIPS:readdata -> onchip_memory_MIPS_s1_translator:av_readdata
wire [3:0] onchip_memory_mips_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_MIPS_s1_translator:av_byteenable -> onchip_memory_MIPS:byteenable
wire [0:0] mm_clock_crossing_bridge_0_m0_burstcount; // mm_clock_crossing_bridge_0:m0_burstcount -> mm_clock_crossing_bridge_0_m0_translator:av_burstcount
wire mm_clock_crossing_bridge_0_m0_waitrequest; // mm_clock_crossing_bridge_0_m0_translator:av_waitrequest -> mm_clock_crossing_bridge_0:m0_waitrequest
wire [17:0] mm_clock_crossing_bridge_0_m0_address; // mm_clock_crossing_bridge_0:m0_address -> mm_clock_crossing_bridge_0_m0_translator:av_address
wire [31:0] mm_clock_crossing_bridge_0_m0_writedata; // mm_clock_crossing_bridge_0:m0_writedata -> mm_clock_crossing_bridge_0_m0_translator:av_writedata
wire mm_clock_crossing_bridge_0_m0_write; // mm_clock_crossing_bridge_0:m0_write -> mm_clock_crossing_bridge_0_m0_translator:av_write
wire mm_clock_crossing_bridge_0_m0_read; // mm_clock_crossing_bridge_0:m0_read -> mm_clock_crossing_bridge_0_m0_translator:av_read
wire [31:0] mm_clock_crossing_bridge_0_m0_readdata; // mm_clock_crossing_bridge_0_m0_translator:av_readdata -> mm_clock_crossing_bridge_0:m0_readdata
wire mm_clock_crossing_bridge_0_m0_debugaccess; // mm_clock_crossing_bridge_0:m0_debugaccess -> mm_clock_crossing_bridge_0_m0_translator:av_debugaccess
wire [3:0] mm_clock_crossing_bridge_0_m0_byteenable; // mm_clock_crossing_bridge_0:m0_byteenable -> mm_clock_crossing_bridge_0_m0_translator:av_byteenable
wire mm_clock_crossing_bridge_0_m0_readdatavalid; // mm_clock_crossing_bridge_0_m0_translator:av_readdatavalid -> mm_clock_crossing_bridge_0:m0_readdatavalid
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest; // Altera_UP_SD_Card_Avalon_Interface_1:o_avalon_waitrequest -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_waitrequest
wire [31:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_writedata -> Altera_UP_SD_Card_Avalon_Interface_1:i_avalon_writedata
wire [7:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_address; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_address -> Altera_UP_SD_Card_Avalon_Interface_1:i_avalon_address
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_chipselect; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_chipselect -> Altera_UP_SD_Card_Avalon_Interface_1:i_avalon_chip_select
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_write; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_write -> Altera_UP_SD_Card_Avalon_Interface_1:i_avalon_write
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_read; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_read -> Altera_UP_SD_Card_Avalon_Interface_1:i_avalon_read
wire [31:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // Altera_UP_SD_Card_Avalon_Interface_1:o_avalon_readdata -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_readdata
wire [3:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:av_byteenable -> Altera_UP_SD_Card_Avalon_Interface_1:i_avalon_byteenable
wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata
wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address
wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect
wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n
wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata
wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // Switches_s1_translator:av_address -> Switches:address
wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // Switches:readdata -> Switches_s1_translator:av_readdata
wire transmit_fifo_in_translator_avalon_anti_slave_0_waitrequest; // transmit_fifo:avalonmm_write_slave_waitrequest -> transmit_fifo_in_translator:av_waitrequest
wire [31:0] transmit_fifo_in_translator_avalon_anti_slave_0_writedata; // transmit_fifo_in_translator:av_writedata -> transmit_fifo:avalonmm_write_slave_writedata
wire [0:0] transmit_fifo_in_translator_avalon_anti_slave_0_address; // transmit_fifo_in_translator:av_address -> transmit_fifo:avalonmm_write_slave_address
wire transmit_fifo_in_translator_avalon_anti_slave_0_write; // transmit_fifo_in_translator:av_write -> transmit_fifo:avalonmm_write_slave_write
wire [31:0] transmit_fifo_in_csr_translator_avalon_anti_slave_0_writedata; // transmit_fifo_in_csr_translator:av_writedata -> transmit_fifo:wrclk_control_slave_writedata
wire [2:0] transmit_fifo_in_csr_translator_avalon_anti_slave_0_address; // transmit_fifo_in_csr_translator:av_address -> transmit_fifo:wrclk_control_slave_address
wire transmit_fifo_in_csr_translator_avalon_anti_slave_0_write; // transmit_fifo_in_csr_translator:av_write -> transmit_fifo:wrclk_control_slave_write
wire transmit_fifo_in_csr_translator_avalon_anti_slave_0_read; // transmit_fifo_in_csr_translator:av_read -> transmit_fifo:wrclk_control_slave_read
wire [31:0] transmit_fifo_in_csr_translator_avalon_anti_slave_0_readdata; // transmit_fifo:wrclk_control_slave_readdata -> transmit_fifo_in_csr_translator:av_readdata
wire receive_fifo_out_translator_avalon_anti_slave_0_waitrequest; // receive_fifo:avalonmm_read_slave_waitrequest -> receive_fifo_out_translator:av_waitrequest
wire [0:0] receive_fifo_out_translator_avalon_anti_slave_0_address; // receive_fifo_out_translator:av_address -> receive_fifo:avalonmm_read_slave_address
wire receive_fifo_out_translator_avalon_anti_slave_0_read; // receive_fifo_out_translator:av_read -> receive_fifo:avalonmm_read_slave_read
wire [31:0] receive_fifo_out_translator_avalon_anti_slave_0_readdata; // receive_fifo:avalonmm_read_slave_readdata -> receive_fifo_out_translator:av_readdata
wire [31:0] receive_fifo_out_csr_translator_avalon_anti_slave_0_writedata; // receive_fifo_out_csr_translator:av_writedata -> receive_fifo:rdclk_control_slave_writedata
wire [2:0] receive_fifo_out_csr_translator_avalon_anti_slave_0_address; // receive_fifo_out_csr_translator:av_address -> receive_fifo:rdclk_control_slave_address
wire receive_fifo_out_csr_translator_avalon_anti_slave_0_write; // receive_fifo_out_csr_translator:av_write -> receive_fifo:rdclk_control_slave_write
wire receive_fifo_out_csr_translator_avalon_anti_slave_0_read; // receive_fifo_out_csr_translator:av_read -> receive_fifo:rdclk_control_slave_read
wire [31:0] receive_fifo_out_csr_translator_avalon_anti_slave_0_readdata; // receive_fifo:rdclk_control_slave_readdata -> receive_fifo_out_csr_translator:av_readdata
wire [31:0] versionrom_s1_translator_avalon_anti_slave_0_writedata; // versionRom_s1_translator:av_writedata -> versionRom:writedata
wire [2:0] versionrom_s1_translator_avalon_anti_slave_0_address; // versionRom_s1_translator:av_address -> versionRom:address
wire versionrom_s1_translator_avalon_anti_slave_0_chipselect; // versionRom_s1_translator:av_chipselect -> versionRom:chipselect
wire versionrom_s1_translator_avalon_anti_slave_0_clken; // versionRom_s1_translator:av_clken -> versionRom:clken
wire versionrom_s1_translator_avalon_anti_slave_0_write; // versionRom_s1_translator:av_write -> versionRom:write
wire [31:0] versionrom_s1_translator_avalon_anti_slave_0_readdata; // versionRom:readdata -> versionRom_s1_translator:av_readdata
wire versionrom_s1_translator_avalon_anti_slave_0_debugaccess; // versionRom_s1_translator:av_debugaccess -> versionRom:debugaccess
wire [3:0] versionrom_s1_translator_avalon_anti_slave_0_byteenable; // versionRom_s1_translator:av_byteenable -> versionRom:byteenable
wire cheri_avalon_master_0_waitrequest; // CHERI_avalon_master_0_translator:av_waitrequest -> CHERI:avm_waitrequest
wire [31:0] cheri_avalon_master_0_address; // CHERI:avm_address -> CHERI_avalon_master_0_translator:av_address
wire [255:0] cheri_avalon_master_0_writedata; // CHERI:avm_writedata -> CHERI_avalon_master_0_translator:av_writedata
wire cheri_avalon_master_0_write; // CHERI:avm_write -> CHERI_avalon_master_0_translator:av_write
wire cheri_avalon_master_0_read; // CHERI:avm_read -> CHERI_avalon_master_0_translator:av_read
wire [255:0] cheri_avalon_master_0_readdata; // CHERI_avalon_master_0_translator:av_readdata -> CHERI:avm_readdata
wire [31:0] cheri_avalon_master_0_byteenable; // CHERI:avm_byteenable -> CHERI_avalon_master_0_translator:av_byteenable
wire cheri_avalon_master_0_readdatavalid; // CHERI_avalon_master_0_translator:av_readdatavalid -> CHERI:avm_readdatavalid
wire peripheral_bridge_s0_translator_avalon_anti_slave_0_waitrequest; // peripheral_bridge:s0_waitrequest -> peripheral_bridge_s0_translator:av_waitrequest
wire [0:0] peripheral_bridge_s0_translator_avalon_anti_slave_0_burstcount; // peripheral_bridge_s0_translator:av_burstcount -> peripheral_bridge:s0_burstcount
wire [31:0] peripheral_bridge_s0_translator_avalon_anti_slave_0_writedata; // peripheral_bridge_s0_translator:av_writedata -> peripheral_bridge:s0_writedata
wire [29:0] peripheral_bridge_s0_translator_avalon_anti_slave_0_address; // peripheral_bridge_s0_translator:av_address -> peripheral_bridge:s0_address
wire peripheral_bridge_s0_translator_avalon_anti_slave_0_write; // peripheral_bridge_s0_translator:av_write -> peripheral_bridge:s0_write
wire peripheral_bridge_s0_translator_avalon_anti_slave_0_read; // peripheral_bridge_s0_translator:av_read -> peripheral_bridge:s0_read
wire [31:0] peripheral_bridge_s0_translator_avalon_anti_slave_0_readdata; // peripheral_bridge:s0_readdata -> peripheral_bridge_s0_translator:av_readdata
wire peripheral_bridge_s0_translator_avalon_anti_slave_0_debugaccess; // peripheral_bridge_s0_translator:av_debugaccess -> peripheral_bridge:s0_debugaccess
wire peripheral_bridge_s0_translator_avalon_anti_slave_0_readdatavalid; // peripheral_bridge:s0_readdatavalid -> peripheral_bridge_s0_translator:av_readdatavalid
wire [3:0] peripheral_bridge_s0_translator_avalon_anti_slave_0_byteenable; // peripheral_bridge_s0_translator:av_byteenable -> peripheral_bridge:s0_byteenable
wire peripheral_bridge_m0_translator_avalon_universal_master_0_waitrequest; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> peripheral_bridge_m0_translator:uav_waitrequest
wire [2:0] peripheral_bridge_m0_translator_avalon_universal_master_0_burstcount; // peripheral_bridge_m0_translator:uav_burstcount -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] peripheral_bridge_m0_translator_avalon_universal_master_0_writedata; // peripheral_bridge_m0_translator:uav_writedata -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
wire [29:0] peripheral_bridge_m0_translator_avalon_universal_master_0_address; // peripheral_bridge_m0_translator:uav_address -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_address
wire peripheral_bridge_m0_translator_avalon_universal_master_0_lock; // peripheral_bridge_m0_translator:uav_lock -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_lock
wire peripheral_bridge_m0_translator_avalon_universal_master_0_write; // peripheral_bridge_m0_translator:uav_write -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_write
wire peripheral_bridge_m0_translator_avalon_universal_master_0_read; // peripheral_bridge_m0_translator:uav_read -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_read
wire [31:0] peripheral_bridge_m0_translator_avalon_universal_master_0_readdata; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> peripheral_bridge_m0_translator:uav_readdata
wire peripheral_bridge_m0_translator_avalon_universal_master_0_debugaccess; // peripheral_bridge_m0_translator:uav_debugaccess -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] peripheral_bridge_m0_translator_avalon_universal_master_0_byteenable; // peripheral_bridge_m0_translator:uav_byteenable -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
wire peripheral_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> peripheral_bridge_m0_translator:uav_readdatavalid
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // mm_clock_crossing_bridge_0_s0_translator:uav_waitrequest -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> mm_clock_crossing_bridge_0_s0_translator:uav_burstcount
wire [31:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> mm_clock_crossing_bridge_0_s0_translator:uav_writedata
wire [29:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_address; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_address -> mm_clock_crossing_bridge_0_s0_translator:uav_address
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_write; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_write -> mm_clock_crossing_bridge_0_s0_translator:uav_write
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_lock; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_lock -> mm_clock_crossing_bridge_0_s0_translator:uav_lock
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_read; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_read -> mm_clock_crossing_bridge_0_s0_translator:uav_read
wire [31:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata; // mm_clock_crossing_bridge_0_s0_translator:uav_readdata -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_readdata
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // mm_clock_crossing_bridge_0_s0_translator:uav_readdatavalid -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> mm_clock_crossing_bridge_0_s0_translator:uav_debugaccess
wire [3:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> mm_clock_crossing_bridge_0_s0_translator:uav_byteenable
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [101:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [101:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // mkMTL_Framebuffer_Flash_0_s0_translator:uav_waitrequest -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_burstcount
wire [31:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_writedata
wire [29:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_address; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_address -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_address
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_write; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_write -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_write
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_lock; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_lock -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_lock
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_read; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_read -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_read
wire [31:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata; // mkMTL_Framebuffer_Flash_0_s0_translator:uav_readdata -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_readdata
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // mkMTL_Framebuffer_Flash_0_s0_translator:uav_readdatavalid -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_debugaccess
wire [3:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> mkMTL_Framebuffer_Flash_0_s0_translator:uav_byteenable
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [101:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [101:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_MIPS_s1_translator:uav_waitrequest -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_MIPS_s1_translator:uav_burstcount
wire [31:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_MIPS_s1_translator:uav_writedata
wire [29:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_MIPS_s1_translator:uav_address
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_MIPS_s1_translator:uav_write
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_MIPS_s1_translator:uav_lock
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_MIPS_s1_translator:uav_read
wire [31:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_MIPS_s1_translator:uav_readdata -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_MIPS_s1_translator:uav_readdatavalid -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_MIPS_s1_translator:uav_debugaccess
wire [3:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_MIPS_s1_translator:uav_byteenable
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [101:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [101:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_waitrequest; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> mm_clock_crossing_bridge_0_m0_translator:uav_waitrequest
wire [2:0] mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_burstcount; // mm_clock_crossing_bridge_0_m0_translator:uav_burstcount -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_writedata; // mm_clock_crossing_bridge_0_m0_translator:uav_writedata -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_writedata
wire [17:0] mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_address; // mm_clock_crossing_bridge_0_m0_translator:uav_address -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_address
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_lock; // mm_clock_crossing_bridge_0_m0_translator:uav_lock -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_lock
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_write; // mm_clock_crossing_bridge_0_m0_translator:uav_write -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_write
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_read; // mm_clock_crossing_bridge_0_m0_translator:uav_read -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_read
wire [31:0] mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_readdata; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_readdata -> mm_clock_crossing_bridge_0_m0_translator:uav_readdata
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_debugaccess; // mm_clock_crossing_bridge_0_m0_translator:uav_debugaccess -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_byteenable; // mm_clock_crossing_bridge_0_m0_translator:uav_byteenable -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_byteenable
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_readdatavalid; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> mm_clock_crossing_bridge_0_m0_translator:uav_readdatavalid
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_waitrequest -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_burstcount
wire [31:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_writedata
wire [17:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_address
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_write
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_lock
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_read
wire [31:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_readdata -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_readdatavalid -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_debugaccess
wire [3:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:uav_byteenable
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount
wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata
wire [17:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address
wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write
wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock
wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read
wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess
wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable
wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Switches_s1_translator:uav_waitrequest -> Switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> Switches_s1_translator:uav_burstcount
wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> Switches_s1_translator:uav_writedata
wire [17:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> Switches_s1_translator:uav_address
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> Switches_s1_translator:uav_write
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> Switches_s1_translator:uav_lock
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> Switches_s1_translator:uav_read
wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // Switches_s1_translator:uav_readdata -> Switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Switches_s1_translator:uav_readdatavalid -> Switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Switches_s1_translator:uav_debugaccess
wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // Switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> Switches_s1_translator:uav_byteenable
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // Switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // Switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_waitrequest; // transmit_fifo_in_translator:uav_waitrequest -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_burstcount; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_burstcount -> transmit_fifo_in_translator:uav_burstcount
wire [31:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_writedata; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_writedata -> transmit_fifo_in_translator:uav_writedata
wire [17:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_address; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_address -> transmit_fifo_in_translator:uav_address
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_write; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_write -> transmit_fifo_in_translator:uav_write
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_lock; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_lock -> transmit_fifo_in_translator:uav_lock
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_read; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_read -> transmit_fifo_in_translator:uav_read
wire [31:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_readdata; // transmit_fifo_in_translator:uav_readdata -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_readdata
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // transmit_fifo_in_translator:uav_readdatavalid -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_debugaccess; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_debugaccess -> transmit_fifo_in_translator:uav_debugaccess
wire [3:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_byteenable; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:m0_byteenable -> transmit_fifo_in_translator:uav_byteenable
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_valid; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_source_valid -> transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_data; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_source_data -> transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_ready; // transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_source_ready
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_sink_data
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rf_sink_ready -> transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // transmit_fifo_in_csr_translator:uav_waitrequest -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> transmit_fifo_in_csr_translator:uav_burstcount
wire [31:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> transmit_fifo_in_csr_translator:uav_writedata
wire [17:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_address; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_address -> transmit_fifo_in_csr_translator:uav_address
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_write; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_write -> transmit_fifo_in_csr_translator:uav_write
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_lock; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_lock -> transmit_fifo_in_csr_translator:uav_lock
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_read; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_read -> transmit_fifo_in_csr_translator:uav_read
wire [31:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // transmit_fifo_in_csr_translator:uav_readdata -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_readdata
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // transmit_fifo_in_csr_translator:uav_readdatavalid -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> transmit_fifo_in_csr_translator:uav_debugaccess
wire [3:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> transmit_fifo_in_csr_translator:uav_byteenable
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_waitrequest; // receive_fifo_out_translator:uav_waitrequest -> receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_burstcount; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_burstcount -> receive_fifo_out_translator:uav_burstcount
wire [31:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_writedata; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_writedata -> receive_fifo_out_translator:uav_writedata
wire [17:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_address; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_address -> receive_fifo_out_translator:uav_address
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_write; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_write -> receive_fifo_out_translator:uav_write
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_lock; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_lock -> receive_fifo_out_translator:uav_lock
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_read; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_read -> receive_fifo_out_translator:uav_read
wire [31:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_readdata; // receive_fifo_out_translator:uav_readdata -> receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_readdata
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // receive_fifo_out_translator:uav_readdatavalid -> receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_debugaccess; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_debugaccess -> receive_fifo_out_translator:uav_debugaccess
wire [3:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_byteenable; // receive_fifo_out_translator_avalon_universal_slave_0_agent:m0_byteenable -> receive_fifo_out_translator:uav_byteenable
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_valid; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_source_valid -> receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_data; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_source_data -> receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_ready; // receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_source_ready
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_sink_data
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rf_sink_ready -> receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest; // receive_fifo_out_csr_translator:uav_waitrequest -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_burstcount; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_burstcount -> receive_fifo_out_csr_translator:uav_burstcount
wire [31:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_writedata; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_writedata -> receive_fifo_out_csr_translator:uav_writedata
wire [17:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_address; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_address -> receive_fifo_out_csr_translator:uav_address
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_write; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_write -> receive_fifo_out_csr_translator:uav_write
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_lock; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_lock -> receive_fifo_out_csr_translator:uav_lock
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_read; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_read -> receive_fifo_out_csr_translator:uav_read
wire [31:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_readdata; // receive_fifo_out_csr_translator:uav_readdata -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_readdata
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // receive_fifo_out_csr_translator:uav_readdatavalid -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_debugaccess -> receive_fifo_out_csr_translator:uav_debugaccess
wire [3:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_byteenable; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:m0_byteenable -> receive_fifo_out_csr_translator:uav_byteenable
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_valid; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_source_valid -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_data; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_source_data -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_ready; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_source_ready
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_sink_data
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rf_sink_ready -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire versionrom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // versionRom_s1_translator:uav_waitrequest -> versionRom_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] versionrom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> versionRom_s1_translator:uav_burstcount
wire [31:0] versionrom_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> versionRom_s1_translator:uav_writedata
wire [17:0] versionrom_s1_translator_avalon_universal_slave_0_agent_m0_address; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_address -> versionRom_s1_translator:uav_address
wire versionrom_s1_translator_avalon_universal_slave_0_agent_m0_write; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_write -> versionRom_s1_translator:uav_write
wire versionrom_s1_translator_avalon_universal_slave_0_agent_m0_lock; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_lock -> versionRom_s1_translator:uav_lock
wire versionrom_s1_translator_avalon_universal_slave_0_agent_m0_read; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_read -> versionRom_s1_translator:uav_read
wire [31:0] versionrom_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // versionRom_s1_translator:uav_readdata -> versionRom_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire versionrom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // versionRom_s1_translator:uav_readdatavalid -> versionRom_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire versionrom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> versionRom_s1_translator:uav_debugaccess
wire [3:0] versionrom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // versionRom_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> versionRom_s1_translator:uav_byteenable
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // versionRom_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // versionRom_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // versionRom_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [91:0] versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // versionRom_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> versionRom_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> versionRom_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> versionRom_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> versionRom_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [91:0] versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> versionRom_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // versionRom_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // versionRom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> versionRom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // versionRom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> versionRom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // versionRom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> versionRom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cheri_avalon_master_0_translator_avalon_universal_master_0_waitrequest; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_waitrequest -> CHERI_avalon_master_0_translator:uav_waitrequest
wire [5:0] cheri_avalon_master_0_translator_avalon_universal_master_0_burstcount; // CHERI_avalon_master_0_translator:uav_burstcount -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_burstcount
wire [255:0] cheri_avalon_master_0_translator_avalon_universal_master_0_writedata; // CHERI_avalon_master_0_translator:uav_writedata -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] cheri_avalon_master_0_translator_avalon_universal_master_0_address; // CHERI_avalon_master_0_translator:uav_address -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_address
wire cheri_avalon_master_0_translator_avalon_universal_master_0_lock; // CHERI_avalon_master_0_translator:uav_lock -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_lock
wire cheri_avalon_master_0_translator_avalon_universal_master_0_write; // CHERI_avalon_master_0_translator:uav_write -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_write
wire cheri_avalon_master_0_translator_avalon_universal_master_0_read; // CHERI_avalon_master_0_translator:uav_read -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_read
wire [255:0] cheri_avalon_master_0_translator_avalon_universal_master_0_readdata; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_readdata -> CHERI_avalon_master_0_translator:uav_readdata
wire cheri_avalon_master_0_translator_avalon_universal_master_0_debugaccess; // CHERI_avalon_master_0_translator:uav_debugaccess -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_debugaccess
wire [31:0] cheri_avalon_master_0_translator_avalon_universal_master_0_byteenable; // CHERI_avalon_master_0_translator:uav_byteenable -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_byteenable
wire cheri_avalon_master_0_translator_avalon_universal_master_0_readdatavalid; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:av_readdatavalid -> CHERI_avalon_master_0_translator:uav_readdatavalid
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // peripheral_bridge_s0_translator:uav_waitrequest -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> peripheral_bridge_s0_translator:uav_burstcount
wire [31:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> peripheral_bridge_s0_translator:uav_writedata
wire [31:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_address -> peripheral_bridge_s0_translator:uav_address
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_write -> peripheral_bridge_s0_translator:uav_write
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_lock -> peripheral_bridge_s0_translator:uav_lock
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_read -> peripheral_bridge_s0_translator:uav_read
wire [31:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata; // peripheral_bridge_s0_translator:uav_readdata -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdata
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // peripheral_bridge_s0_translator:uav_readdatavalid -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> peripheral_bridge_s0_translator:uav_debugaccess
wire [3:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> peripheral_bridge_s0_translator:uav_byteenable
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [100:0] peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_data; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_valid; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [100:0] mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_data; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:rp_ready
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_valid; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [100:0] mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_data; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:rp_ready
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [100:0] onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_endofpacket; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_valid; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_startofpacket; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [90:0] mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_data; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:cp_ready
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [90:0] altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [90:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // Switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [90:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // Switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> Switches_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_endofpacket; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_valid; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_startofpacket; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
wire [90:0] transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_data; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
wire transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:rp_ready
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_valid; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
wire [90:0] transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_data; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
wire transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:rp_ready
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_endofpacket; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_valid; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_startofpacket; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
wire [90:0] receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_data; // receive_fifo_out_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
wire receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> receive_fifo_out_translator_avalon_universal_slave_0_agent:rp_ready
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_valid; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
wire [90:0] receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_data; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
wire receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:rp_ready
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // versionRom_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rp_valid; // versionRom_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // versionRom_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
wire [90:0] versionrom_s1_translator_avalon_universal_slave_0_agent_rp_data; // versionRom_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
wire versionrom_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> versionRom_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_valid; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [358:0] cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_data; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:cp_ready
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
wire [106:0] peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
wire peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [100:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [2:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [100:0] limiter_rsp_src_data; // limiter:rsp_src_data -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:rp_data
wire [2:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> peripheral_bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // peripheral_bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [90:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [90:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_001_rsp_src_ready; // mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] burst_adapter_source0_data; // burst_adapter:source0_data -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire burst_adapter_source0_channel; // burst_adapter:source0_channel -> peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:cp_channel
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [CHERI:csi_clockreset_reset_n, CHERI_avalon_master_0_translator:reset, CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:reset, addr_router:reset, addr_router_002:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_002:reset, dc_fifo_0:in_reset_n, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_011:reset, irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, limiter:reset, limiter_pipeline:reset, limiter_pipeline_001:reset, mkMTL_Framebuffer_Flash_0:csi_clockreset_reset_n, mkMTL_Framebuffer_Flash_0_s0_translator:reset, mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:reset, mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, mm_clock_crossing_bridge_0:s0_reset, mm_clock_crossing_bridge_0_s0_translator:reset, mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:reset, mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory_MIPS:reset, onchip_memory_MIPS_s1_translator:reset, onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, peripheral_bridge:reset, peripheral_bridge_m0_translator:reset, peripheral_bridge_m0_translator_avalon_universal_master_0_agent:reset, peripheral_bridge_s0_translator:reset, peripheral_bridge_s0_translator_avalon_universal_slave_0_agent:reset, peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_011:reset, rsp_xbar_mux:reset, width_adapter:reset, width_adapter_001:reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [Altera_UP_SD_Card_Avalon_Interface_1:i_reset_n, Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator:reset, Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, AvalonStream2MTL_LCD24bit_0:csi_clockreset_reset_n, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Switches:reset_n, Switches_s1_translator:reset, Switches_s1_translator_avalon_universal_slave_0_agent:reset, Switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router_001:reset, cmd_xbar_demux_001:reset, dc_fifo_0:out_reset_n, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, irq_synchronizer:receiver_reset, irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, limiter_001:reset, limiter_pipeline_002:reset, limiter_pipeline_003:reset, mm_clock_crossing_bridge_0:m0_reset, mm_clock_crossing_bridge_0_m0_translator:reset, mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent:reset, receive_fifo:rdreset_n, receive_fifo:wrreset_n, receive_fifo_out_csr_translator:reset, receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:reset, receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, receive_fifo_out_translator:reset, receive_fifo_out_translator_avalon_universal_slave_0_agent:reset, receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_mux_001:reset, timing_adapter:reset_n, timing_adapter_1:reset_n, transmit_fifo:reset_n, transmit_fifo_in_csr_translator:reset, transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:reset, transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, transmit_fifo_in_translator:reset, transmit_fifo_in_translator_avalon_universal_slave_0_agent:reset, transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, versionRom:reset, versionRom_s1_translator:reset, versionRom_s1_translator_avalon_universal_slave_0_agent:reset, versionRom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [100:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:cp_data
wire [2:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [100:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:cp_data
wire [2:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [100:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [2:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [100:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [2:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [100:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [2:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [100:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [2:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire cmd_xbar_demux_src0_ready; // mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src0_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [100:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [2:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_demux_src1_ready; // mkMTL_Framebuffer_Flash_0_s0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src1_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [100:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [2:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_demux_src2_ready; // onchip_memory_MIPS_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [100:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [2:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> Switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> Switches_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> Switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> Switches_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> Switches_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> transmit_fifo_in_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> receive_fifo_out_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> receive_fifo_out_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> receive_fifo_out_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> receive_fifo_out_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> receive_fifo_out_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> versionRom_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> versionRom_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> versionRom_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [90:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> versionRom_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> versionRom_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [90:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink0_data
wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [90:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink1_data
wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [90:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink2_data
wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [90:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink3_data
wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_006:src0_ready
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [90:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink4_data
wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_007:src0_ready
wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [90:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink5_data
wire [7:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_008:src0_ready
wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink6_valid
wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
wire [90:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink6_data
wire [7:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink6_channel
wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_009:src0_ready
wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink7_valid
wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
wire [90:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink7_data
wire [7:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink7_channel
wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_010:src0_ready
wire cmd_xbar_demux_001_src0_ready; // Altera_UP_SD_Card_Avalon_Interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src0_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [90:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_001_src1_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src1_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [90:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src2_ready; // Switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [90:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_demux_001_src3_ready; // transmit_fifo_in_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
wire [90:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
wire cmd_xbar_demux_001_src4_ready; // transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
wire [90:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
wire cmd_xbar_demux_001_src5_ready; // receive_fifo_out_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
wire [90:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
wire [7:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
wire cmd_xbar_demux_001_src6_ready; // receive_fifo_out_csr_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
wire [90:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data
wire [7:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
wire cmd_xbar_demux_001_src7_ready; // versionRom_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
wire [90:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data
wire [7:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> width_adapter:in_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> width_adapter:in_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> width_adapter:in_startofpacket
wire [358:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> width_adapter:in_data
wire [0:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> width_adapter:in_channel
wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [358:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:rp_data
wire [0:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:rp_channel
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [358:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
wire [0:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
wire rsp_xbar_demux_011_src0_ready; // CHERI_avalon_master_0_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_011:src0_ready
wire cmd_xbar_demux_002_src0_ready; // width_adapter:in_ready -> cmd_xbar_demux_002:src0_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> burst_adapter:sink0_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
wire [106:0] width_adapter_src_data; // width_adapter:out_data -> burst_adapter:sink0_data
wire width_adapter_src_ready; // burst_adapter:sink0_ready -> width_adapter:out_ready
wire width_adapter_src_channel; // width_adapter:out_channel -> burst_adapter:sink0_channel
wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> width_adapter_001:in_endofpacket
wire id_router_011_src_valid; // id_router_011:src_valid -> width_adapter_001:in_valid
wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> width_adapter_001:in_startofpacket
wire [106:0] id_router_011_src_data; // id_router_011:src_data -> width_adapter_001:in_data
wire [0:0] id_router_011_src_channel; // id_router_011:src_channel -> width_adapter_001:in_channel
wire id_router_011_src_ready; // width_adapter_001:in_ready -> id_router_011:src_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_011:sink_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
wire [358:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_011:sink_data
wire width_adapter_001_src_ready; // rsp_xbar_demux_011:sink_ready -> width_adapter_001:out_ready
wire width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_011:sink_channel
wire limiter_pipeline_source0_endofpacket; // limiter_pipeline:out_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_pipeline_source0_valid; // limiter_pipeline:out_valid -> cmd_xbar_demux:sink_valid
wire limiter_pipeline_source0_startofpacket; // limiter_pipeline:out_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [100:0] limiter_pipeline_source0_data; // limiter_pipeline:out_data -> cmd_xbar_demux:sink_data
wire [2:0] limiter_pipeline_source0_channel; // limiter_pipeline:out_channel -> cmd_xbar_demux:sink_channel
wire limiter_pipeline_source0_ready; // cmd_xbar_demux:sink_ready -> limiter_pipeline:out_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> limiter_pipeline:in_endofpacket
wire [0:0] limiter_cmd_src_valid; // limiter:cmd_src_valid -> limiter_pipeline:in_valid
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> limiter_pipeline:in_startofpacket
wire [100:0] limiter_cmd_src_data; // limiter:cmd_src_data -> limiter_pipeline:in_data
wire [2:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> limiter_pipeline:in_channel
wire limiter_cmd_src_ready; // limiter_pipeline:in_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter_pipeline_001:in_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter_pipeline_001:in_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter_pipeline_001:in_startofpacket
wire [100:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter_pipeline_001:in_data
wire [2:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter_pipeline_001:in_channel
wire rsp_xbar_mux_src_ready; // limiter_pipeline_001:in_ready -> rsp_xbar_mux:src_ready
wire limiter_pipeline_001_source0_endofpacket; // limiter_pipeline_001:out_endofpacket -> limiter:rsp_sink_endofpacket
wire limiter_pipeline_001_source0_valid; // limiter_pipeline_001:out_valid -> limiter:rsp_sink_valid
wire limiter_pipeline_001_source0_startofpacket; // limiter_pipeline_001:out_startofpacket -> limiter:rsp_sink_startofpacket
wire [100:0] limiter_pipeline_001_source0_data; // limiter_pipeline_001:out_data -> limiter:rsp_sink_data
wire [2:0] limiter_pipeline_001_source0_channel; // limiter_pipeline_001:out_channel -> limiter:rsp_sink_channel
wire limiter_pipeline_001_source0_ready; // limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
wire limiter_pipeline_002_source0_endofpacket; // limiter_pipeline_002:out_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_pipeline_002_source0_valid; // limiter_pipeline_002:out_valid -> cmd_xbar_demux_001:sink_valid
wire limiter_pipeline_002_source0_startofpacket; // limiter_pipeline_002:out_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [90:0] limiter_pipeline_002_source0_data; // limiter_pipeline_002:out_data -> cmd_xbar_demux_001:sink_data
wire [7:0] limiter_pipeline_002_source0_channel; // limiter_pipeline_002:out_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_pipeline_002_source0_ready; // cmd_xbar_demux_001:sink_ready -> limiter_pipeline_002:out_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> limiter_pipeline_002:in_endofpacket
wire [0:0] limiter_001_cmd_src_valid; // limiter_001:cmd_src_valid -> limiter_pipeline_002:in_valid
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> limiter_pipeline_002:in_startofpacket
wire [90:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> limiter_pipeline_002:in_data
wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> limiter_pipeline_002:in_channel
wire limiter_001_cmd_src_ready; // limiter_pipeline_002:in_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_pipeline_003:in_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_pipeline_003:in_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_pipeline_003:in_startofpacket
wire [90:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_pipeline_003:in_data
wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_pipeline_003:in_channel
wire rsp_xbar_mux_001_src_ready; // limiter_pipeline_003:in_ready -> rsp_xbar_mux_001:src_ready
wire limiter_pipeline_003_source0_endofpacket; // limiter_pipeline_003:out_endofpacket -> limiter_001:rsp_sink_endofpacket
wire limiter_pipeline_003_source0_valid; // limiter_pipeline_003:out_valid -> limiter_001:rsp_sink_valid
wire limiter_pipeline_003_source0_startofpacket; // limiter_pipeline_003:out_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [90:0] limiter_pipeline_003_source0_data; // limiter_pipeline_003:out_data -> limiter_001:rsp_sink_data
wire [7:0] limiter_pipeline_003_source0_channel; // limiter_pipeline_003:out_channel -> limiter_001:rsp_sink_channel
wire limiter_pipeline_003_source0_ready; // limiter_001:rsp_sink_ready -> limiter_pipeline_003:out_ready
wire [4:0] cheri_irq_irq; // irq_mapper:sender_irq -> CHERI:avm_irq_irqs
wire irq_mapper_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
wire [0:0] irq_synchronizer_receiver_irq; // receive_fifo:rdclk_control_slave_irq -> irq_synchronizer:receiver_irq
wire irq_mapper_receiver1_irq; // irq_synchronizer_001:sender_irq -> irq_mapper:receiver1_irq
wire [0:0] irq_synchronizer_001_receiver_irq; // transmit_fifo:wrclk_control_slave_irq -> irq_synchronizer_001:receiver_irq
wire irq_mapper_receiver2_irq; // irq_synchronizer_002:sender_irq -> irq_mapper:receiver2_irq
wire [0:0] irq_synchronizer_002_receiver_irq; // Altera_UP_SD_Card_Avalon_Interface_1:o_avalon_irq -> irq_synchronizer_002:receiver_irq
DE4_SOPC_onchip_memory_MIPS onchip_memory_mips (
.clk (clk_50), // clk1.clk
.address (onchip_memory_mips_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (onchip_memory_mips_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (onchip_memory_mips_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (onchip_memory_mips_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (onchip_memory_mips_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (onchip_memory_mips_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (onchip_memory_mips_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset) // reset1.reset
);
DE4_SOPC_LEDs leds (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (leds_s1_translator_avalon_anti_slave_0_address), // s1.address
.write_n (~leds_s1_translator_avalon_anti_slave_0_write), // .write_n
.writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.out_port (leds_external_connection_export) // external_connection.export
);
mkTopAvalonPhy cheri (
.csi_clockreset_clk (clk_50), // clockreset.clk
.csi_clockreset_reset_n (~rst_controller_reset_out_reset), // clockreset_reset.reset_n
.avm_readdata (cheri_avalon_master_0_readdata), // avalon_master_0.readdata
.avm_readdatavalid (cheri_avalon_master_0_readdatavalid), // .readdatavalid
.avm_waitrequest (cheri_avalon_master_0_waitrequest), // .waitrequest
.avm_writedata (cheri_avalon_master_0_writedata), // .writedata
.avm_address (cheri_avalon_master_0_address), // .address
.avm_read (cheri_avalon_master_0_read), // .read
.avm_write (cheri_avalon_master_0_write), // .write
.avm_byteenable (cheri_avalon_master_0_byteenable), // .byteenable
.avm_irq_irqs (cheri_irq_irq), // irq.irq
.debugStreamSink_stream_in_data (), // avalon_streaming_sink.data
.debugStreamSink_stream_in_valid (), // .valid
.debugStreamSource_stream_out_data (), // avalon_streaming_source.data
.debugStreamSource_stream_out_valid (), // .valid
.debugStreamSource_stream_out_ready () // .ready
);
DE4_SOPC_transmit_fifo transmit_fifo (
.wrclock (clk_50), // clk_in.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset_in.reset_n
.avalonmm_write_slave_writedata (transmit_fifo_in_translator_avalon_anti_slave_0_writedata), // in.writedata
.avalonmm_write_slave_write (transmit_fifo_in_translator_avalon_anti_slave_0_write), // .write
.avalonmm_write_slave_address (transmit_fifo_in_translator_avalon_anti_slave_0_address), // .address
.avalonmm_write_slave_waitrequest (transmit_fifo_in_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.wrclk_control_slave_address (transmit_fifo_in_csr_translator_avalon_anti_slave_0_address), // in_csr.address
.wrclk_control_slave_read (transmit_fifo_in_csr_translator_avalon_anti_slave_0_read), // .read
.wrclk_control_slave_writedata (transmit_fifo_in_csr_translator_avalon_anti_slave_0_writedata), // .writedata
.wrclk_control_slave_write (transmit_fifo_in_csr_translator_avalon_anti_slave_0_write), // .write
.wrclk_control_slave_readdata (transmit_fifo_in_csr_translator_avalon_anti_slave_0_readdata), // .readdata
.wrclk_control_slave_irq (irq_synchronizer_001_receiver_irq), // in_irq.irq
.avalonst_source_valid (transmit_fifo_out_valid), // out.valid
.avalonst_source_data (transmit_fifo_out_data), // .data
.avalonst_source_error (transmit_fifo_out_error), // .error
.avalonst_source_startofpacket (transmit_fifo_out_startofpacket), // .startofpacket
.avalonst_source_endofpacket (transmit_fifo_out_endofpacket), // .endofpacket
.avalonst_source_empty (transmit_fifo_out_empty), // .empty
.avalonst_source_ready (transmit_fifo_out_ready) // .ready
);
DE4_SOPC_receive_fifo receive_fifo (
.wrclock (clk_50), // clk_in.clk
.wrreset_n (~rst_controller_001_reset_out_reset), // reset_in.reset_n
.avalonst_sink_valid (timing_adapter_1_out_valid), // in.valid
.avalonst_sink_data (timing_adapter_1_out_data), // .data
.avalonst_sink_error (timing_adapter_1_out_error), // .error
.avalonst_sink_startofpacket (timing_adapter_1_out_startofpacket), // .startofpacket
.avalonst_sink_endofpacket (timing_adapter_1_out_endofpacket), // .endofpacket
.avalonst_sink_empty (timing_adapter_1_out_empty), // .empty
.avalonst_sink_ready (timing_adapter_1_out_ready), // .ready
.rdclock (clk_50), // clk_out.clk
.rdreset_n (~rst_controller_001_reset_out_reset), // reset_out.reset_n
.avalonmm_read_slave_readdata (receive_fifo_out_translator_avalon_anti_slave_0_readdata), // out.readdata
.avalonmm_read_slave_read (receive_fifo_out_translator_avalon_anti_slave_0_read), // .read
.avalonmm_read_slave_address (receive_fifo_out_translator_avalon_anti_slave_0_address), // .address
.avalonmm_read_slave_waitrequest (receive_fifo_out_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.rdclk_control_slave_address (receive_fifo_out_csr_translator_avalon_anti_slave_0_address), // out_csr.address
.rdclk_control_slave_read (receive_fifo_out_csr_translator_avalon_anti_slave_0_read), // .read
.rdclk_control_slave_writedata (receive_fifo_out_csr_translator_avalon_anti_slave_0_writedata), // .writedata
.rdclk_control_slave_write (receive_fifo_out_csr_translator_avalon_anti_slave_0_write), // .write
.rdclk_control_slave_readdata (receive_fifo_out_csr_translator_avalon_anti_slave_0_readdata), // .readdata
.rdclk_control_slave_irq (irq_synchronizer_receiver_irq) // out_irq.irq
);
DE4_SOPC_timing_adapter timing_adapter (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.in_ready (transmit_fifo_out_ready), // in.ready
.in_valid (transmit_fifo_out_valid), // .valid
.in_data (transmit_fifo_out_data), // .data
.in_error (transmit_fifo_out_error), // .error
.in_startofpacket (transmit_fifo_out_startofpacket), // .startofpacket
.in_endofpacket (transmit_fifo_out_endofpacket), // .endofpacket
.in_empty (transmit_fifo_out_empty), // .empty
.out_ready (), // out.ready
.out_valid (), // .valid
.out_data (), // .data
.out_error (), // .error
.out_startofpacket (), // .startofpacket
.out_endofpacket (), // .endofpacket
.out_empty () // .empty
);
DE4_SOPC_timing_adapter_1 timing_adapter_1 (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.in_ready (), // in.ready
.in_valid (), // .valid
.in_data (), // .data
.in_error (), // .error
.in_startofpacket (), // .startofpacket
.in_endofpacket (), // .endofpacket
.in_empty (), // .empty
.out_ready (timing_adapter_1_out_ready), // out.ready
.out_valid (timing_adapter_1_out_valid), // .valid
.out_data (timing_adapter_1_out_data), // .data
.out_error (timing_adapter_1_out_error), // .error
.out_startofpacket (timing_adapter_1_out_startofpacket), // .startofpacket
.out_endofpacket (timing_adapter_1_out_endofpacket), // .endofpacket
.out_empty (timing_adapter_1_out_empty) // .empty
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (30),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) peripheral_bridge (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.s0_waitrequest (peripheral_bridge_s0_translator_avalon_anti_slave_0_waitrequest), // s0.waitrequest
.s0_readdata (peripheral_bridge_s0_translator_avalon_anti_slave_0_readdata), // .readdata
.s0_readdatavalid (peripheral_bridge_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.s0_burstcount (peripheral_bridge_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
.s0_writedata (peripheral_bridge_s0_translator_avalon_anti_slave_0_writedata), // .writedata
.s0_address (peripheral_bridge_s0_translator_avalon_anti_slave_0_address), // .address
.s0_write (peripheral_bridge_s0_translator_avalon_anti_slave_0_write), // .write
.s0_read (peripheral_bridge_s0_translator_avalon_anti_slave_0_read), // .read
.s0_byteenable (peripheral_bridge_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.s0_debugaccess (peripheral_bridge_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.m0_waitrequest (peripheral_bridge_m0_waitrequest), // m0.waitrequest
.m0_readdata (peripheral_bridge_m0_readdata), // .readdata
.m0_readdatavalid (peripheral_bridge_m0_readdatavalid), // .readdatavalid
.m0_burstcount (peripheral_bridge_m0_burstcount), // .burstcount
.m0_writedata (peripheral_bridge_m0_writedata), // .writedata
.m0_address (peripheral_bridge_m0_address), // .address
.m0_write (peripheral_bridge_m0_write), // .write
.m0_read (peripheral_bridge_m0_read), // .read
.m0_byteenable (peripheral_bridge_m0_byteenable), // .byteenable
.m0_debugaccess (peripheral_bridge_m0_debugaccess) // .debugaccess
);
altera_avalon_dc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (24),
.FIFO_DEPTH (32),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_IN_FILL_LEVEL (0),
.USE_OUT_FILL_LEVEL (0),
.WR_SYNC_DEPTH (2),
.RD_SYNC_DEPTH (2)
) dc_fifo_0 (
.in_clk (clk_50), // in_clk.clk
.in_reset_n (~rst_controller_reset_out_reset), // in_clk_reset.reset_n
.out_clk (clk_50), // out_clk.clk
.out_reset_n (~rst_controller_001_reset_out_reset), // out_clk_reset.reset_n
.in_data (mkmtl_framebuffer_flash_0_stream_out_data), // in.data
.in_valid (mkmtl_framebuffer_flash_0_stream_out_valid), // .valid
.in_ready (mkmtl_framebuffer_flash_0_stream_out_ready), // .ready
.in_startofpacket (mkmtl_framebuffer_flash_0_stream_out_startofpacket), // .startofpacket
.in_endofpacket (mkmtl_framebuffer_flash_0_stream_out_endofpacket), // .endofpacket
.out_data (dc_fifo_0_out_data), // out.data
.out_valid (dc_fifo_0_out_valid), // .valid
.out_ready (dc_fifo_0_out_ready), // .ready
.out_startofpacket (dc_fifo_0_out_startofpacket), // .startofpacket
.out_endofpacket (dc_fifo_0_out_endofpacket), // .endofpacket
.in_csr_address (1'b0), // (terminated)
.in_csr_read (1'b0), // (terminated)
.in_csr_write (1'b0), // (terminated)
.in_csr_readdata (), // (terminated)
.in_csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.out_csr_address (1'b0), // (terminated)
.out_csr_read (1'b0), // (terminated)
.out_csr_write (1'b0), // (terminated)
.out_csr_readdata (), // (terminated)
.out_csr_writedata (32'b00000000000000000000000000000000) // (terminated)
);
mkAvalonStream2MTL_LCD24bit avalonstream2mtl_lcd24bit_0 (
.csi_clockreset_clk (clk_50), // clockreset.clk
.csi_clockreset_reset_n (~rst_controller_001_reset_out_reset), // clockreset_reset.reset_n
.asi_stream_in_data (dc_fifo_0_out_data), // stream_in.data
.asi_stream_in_valid (dc_fifo_0_out_valid), // .valid
.asi_stream_in_startofpacket (dc_fifo_0_out_startofpacket), // .startofpacket
.asi_stream_in_endofpacket (dc_fifo_0_out_endofpacket), // .endofpacket
.asi_stream_in_ready (dc_fifo_0_out_ready), // .ready
.coe_tpadlcd_mtl_r (mtl_lcd_r), // conduit_end_0.export
.coe_tpadlcd_mtl_g (mtl_lcd_g), // .export
.coe_tpadlcd_mtl_b (mtl_lcd_b), // .export
.coe_tpadlcd_mtl_hsd (mtl_lcd_hsd), // .export
.coe_tpadlcd_mtl_vsd (mtl_lcd_vsd) // .export
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (18),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (4),
.RESPONSE_FIFO_DEPTH (4),
.MASTER_SYNC_DEPTH (2),
.SLAVE_SYNC_DEPTH (2)
) mm_clock_crossing_bridge_0 (
.m0_clk (clk_50), // m0_clk.clk
.m0_reset (rst_controller_001_reset_out_reset), // m0_reset.reset
.s0_clk (clk_50), // s0_clk.clk
.s0_reset (rst_controller_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_waitrequest), // s0.waitrequest
.s0_readdata (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_readdata), // .readdata
.s0_readdatavalid (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
.s0_writedata (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_writedata), // .writedata
.s0_address (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_address), // .address
.s0_write (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_write), // .write
.s0_read (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_read), // .read
.s0_byteenable (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.s0_debugaccess (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.m0_waitrequest (mm_clock_crossing_bridge_0_m0_waitrequest), // m0.waitrequest
.m0_readdata (mm_clock_crossing_bridge_0_m0_readdata), // .readdata
.m0_readdatavalid (mm_clock_crossing_bridge_0_m0_readdatavalid), // .readdatavalid
.m0_burstcount (mm_clock_crossing_bridge_0_m0_burstcount), // .burstcount
.m0_writedata (mm_clock_crossing_bridge_0_m0_writedata), // .writedata
.m0_address (mm_clock_crossing_bridge_0_m0_address), // .address
.m0_write (mm_clock_crossing_bridge_0_m0_write), // .write
.m0_read (mm_clock_crossing_bridge_0_m0_read), // .read
.m0_byteenable (mm_clock_crossing_bridge_0_m0_byteenable), // .byteenable
.m0_debugaccess (mm_clock_crossing_bridge_0_m0_debugaccess) // .debugaccess
);
mkMTL_Framebuffer_Flash mkmtl_framebuffer_flash_0 (
.csi_clockreset_clk (clk_50), // clockreset.clk
.csi_clockreset_reset_n (~rst_controller_reset_out_reset), // clockreset_reset.reset_n
.avs_s0_address (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_address), // s0.address
.avs_s0_writedata (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_writedata), // .writedata
.avs_s0_write (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_write), // .write
.avs_s0_read (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_read), // .read
.avs_s0_byteenable (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.avs_s0_readdata (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_readdata), // .readdata
.avs_s0_waitrequest (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.aso_stream_out_data (mkmtl_framebuffer_flash_0_stream_out_data), // stream_out.data
.aso_stream_out_valid (mkmtl_framebuffer_flash_0_stream_out_valid), // .valid
.aso_stream_out_ready (mkmtl_framebuffer_flash_0_stream_out_ready), // .ready
.aso_stream_out_startofpacket (mkmtl_framebuffer_flash_0_stream_out_startofpacket), // .startofpacket
.aso_stream_out_endofpacket (mkmtl_framebuffer_flash_0_stream_out_endofpacket), // .endofpacket
.coe_touch_x1 (touch_x1), // conduit_end_touch.export
.coe_touch_y1 (touch_y1), // .export
.coe_touch_x2 (touch_x2), // .export
.coe_touch_y2 (touch_y2), // .export
.coe_touch_count_gesture (touch_count_gesture), // .export
.coe_touch_touch_valid (touch_touch_valid), // .export
.coe_ssram_adv (mem_ssram_adv), // conduit_end_mem.export
.coe_ssram_bwa_n (mem_ssram_bwa_n), // .export
.coe_ssram_bwb_n (mem_ssram_bwb_n), // .export
.coe_ssram_ce_n (mem_ssram_ce_n), // .export
.coe_ssram_cke_n (mem_ssram_cke_n), // .export
.coe_ssram_oe_n (mem_ssram_oe_n), // .export
.coe_ssram_we_n (mem_ssram_we_n), // .export
.coe_fsm_a (mem_fsm_a), // .export
.coe_fsm_d_out (mem_fsm_d_out), // .export
.coe_fsm_d_in (mem_fsm_d_in), // .export
.coe_fsm_dout_req (mem_fsm_dout_req), // .export
.coe_flash_adv_n (mem_flash_adv_n), // .export
.coe_flash_ce_n (mem_flash_ce_n), // .export
.coe_flash_clk (mem_flash_clk), // .export
.coe_flash_oe_n (mem_flash_oe_n), // .export
.coe_flash_we_n (mem_flash_we_n) // .export
);
Altera_UP_SD_Card_Avalon_Interface #(
.ADDRESS_BUFFER (8'b00000000),
.ADDRESS_CID (8'b10000000),
.ADDRESS_CSD (8'b10000100),
.ADDRESS_OCR (8'b10001000),
.ADDRESS_SR (8'b10001001),
.ADDRESS_RCA (8'b10001010),
.ADDRESS_ARGUMENT (8'b10001011),
.ADDRESS_COMMAND (8'b10001100),
.ADDRESS_ASR (8'b10001101),
.ADDRESS_R1 (8'b10001110)
) altera_up_sd_card_avalon_interface_1 (
.i_avalon_chip_select (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // avalon_slave_0.chipselect
.o_avalon_readdata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.i_avalon_writedata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.i_avalon_byteenable (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.i_avalon_write (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
.i_avalon_read (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.i_avalon_address (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_address), // .address
.o_avalon_waitrequest (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.b_SD_cmd (sd_b_SD_cmd), // conduit_end.export
.b_SD_dat (sd_b_SD_dat), // .export
.b_SD_dat3 (sd_b_SD_dat3), // .export
.o_SD_clock (sd_o_SD_clock), // .export
.i_clock (clk_50), // clock_sink.clk
.o_avalon_irq (irq_synchronizer_002_receiver_irq), // interrupt_sender.irq
.i_reset_n (~rst_controller_001_reset_out_reset) // reset_sink.reset_n
);
DE4_SOPC_Switches switches (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address
.readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.in_port (switches_export) // external_connection.export
);
DE4_SOPC_versionRom versionrom (
.clk (clk_50), // clk1.clk
.address (versionrom_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (versionrom_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (versionrom_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (versionrom_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (versionrom_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (versionrom_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.debugaccess (versionrom_s1_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.byteenable (versionrom_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_001_reset_out_reset) // reset1.reset
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) peripheral_bridge_m0_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (peripheral_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (peripheral_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (peripheral_bridge_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (peripheral_bridge_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (peripheral_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (peripheral_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (peripheral_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (peripheral_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (peripheral_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (peripheral_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (peripheral_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (peripheral_bridge_m0_address), // avalon_anti_master_0.address
.av_waitrequest (peripheral_bridge_m0_waitrequest), // .waitrequest
.av_burstcount (peripheral_bridge_m0_burstcount), // .burstcount
.av_byteenable (peripheral_bridge_m0_byteenable), // .byteenable
.av_read (peripheral_bridge_m0_read), // .read
.av_readdata (peripheral_bridge_m0_readdata), // .readdata
.av_readdatavalid (peripheral_bridge_m0_readdatavalid), // .readdatavalid
.av_write (peripheral_bridge_m0_write), // .write
.av_writedata (peripheral_bridge_m0_writedata), // .writedata
.av_debugaccess (peripheral_bridge_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (18),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mm_clock_crossing_bridge_0_s0_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_write), // .write
.av_read (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_read), // .read
.av_readdata (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_writedata), // .writedata
.av_burstcount (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
.av_byteenable (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_debugaccess (mm_clock_crossing_bridge_0_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mkmtl_framebuffer_flash_0_s0_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_write), // .write
.av_read (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_read), // .read
.av_readdata (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (mkmtl_framebuffer_flash_0_s0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory_mips_s1_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory_mips_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (onchip_memory_mips_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (onchip_memory_mips_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (onchip_memory_mips_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (onchip_memory_mips_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (onchip_memory_mips_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (onchip_memory_mips_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (18),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) mm_clock_crossing_bridge_0_m0_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (mm_clock_crossing_bridge_0_m0_address), // avalon_anti_master_0.address
.av_waitrequest (mm_clock_crossing_bridge_0_m0_waitrequest), // .waitrequest
.av_burstcount (mm_clock_crossing_bridge_0_m0_burstcount), // .burstcount
.av_byteenable (mm_clock_crossing_bridge_0_m0_byteenable), // .byteenable
.av_read (mm_clock_crossing_bridge_0_m0_read), // .read
.av_readdata (mm_clock_crossing_bridge_0_m0_readdata), // .readdata
.av_readdatavalid (mm_clock_crossing_bridge_0_m0_readdatavalid), // .readdatavalid
.av_write (mm_clock_crossing_bridge_0_m0_write), // .write
.av_writedata (mm_clock_crossing_bridge_0_m0_writedata), // .writedata
.av_debugaccess (mm_clock_crossing_bridge_0_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
.av_read (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.av_readdata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) leds_s1_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (leds_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (leds_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switches_s1_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) transmit_fifo_in_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (transmit_fifo_in_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (transmit_fifo_in_translator_avalon_anti_slave_0_write), // .write
.av_writedata (transmit_fifo_in_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (transmit_fifo_in_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_read (), // (terminated)
.av_readdata (32'b11011110101011011101111010101101), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) transmit_fifo_in_csr_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (transmit_fifo_in_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (transmit_fifo_in_csr_translator_avalon_anti_slave_0_write), // .write
.av_read (transmit_fifo_in_csr_translator_avalon_anti_slave_0_read), // .read
.av_readdata (transmit_fifo_in_csr_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (transmit_fifo_in_csr_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) receive_fifo_out_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (receive_fifo_out_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_read (receive_fifo_out_translator_avalon_anti_slave_0_read), // .read
.av_readdata (receive_fifo_out_translator_avalon_anti_slave_0_readdata), // .readdata
.av_waitrequest (receive_fifo_out_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) receive_fifo_out_csr_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (receive_fifo_out_csr_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (receive_fifo_out_csr_translator_avalon_anti_slave_0_write), // .write
.av_read (receive_fifo_out_csr_translator_avalon_anti_slave_0_read), // .read
.av_readdata (receive_fifo_out_csr_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (receive_fifo_out_csr_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) versionrom_s1_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (versionrom_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (versionrom_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (versionrom_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (versionrom_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (versionrom_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (versionrom_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (versionrom_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_debugaccess (versionrom_s1_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) cheri_avalon_master_0_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cheri_avalon_master_0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cheri_avalon_master_0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cheri_avalon_master_0_translator_avalon_universal_master_0_read), // .read
.uav_write (cheri_avalon_master_0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cheri_avalon_master_0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cheri_avalon_master_0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cheri_avalon_master_0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cheri_avalon_master_0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cheri_avalon_master_0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cheri_avalon_master_0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cheri_avalon_master_0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cheri_avalon_master_0_address), // avalon_anti_master_0.address
.av_waitrequest (cheri_avalon_master_0_waitrequest), // .waitrequest
.av_byteenable (cheri_avalon_master_0_byteenable), // .byteenable
.av_read (cheri_avalon_master_0_read), // .read
.av_readdata (cheri_avalon_master_0_readdata), // .readdata
.av_readdatavalid (cheri_avalon_master_0_readdatavalid), // .readdatavalid
.av_write (cheri_avalon_master_0_write), // .write
.av_writedata (cheri_avalon_master_0_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) peripheral_bridge_s0_translator (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (peripheral_bridge_s0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (peripheral_bridge_s0_translator_avalon_anti_slave_0_write), // .write
.av_read (peripheral_bridge_s0_translator_avalon_anti_slave_0_read), // .read
.av_readdata (peripheral_bridge_s0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (peripheral_bridge_s0_translator_avalon_anti_slave_0_writedata), // .writedata
.av_burstcount (peripheral_bridge_s0_translator_avalon_anti_slave_0_burstcount), // .burstcount
.av_byteenable (peripheral_bridge_s0_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (peripheral_bridge_s0_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (peripheral_bridge_s0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_debugaccess (peripheral_bridge_s0_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (94),
.PKT_PROTECTION_L (92),
.PKT_BEGIN_BURST (85),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_BURST_TYPE_H (82),
.PKT_BURST_TYPE_L (81),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (89),
.PKT_THREAD_ID_H (91),
.PKT_THREAD_ID_L (91),
.PKT_CACHE_H (98),
.PKT_CACHE_L (95),
.PKT_DATA_SIDEBAND_H (84),
.PKT_DATA_SIDEBAND_L (84),
.PKT_QOS_H (86),
.PKT_QOS_L (86),
.PKT_ADDR_SIDEBAND_H (83),
.PKT_ADDR_SIDEBAND_L (83),
.ST_DATA_W (101),
.ST_CHANNEL_W (3),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) peripheral_bridge_m0_translator_avalon_universal_master_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (peripheral_bridge_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (peripheral_bridge_m0_translator_avalon_universal_master_0_write), // .write
.av_read (peripheral_bridge_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (peripheral_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (peripheral_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (peripheral_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (peripheral_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (peripheral_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (peripheral_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (peripheral_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (peripheral_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (85),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (72),
.PKT_PROTECTION_H (94),
.PKT_PROTECTION_L (92),
.PKT_RESPONSE_STATUS_H (100),
.PKT_RESPONSE_STATUS_L (99),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.ST_CHANNEL_W (3),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src0_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src0_valid), // .valid
.cp_data (cmd_xbar_demux_src0_data), // .data
.cp_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src0_channel), // .channel
.rf_sink_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (9),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (85),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (72),
.PKT_PROTECTION_H (94),
.PKT_PROTECTION_L (92),
.PKT_RESPONSE_STATUS_H (100),
.PKT_RESPONSE_STATUS_L (99),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.ST_CHANNEL_W (3),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src1_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src1_valid), // .valid
.cp_data (cmd_xbar_demux_src1_data), // .data
.cp_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src1_channel), // .channel
.rf_sink_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (85),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (72),
.PKT_PROTECTION_H (94),
.PKT_PROTECTION_L (92),
.PKT_RESPONSE_STATUS_H (100),
.PKT_RESPONSE_STATUS_L (99),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.ST_CHANNEL_W (3),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src2_valid), // .valid
.cp_data (cmd_xbar_demux_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src2_channel), // .channel
.rf_sink_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BEGIN_BURST (73),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.PKT_BURST_TYPE_H (70),
.PKT_BURST_TYPE_L (69),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_TRANS_EXCLUSIVE (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_THREAD_ID_H (81),
.PKT_THREAD_ID_L (81),
.PKT_CACHE_H (88),
.PKT_CACHE_L (85),
.PKT_DATA_SIDEBAND_H (72),
.PKT_DATA_SIDEBAND_L (72),
.PKT_QOS_H (74),
.PKT_QOS_L (74),
.PKT_ADDR_SIDEBAND_H (71),
.PKT_ADDR_SIDEBAND_L (71),
.ST_DATA_W (91),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.av_address (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_write), // .write
.av_read (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_001_rsp_src_valid), // rp.valid
.rp_data (limiter_001_rsp_src_data), // .data
.rp_channel (limiter_001_rsp_src_channel), // .channel
.rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_001_rsp_src_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src0_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src0_valid), // .valid
.cp_data (cmd_xbar_demux_001_src0_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src0_channel), // .channel
.rf_sink_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) leds_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src1_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src1_valid), // .valid
.cp_data (cmd_xbar_demux_001_src1_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src1_channel), // .channel
.rf_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) switches_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src2_valid), // .valid
.cp_data (cmd_xbar_demux_001_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src2_channel), // .channel
.rf_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) transmit_fifo_in_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (transmit_fifo_in_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src3_valid), // .valid
.cp_data (cmd_xbar_demux_001_src3_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src3_channel), // .channel
.rf_sink_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
.cp_data (cmd_xbar_demux_001_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
.rf_sink_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) receive_fifo_out_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (receive_fifo_out_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) receive_fifo_out_csr_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
.cp_data (cmd_xbar_demux_001_src6_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
.rf_sink_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (73),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_TRANS_LOCK (58),
.PKT_SRC_ID_H (77),
.PKT_SRC_ID_L (75),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (68),
.PKT_BURST_SIZE_L (66),
.ST_CHANNEL_W (8),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) versionrom_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (versionrom_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
.cp_data (cmd_xbar_demux_001_src7_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
.rf_sink_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (352),
.PKT_PROTECTION_L (350),
.PKT_BEGIN_BURST (345),
.PKT_BURSTWRAP_H (337),
.PKT_BURSTWRAP_L (332),
.PKT_BURST_SIZE_H (340),
.PKT_BURST_SIZE_L (338),
.PKT_BURST_TYPE_H (342),
.PKT_BURST_TYPE_L (341),
.PKT_BYTE_CNT_H (331),
.PKT_BYTE_CNT_L (326),
.PKT_ADDR_H (319),
.PKT_ADDR_L (288),
.PKT_TRANS_COMPRESSED_READ (320),
.PKT_TRANS_POSTED (321),
.PKT_TRANS_WRITE (322),
.PKT_TRANS_READ (323),
.PKT_TRANS_LOCK (324),
.PKT_TRANS_EXCLUSIVE (325),
.PKT_DATA_H (255),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (287),
.PKT_BYTEEN_L (256),
.PKT_SRC_ID_H (347),
.PKT_SRC_ID_L (347),
.PKT_DEST_ID_H (348),
.PKT_DEST_ID_L (348),
.PKT_THREAD_ID_H (349),
.PKT_THREAD_ID_L (349),
.PKT_CACHE_H (356),
.PKT_CACHE_L (353),
.PKT_DATA_SIDEBAND_H (344),
.PKT_DATA_SIDEBAND_L (344),
.PKT_QOS_H (346),
.PKT_QOS_L (346),
.PKT_ADDR_SIDEBAND_H (343),
.PKT_ADDR_SIDEBAND_L (343),
.ST_DATA_W (359),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (63),
.CACHE_VALUE (4'b0000)
) cheri_avalon_master_0_translator_avalon_universal_master_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cheri_avalon_master_0_translator_avalon_universal_master_0_address), // av.address
.av_write (cheri_avalon_master_0_translator_avalon_universal_master_0_write), // .write
.av_read (cheri_avalon_master_0_translator_avalon_universal_master_0_read), // .read
.av_writedata (cheri_avalon_master_0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cheri_avalon_master_0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cheri_avalon_master_0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cheri_avalon_master_0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cheri_avalon_master_0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cheri_avalon_master_0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cheri_avalon_master_0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cheri_avalon_master_0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_011_src0_valid), // rp.valid
.rp_data (rsp_xbar_demux_011_src0_data), // .data
.rp_channel (rsp_xbar_demux_011_src0_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_011_src0_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_011_src0_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (93),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (95),
.PKT_SRC_ID_L (95),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (96),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (80),
.PKT_BYTE_CNT_H (79),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.ST_CHANNEL_W (1),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1)
) peripheral_bridge_s0_translator_avalon_universal_slave_0_agent (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (5),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
DE4_SOPC_addr_router addr_router (
.sink_ready (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (peripheral_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router id_router (
.sink_ready (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router id_router_001 (
.sink_ready (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mkmtl_framebuffer_flash_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router id_router_002 (
.sink_ready (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory_mips_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
DE4_SOPC_addr_router_001 addr_router_001 (
.sink_ready (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_003 (
.sink_ready (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altera_up_sd_card_avalon_interface_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_004 (
.sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_005 (
.sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_006 (
.sink_ready (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (transmit_fifo_in_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_006_src_ready), // src.ready
.src_valid (id_router_006_src_valid), // .valid
.src_data (id_router_006_src_data), // .data
.src_channel (id_router_006_src_channel), // .channel
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_007 (
.sink_ready (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (transmit_fifo_in_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_007_src_ready), // src.ready
.src_valid (id_router_007_src_valid), // .valid
.src_data (id_router_007_src_data), // .data
.src_channel (id_router_007_src_channel), // .channel
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_008 (
.sink_ready (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (receive_fifo_out_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_008_src_ready), // src.ready
.src_valid (id_router_008_src_valid), // .valid
.src_data (id_router_008_src_data), // .data
.src_channel (id_router_008_src_channel), // .channel
.src_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_008_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_009 (
.sink_ready (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (receive_fifo_out_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_009_src_ready), // src.ready
.src_valid (id_router_009_src_valid), // .valid
.src_data (id_router_009_src_data), // .data
.src_channel (id_router_009_src_channel), // .channel
.src_startofpacket (id_router_009_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_009_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_003 id_router_010 (
.sink_ready (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (versionrom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_010_src_ready), // src.ready
.src_valid (id_router_010_src_valid), // .valid
.src_data (id_router_010_src_data), // .data
.src_channel (id_router_010_src_channel), // .channel
.src_startofpacket (id_router_010_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_010_src_endofpacket) // .endofpacket
);
DE4_SOPC_addr_router_002 addr_router_002 (
.sink_ready (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cheri_avalon_master_0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
DE4_SOPC_id_router_011 id_router_011 (
.sink_ready (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (peripheral_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_011_src_ready), // src.ready
.src_valid (id_router_011_src_valid), // .valid
.src_data (id_router_011_src_data), // .data
.src_channel (id_router_011_src_channel), // .channel
.src_startofpacket (id_router_011_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_011_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (89),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.MAX_OUTSTANDING_RESPONSES (12),
.PIPELINED (0),
.ST_DATA_W (101),
.ST_CHANNEL_W (3),
.VALID_WIDTH (1),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (72),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_src_valid), // .valid
.rsp_sink_ready (limiter_pipeline_001_source0_ready), // rsp_sink.ready
.rsp_sink_valid (limiter_pipeline_001_source0_valid), // .valid
.rsp_sink_channel (limiter_pipeline_001_source0_channel), // .channel
.rsp_sink_data (limiter_pipeline_001_source0_data), // .data
.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket), // .startofpacket
.rsp_sink_endofpacket (limiter_pipeline_001_source0_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (78),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (91),
.ST_CHANNEL_W (8),
.VALID_WIDTH (1),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter_001 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_src_valid), // .valid
.rsp_sink_ready (limiter_pipeline_003_source0_ready), // rsp_sink.ready
.rsp_sink_valid (limiter_pipeline_003_source0_valid), // .valid
.rsp_sink_channel (limiter_pipeline_003_source0_channel), // .channel
.rsp_sink_data (limiter_pipeline_003_source0_data), // .data
.rsp_sink_startofpacket (limiter_pipeline_003_source0_startofpacket), // .startofpacket
.rsp_sink_endofpacket (limiter_pipeline_003_source0_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (93),
.PKT_BYTE_CNT_H (79),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_BURST_TYPE_H (90),
.PKT_BURST_TYPE_L (89),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (80),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (107),
.ST_CHANNEL_W (1),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (85),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (0),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63)
) burst_adapter (
.clk (clk_50), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.sink0_valid (width_adapter_src_valid), // sink0.valid
.sink0_data (width_adapter_src_data), // .data
.sink0_channel (width_adapter_src_channel), // .channel
.sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_50), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_50), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
DE4_SOPC_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_pipeline_source0_ready), // sink.ready
.sink_channel (limiter_pipeline_source0_channel), // .channel
.sink_data (limiter_pipeline_source0_data), // .data
.sink_startofpacket (limiter_pipeline_source0_startofpacket), // .startofpacket
.sink_endofpacket (limiter_pipeline_source0_endofpacket), // .endofpacket
.sink_valid (limiter_pipeline_source0_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux rsp_xbar_demux_002 (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
DE4_SOPC_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_pipeline_002_source0_ready), // sink.ready
.sink_channel (limiter_pipeline_002_source0_channel), // .channel
.sink_data (limiter_pipeline_002_source0_data), // .data
.sink_startofpacket (limiter_pipeline_002_source0_startofpacket), // .startofpacket
.sink_endofpacket (limiter_pipeline_002_source0_endofpacket), // .endofpacket
.sink_valid (limiter_pipeline_002_source0_valid), // .valid
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
.src6_data (cmd_xbar_demux_001_src6_data), // .data
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
.src7_data (cmd_xbar_demux_001_src7_data), // .data
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_003 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_004 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_005 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_006 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_006_src_ready), // sink.ready
.sink_channel (id_router_006_src_channel), // .channel
.sink_data (id_router_006_src_data), // .data
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
.sink_valid (id_router_006_src_valid), // .valid
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
.src0_data (rsp_xbar_demux_006_src0_data), // .data
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_007 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_007_src_ready), // sink.ready
.sink_channel (id_router_007_src_channel), // .channel
.sink_data (id_router_007_src_data), // .data
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
.sink_valid (id_router_007_src_valid), // .valid
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
.src0_data (rsp_xbar_demux_007_src0_data), // .data
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_008 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_008_src_ready), // sink.ready
.sink_channel (id_router_008_src_channel), // .channel
.sink_data (id_router_008_src_data), // .data
.sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket
.sink_valid (id_router_008_src_valid), // .valid
.src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_008_src0_valid), // .valid
.src0_data (rsp_xbar_demux_008_src0_data), // .data
.src0_channel (rsp_xbar_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_009 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_009_src_ready), // sink.ready
.sink_channel (id_router_009_src_channel), // .channel
.sink_data (id_router_009_src_data), // .data
.sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket
.sink_valid (id_router_009_src_valid), // .valid
.src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_009_src0_valid), // .valid
.src0_data (rsp_xbar_demux_009_src0_data), // .data
.src0_channel (rsp_xbar_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_demux_003 rsp_xbar_demux_010 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_010_src_ready), // sink.ready
.sink_channel (id_router_010_src_channel), // .channel
.sink_data (id_router_010_src_data), // .data
.sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket
.sink_valid (id_router_010_src_valid), // .valid
.src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_010_src0_valid), // .valid
.src0_data (rsp_xbar_demux_010_src0_data), // .data
.src0_channel (rsp_xbar_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket
);
DE4_SOPC_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clk_50), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_003_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_003_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_004_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_004_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_005_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_005_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_006_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_006_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_006_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_006_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_007_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_007_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_007_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_007_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_008_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_008_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_008_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_008_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_xbar_demux_009_src0_ready), // sink6.ready
.sink6_valid (rsp_xbar_demux_009_src0_valid), // .valid
.sink6_channel (rsp_xbar_demux_009_src0_channel), // .channel
.sink6_data (rsp_xbar_demux_009_src0_data), // .data
.sink6_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_xbar_demux_010_src0_ready), // sink7.ready
.sink7_valid (rsp_xbar_demux_010_src0_valid), // .valid
.sink7_channel (rsp_xbar_demux_010_src0_channel), // .channel
.sink7_data (rsp_xbar_demux_010_src0_data), // .data
.sink7_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket
);
DE4_SOPC_cmd_xbar_demux_002 cmd_xbar_demux_002 (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_002_src_ready), // sink.ready
.sink_channel (addr_router_002_src_channel), // .channel
.sink_data (addr_router_002_src_data), // .data
.sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.sink_valid (addr_router_002_src_valid), // .valid
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
DE4_SOPC_cmd_xbar_demux_002 rsp_xbar_demux_011 (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (width_adapter_001_src_ready), // sink.ready
.sink_channel (width_adapter_001_src_channel), // .channel
.sink_data (width_adapter_001_src_data), // .data
.sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_011_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_011_src0_valid), // .valid
.src0_data (rsp_xbar_demux_011_src0_data), // .data
.src0_channel (rsp_xbar_demux_011_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (319),
.IN_PKT_ADDR_L (288),
.IN_PKT_DATA_H (255),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (287),
.IN_PKT_BYTEEN_L (256),
.IN_PKT_BYTE_CNT_H (331),
.IN_PKT_BYTE_CNT_L (326),
.IN_PKT_TRANS_COMPRESSED_READ (320),
.IN_PKT_BURSTWRAP_H (337),
.IN_PKT_BURSTWRAP_L (332),
.IN_PKT_BURST_SIZE_H (340),
.IN_PKT_BURST_SIZE_L (338),
.IN_PKT_RESPONSE_STATUS_H (358),
.IN_PKT_RESPONSE_STATUS_L (357),
.IN_PKT_TRANS_EXCLUSIVE (325),
.IN_PKT_BURST_TYPE_H (342),
.IN_PKT_BURST_TYPE_L (341),
.IN_ST_DATA_W (359),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (79),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (88),
.OUT_PKT_BURST_SIZE_L (86),
.OUT_PKT_RESPONSE_STATUS_H (106),
.OUT_PKT_RESPONSE_STATUS_L (105),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (90),
.OUT_PKT_BURST_TYPE_L (89),
.OUT_ST_DATA_W (107),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0)
) width_adapter (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_demux_002_src0_valid), // sink.valid
.in_channel (cmd_xbar_demux_002_src0_channel), // .channel
.in_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
.in_ready (cmd_xbar_demux_002_src0_ready), // .ready
.in_data (cmd_xbar_demux_002_src0_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (79),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (85),
.IN_PKT_BURSTWRAP_L (80),
.IN_PKT_BURST_SIZE_H (88),
.IN_PKT_BURST_SIZE_L (86),
.IN_PKT_RESPONSE_STATUS_H (106),
.IN_PKT_RESPONSE_STATUS_L (105),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (90),
.IN_PKT_BURST_TYPE_L (89),
.IN_ST_DATA_W (107),
.OUT_PKT_ADDR_H (319),
.OUT_PKT_ADDR_L (288),
.OUT_PKT_DATA_H (255),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (287),
.OUT_PKT_BYTEEN_L (256),
.OUT_PKT_BYTE_CNT_H (331),
.OUT_PKT_BYTE_CNT_L (326),
.OUT_PKT_TRANS_COMPRESSED_READ (320),
.OUT_PKT_BURST_SIZE_H (340),
.OUT_PKT_BURST_SIZE_L (338),
.OUT_PKT_RESPONSE_STATUS_H (358),
.OUT_PKT_RESPONSE_STATUS_L (357),
.OUT_PKT_TRANS_EXCLUSIVE (325),
.OUT_PKT_BURST_TYPE_H (342),
.OUT_PKT_BURST_TYPE_L (341),
.OUT_ST_DATA_W (359),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1)
) width_adapter_001 (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (id_router_011_src_valid), // sink.valid
.in_channel (id_router_011_src_channel), // .channel
.in_startofpacket (id_router_011_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_011_src_endofpacket), // .endofpacket
.in_ready (id_router_011_src_ready), // .ready
.in_data (id_router_011_src_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_pipeline_stage #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_EMPTY (0),
.EMPTY_WIDTH (0),
.CHANNEL_WIDTH (3),
.PACKET_WIDTH (2),
.ERROR_WIDTH (0),
.PIPELINE_READY (1)
) limiter_pipeline (
.clk (clk_50), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.in_ready (limiter_cmd_src_ready), // sink0.ready
.in_valid (limiter_cmd_src_valid), // .valid
.in_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.in_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.in_data (limiter_cmd_src_data), // .data
.in_channel (limiter_cmd_src_channel), // .channel
.out_ready (limiter_pipeline_source0_ready), // source0.ready
.out_valid (limiter_pipeline_source0_valid), // .valid
.out_startofpacket (limiter_pipeline_source0_startofpacket), // .startofpacket
.out_endofpacket (limiter_pipeline_source0_endofpacket), // .endofpacket
.out_data (limiter_pipeline_source0_data), // .data
.out_channel (limiter_pipeline_source0_channel), // .channel
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error (), // (terminated)
.in_error (1'b0) // (terminated)
);
altera_avalon_st_pipeline_stage #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_EMPTY (0),
.EMPTY_WIDTH (0),
.CHANNEL_WIDTH (3),
.PACKET_WIDTH (2),
.ERROR_WIDTH (0),
.PIPELINE_READY (1)
) limiter_pipeline_001 (
.clk (clk_50), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.in_ready (rsp_xbar_mux_src_ready), // sink0.ready
.in_valid (rsp_xbar_mux_src_valid), // .valid
.in_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.in_data (rsp_xbar_mux_src_data), // .data
.in_channel (rsp_xbar_mux_src_channel), // .channel
.out_ready (limiter_pipeline_001_source0_ready), // source0.ready
.out_valid (limiter_pipeline_001_source0_valid), // .valid
.out_startofpacket (limiter_pipeline_001_source0_startofpacket), // .startofpacket
.out_endofpacket (limiter_pipeline_001_source0_endofpacket), // .endofpacket
.out_data (limiter_pipeline_001_source0_data), // .data
.out_channel (limiter_pipeline_001_source0_channel), // .channel
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error (), // (terminated)
.in_error (1'b0) // (terminated)
);
altera_avalon_st_pipeline_stage #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.USE_PACKETS (1),
.USE_EMPTY (0),
.EMPTY_WIDTH (0),
.CHANNEL_WIDTH (8),
.PACKET_WIDTH (2),
.ERROR_WIDTH (0),
.PIPELINE_READY (1)
) limiter_pipeline_002 (
.clk (clk_50), // cr0.clk
.reset (rst_controller_001_reset_out_reset), // cr0_reset.reset
.in_ready (limiter_001_cmd_src_ready), // sink0.ready
.in_valid (limiter_001_cmd_src_valid), // .valid
.in_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.in_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.in_data (limiter_001_cmd_src_data), // .data
.in_channel (limiter_001_cmd_src_channel), // .channel
.out_ready (limiter_pipeline_002_source0_ready), // source0.ready
.out_valid (limiter_pipeline_002_source0_valid), // .valid
.out_startofpacket (limiter_pipeline_002_source0_startofpacket), // .startofpacket
.out_endofpacket (limiter_pipeline_002_source0_endofpacket), // .endofpacket
.out_data (limiter_pipeline_002_source0_data), // .data
.out_channel (limiter_pipeline_002_source0_channel), // .channel
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error (), // (terminated)
.in_error (1'b0) // (terminated)
);
altera_avalon_st_pipeline_stage #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.USE_PACKETS (1),
.USE_EMPTY (0),
.EMPTY_WIDTH (0),
.CHANNEL_WIDTH (8),
.PACKET_WIDTH (2),
.ERROR_WIDTH (0),
.PIPELINE_READY (1)
) limiter_pipeline_003 (
.clk (clk_50), // cr0.clk
.reset (rst_controller_001_reset_out_reset), // cr0_reset.reset
.in_ready (rsp_xbar_mux_001_src_ready), // sink0.ready
.in_valid (rsp_xbar_mux_001_src_valid), // .valid
.in_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.in_data (rsp_xbar_mux_001_src_data), // .data
.in_channel (rsp_xbar_mux_001_src_channel), // .channel
.out_ready (limiter_pipeline_003_source0_ready), // source0.ready
.out_valid (limiter_pipeline_003_source0_valid), // .valid
.out_startofpacket (limiter_pipeline_003_source0_startofpacket), // .startofpacket
.out_endofpacket (limiter_pipeline_003_source0_endofpacket), // .endofpacket
.out_data (limiter_pipeline_003_source0_data), // .data
.out_channel (limiter_pipeline_003_source0_channel), // .channel
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error (), // (terminated)
.in_error (1'b0) // (terminated)
);
DE4_SOPC_irq_mapper irq_mapper (
.clk (clk_50), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (cheri_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (clk_50), // receiver_clk.clk
.sender_clk (clk_50), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver0_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_001 (
.receiver_clk (clk_50), // receiver_clk.clk
.sender_clk (clk_50), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_001_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver1_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_002 (
.receiver_clk (clk_50), // receiver_clk.clk
.sender_clk (clk_50), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_002_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver2_irq) // sender.irq
);
assign sram_clk_clk = clk_50;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************
// File name: addr_cmd_non_ldc_pad.v
//
// Address/command pad using non-memip-specific hardware.
//
// Only SDR addr/cmd is supported at the moment.
//
// *****************************************************************
`timescale 1 ps / 1 ps
module addr_cmd_non_ldc_pad (
pll_afi_clk,
pll_hr_clk,
afi_datain,
mem_dataout
);
// *****************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in
// from higher level wrapper with the controller and driver
parameter AFI_DATA_WIDTH = "";
parameter MEM_DATA_WIDTH = "";
parameter REGISTER_C2P = "";
// *****************************************************************
// BEGIN PORT SECTION
input pll_afi_clk;
input pll_hr_clk;
input [AFI_DATA_WIDTH-1:0] afi_datain;
output [MEM_DATA_WIDTH-1:0] mem_dataout;
// *****************************************************************
// BEGIN SIGNALS SECTION
reg [AFI_DATA_WIDTH-1:0] afi_datain_r;
wire [2*MEM_DATA_WIDTH:0] fr_ddio_out_datain;
wire fr_ddio_out_clk;
// *****************************************************************
// Register the C2P boundary if needed.
generate
if (REGISTER_C2P == "false") begin
always @* begin
afi_datain_r <= afi_datain;
end
end else begin
always @(posedge pll_afi_clk) begin
afi_datain_r <= afi_datain;
end
end
endgenerate
// *****************************************************************
// AFI data will be fed into DDIO_OUTs to perform HR->FR conversion
// using pll_afi_clk.
assign fr_ddio_out_datain = afi_datain_r;
assign fr_ddio_out_clk = pll_afi_clk;
// *****************************************************************
// Register output data using DDIO_OUTs in periphery.
DE4_SOPC_ddr2_0_p0_simple_ddio_out # (
.DATA_WIDTH (MEM_DATA_WIDTH),
.OUTPUT_FULL_DATA_WIDTH (MEM_DATA_WIDTH),
.USE_CORE_LOGIC ("false"),
.HALF_RATE_MODE ("false"),
.REGISTER_OUTPUT ("false")
) fr_ddio_out (
.clk (fr_ddio_out_clk),
.datain (fr_ddio_out_datain),
.dataout (mem_dataout),
.reset_n (1'b1)
);
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// Filename: afi_mux.v
// This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals
// During calibration, mux_sel = 1, sequencer AFI signals are selected
// After calibration is succesfu, mux_sel = 0, controller AFI signals are selected
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module afi_mux_ddrx (
clk,
mux_sel,
afi_addr,
`ifdef DDRIISRAM
afi_ld_n,
afi_rw_n,
afi_bws_n,
`endif
afi_ba,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dm,
afi_wlat,
afi_rlat,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_cal_success,
afi_cal_fail,
seq_mux_addr,
`ifdef DDRIISRAM
seq_mux_ld_n,
seq_mux_rw_n,
seq_mux_doff_n,
seq_mux_bws_n,
`endif
seq_mux_ba,
seq_mux_cs_n,
seq_mux_cke,
seq_mux_odt,
seq_mux_ras_n,
seq_mux_cas_n,
seq_mux_we_n,
seq_mux_dm,
seq_mux_dqs_burst,
seq_mux_wdata,
seq_mux_wdata_valid,
seq_mux_rdata_en,
seq_mux_rdata_en_full,
seq_mux_rdata,
seq_mux_rdata_valid,
phy_mux_addr,
`ifdef DDRIISRAM
phy_mux_ld_n,
phy_mux_rw_n,
phy_mux_doff_n,
phy_mux_bws_n,
`endif
phy_mux_ba,
phy_mux_cs_n,
phy_mux_cke,
phy_mux_odt,
phy_mux_ras_n,
phy_mux_cas_n,
phy_mux_we_n,
phy_mux_dm,
phy_mux_wlat,
phy_mux_rlat,
phy_mux_dqs_burst,
phy_mux_wdata,
phy_mux_wdata_valid,
phy_mux_rdata_en,
phy_mux_rdata_en_full,
phy_mux_rdata,
phy_mux_rdata_valid,
phy_mux_cal_success,
phy_mux_cal_fail
);
parameter AFI_ADDR_WIDTH = 0;
`ifdef DDRIISRAM
parameter AFI_CS_WIDTH = 0;
`endif
parameter AFI_BANKADDR_WIDTH = 0;
parameter AFI_CS_WIDTH = 0;
parameter AFI_CLK_EN_WIDTH = 0;
parameter AFI_ODT_WIDTH = 0;
parameter AFI_WLAT_WIDTH = 0;
parameter AFI_RLAT_WIDTH = 0;
parameter AFI_DM_WIDTH = 0;
parameter AFI_CONTROL_WIDTH = 0;
parameter AFI_DQ_WIDTH = 0;
parameter AFI_WRITE_DQS_WIDTH = 0;
parameter AFI_RATE_RATIO = 0;
input clk;
input mux_sel;
// AFI inputs from the controller
input [AFI_ADDR_WIDTH-1:0] afi_addr;
`ifdef DDRIISRAM
input [AFI_CS_WIDTH-1:0] afi_ld_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rw_n;
input [AFI_DM_WIDTH-1:0] afi_bws_n;
`endif
input [AFI_BANKADDR_WIDTH-1:0] afi_ba;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CS_WIDTH-1:0] afi_cs_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_DM_WIDTH-1:0] afi_dm;
output [AFI_WLAT_WIDTH-1:0] afi_wlat;
output [AFI_RLAT_WIDTH-1:0] afi_rlat;
input [AFI_WRITE_DQS_WIDTH-1:0] afi_dqs_burst;
input [AFI_DQ_WIDTH-1:0] afi_wdata;
input [AFI_WRITE_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_RATE_RATIO-1:0] afi_rdata_en;
input [AFI_RATE_RATIO-1:0] afi_rdata_en_full;
output [AFI_DQ_WIDTH-1:0] afi_rdata;
output [AFI_RATE_RATIO-1:0] afi_rdata_valid;
output afi_cal_success;
output afi_cal_fail;
// AFI inputs from the sequencer
input [AFI_ADDR_WIDTH-1:0] seq_mux_addr;
`ifdef DDRIISRAM
input [AFI_CS_WIDTH-1:0] seq_mux_ld_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_rw_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_doff_n;
input [AFI_DM_WIDTH-1:0] seq_mux_bws_n;
`endif
input [AFI_BANKADDR_WIDTH-1:0] seq_mux_ba;
input [AFI_CS_WIDTH-1:0] seq_mux_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke;
input [AFI_ODT_WIDTH-1:0] seq_mux_odt;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n;
input [AFI_DM_WIDTH-1:0] seq_mux_dm;
input [AFI_WRITE_DQS_WIDTH-1:0] seq_mux_dqs_burst;
input [AFI_DQ_WIDTH-1:0] seq_mux_wdata;
input [AFI_WRITE_DQS_WIDTH-1:0] seq_mux_wdata_valid;
input [AFI_RATE_RATIO-1:0] seq_mux_rdata_en;
input [AFI_RATE_RATIO-1:0] seq_mux_rdata_en_full;
output [AFI_DQ_WIDTH-1:0] seq_mux_rdata;
output [AFI_RATE_RATIO-1:0] seq_mux_rdata_valid;
// Mux output to the rest of the PHY logic
output [AFI_ADDR_WIDTH-1:0] phy_mux_addr;
`ifdef DDRIISRAM
output [AFI_CS_WIDTH-1:0] phy_mux_ld_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_rw_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_doff_n;
output [AFI_DM_WIDTH-1:0] phy_mux_bws_n;
`endif
output [AFI_BANKADDR_WIDTH-1:0] phy_mux_ba;
output [AFI_CS_WIDTH-1:0] phy_mux_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_mux_cke;
output [AFI_ODT_WIDTH-1:0] phy_mux_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_we_n;
output [AFI_DM_WIDTH-1:0] phy_mux_dm;
input [AFI_WLAT_WIDTH-1:0] phy_mux_wlat;
input [AFI_RLAT_WIDTH-1:0] phy_mux_rlat;
output [AFI_WRITE_DQS_WIDTH-1:0] phy_mux_dqs_burst;
output [AFI_DQ_WIDTH-1:0] phy_mux_wdata;
output [AFI_WRITE_DQS_WIDTH-1:0] phy_mux_wdata_valid;
output [AFI_RATE_RATIO-1:0] phy_mux_rdata_en;
output [AFI_RATE_RATIO-1:0] phy_mux_rdata_en_full;
input [AFI_DQ_WIDTH-1:0] phy_mux_rdata;
input [AFI_RATE_RATIO-1:0] phy_mux_rdata_valid;
input phy_mux_cal_success;
input phy_mux_cal_fail;
reg [AFI_ADDR_WIDTH-1:0] afi_addr_r;
`ifdef DDRIISRAM
reg [AFI_CS_WIDTH-1:0] afi_ld_n_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_rw_n_r;
`endif
reg [AFI_BANKADDR_WIDTH-1:0] afi_ba_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] afi_cke_r;
reg [AFI_CS_WIDTH-1:0] afi_cs_n_r;
reg [AFI_ODT_WIDTH-1:0] afi_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_we_n_r;
reg [AFI_ADDR_WIDTH-1:0] seq_mux_addr_r;
`ifdef DDRIISRAM
reg [AFI_CS_WIDTH-1:0] seq_mux_ld_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_rw_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_doff_n_r;
`endif
reg [AFI_BANKADDR_WIDTH-1:0] seq_mux_ba_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke_r;
reg [AFI_CS_WIDTH-1:0] seq_mux_cs_n_r;
reg [AFI_ODT_WIDTH-1:0] seq_mux_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n_r;
always @(posedge clk)
`ifdef DDRIISRAM
always @*
`endif
begin
afi_addr_r <= afi_addr;
`ifdef DDRIISRAM
afi_ld_n_r <= afi_ld_n;
afi_rw_n_r <= afi_rw_n;
`endif
afi_ba_r <= afi_ba;
afi_cs_n_r <= afi_cs_n;
afi_cke_r <= afi_cke;
afi_odt_r <= afi_odt;
afi_ras_n_r <= afi_ras_n;
afi_cas_n_r <= afi_cas_n;
afi_we_n_r <= afi_we_n;
seq_mux_addr_r <= seq_mux_addr;
`ifdef DDRIISRAM
seq_mux_ld_n_r <= seq_mux_ld_n;
seq_mux_rw_n_r <= seq_mux_rw_n;
seq_mux_doff_n_r <= seq_mux_doff_n;
`endif
seq_mux_ba_r <= seq_mux_ba;
seq_mux_cs_n_r <= seq_mux_cs_n;
seq_mux_cke_r <= seq_mux_cke;
seq_mux_odt_r <= seq_mux_odt;
seq_mux_ras_n_r <= seq_mux_ras_n;
seq_mux_cas_n_r <= seq_mux_cas_n;
seq_mux_we_n_r <= seq_mux_we_n;
end
wire [AFI_DQ_WIDTH-1:0] afi_wdata_int;
assign afi_rdata = phy_mux_rdata;
assign afi_wdata_int = afi_wdata;
assign afi_rdata_valid = mux_sel ? {AFI_RATE_RATIO{1'b0}} : phy_mux_rdata_valid;
assign seq_mux_rdata = phy_mux_rdata;
assign seq_mux_rdata_valid = phy_mux_rdata_valid;
assign phy_mux_addr = mux_sel ? seq_mux_addr_r : afi_addr_r;
`ifdef DDRIISRAM
assign phy_mux_ld_n = mux_sel ? seq_mux_ld_n_r : afi_ld_n_r;
assign phy_mux_rw_n = mux_sel ? seq_mux_rw_n_r : afi_rw_n_r;
assign phy_mux_doff_n = seq_mux_doff_n_r;
assign phy_mux_bws_n = mux_sel ? seq_mux_bws_n : afi_bws_n;
`endif
assign phy_mux_ba = mux_sel ? seq_mux_ba_r : afi_ba_r;
assign phy_mux_cs_n = mux_sel ? seq_mux_cs_n_r : afi_cs_n_r;
assign phy_mux_cke = mux_sel ? seq_mux_cke_r : afi_cke_r;
assign phy_mux_odt = mux_sel ? seq_mux_odt_r : afi_odt_r;
assign phy_mux_ras_n = mux_sel ? seq_mux_ras_n_r : afi_ras_n_r;
assign phy_mux_cas_n = mux_sel ? seq_mux_cas_n_r : afi_cas_n_r;
assign phy_mux_we_n = mux_sel ? seq_mux_we_n_r : afi_we_n_r;
assign phy_mux_dm = mux_sel ? seq_mux_dm : afi_dm;
assign afi_wlat = phy_mux_wlat;
assign afi_rlat = phy_mux_rlat;
assign phy_mux_dqs_burst = mux_sel ? seq_mux_dqs_burst : afi_dqs_burst;
assign phy_mux_wdata = mux_sel ? seq_mux_wdata : afi_wdata_int;
assign phy_mux_wdata_valid = mux_sel ? seq_mux_wdata_valid : afi_wdata_valid;
assign phy_mux_rdata_en = mux_sel ? seq_mux_rdata_en : afi_rdata_en;
assign phy_mux_rdata_en_full = mux_sel ? seq_mux_rdata_en_full : afi_rdata_en_full;
assign afi_cal_success = phy_mux_cal_success;
assign afi_cal_fail = phy_mux_cal_fail;
endmodule
|
// $File: //acds/rel/12.1/ip/sopc/components/altera_avalon_dc_fifo/altera_avalon_dc_fifo.v $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
//-------------------------------------------------------------------------------
// Description: Dual clocked single channel FIFO with fill levels and status
// information.
// ---------------------------------------------------------------------
`timescale 1 ns / 100 ps
//altera message_off 10036 10858 10230 10030 10034
module altera_avalon_dc_fifo(
in_clk,
in_reset_n,
out_clk,
out_reset_n,
// sink
in_data,
in_valid,
in_ready,
in_startofpacket,
in_endofpacket,
in_empty,
in_error,
in_channel,
// source
out_data,
out_valid,
out_ready,
out_startofpacket,
out_endofpacket,
out_empty,
out_error,
out_channel,
// in csr
in_csr_address,
in_csr_write,
in_csr_read,
in_csr_readdata,
in_csr_writedata,
// out csr
out_csr_address,
out_csr_write,
out_csr_read,
out_csr_readdata,
out_csr_writedata,
// streaming in status
almost_full_valid,
almost_full_data,
// streaming out status
almost_empty_valid,
almost_empty_data,
// (internal, experimental interface) space available st source
space_avail_data
);
// ---------------------------------------------------------------------
// Parameters
// ---------------------------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FIFO_DEPTH = 16;
parameter CHANNEL_WIDTH = 0;
parameter ERROR_WIDTH = 0;
parameter USE_PACKETS = 0;
parameter USE_IN_FILL_LEVEL = 0;
parameter USE_OUT_FILL_LEVEL = 0;
parameter WR_SYNC_DEPTH = 2;
parameter RD_SYNC_DEPTH = 2;
parameter STREAM_ALMOST_FULL = 0;
parameter STREAM_ALMOST_EMPTY = 0;
// experimental, internal parameter
parameter USE_SPACE_AVAIL_IF = 0;
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
localparam EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT);
localparam PACKET_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// ---------------------------------------------------------------------
// Input/Output Signals
// ---------------------------------------------------------------------
input in_clk;
input in_reset_n;
input out_clk;
input out_reset_n;
input [DATA_WIDTH - 1 : 0] in_data;
input in_valid;
input in_startofpacket;
input in_endofpacket;
input [EMPTY_WIDTH - 1 : 0] in_empty;
input [ERROR_WIDTH - 1 : 0] in_error;
input [CHANNEL_WIDTH - 1: 0] in_channel;
output in_ready;
output [DATA_WIDTH - 1 : 0] out_data;
output reg out_valid;
output out_startofpacket;
output out_endofpacket;
output [EMPTY_WIDTH - 1 : 0] out_empty;
output [ERROR_WIDTH - 1 : 0] out_error;
output [CHANNEL_WIDTH - 1: 0] out_channel;
input out_ready;
input in_csr_address;
input in_csr_read;
input in_csr_write;
input [31 : 0] in_csr_writedata;
output reg [31 : 0] in_csr_readdata;
input out_csr_address;
input out_csr_read;
input out_csr_write;
input [31 : 0] out_csr_writedata;
output reg [31 : 0] out_csr_readdata;
output reg almost_full_valid;
output reg almost_full_data;
output reg almost_empty_valid;
output reg almost_empty_data;
output [ADDR_WIDTH : 0] space_avail_data;
// ---------------------------------------------------------------------
// Memory Pointers
// ---------------------------------------------------------------------
(* ramstyle="no_rw_check" *) reg [PAYLOAD_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
wire [ADDR_WIDTH - 1 : 0] mem_wr_ptr;
wire [ADDR_WIDTH - 1 : 0] mem_rd_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr;
reg [ADDR_WIDTH : 0] out_rd_ptr;
// ---------------------------------------------------------------------
// Internal Signals
// ---------------------------------------------------------------------
wire [ADDR_WIDTH : 0] next_out_wr_ptr;
wire [ADDR_WIDTH : 0] next_in_wr_ptr;
wire [ADDR_WIDTH : 0] next_out_rd_ptr;
wire [ADDR_WIDTH : 0] next_in_rd_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
wire [ADDR_WIDTH : 0] out_wr_ptr_gray;
reg [ADDR_WIDTH : 0] out_rd_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
wire [ADDR_WIDTH : 0] in_rd_ptr_gray;
reg full;
reg empty;
wire [PAYLOAD_WIDTH - 1 : 0] in_payload;
reg [PAYLOAD_WIDTH - 1 : 0] out_payload;
reg [PAYLOAD_WIDTH - 1 : 0] internal_out_payload;
wire [PACKET_SIGNALS_WIDTH - 1 : 0] in_packet_signals;
wire [PACKET_SIGNALS_WIDTH - 1 : 0] out_packet_signals;
wire internal_out_ready;
wire internal_out_valid;
wire [ADDR_WIDTH : 0] out_fill_level;
reg [ADDR_WIDTH : 0] out_fifo_fill_level;
reg [ADDR_WIDTH : 0] in_fill_level;
reg [ADDR_WIDTH : 0] in_space_avail;
reg [23 : 0] almost_empty_threshold;
reg [23 : 0] almost_full_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// ---------------------------------------------------------------------
// Memory
//
// Infers a simple dual clock memory with unregistered outputs
// ---------------------------------------------------------------------
always @(posedge in_clk) begin
if (in_valid && in_ready)
mem[mem_wr_ptr] <= in_payload;
end
always @(posedge out_clk) begin
internal_out_payload <= mem[mem_rd_ptr];
end
assign mem_rd_ptr = next_out_rd_ptr;
assign mem_wr_ptr = in_wr_ptr;
// ---------------------------------------------------------------------
// Pointer Management
//
// Increment our good old read and write pointers on their native
// clock domains.
// ---------------------------------------------------------------------
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n)
in_wr_ptr <= 0;
else
in_wr_ptr <= next_in_wr_ptr;
end
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n)
out_rd_ptr <= 0;
else
out_rd_ptr <= next_out_rd_ptr;
end
assign next_in_wr_ptr = (in_ready && in_valid) ? in_wr_ptr + 1'b1 : in_wr_ptr;
assign next_out_rd_ptr = (internal_out_ready && internal_out_valid) ? out_rd_ptr + 1'b1 : out_rd_ptr;
// ---------------------------------------------------------------------
// Empty/Full Signal Generation
//
// We keep read and write pointers that are one bit wider than
// required, and use that additional bit to figure out if we're
// full or empty.
// ---------------------------------------------------------------------
always @(posedge out_clk or negedge out_reset_n) begin
if(!out_reset_n)
empty <= 1;
else
empty <= (next_out_rd_ptr == next_out_wr_ptr);
end
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n)
full <= 0;
else
full <= (next_in_rd_ptr[ADDR_WIDTH - 1 : 0] == next_in_wr_ptr[ADDR_WIDTH - 1 : 0]) && (next_in_rd_ptr[ADDR_WIDTH] != next_in_wr_ptr[ADDR_WIDTH]);
end
// ---------------------------------------------------------------------
// Write Pointer Clock Crossing
//
// Clock crossing is done with gray encoding of the pointers. What? You
// want to know more? We ensure a one bit change at sampling time,
// and then metastable harden the sampled gray pointer.
// ---------------------------------------------------------------------
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n)
in_wr_ptr_gray <= 0;
else
in_wr_ptr_gray <= bin2gray(in_wr_ptr);
end
altera_dcfifo_synchronizer_bundle #(.WIDTH(ADDR_WIDTH+1), .DEPTH(WR_SYNC_DEPTH))
write_crosser (
.clk(out_clk),
.reset_n(out_reset_n),
.din(in_wr_ptr_gray),
.dout(out_wr_ptr_gray)
);
assign next_out_wr_ptr = gray2bin(out_wr_ptr_gray);
// ---------------------------------------------------------------------
// Read Pointer Clock Crossing
//
// Go the other way, go the other way...
// ---------------------------------------------------------------------
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n)
out_rd_ptr_gray <= 0;
else
out_rd_ptr_gray <= bin2gray(out_rd_ptr);
end
altera_dcfifo_synchronizer_bundle #(.WIDTH(ADDR_WIDTH+1), .DEPTH(RD_SYNC_DEPTH))
read_crosser (
.clk(in_clk),
.reset_n(in_reset_n),
.din(out_rd_ptr_gray),
.dout(in_rd_ptr_gray)
);
assign next_in_rd_ptr = gray2bin(in_rd_ptr_gray);
// ---------------------------------------------------------------------
// Avalon ST Signals
// ---------------------------------------------------------------------
assign in_ready = !full;
assign internal_out_valid = !empty;
// --------------------------------------------------
// Output Pipeline Stage
//
// We do this on the single clock FIFO to keep fmax
// up because the memory outputs are kind of slow.
// Therefore, this stage is even more critical on a dual clock
// FIFO, wouldn't you say? No one wants a slow dcfifo.
// --------------------------------------------------
assign internal_out_ready = out_ready || !out_valid;
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid;
out_payload <= internal_out_payload;
end
end
end
// ---------------------------------------------------------------------
// Out Fill Level
//
// As in the SCFIFO, we account for the output stage as well in the
// fill level calculations. This means that the out fill level always
// gives the most accurate fill level report.
//
// On a full 16-deep FIFO, the out fill level will read 17. Funny, but
// accurate.
//
// That's essential on the output side, because a downstream component
// might want to know the exact amount of data in the FIFO at any time.
// ---------------------------------------------------------------------
generate
if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_fifo_fill_level <= 0;
end
else begin
out_fifo_fill_level <= next_out_wr_ptr - next_out_rd_ptr;
end
end
assign out_fill_level = out_fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
endgenerate
// ---------------------------------------------------------------------
// Almost Empty Streaming Status & Out CSR
//
// This is banal by now, but where's the empty signal? The output side.
// Where's the almost empty status? The output side.
//
// The almost empty signal is asserted when the output fill level
// in the FIFO falls below the user-specified threshold.
//
// Output CSR address map:
//
// | Addr | RW | 31 - 24 | 23 - 0 |
// | 0 | R | Reserved | Out fill level |
// | 1 | RW | Reserved | Almost empty threshold |
// ---------------------------------------------------------------------
generate
if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_csr_readdata <= 0;
if (STREAM_ALMOST_EMPTY)
almost_empty_threshold <= 0;
end
else begin
if (out_csr_write) begin
if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
almost_empty_threshold <= out_csr_writedata[23 : 0];
end
else if (out_csr_read) begin
out_csr_readdata <= 0;
if (out_csr_address == 0)
out_csr_readdata[23 : 0] <= out_fill_level;
else if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
out_csr_readdata[23 : 0] <= almost_empty_threshold;
end
end
end
end
if (STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
almost_empty_valid <= 0;
almost_empty_data <= 0;
end
else begin
almost_empty_valid <= 1'b1;
almost_empty_data <= (out_fill_level <= almost_empty_threshold);
end
end
end
endgenerate
// ---------------------------------------------------------------------
// In Fill Level & In Status Connection Point
//
// Note that the input fill level does not account for the output
// stage i.e it is only the fifo fill level.
//
// Is this a problem? No, because the input fill is usually used to
// see how much data can still be pushed into this FIFO. The FIFO
// fill level gives exactly this information, and there's no need to
// make our lives more difficult by including the output stage here.
//
// One might ask: why not just report a space available level on the
// input side? Well, I'd like to make this FIFO be as similar as possible
// to its single clock cousin, and that uses fill levels and
// fill thresholds with nary a mention of space available.
// ---------------------------------------------------------------------
generate
if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_fill_level <= 0;
end
else begin
in_fill_level <= next_in_wr_ptr - next_in_rd_ptr;
end
end
end
endgenerate
generate
if (USE_SPACE_AVAIL_IF) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_space_avail <= FIFO_DEPTH;
end
else begin
// -------------------------------------
// space = DEPTH-fill = DEPTH-(wr-rd) = DEPTH+rd-wr
// Conveniently, DEPTH requires the same number of bits
// as the pointers, e.g. a dcfifo with depth = 8
// requires 4-bit pointers.
//
// Adding 8 to a 4-bit pointer is simply negating the
// first bit... as is done below.
// -------------------------------------
in_space_avail <= {~next_in_rd_ptr[ADDR_WIDTH],
next_in_rd_ptr[ADDR_WIDTH-1:0]} -
next_in_wr_ptr;
end
end
end
assign space_avail_data = in_space_avail;
endgenerate
// ---------------------------------------------------------------------
// Almost Full Streaming Status & In CSR
//
// Where's the full signal? The input side.
// Where's the almost full status? The input side.
//
// The almost full data bit is asserted when the input fill level
// in the FIFO goes above the user-specified threshold.
//
// Input csr port address map:
//
// | Addr | RW | 31 - 24 | 23 - 0 |
// | 0 | R | Reserved | In fill level |
// | 1 | RW | Reserved | Almost full threshold |
// ---------------------------------------------------------------------
generate
if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_csr_readdata <= 0;
if (STREAM_ALMOST_FULL)
almost_full_threshold <= 0;
end
else begin
if (in_csr_write) begin
if (STREAM_ALMOST_FULL && (in_csr_address == 1))
almost_full_threshold <= in_csr_writedata[23 : 0];
end
else if (in_csr_read) begin
in_csr_readdata <= 0;
if (in_csr_address == 0)
in_csr_readdata[23 : 0] <= in_fill_level;
else if (STREAM_ALMOST_FULL && (in_csr_address == 1))
in_csr_readdata[23 : 0] <= almost_full_threshold;
end
end
end
end
if (STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
almost_full_valid <= 0;
almost_full_data <= 0;
end
else begin
almost_full_valid <= 1'b1;
almost_full_data <= (in_fill_level >= almost_full_threshold);
end
end
end
endgenerate
// ---------------------------------------------------------------------
// Gray Functions
//
// These are real beasts when you look at them. But they'll be
// tested thoroughly.
// ---------------------------------------------------------------------
function [ADDR_WIDTH : 0] bin2gray;
input [ADDR_WIDTH : 0] bin_val;
integer i;
for (i = 0; i <= ADDR_WIDTH; i = i + 1)
begin
if (i == ADDR_WIDTH)
bin2gray[i] = bin_val[i];
else
bin2gray[i] = bin_val[i+1] ^ bin_val[i];
end
endfunction
function [ADDR_WIDTH : 0] gray2bin;
input [ADDR_WIDTH : 0] gray_val;
integer i;
integer j;
for (i = 0; i <= ADDR_WIDTH; i = i + 1) begin
gray2bin[i] = gray_val[i];
for (j = ADDR_WIDTH; j > i; j = j - 1) begin
gray2bin[i] = gray2bin[i] ^ gray_val[j];
end
end
endfunction
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM pipeline bridge
//
// Optionally registers Avalon-MM command and response signals
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter ADDRESS_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input clk,
input reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [ADDRESS_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [ADDRESS_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
// --------------------------------------
// Registers & signals
// --------------------------------------
reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount;
reg [DATA_WIDTH-1:0] cmd_writedata;
reg [ADDRESS_WIDTH-1:0] cmd_address;
reg cmd_write;
reg cmd_read;
reg [BYTEEN_WIDTH-1:0] cmd_byteenable;
wire cmd_waitrequest;
reg cmd_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount;
reg [DATA_WIDTH-1:0] wr_writedata;
reg [ADDRESS_WIDTH-1:0] wr_address;
reg wr_write;
reg wr_read;
reg [BYTEEN_WIDTH-1:0] wr_byteenable;
reg wr_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount;
reg [DATA_WIDTH-1:0] wr_reg_writedata;
reg [ADDRESS_WIDTH-1:0] wr_reg_address;
reg wr_reg_write;
reg wr_reg_read;
reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable;
reg wr_reg_waitrequest;
reg wr_reg_debugaccess;
reg use_reg;
wire wait_rise;
reg [DATA_WIDTH-1:0] rsp_readdata;
reg rsp_readdatavalid;
// --------------------------------------
// Command pipeline
//
// Registers all command signals, including waitrequest
// --------------------------------------
generate if (PIPELINE_COMMAND == 1) begin
// --------------------------------------
// Waitrequest Pipeline Stage
//
// Output waitrequest is delayed by one cycle, which means
// that a master will see waitrequest assertions one cycle
// too late.
//
// Solution: buffer the command when waitrequest transitions
// from low->high. As an optimization, we can safely assume
// waitrequest is low by default because downstream logic
// in the bridge ensures this.
//
// Note: this implementation buffers idle cycles should
// waitrequest transition on such cycles. This is a potential
// cause for throughput loss, but ye olde pipeline bridge did
// the same for years and no one complained. Not buffering idle
// cycles costs logic on the waitrequest path.
// --------------------------------------
assign s0_waitrequest = wr_reg_waitrequest;
assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest;
always @(posedge clk, posedge reset) begin
if (reset) begin
wr_reg_waitrequest <= 1'b1;
// --------------------------------------
// Bit of trickiness here, deserving of a long comment.
//
// On the first cycle after reset, the pass-through
// must not be used or downstream logic may sample
// the same command twice because of the delay in
// transmitting a falling waitrequest.
//
// Using the registered command works on the condition
// that downstream logic deasserts waitrequest
// immediately after reset, which is true of the
// next stage in this bridge.
// --------------------------------------
use_reg <= 1'b1;
wr_reg_burstcount <= 1'b1;
wr_reg_writedata <= 0;
wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}};
wr_reg_address <= 0;
wr_reg_write <= 1'b0;
wr_reg_read <= 1'b0;
wr_reg_debugaccess <= 1'b0;
end else begin
wr_reg_waitrequest <= cmd_waitrequest;
if (wait_rise) begin
use_reg <= 1'b1;
wr_reg_writedata <= s0_writedata;
wr_reg_byteenable <= s0_byteenable;
wr_reg_address <= s0_address;
wr_reg_write <= s0_write;
wr_reg_read <= s0_read;
wr_reg_burstcount <= s0_burstcount;
wr_reg_debugaccess <= s0_debugaccess;
end
// stop using the buffer when waitrequest is low
if (~cmd_waitrequest)
use_reg <= 1'b0;
end
end
always @* begin
wr_burstcount = s0_burstcount;
wr_writedata = s0_writedata;
wr_address = s0_address;
wr_write = s0_write;
wr_read = s0_read;
wr_byteenable = s0_byteenable;
wr_debugaccess = s0_debugaccess;
if (use_reg) begin
wr_burstcount = wr_reg_burstcount;
wr_writedata = wr_reg_writedata;
wr_address = wr_reg_address;
wr_write = wr_reg_write;
wr_read = wr_reg_read;
wr_byteenable = wr_reg_byteenable;
wr_debugaccess = wr_reg_debugaccess;
end
end
// --------------------------------------
// Master-Slave Signal Pipeline Stage
//
// One notable detail is that cmd_waitrequest is deasserted
// when this stage is idle. This allows us to make logic
// optimizations in the waitrequest pipeline stage.
//
// Also note that cmd_waitrequest is deasserted during reset,
// which is not spec-compliant, but is ok for an internal
// signal.
// --------------------------------------
wire no_command;
assign no_command = ~(cmd_read || cmd_write);
assign cmd_waitrequest = m0_waitrequest & ~no_command;
always @(posedge clk, posedge reset) begin
if (reset) begin
cmd_burstcount <= 1'b1;
cmd_writedata <= 0;
cmd_byteenable <= {BYTEEN_WIDTH{1'b1}};
cmd_address <= 0;
cmd_write <= 1'b0;
cmd_read <= 1'b0;
cmd_debugaccess <= 1'b0;
end
else begin
if (~cmd_waitrequest) begin
cmd_writedata <= wr_writedata;
cmd_byteenable <= wr_byteenable;
cmd_address <= wr_address;
cmd_write <= wr_write;
cmd_read <= wr_read;
cmd_burstcount <= wr_burstcount;
cmd_debugaccess <= wr_debugaccess;
end
end
end
end // conditional command pipeline
else begin
assign s0_waitrequest = m0_waitrequest;
always @* begin
cmd_burstcount = s0_burstcount;
cmd_writedata = s0_writedata;
cmd_address = s0_address;
cmd_write = s0_write;
cmd_read = s0_read;
cmd_byteenable = s0_byteenable;
cmd_debugaccess = s0_debugaccess;
end
end
endgenerate
assign m0_burstcount = cmd_burstcount;
assign m0_writedata = cmd_writedata;
assign m0_address = cmd_address;
assign m0_write = cmd_write;
assign m0_read = cmd_read;
assign m0_byteenable = cmd_byteenable;
assign m0_debugaccess = cmd_debugaccess;
// --------------------------------------
// Response pipeline
//
// Registers all response signals
// --------------------------------------
generate if (PIPELINE_RESPONSE == 1) begin
always @(posedge clk, posedge reset) begin
if (reset) begin
rsp_readdatavalid <= 1'b0;
rsp_readdata <= 0;
end
else begin
rsp_readdatavalid <= m0_readdatavalid;
rsp_readdata <= m0_readdata;
end
end
end // conditional response pipeline
else begin
always @* begin
rsp_readdatavalid = m0_readdatavalid;
rsp_readdata = m0_readdata;
end
end
endgenerate
assign s0_readdatavalid = rsp_readdatavalid;
assign s0_readdata = rsp_readdata;
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1/ip/merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge.v#1 $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM clock crossing bridge
//
// Clock crosses MM commands and responses with the
// help of asynchronous FIFOs.
//
// This bridge will stop emitting read commands when
// too many read commands are in flight to avoid
// response FIFO overflow.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_clock_crossing_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter ADDRESS_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter COMMAND_FIFO_DEPTH = 4,
parameter RESPONSE_FIFO_DEPTH = 4,
parameter MASTER_SYNC_DEPTH = 2,
parameter SLAVE_SYNC_DEPTH = 2,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input s0_clk,
input s0_reset,
input m0_clk,
input m0_reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [ADDRESS_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [ADDRESS_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
localparam CMD_WIDTH = BURSTCOUNT_WIDTH + DATA_WIDTH + ADDRESS_WIDTH
+ BYTEEN_WIDTH
+ 3; // read, write, debugaccess
localparam NUMSYMBOLS = DATA_WIDTH / SYMBOL_WIDTH;
localparam RSP_WIDTH = DATA_WIDTH;
localparam MAX_BURST = (1 << (BURSTCOUNT_WIDTH-1));
localparam COUNTER_WIDTH = log2ceil(RESPONSE_FIFO_DEPTH) + 1;
localparam NON_BURSTING = (MAX_BURST == 1);
localparam BURST_WORDS_W = BURSTCOUNT_WIDTH;
// --------------------------------------
// Signals
// --------------------------------------
wire [CMD_WIDTH-1:0] s0_cmd_payload;
wire [CMD_WIDTH-1:0] m0_cmd_payload;
wire s0_cmd_valid;
wire m0_cmd_valid;
wire m0_internal_write;
wire m0_internal_read;
wire s0_cmd_ready;
wire m0_cmd_ready;
reg [COUNTER_WIDTH-1:0] pending_read_count;
wire [COUNTER_WIDTH-1:0] space_avail;
wire stop_cmd;
reg stop_cmd_r;
wire m0_read_accepted;
wire m0_rsp_ready;
reg old_read;
wire [BURST_WORDS_W-1:0] m0_burstcount_words;
// --------------------------------------
// Command FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (CMD_WIDTH),
.FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.WR_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.RD_SYNC_DEPTH (SLAVE_SYNC_DEPTH)
)
cmd_fifo
(
.in_clk (s0_clk),
.in_reset_n (~s0_reset),
.out_clk (m0_clk),
.out_reset_n (~m0_reset),
.in_data (s0_cmd_payload),
.in_valid (s0_cmd_valid),
.in_ready (s0_cmd_ready),
.out_data (m0_cmd_payload),
.out_valid (m0_cmd_valid),
.out_ready (m0_cmd_ready)
);
// --------------------------------------
// Command payload
// --------------------------------------
assign s0_waitrequest = ~s0_cmd_ready;
assign s0_cmd_valid = s0_write | s0_read;
assign s0_cmd_payload = {s0_address,
s0_burstcount,
s0_read,
s0_write,
s0_writedata,
s0_byteenable,
s0_debugaccess};
assign {m0_address,
m0_burstcount,
m0_internal_read,
m0_internal_write,
m0_writedata,
m0_byteenable,
m0_debugaccess} = m0_cmd_payload;
assign m0_cmd_ready = ~m0_waitrequest &
~(m0_internal_read & stop_cmd_r & ~old_read);
assign m0_write = m0_internal_write & m0_cmd_valid;
assign m0_read = m0_internal_read & m0_cmd_valid & (~stop_cmd_r | old_read);
assign m0_read_accepted = m0_read & ~m0_waitrequest;
// ---------------------------------------------
// the non-bursting case
// ---------------------------------------------
generate if (NON_BURSTING)
begin
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted)
pending_read_count <= pending_read_count + 1;
if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count;
end
end
end
// ---------------------------------------------
// the bursting case
// ---------------------------------------------
else begin
assign m0_burstcount_words = m0_burstcount;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted)
pending_read_count <= pending_read_count +
m0_burstcount_words;
if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count +
m0_burstcount_words - 1;
end
end
end
endgenerate
assign stop_cmd = (pending_read_count + 2*MAX_BURST) > space_avail;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
stop_cmd_r <= 1'b0;
old_read <= 1'b0;
end
else begin
stop_cmd_r <= stop_cmd;
old_read <= m0_read & m0_waitrequest;
end
end
// --------------------------------------
// Response FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RSP_WIDTH),
.FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
.WR_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.RD_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.USE_SPACE_AVAIL_IF (1)
)
rsp_fifo
(
.in_clk (m0_clk),
.in_reset_n (~m0_reset),
.out_clk (s0_clk),
.out_reset_n (~s0_reset),
.in_data (m0_readdata),
.in_valid (m0_readdatavalid),
// ------------------------------------
// must never overflow, or we're in trouble
// (we cannot backpressure the response)
// ------------------------------------
.in_ready (m0_rsp_ready),
.out_data (s0_readdata),
.out_valid (s0_readdatavalid),
.out_ready (1'b1),
.space_avail_data (space_avail)
);
// synthesis translate_off
always @(posedge m0_clk) begin
if (~m0_rsp_ready & m0_readdatavalid) begin
$display("%t %m: internal error, response fifo overflow", $time);
end
if (pending_read_count > space_avail) begin
$display("%t %m: internal error, too many pending reads", $time);
end
end
// synthesis translate_on
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg [15:0] pkt_cnt_r;
reg [15:0] pkt_cnt_plusone;
reg [15:0] pkt_cnt_minusone;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
reg pkt_cnt_changed;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
if (EMPTY_LATENCY == 1) begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
if (write)
mem_used[0] <= 1;
end
end
end
if (DEPTH > 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (read)
mem_used[i] <= mem_used[i+1];
if (write)
mem_used[i] <= mem_used[i-1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin
wire [31:0] depth32;
assign depth32 = DEPTH;
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
end
end
end
end
else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= fill_level;
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_cnt_r <= 0;
pkt_cnt_plusone <= 1;
pkt_cnt_minusone <= 0;
pkt_cnt_changed <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
pkt_cnt_plusone <= pkt_cnt + 1'b1;
pkt_cnt_minusone <= pkt_cnt - 1'b1;
pkt_cnt_r <= pkt_cnt;
pkt_cnt_changed <= 1'b0;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
end
else begin
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface (
clk,
reset_n,
source_ready,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest,
debug_reset,
mgmt_valid,
mgmt_channel,
mgmt_data
);
input clk;
input reset_n;
output [7:0] source_data;
input source_ready;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
output resetrequest;
output debug_reset;
output mgmt_valid;
output mgmt_data;
parameter PURPOSE = 0; // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
parameter MGMT_CHANNEL_WIDTH = -1;
parameter USE_PLI = 0; // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000; // PLI Simulation Port
output [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel;
wire clk;
wire resetrequest;
wire [7:0] source_data;
wire source_ready;
wire source_valid;
wire [7:0] sink_data;
wire sink_valid;
wire sink_ready;
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
altera_pli_streaming #(.PURPOSE(PURPOSE), .PLI_PORT(PLI_PORT)) pli_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.source_ready(source_ready),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest)
);
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// $File: //acds/rel/12.1/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
//-------------------------------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_dcfifo_synchronizer_bundle(
clk,
reset_n,
din,
dout
);
parameter WIDTH = 1;
parameter DEPTH = 3;
input clk;
input reset_n;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
genvar i;
generate
for (i=0; i<WIDTH; i=i+1)
begin : sync
altera_std_synchronizer #(.depth(DEPTH))
u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
|
// This module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
// This module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
module altera_jtag_dc_streaming (
clk,
reset_n,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest,
debug_reset,
mgmt_valid,
mgmt_channel,
mgmt_data
);
input clk;
input reset_n;
output [7:0] source_data;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
output resetrequest;
output debug_reset;
output mgmt_valid;
output mgmt_data;
parameter PURPOSE = 0; // for discovery of services behind this JTAG Phy
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
parameter MGMT_CHANNEL_WIDTH = -1;
// the tck to sysclk sync depth is fixed at 8
// 8 is the worst case scenario from our metastability analysis, and since
// using TCK serially is so slow we should have plenty of clock cycles.
parameter TCK_TO_SYSCLK_SYNC_DEPTH = 8;
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
// Since the tck clock is so slow, no parameter is exposed.
parameter SYSCLK_TO_TCK_SYNC_DEPTH = 3;
output [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel;
// Signals in the JTAG clock domain
wire jtag_clock;
wire jtag_clock_reset_n; // system reset is synchronized with jtag_clock
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire [7:0] jtag_sink_data;
wire jtag_sink_valid;
wire jtag_sink_ready;
/* Reset Synchronizer module.
*
* The SLD Node does not provide a reset for the TCK clock domain.
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
* internal states need to be reset to 0 in order to guarantee proper
* functionality throughout resets.
*
* This reset block will asynchronously assert reset, and synchronously
* deassert reset for the tck clock domain.
*/
altera_std_synchronizer #(
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
) synchronizer (
.clk(jtag_clock),
.reset_n(reset_n),
.din(1'b1),
.dout(jtag_clock_reset_n)
);
altera_jtag_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_streaming (
.tck(jtag_clock),
.reset_n(jtag_clock_reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(jtag_sink_data),
.sink_valid(jtag_sink_valid),
.sink_ready(jtag_sink_ready),
.clock_to_sample(clk),
.reset_to_sample(reset_n),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
altera_avalon_st_clock_crosser #(
.SYMBOLS_PER_BEAT(1),
.BITS_PER_SYMBOL(8),
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) sink_crosser (
.in_clk(clk),
.in_reset(~reset_n),
.in_data(sink_data),
.in_ready(sink_ready),
.in_valid(sink_valid),
.out_clk(jtag_clock),
.out_reset(~jtag_clock_reset_n),
.out_data(jtag_sink_data),
.out_ready(jtag_sink_ready),
.out_valid(jtag_sink_valid)
);
altera_jtag_src_crosser #(
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) source_crosser (
.sink_clk(jtag_clock),
.sink_reset_n(jtag_clock_reset_n),
.sink_valid(jtag_source_valid),
.sink_data(jtag_source_data),
.src_clk(clk),
.src_reset_n(reset_n),
.src_valid(source_valid),
.src_data(source_data)
);
endmodule
|
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_sld_node (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
parameter TCK_FREQ_MHZ = 20;
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
localparam IRWIDTH = 3;
input [IRWIDTH - 1:0] ir_out;
input tdo;
output reg [IRWIDTH - 1:0] ir_in;
output tck;
output reg tdi = 1'b0;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
// PHY Simulation signals
`ifndef ALTERA_RESERVED_QIS
reg simulation_clock;
reg sdrs;
reg cdr;
reg sdr;
reg e1dr;
reg udr;
reg [7:0] bit_index;
`endif
// PHY Instantiation
`ifdef ALTERA_RESERVED_QIS
sld_virtual_jtag_basic sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.tdi (tdi),
.tck (tck),
.ir_in (ir_in),
.virtual_state_cir (virtual_state_cir),
.virtual_state_pdr (virtual_state_pdr),
.virtual_state_uir (virtual_state_uir),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_e1dr (virtual_state_e1dr),
.virtual_state_e2dr (virtual_state_e2dr)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_mfg_id = 110,
sld_virtual_jtag_component.sld_type_id = 132,
sld_virtual_jtag_component.sld_version = 1,
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
sld_virtual_jtag_component.sld_sim_action = "",
sld_virtual_jtag_component.sld_sim_n_scan = 0,
sld_virtual_jtag_component.sld_sim_total_length = 0;
`endif
// PHY Simulation
`ifndef ALTERA_RESERVED_QIS
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
always
//#TCK_HALF_PERIOD_US simulation_clock = $random;
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
assign tck = simulation_clock;
assign virtual_state_cdr = cdr;
assign virtual_state_sdr = sdr;
assign virtual_state_e1dr = e1dr;
assign virtual_state_udr = udr;
task reset_jtag_state;
begin
simulation_clock = 0;
enter_data_mode;
clear_states_async;
end
endtask
task enter_data_mode;
begin
ir_in = DATA;
clear_states;
end
endtask
task enter_loopback_mode;
begin
ir_in = LOOPBACK;
clear_states;
end
endtask
task enter_debug_mode;
begin
ir_in = DEBUG;
clear_states;
end
endtask
task enter_info_mode;
begin
ir_in = INFO;
clear_states;
end
endtask
task enter_control_mode;
begin
ir_in = CONTROL;
clear_states;
end
endtask
task enter_mgmt_mode;
begin
ir_in = MGMT;
clear_states;
end
endtask
task enter_sdrs_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_cdr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_e1dr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_udr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
tdi = 1'b0;
@(posedge tck);
end
endtask
task clear_states;
begin
clear_states_async;
@(posedge tck);
end
endtask
task clear_states_async;
begin
{cdr, sdr, e1dr, udr} = 4'b0000;
end
endtask
task shift_one_bit;
input bit_to_send;
output reg bit_received;
begin
{cdr, sdr, e1dr, udr} = 4'b0100;
tdi = bit_to_send;
@(posedge tck);
bit_received = tdo;
end
endtask
task shift_one_byte;
input [7:0] byte_to_send;
output reg [7:0] byte_received;
integer i;
reg bit_received;
begin
for (i=0; i<8; i=i+1)
begin
bit_index = i;
shift_one_bit(byte_to_send[i], bit_received);
byte_received[i] = bit_received;
end
end
endtask
`endif
endmodule
|
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_streaming (
tck,
reset_n,
// Source Signals
source_data,
source_valid,
// Sink Signals
sink_data,
sink_valid,
sink_ready,
// Clock Debug Signals
clock_to_sample,
reset_to_sample,
// Resetrequest signal
resetrequest,
// Debug reset and management channel
debug_reset,
mgmt_valid,
mgmt_channel,
mgmt_data
);
// function to calculate log2, floored.
function integer flog2;
input [31:0] Depth;
integer i;
begin
i = Depth;
if ( i <= 0 ) flog2 = 0;
else begin
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
i = i >> 1;
end
end
endfunction // flog2
// Used to identify the purpose of this physical endpoint
// This allows the appropriate service to be mounted on top of this node
// Possible Values:
// UNKNOWN 0
// TRANSACTO 1
// CONFIG_ROM 2
// PACKETSTREAM 3
// X8_DEBUGGER 4
parameter PURPOSE = 0;
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
parameter MGMT_CHANNEL_WIDTH = -1;
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
parameter TCK_TO_SYSCLK_SYNC_DEPTH = 8;
parameter SYSCLK_TO_TCK_SYNC_DEPTH = 3;
// IR values determine the operating modes
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
// Operating Modes:
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
// Loopback - To become a JTAG loopback with a bypass register
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
// Control - To set the offset of bit-padding and to do a reset request
// Mgmt - Send management commands (resets mostly) to agents
localparam IRWIDTH = 3;
output tck;
input reset_n;
output [7:0] source_data;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
input clock_to_sample;
input reset_to_sample;
output reg resetrequest = 1'b0;
output wire debug_reset;
output reg mgmt_valid;
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel;
output reg mgmt_data;
// JTAG Signals
wire [IRWIDTH - 1 : 0] ir_out;
wire [IRWIDTH - 1 : 0] ir_in;
reg tdo = 0;
wire tdi;
wire sdr;
wire cdr;
wire udr;
// State machine encoding for write_state
localparam ST_BYPASS = 'h0;
localparam ST_HEADER_1 = 'h1;
localparam ST_HEADER_2 = 'h2;
localparam ST_WRITE_DATA = 'h3;
// State machine encoding for read_state
localparam ST_HEADER = 'h0;
localparam ST_PADDED = 'h1;
localparam ST_READ_DATA = 'h2;
reg [1:0] write_state = ST_BYPASS;
reg [1:0] read_state = ST_HEADER;
reg [ 7:0] dr_data_in = 'b0;
reg [ 7:0] dr_data_out = 'b0;
reg dr_loopback = 'b0;
reg [ 2:0] dr_debug = 'b0;
reg [10:0] dr_info = 'b0;
reg [ 8:0] dr_control = 'b0;
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
reg [ 8:0] padded_bit_counter = 'b0;
reg [ 7:0] bypass_bit_counter = 'b0;
reg [ 2:0] write_data_bit_counter = 'b0;
reg [ 2:0] read_data_bit_counter = 'b0;
reg [ 3:0] header_in_bit_counter = 'b0;
reg [ 3:0] header_out_bit_counter = 'b0;
reg [18:0] scan_length_byte_counter = 'b0;
reg [18:0] valid_write_data_length_byte_counter = 'b0;
reg write_data_valid = 'b0;
reg read_data_valid = 'b0;
reg read_data_all_valid = 'b0;
reg decode_header_1 = 'b0;
reg decode_header_2 = 'b0;
wire write_data_byte_aligned;
wire read_data_byte_aligned;
wire padded_bit_byte_aligned;
wire bytestream_end;
assign write_data_byte_aligned = (write_data_bit_counter == 1);
assign read_data_byte_aligned = (read_data_bit_counter == 1);
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
assign bytestream_end = (scan_length_byte_counter == 'b0);
reg [ 7:0] offset = 'b0;
reg [15:0] header_in = 'b0;
reg [9:0] scan_length = 'b0;
reg [2:0] read_data_length = 'b0;
reg [2:0] write_data_length = 'b0;
wire [7:0] idle_inserter_sink_data;
wire idle_inserter_sink_valid;
wire idle_inserter_sink_ready;
wire [7:0] idle_inserter_source_data;
reg idle_inserter_source_ready = 'b0;
reg [7:0] idle_remover_sink_data = 'b0;
reg idle_remover_sink_valid = 'b0;
wire [7:0] idle_remover_source_data;
wire idle_remover_source_valid;
assign source_data = idle_remover_source_data;
assign source_valid = idle_remover_source_valid;
assign sink_ready = idle_inserter_sink_ready;
assign idle_inserter_sink_data = sink_data;
assign idle_inserter_sink_valid = sink_valid;
reg clock_sensor = 'b0;
reg clock_to_sample_div2 = 'b0;
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
wire data_available;
assign data_available = sink_valid;
wire [18:0] decoded_scan_length;
wire [18:0] decoded_write_data_length;
wire [18:0] decoded_read_data_length;
assign decoded_scan_length = { scan_length, {8{1'b1}} };
// +-------------------+----------------+---------------------+
// | scan_length | Length (bytes) | decoded_scan_length |
// +-------------------+----------------+---------------------+
// | 0x0 | 256 | 0x0ff (255) |
// | 0x1 | 512 | 0x1ff (511) |
// | 0x2 | 768 | 0x2ff (767) |
// | . | . | . |
// | 0x3ff | 256k | 0x3ff (256k-1) |
// +-------------------+----------------+---------------------+
// TODO: use look up table to save LEs?
// Decoded value is correct except for 0x7
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
// +-------------------+---------------+---------------------------+
// | read_data_length | Length | decoded_read_data_length |
// | write_data_length | (bytes) | decoded_write_data_length |
// +-------------------+---------------+---------------------------+
// | 0x0 | 0 | 0x0000 (0) |
// | 0x1 | 256 | 0x0100 (256) |
// | 0x2 | 512 | 0x0200 (512) |
// | 0x3 | 1k | 0x0400 (1024) |
// | 0x4 | 2k | 0x0800 (2048) |
// | 0x5 | 4k | 0x1000 (4096) |
// | 0x6 | 8k | 0x2000 (8192) |
// | 0x7 | scan_length | invalid |
// +-------------------+---------------+---------------------------+
wire clock_sensor_sync;
wire reset_to_sample_sync;
wire clock_to_sample_div2_sync;
wire clock_sense_reset_n_sync;
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_sensor),
.dout(clock_sensor_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(reset_to_sample),
.dout(reset_to_sample_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_to_sample_div2),
.dout(clock_to_sample_div2_sync));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
.clk(clock_to_sample),
.reset_n(clock_sense_reset_n),
.din(1'b1),
.dout(clock_sense_reset_n_sync));
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
if (~clock_sense_reset_n_sync) begin
clock_sensor <= 1'b0;
end else begin
clock_sensor <= 1'b1;
end
end
always @ (posedge clock_to_sample) begin
clock_to_sample_div2 <= ~clock_to_sample_div2;
end
always @ (posedge tck) begin
idle_remover_sink_valid <= 1'b0;
idle_inserter_source_ready <= 1'b0;
// Data mode sourcing (write)
// offset(rounded 8) m-i i 16 offset
// +------------+-----------+------------------+--------+------------+
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
// +------------+-----------+------------------+--------+------------+
// Data mode DR data stream write format (as seen by hardware)
//
if (ir_in == DATA) begin
if (cdr) begin
if (offset == 'b0) begin
write_state <= ST_HEADER_1;
end else begin
write_state <= ST_BYPASS;
end
// 8-bit bypass_bit_counter
bypass_bit_counter <= offset;
// 4-bit header_in_bit_counter
header_in_bit_counter <= 15;
// 3-bit write_data_bit_counter
write_data_bit_counter <= 0;
// Reset the registers
// TODO: not necessarily all, reduce LE
decode_header_1 <= 1'b0;
decode_header_2 <= 1'b0;
read_data_all_valid <= 1'b0;
valid_write_data_length_byte_counter <= 0;
end
if (sdr) begin
// Discard bypass bits, then decode the 16-bit header
// 3 3 10
// +-------------------+------------------+-------------+
// | write_data_length | read_data_length | scan_length |
// +-------------------+------------------+-------------+
// Header format
case (write_state)
ST_BYPASS: begin
// Discard the bypass bit
bypass_bit_counter <= bypass_bit_counter - 1'b1;
if (bypass_bit_counter == 1) begin
write_state <= ST_HEADER_1;
end
end
// Shift the scan_length and read_data_length
ST_HEADER_1: begin
// TODO: header_in can be shorter
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
if (header_in_bit_counter == 3) begin
read_data_length <= {tdi, header_in[15:14]};
scan_length <= header_in[13:4];
write_state <= ST_HEADER_2;
decode_header_1 <= 1'b1;
end
end
// Shift the write_data_length
ST_HEADER_2: begin
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
// Decode read_data_length and scan_length
if (decode_header_1) begin
decode_header_1 <= 1'b0;
// Set read_data_all_valid
if (read_data_length == 3'b111) begin
read_data_all_valid <= 1'b1;
end
// Load scan_length_byte_counter
scan_length_byte_counter <= decoded_scan_length;
end
if (header_in_bit_counter == 0) begin
write_data_length <= {tdi, header_in[15:14]};
write_state <= ST_WRITE_DATA;
decode_header_2 <= 1'b1;
end
end
// Shift the valid_write_data
ST_WRITE_DATA: begin
// Shift into dr_data_in
dr_data_in <= {tdi, dr_data_in[7:1]};
// Decode write_data_length
if (decode_header_2) begin
decode_header_2 <= 1'b0;
// Load valid_write_data_length_byte_counter
case (write_data_length)
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
3'b000: valid_write_data_length_byte_counter <= 'b0;
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
endcase
end
write_data_bit_counter <= write_data_bit_counter - 1'b1;
write_data_valid <= (valid_write_data_length_byte_counter != 0);
// Feed the data to the idle remover
if (write_data_byte_aligned && write_data_valid) begin
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
idle_remover_sink_valid <= 1'b1;
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
end
end
endcase
end
end
// Data mode sinking (read)
// i m-i offset(rounded 8) 16
// +-----------------+-----------+------------+--------+
// | valid_read_data | undefined | padded_bit | header | -> tdo
// +-----------------+-----------+------------+--------+
// Data mode DR data stream read format (as seen by hardware)
//
if (ir_in == DATA) begin
if (cdr) begin
read_state <= ST_HEADER;
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
// 9-bit padded_bit_counter
if (|offset[2:0]) begin
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
padded_bit_counter[2:0] <= 3'b0;
end else begin
padded_bit_counter <= {1'b0, offset};
end
// 4-bit header_out_bit_counter
header_out_bit_counter <= 0;
// 3-bit read_data_bit_counter
read_data_bit_counter <= 0;
// Load the data_available bit into header
dr_data_out <= {{7{1'b0}}, data_available};
read_data_valid <= 0;
end
if (sdr) begin
// 10 1
// +-----------------------------------+----------------+
// | reserved | data_available |
// +-----------------------------------+----------------+
// Header format
dr_data_out <= {1'b0, dr_data_out[7:1]};
case (read_state)
// Shift the scan_length and read_data_length
ST_HEADER: begin
header_out_bit_counter <= header_out_bit_counter - 1'b1;
// Retrieve data from idle inserter for the next shift if no paddded bits
if (header_out_bit_counter == 2) begin
if (padded_bit_counter == 0) begin
idle_inserter_source_ready <= read_data_all_valid;
end
end
if (header_out_bit_counter == 1) begin
if (padded_bit_counter == 0) begin
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end else begin
read_state <= ST_PADDED;
padded_bit_counter <= padded_bit_counter - 1'b1;
idle_inserter_source_ready <= 1'b0;
dr_data_out <= 8'h4a;
end
end
end
ST_PADDED: begin
padded_bit_counter <= padded_bit_counter - 1'b1;
if (padded_bit_byte_aligned) begin
// Load idle character into data register
dr_data_out <= 8'h4a;
end
// Retrieve data from idle inserter for the next shift when padded bits finish
if (padded_bit_counter == 1) begin
idle_inserter_source_ready <= read_data_all_valid;
end
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end
end
ST_READ_DATA: begin
read_data_bit_counter <= read_data_bit_counter - 1'b1;
// Retrieve data from idle inserter just before read_data_byte_aligned
if (read_data_bit_counter == 2) begin
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
end
if (read_data_byte_aligned) begin
// Note that bytestream_end is driven by scan_length_byte_counter
if (~bytestream_end) begin
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
end
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
// Load idle character if bytestream has ended, else get data from the idle inserter
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
end
end
endcase
end
end
// Loopback mode
if (ir_in == LOOPBACK) begin
if (cdr) begin
dr_loopback <= 1'b0; // capture 0
end
if (sdr) begin
// Shift dr_loopback
dr_loopback <= tdi;
end
end
// Debug mode
if (ir_in == DEBUG) begin
if (cdr) begin
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
end
if (sdr) begin
// Shift dr_debug
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
end
if (udr) begin
clock_sense_reset_n <= 1'b0;
end else begin
clock_sense_reset_n <= 1'b1;
end
end
// Info mode
if (ir_in == INFO) begin
if (cdr) begin
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
end
if (sdr) begin
// Shift dr_info
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
end
end
// Control mode
if (ir_in == CONTROL) begin
if (cdr) begin
dr_control <= 'b0; // capture 0
end
if (sdr) begin
// Shift dr_control
dr_control <= {tdi, dr_control[8:1]};
end
if (udr) begin
// Update resetrequest and offset
{resetrequest, offset} <= dr_control;
end
end
end
always @ * begin
if (sdr) begin
case (ir_in)
DATA: tdo <= dr_data_out[0];
LOOPBACK: tdo <= dr_loopback;
DEBUG: tdo <= dr_debug[0];
INFO: tdo <= dr_info[0];
CONTROL: tdo <= dr_control[0];
MGMT: tdo <= dr_mgmt[0];
default: tdo <= 1'b0;
endcase
end else begin
tdo <= 1'b0;
end
end
// SLD node instantiation
altera_jtag_sld_node node (
.ir_out (ir_out),
.tdo (tdo),
.ir_in (ir_in),
.tck (tck),
.tdi (tdi),
.virtual_state_cdr (cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (sdr),
.virtual_state_udr (udr),
.virtual_state_uir ()
);
// Idle Remover
altera_avalon_st_idle_remover idle_remover (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (), // left disconnected
.in_valid (idle_remover_sink_valid),
.in_data (idle_remover_sink_data),
// Interface: ST out
.out_ready (1'b1), // downstream is expected to be always ready
.out_valid (idle_remover_source_valid),
.out_data (idle_remover_source_data)
);
// Idle Inserter
altera_avalon_st_idle_inserter idle_inserter (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (idle_inserter_sink_ready),
.in_valid (idle_inserter_sink_valid),
.in_data (idle_inserter_sink_data),
// Interface: ST out
.out_ready (idle_inserter_source_ready),
.out_valid (),
.out_data (idle_inserter_source_data)
);
generate
if (MGMT_CHANNEL_WIDTH > 0)
begin : has_mgmt
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
reg mgmt_toggle = 1'b0;
wire mgmt_toggle_sync;
reg mgmt_toggle_prev;
always @ (posedge tck) begin
// Debug mode
if (ir_in == MGMT) begin
if (cdr) begin
dr_mgmt <= 'b0;
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
end
if (sdr) begin
// Shift dr_debug
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
end
if (udr) begin
mgmt_out <= dr_mgmt;
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
end
end
end
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
.dout(debug_reset));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_toggle_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_toggle),
.dout(mgmt_toggle_sync));
always @ (posedge clock_to_sample or posedge debug_reset) begin
if (debug_reset) begin
mgmt_valid <= 1'b0;
mgmt_toggle_prev <= 1'b0;
end else begin
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out[MGMT_CHANNEL_WIDTH+1]) begin
mgmt_valid <= 1'b1;
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
mgmt_data <= mgmt_out[0];
end else begin
mgmt_valid <= 1'b0;
end
mgmt_toggle_prev <= mgmt_toggle_sync;
end
end
end
else
begin : no_mgmt
always @ (posedge tck) begin
dr_mgmt[0] <= 1'b0;
end
assign debug_reset = 1'b0;
always @ (posedge clock_to_sample) begin
mgmt_valid <= 1'b0;
mgmt_data <= 'b0;
mgmt_channel <= 'b0;
end
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
no_ci_readra
)
;
output [ 19: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 16: 0] i_address;
output i_read;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 14: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 19: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 14: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 14: 0] F_pc_no_crst_nxt;
wire [ 14: 0] F_pc_nxt;
wire [ 14: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 16: 0] F_pcb;
wire [ 16: 0] F_pcb_nxt;
wire [ 16: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 19: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 19: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
wire hbreak_req;
wire [ 16: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire no_ci_readra;
wire [ 31: 0] oci_ienable;
wire test_has_ended;
//the_altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench, which is an e_instance
altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench the_altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_alu_result (E_alu_result),
.E_mem_byte_en (E_mem_byte_en),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_exception (R_ctrl_exception),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_bstatus_reg (W_bstatus_reg),
.W_cmp_result (W_cmp_result),
.W_estatus_reg (W_estatus_reg),
.W_ienable_reg (W_ienable_reg),
.W_ipending_reg (W_ipending_reg),
.W_mem_baddr (W_mem_baddr),
.W_rf_wr_data (W_rf_wr_data),
.W_status_reg (W_status_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000000;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 16392 :
(F_pc_sel_nxt == 2'b01)? 16392 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[16 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 16384;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign hbreak_req = 1'b0;
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a, which is an nios_sdp_ram
altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a_module altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_rf_ram_a.dat";
`else
defparam altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b, which is an nios_sdp_ram
altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b_module altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_rf_ram_b.dat";
`else
defparam altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[19 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[19 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000000;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000000;
assign oci_ienable = {32{1'b1}};
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_alu_result,
E_mem_byte_en,
E_st_data,
E_valid,
F_pcb,
F_valid,
R_ctrl_exception,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_bstatus_reg,
W_cmp_result,
W_estatus_reg,
W_ienable_reg,
W_ipending_reg,
W_mem_baddr,
W_rf_wr_data,
W_status_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write_nxt,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
d_write,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output d_write;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input [ 31: 0] E_alu_result;
input [ 3: 0] E_mem_byte_en;
input [ 31: 0] E_st_data;
input E_valid;
input [ 16: 0] F_pcb;
input F_valid;
input R_ctrl_exception;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_bstatus_reg;
input W_cmp_result;
input W_estatus_reg;
input [ 31: 0] W_ienable_reg;
input [ 31: 0] W_ipending_reg;
input [ 19: 0] W_mem_baddr;
input [ 31: 0] W_rf_wr_data;
input W_status_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 19: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write_nxt;
input [ 16: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
reg d_write;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (W_valid)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
// -----------------------------------------------------------
// PLI byte transport HDL interface
//
// @author jyeap, gkwan
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [7 : 0] source_data;
input source_ready;
input sink_valid;
input [7 : 0] sink_data;
output reg sink_ready;
output reg resetrequest;
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(.PURPOSE(PURPOSE)) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)
);
always @* begin
source_valid = jtag_source_valid;
source_data = jtag_source_data;
sink_ready = jtag_sink_ready;
resetrequest = jtag_resetrequest;
//synthesis translate_off
source_valid = pli_out_valid;
source_data = pli_out_data;
sink_ready = pli_in_ready;
resetrequest = 0;
//synthesis translate_on
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input clk,
output reset_out
);
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
wire merged_reset;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin
assign reset_out = merged_reset;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out)
);
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
// megafunction wizard: %ALT2GXB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt2gxb
// ============================================================
// File Name: altera_tse_alt2gxb_basic.v
// Megafunction Name(s):
// alt2gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Internal Build 78 11/25/2008 PN Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// related_files : altera_tse_alt2gxb_basic.v
// ipfs_files : altera_tse_alt2gxb_basic.vo
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_alt2gxb_basic (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_datain,
tx_digitalreset,
rx_clkout,
rx_dataout,
rx_patterndetect,
tx_clkout,
tx_dataout);
input cal_blk_clk;
input [0:0] gxb_powerdown;
input pll_inclk;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [9:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] rx_clkout;
output [9:0] rx_dataout;
output [0:0] rx_patterndetect;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [9:0] sub_wire4;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] rx_clkout = sub_wire1[0:0];
wire [0:0] tx_dataout = sub_wire2[0:0];
wire [0:0] tx_clkout = sub_wire3[0:0];
wire [9:0] rx_dataout = sub_wire4[9:0];
alt2gxb alt2gxb_component (
.pll_inclk (pll_inclk),
.gxb_powerdown (gxb_powerdown),
.tx_datain (tx_datain),
.rx_revbitorderwa (sub_wire5),
.rx_cruclk (rx_cruclk),
.cal_blk_clk (cal_blk_clk),
.rx_seriallpbken (rx_seriallpbken),
.rx_datain (rx_datain),
.rx_analogreset (rx_analogreset),
.rx_digitalreset (rx_digitalreset),
.tx_digitalreset (tx_digitalreset),
.rx_patterndetect (sub_wire0),
.rx_clkout (sub_wire1),
.tx_dataout (sub_wire2),
.tx_clkout (sub_wire3),
.rx_dataout (sub_wire4)
// synopsys translate_off
,
.aeq_fromgxb (),
.aeq_togxb (),
.cal_blk_calibrationstatus (),
.cal_blk_powerdown (),
.coreclkout (),
.debug_rx_phase_comp_fifo_error (),
.debug_tx_phase_comp_fifo_error (),
.fixedclk (),
.gxb_enable (),
.pipe8b10binvpolarity (),
.pipedatavalid (),
.pipeelecidle (),
.pipephydonestatus (),
.pipestatus (),
.pll_inclk_alt (),
.pll_inclk_rx_cruclk (),
.pll_locked (),
.pll_locked_alt (),
.powerdn (),
.reconfig_clk (),
.reconfig_fromgxb (),
.reconfig_fromgxb_oe (),
.reconfig_togxb (),
.rx_a1a2size (),
.rx_a1a2sizeout (),
.rx_a1detect (),
.rx_a2detect (),
.rx_bistdone (),
.rx_bisterr (),
.rx_bitslip (),
.rx_byteorderalignstatus (),
.rx_channelaligned (),
.rx_coreclk (),
.rx_cruclk_alt (),
.rx_ctrldetect (),
.rx_dataoutfull (),
.rx_disperr (),
.rx_enabyteord (),
.rx_enapatternalign (),
.rx_errdetect (),
.rx_freqlocked (),
.rx_invpolarity (),
.rx_k1detect (),
.rx_k2detect (),
.rx_locktodata (),
.rx_locktorefclk (),
.rx_phfifooverflow (),
.rx_phfifordenable (),
.rx_phfiforeset (),
.rx_phfifounderflow (),
.rx_phfifowrdisable (),
.rx_pll_locked (),
.rx_powerdown (),
.rx_recovclkout (),
.rx_revbyteorderwa (),
.rx_rlv (),
.rx_rmfifoalmostempty (),
.rx_rmfifoalmostfull (),
.rx_rmfifodatadeleted (),
.rx_rmfifodatainserted (),
.rx_rmfifoempty (),
.rx_rmfifofull (),
.rx_rmfifordena (),
.rx_rmfiforeset (),
.rx_rmfifowrena (),
.rx_runningdisp (),
.rx_signaldetect (),
.rx_syncstatus (),
.tx_coreclk (),
.tx_ctrlenable (),
.tx_datainfull (),
.tx_detectrxloop (),
.tx_dispval (),
.tx_forcedisp (),
.tx_forcedispcompliance (),
.tx_forceelecidle (),
.tx_invpolarity (),
.tx_phfifooverflow (),
.tx_phfiforeset (),
.tx_phfifounderflow (),
.tx_revparallellpbken ()
// synopsys translate_on
);
defparam
alt2gxb_component.cmu_pll_inclock_period = 8000,
alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
alt2gxb_component.digitalreset_port_width = 1,
alt2gxb_component.en_local_clk_div_ctrl = "true",
alt2gxb_component.equalizer_ctrl_a_setting = 0,
alt2gxb_component.equalizer_ctrl_b_setting = 0,
alt2gxb_component.equalizer_ctrl_c_setting = 0,
alt2gxb_component.equalizer_ctrl_d_setting = 0,
alt2gxb_component.equalizer_ctrl_v_setting = 0,
alt2gxb_component.equalizer_dcgain_setting = 0,
alt2gxb_component.intended_device_family = "Stratix II GX",
alt2gxb_component.loopback_mode = "slb",
alt2gxb_component.lpm_type = "alt2gxb",
alt2gxb_component.number_of_channels = 1,
alt2gxb_component.operation_mode = "duplex",
alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
alt2gxb_component.protocol = "3g_basic",
alt2gxb_component.receiver_termination = "oct_100_ohms",
alt2gxb_component.reconfig_dprio_mode = 0,
alt2gxb_component.reverse_loopback_mode = "none",
alt2gxb_component.rx_8b_10b_compatibility_mode = "false",
alt2gxb_component.rx_8b_10b_mode = "none",
alt2gxb_component.rx_align_loss_sync_error_num = 1,
alt2gxb_component.rx_align_pattern = "0101111100",
alt2gxb_component.rx_align_pattern_length = 10,
alt2gxb_component.rx_allow_align_polarity_inversion = "false",
alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
alt2gxb_component.rx_bandwidth_mode = 1,
alt2gxb_component.rx_bitslip_enable = "false",
alt2gxb_component.rx_byte_ordering_mode = "none",
alt2gxb_component.rx_channel_width = 10,
alt2gxb_component.rx_common_mode = "0.9v",
alt2gxb_component.rx_cru_inclock_period = 8000,
alt2gxb_component.rx_cru_pre_divide_by = 1,
alt2gxb_component.rx_datapath_protocol = "basic",
alt2gxb_component.rx_data_rate = 1250,
alt2gxb_component.rx_data_rate_remainder = 0,
alt2gxb_component.rx_disable_auto_idle_insertion = "true",
alt2gxb_component.rx_enable_bit_reversal = "false",
alt2gxb_component.rx_enable_deep_align_byte_swap = "false",
alt2gxb_component.rx_enable_lock_to_data_sig = "false",
alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
alt2gxb_component.rx_enable_self_test_mode = "false",
alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
alt2gxb_component.rx_flip_rx_out = "false",
alt2gxb_component.rx_force_signal_detect = "true",
alt2gxb_component.rx_num_align_cons_good_data = 1,
alt2gxb_component.rx_num_align_cons_pat = 1,
alt2gxb_component.rx_ppmselect = 32,
alt2gxb_component.rx_rate_match_fifo_mode = "none",
alt2gxb_component.rx_run_length_enable = "false",
alt2gxb_component.rx_signal_detect_threshold = 2,
alt2gxb_component.rx_use_align_state_machine = "true",
alt2gxb_component.rx_use_clkout = "true",
alt2gxb_component.rx_use_coreclk = "false",
alt2gxb_component.rx_use_cruclk = "true",
alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
alt2gxb_component.rx_use_deskew_fifo = "false",
alt2gxb_component.rx_use_double_data_mode = "false",
alt2gxb_component.transmitter_termination = "oct_100_ohms",
alt2gxb_component.tx_8b_10b_compatibility_mode = "false",
alt2gxb_component.tx_8b_10b_mode = "none",
alt2gxb_component.tx_allow_polarity_inversion = "false",
alt2gxb_component.tx_analog_power = "1.5v",
alt2gxb_component.tx_channel_width = 10,
alt2gxb_component.tx_common_mode = "0.6v",
alt2gxb_component.tx_data_rate = 1250,
alt2gxb_component.tx_data_rate_remainder = 0,
alt2gxb_component.tx_enable_bit_reversal = "false",
alt2gxb_component.tx_enable_idle_selection = "false",
alt2gxb_component.tx_enable_self_test_mode = "false",
alt2gxb_component.tx_flip_tx_in = "false",
alt2gxb_component.tx_force_disparity_mode = "false",
alt2gxb_component.tx_refclk_divide_by = 1,
alt2gxb_component.tx_transmit_protocol = "basic",
alt2gxb_component.tx_use_coreclk = "false",
alt2gxb_component.tx_use_double_data_mode = "false",
alt2gxb_component.tx_use_serializer_double_data_mode = "false",
alt2gxb_component.use_calibration_block = "true",
alt2gxb_component.vod_ctrl_setting = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "71"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.00"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "312.500000 250.000000 156.250000 125.000000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "312.500000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 78.125 125.0 156.25 250.0 312.5"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.00"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Serial Loopback"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_LEGAL_MULTIPLIER_LIST STRING "disable_4_5_mult_above_3125"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "3g_basic"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "false"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "none"
// Retrieval info: CONSTANT: RX_ALIGN_LOSS_SYNC_ERROR_NUM NUMERIC "1"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "true"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_DEEP_ALIGN_BYTE_SWAP STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
// Retrieval info: CONSTANT: RX_FLIP_RX_OUT STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_NUM_ALIGN_CONS_GOOD_DATA NUMERIC "1"
// Retrieval info: CONSTANT: RX_NUM_ALIGN_CONS_PAT NUMERIC "1"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "none"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "false"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "none"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "10"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_FLIP_TX_IN STRING "false"
// Retrieval info: CONSTANT: TX_FORCE_DISPARITY_MODE STRING "false"
// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 1 0 OUTPUT NODEFVAL "rx_clkout[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 10 0 OUTPUT NODEFVAL "rx_dataout[9..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 10 0 INPUT NODEFVAL "tx_datain[9..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 10 0 @rx_dataout 0 0 10 0
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_revbitorderwa 0 0 1 0 GND 0 0 1 0
// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
// Retrieval info: CONNECT: rx_clkout 0 0 1 0 @rx_clkout 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 10 0 tx_datain 0 0 10 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.vo TRUE FALSE
|
// megafunction wizard: %ALT2GXB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt2gxb
// ============================================================
// File Name: altera_tse_alt2gxb_gige.v
// Megafunction Name(s):
// alt2gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Internal Build 138 03/15/2011 PN Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_alt2gxb_gige (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout);
input cal_blk_clk;
input [0:0] gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [2:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [0:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
// Please this parameter and the section that use it when this module is regenerated
parameter ENABLE_ALT_RECONFIG = 1;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [0:0] reconfig_fromgxb = sub_wire2[0:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
alt2gxb alt2gxb_component (
.pll_inclk (pll_inclk),
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.rx_seriallpbken (rx_seriallpbken),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.tx_ctrlenable (tx_ctrlenable),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16)
// synopsys translate_off
,
.aeq_fromgxb (),
.aeq_togxb (),
.cal_blk_calibrationstatus (),
.cal_blk_powerdown (),
.coreclkout (),
.debug_rx_phase_comp_fifo_error (),
.debug_tx_phase_comp_fifo_error (),
.fixedclk (),
.gxb_enable (),
.pipe8b10binvpolarity (),
.pipedatavalid (),
.pipeelecidle (),
.pipephydonestatus (),
.pipestatus (),
.pll_inclk_alt (),
.pll_inclk_rx_cruclk (),
.pll_locked_alt (),
.powerdn (),
.reconfig_fromgxb_oe (),
.rx_a1a2size (),
.rx_a1a2sizeout (),
.rx_a1detect (),
.rx_a2detect (),
.rx_bistdone (),
.rx_bisterr (),
.rx_bitslip (),
.rx_byteorderalignstatus (),
.rx_channelaligned (),
.rx_coreclk (),
.rx_cruclk_alt (),
.rx_dataoutfull (),
.rx_enabyteord (),
.rx_enapatternalign (),
.rx_invpolarity (),
.rx_k1detect (),
.rx_k2detect (),
.rx_locktodata (),
.rx_locktorefclk (),
.rx_phfifooverflow (),
.rx_phfifordenable (),
.rx_phfiforeset (),
.rx_phfifounderflow (),
.rx_phfifowrdisable (),
.rx_pll_locked (),
.rx_powerdown (),
.rx_revbitorderwa (),
.rx_revbyteorderwa (),
.rx_rmfifoalmostempty (),
.rx_rmfifoalmostfull (),
.rx_rmfifoempty (),
.rx_rmfifofull (),
.rx_rmfifordena (),
.rx_rmfiforeset (),
.rx_rmfifowrena (),
.rx_signaldetect (),
.tx_coreclk (),
.tx_datainfull (),
.tx_detectrxloop (),
.tx_dispval (),
.tx_forcedisp (),
.tx_forcedispcompliance (),
.tx_forceelecidle (),
.tx_invpolarity (),
.tx_phfifooverflow (),
.tx_phfiforeset (),
.tx_phfifounderflow (),
.tx_revparallellpbken ()
// synopsys translate_on
);
defparam
alt2gxb_component.starting_channel_number = starting_channel_number,
alt2gxb_component.cmu_pll_inclock_period = 8000,
alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
alt2gxb_component.digitalreset_port_width = 1,
alt2gxb_component.en_local_clk_div_ctrl = "true",
alt2gxb_component.equalizer_ctrl_a_setting = 0,
alt2gxb_component.equalizer_ctrl_b_setting = 0,
alt2gxb_component.equalizer_ctrl_c_setting = 0,
alt2gxb_component.equalizer_ctrl_d_setting = 0,
alt2gxb_component.equalizer_ctrl_v_setting = 0,
alt2gxb_component.equalizer_dcgain_setting = 0,
alt2gxb_component.gen_reconfig_pll = "false",
alt2gxb_component.intended_device_family = "Stratix II GX",
alt2gxb_component.loopback_mode = "slb",
alt2gxb_component.lpm_type = "alt2gxb",
alt2gxb_component.number_of_channels = 1,
alt2gxb_component.operation_mode = "duplex",
alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
alt2gxb_component.protocol = "gige",
alt2gxb_component.receiver_termination = "oct_100_ohms",
alt2gxb_component.reconfig_dprio_mode = ENABLE_ALT_RECONFIG,
alt2gxb_component.reverse_loopback_mode = "none",
alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
alt2gxb_component.rx_8b_10b_mode = "normal",
alt2gxb_component.rx_align_pattern = "0101111100",
alt2gxb_component.rx_align_pattern_length = 10,
alt2gxb_component.rx_allow_align_polarity_inversion = "false",
alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
alt2gxb_component.rx_bandwidth_mode = 1,
alt2gxb_component.rx_bitslip_enable = "false",
alt2gxb_component.rx_byte_ordering_mode = "none",
alt2gxb_component.rx_channel_width = 8,
alt2gxb_component.rx_common_mode = "0.9v",
alt2gxb_component.rx_cru_inclock_period = 8000,
alt2gxb_component.rx_cru_pre_divide_by = 1,
alt2gxb_component.rx_datapath_protocol = "basic",
alt2gxb_component.rx_data_rate = 1250,
alt2gxb_component.rx_data_rate_remainder = 0,
alt2gxb_component.rx_disable_auto_idle_insertion = "true",
alt2gxb_component.rx_enable_bit_reversal = "false",
alt2gxb_component.rx_enable_lock_to_data_sig = "false",
alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
alt2gxb_component.rx_enable_self_test_mode = "false",
alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
alt2gxb_component.rx_force_signal_detect = "true",
alt2gxb_component.rx_ppmselect = 32,
alt2gxb_component.rx_rate_match_back_to_back = "true",
alt2gxb_component.rx_rate_match_fifo_mode = "normal",
alt2gxb_component.rx_rate_match_fifo_mode_manual_control = "normal",
alt2gxb_component.rx_rate_match_ordered_set_based = "true",
alt2gxb_component.rx_rate_match_pattern1 = "10100010010101111100",
alt2gxb_component.rx_rate_match_pattern2 = "10101011011010000011",
alt2gxb_component.rx_rate_match_pattern_size = 20,
alt2gxb_component.rx_rate_match_skip_set_based = "true",
alt2gxb_component.rx_run_length = 5,
alt2gxb_component.rx_run_length_enable = "true",
alt2gxb_component.rx_signal_detect_threshold = 2,
alt2gxb_component.rx_use_align_state_machine = "true",
alt2gxb_component.rx_use_clkout = "true",
alt2gxb_component.rx_use_coreclk = "false",
alt2gxb_component.rx_use_cruclk = "true",
alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
alt2gxb_component.rx_use_deskew_fifo = "false",
alt2gxb_component.rx_use_double_data_mode = "false",
alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
alt2gxb_component.transmitter_termination = "oct_100_ohms",
alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
alt2gxb_component.tx_8b_10b_mode = "normal",
alt2gxb_component.tx_allow_polarity_inversion = "false",
alt2gxb_component.tx_analog_power = "1.5v",
alt2gxb_component.tx_channel_width = 8,
alt2gxb_component.tx_common_mode = "0.6v",
alt2gxb_component.tx_data_rate = 1250,
alt2gxb_component.tx_data_rate_remainder = 0,
alt2gxb_component.tx_enable_bit_reversal = "false",
alt2gxb_component.tx_enable_idle_selection = "true",
alt2gxb_component.tx_enable_self_test_mode = "false",
alt2gxb_component.tx_refclk_divide_by = 1,
alt2gxb_component.tx_transmit_protocol = "basic",
alt2gxb_component.tx_use_coreclk = "false",
alt2gxb_component.tx_use_double_data_mode = "false",
alt2gxb_component.tx_use_serializer_double_data_mode = "false",
alt2gxb_component.use_calibration_block = "true",
alt2gxb_component.vod_ctrl_setting = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "74"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "50.0 62.5 78.125 100.0 125.0 156.25 250.0 312.5 500.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "50.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "GIGE-Enhanced"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_LEGAL_MULTIPLIER_LIST STRING "disable_4_5_mult_above_3125"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "true"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "true"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_BACK_TO_BACK STRING "true"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_ORDERED_SET_BASED STRING "true"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RATE_MATCH_SKIP_SET_BASED STRING "true"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "true"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "true"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_bb.v FALSE
|
// megafunction wizard: %ALT2GXB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt2gxb
// ============================================================
// File Name: altera_tse_alt2gxb_gige_wo_rmfifo.v
// Megafunction Name(s):
// alt2gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Internal Build 138 03/15/2011 PN Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_alt2gxb_gige_wo_rmfifo (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout);
input cal_blk_clk;
input [0:0] gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [2:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [0:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
// Please this parameter and the section that use it when this module is regenerated
parameter ENABLE_ALT_RECONFIG = 1;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [0:0] reconfig_fromgxb = sub_wire2[0:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
alt2gxb alt2gxb_component (
.pll_inclk (pll_inclk),
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.rx_seriallpbken (rx_seriallpbken),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.tx_ctrlenable (tx_ctrlenable),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16)
// synopsys translate_off
,
.aeq_fromgxb (),
.aeq_togxb (),
.cal_blk_calibrationstatus (),
.cal_blk_powerdown (),
.coreclkout (),
.debug_rx_phase_comp_fifo_error (),
.debug_tx_phase_comp_fifo_error (),
.fixedclk (),
.gxb_enable (),
.pipe8b10binvpolarity (),
.pipedatavalid (),
.pipeelecidle (),
.pipephydonestatus (),
.pipestatus (),
.pll_inclk_alt (),
.pll_inclk_rx_cruclk (),
.pll_locked_alt (),
.powerdn (),
.reconfig_fromgxb_oe (),
.rx_a1a2size (),
.rx_a1a2sizeout (),
.rx_a1detect (),
.rx_a2detect (),
.rx_bistdone (),
.rx_bisterr (),
.rx_bitslip (),
.rx_byteorderalignstatus (),
.rx_channelaligned (),
.rx_coreclk (),
.rx_cruclk_alt (),
.rx_dataoutfull (),
.rx_enabyteord (),
.rx_enapatternalign (),
.rx_invpolarity (),
.rx_k1detect (),
.rx_k2detect (),
.rx_locktodata (),
.rx_locktorefclk (),
.rx_phfifooverflow (),
.rx_phfifordenable (),
.rx_phfiforeset (),
.rx_phfifounderflow (),
.rx_phfifowrdisable (),
.rx_pll_locked (),
.rx_powerdown (),
.rx_revbitorderwa (),
.rx_revbyteorderwa (),
.rx_rmfifoalmostempty (),
.rx_rmfifoalmostfull (),
.rx_rmfifoempty (),
.rx_rmfifofull (),
.rx_rmfifordena (),
.rx_rmfiforeset (),
.rx_rmfifowrena (),
.rx_signaldetect (),
.tx_coreclk (),
.tx_datainfull (),
.tx_detectrxloop (),
.tx_dispval (),
.tx_forcedisp (),
.tx_forcedispcompliance (),
.tx_forceelecidle (),
.tx_invpolarity (),
.tx_phfifooverflow (),
.tx_phfiforeset (),
.tx_phfifounderflow (),
.tx_revparallellpbken ()
// synopsys translate_on
);
defparam
alt2gxb_component.starting_channel_number = starting_channel_number,
alt2gxb_component.cmu_pll_inclock_period = 8000,
alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
alt2gxb_component.digitalreset_port_width = 1,
alt2gxb_component.en_local_clk_div_ctrl = "true",
alt2gxb_component.equalizer_ctrl_a_setting = 0,
alt2gxb_component.equalizer_ctrl_b_setting = 0,
alt2gxb_component.equalizer_ctrl_c_setting = 0,
alt2gxb_component.equalizer_ctrl_d_setting = 0,
alt2gxb_component.equalizer_ctrl_v_setting = 0,
alt2gxb_component.equalizer_dcgain_setting = 0,
alt2gxb_component.gen_reconfig_pll = "false",
alt2gxb_component.intended_device_family = "Stratix II GX",
alt2gxb_component.loopback_mode = "slb",
alt2gxb_component.lpm_type = "alt2gxb",
alt2gxb_component.number_of_channels = 1,
alt2gxb_component.operation_mode = "duplex",
alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
alt2gxb_component.protocol = "gige",
alt2gxb_component.receiver_termination = "oct_100_ohms",
alt2gxb_component.reconfig_dprio_mode = ENABLE_ALT_RECONFIG,
alt2gxb_component.reverse_loopback_mode = "none",
alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
alt2gxb_component.rx_8b_10b_mode = "normal",
alt2gxb_component.rx_align_pattern = "0101111100",
alt2gxb_component.rx_align_pattern_length = 10,
alt2gxb_component.rx_allow_align_polarity_inversion = "false",
alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
alt2gxb_component.rx_bandwidth_mode = 1,
alt2gxb_component.rx_bitslip_enable = "false",
alt2gxb_component.rx_byte_ordering_mode = "none",
alt2gxb_component.rx_channel_width = 8,
alt2gxb_component.rx_common_mode = "0.9v",
alt2gxb_component.rx_cru_inclock_period = 8000,
alt2gxb_component.rx_cru_pre_divide_by = 1,
alt2gxb_component.rx_datapath_protocol = "basic",
alt2gxb_component.rx_data_rate = 1250,
alt2gxb_component.rx_data_rate_remainder = 0,
alt2gxb_component.rx_disable_auto_idle_insertion = "true",
alt2gxb_component.rx_enable_bit_reversal = "false",
alt2gxb_component.rx_enable_lock_to_data_sig = "false",
alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
alt2gxb_component.rx_enable_self_test_mode = "false",
alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
alt2gxb_component.rx_force_signal_detect = "true",
alt2gxb_component.rx_ppmselect = 32,
alt2gxb_component.rx_rate_match_back_to_back = "true",
alt2gxb_component.rx_rate_match_fifo_mode = "normal",
alt2gxb_component.rx_rate_match_fifo_mode_manual_control = "none",
alt2gxb_component.rx_rate_match_ordered_set_based = "true",
alt2gxb_component.rx_rate_match_pattern1 = "10100010010101111100",
alt2gxb_component.rx_rate_match_pattern2 = "10101011011010000011",
alt2gxb_component.rx_rate_match_pattern_size = 20,
alt2gxb_component.rx_rate_match_skip_set_based = "true",
alt2gxb_component.rx_run_length = 5,
alt2gxb_component.rx_run_length_enable = "true",
alt2gxb_component.rx_signal_detect_threshold = 2,
alt2gxb_component.rx_use_align_state_machine = "true",
alt2gxb_component.rx_use_clkout = "true",
alt2gxb_component.rx_use_coreclk = "false",
alt2gxb_component.rx_use_cruclk = "true",
alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
alt2gxb_component.rx_use_deskew_fifo = "false",
alt2gxb_component.rx_use_double_data_mode = "false",
alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
alt2gxb_component.transmitter_termination = "oct_100_ohms",
alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
alt2gxb_component.tx_8b_10b_mode = "normal",
alt2gxb_component.tx_allow_polarity_inversion = "false",
alt2gxb_component.tx_analog_power = "1.5v",
alt2gxb_component.tx_channel_width = 8,
alt2gxb_component.tx_common_mode = "0.6v",
alt2gxb_component.tx_data_rate = 1250,
alt2gxb_component.tx_data_rate_remainder = 0,
alt2gxb_component.tx_enable_bit_reversal = "false",
alt2gxb_component.tx_enable_idle_selection = "true",
alt2gxb_component.tx_enable_self_test_mode = "false",
alt2gxb_component.tx_refclk_divide_by = 1,
alt2gxb_component.tx_transmit_protocol = "basic",
alt2gxb_component.tx_use_coreclk = "false",
alt2gxb_component.tx_use_double_data_mode = "false",
alt2gxb_component.tx_use_serializer_double_data_mode = "false",
alt2gxb_component.use_calibration_block = "true",
alt2gxb_component.vod_ctrl_setting = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "74"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "50.0 62.5 78.125 100.0 125.0 156.25 250.0 312.5 500.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "50.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "GIGE-Enhanced"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_LEGAL_MULTIPLIER_LIST STRING "disable_4_5_mult_above_3125"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "true"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "true"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_BACK_TO_BACK STRING "true"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "none"
// Retrieval info: CONSTANT: RX_RATE_MATCH_ORDERED_SET_BASED STRING "true"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RATE_MATCH_SKIP_SET_BASED STRING "true"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "true"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "true"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo_bb.v FALSE
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: altera_tse_alt4gxb_gige.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
// stratixiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Internal Build 147 03/05/2012 PN Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" effective_data_rate="1250.0 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="1111100" rx_align_pattern_length=7 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_seriallpbken rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset
//VERSION_BEGIN 12.0 cbx_alt4gxb 2012:03:05:21:09:17:PN cbx_mgl 2012:03:05:22:13:55:PN cbx_tgx 2012:03:05:21:09:17:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 8 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=c104"} *)
module altera_tse_alt4gxb_gige_alt4gxb_lnca
(
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_inclk,
pll_locked,
pll_powerdown,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_clkout,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_seriallpbken,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_digitalreset) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input pll_inclk;
output [0:0] pll_locked;
input [0:0] pll_powerdown;
input reconfig_clk;
output [16:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
output [0:0] rx_clkout;
input [0:0] rx_cruclk;
output [0:0] rx_ctrldetect;
input [0:0] rx_datain;
output [7:0] rx_dataout;
input [0:0] rx_digitalreset;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
input [0:0] rx_seriallpbken;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
output [0:0] tx_dataout;
input [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri1 [5:0] fixedclk_fast;
tri0 [0:0] gxb_powerdown;
tri0 pll_inclk;
tri0 [0:0] pll_powerdown;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_cruclk;
tri0 [0:0] rx_digitalreset;
tri0 [0:0] rx_seriallpbken;
tri0 [0:0] tx_ctrlenable;
tri0 [7:0] tx_datain;
tri0 [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
reg fixedclk_div0quad0c;
wire wire_fixedclk_div0quad0c_clk;
reg fixedclk_div1quad0c;
wire wire_fixedclk_div1quad0c_clk;
reg fixedclk_div2quad0c;
wire wire_fixedclk_div2quad0c_clk;
reg fixedclk_div3quad0c;
wire wire_fixedclk_div3quad0c_clk;
reg fixedclk_div4quad0c;
wire wire_fixedclk_div4quad0c_clk;
reg fixedclk_div5quad0c;
wire wire_fixedclk_div5quad0c_clk;
reg [1:0] reconfig_togxb_busy_reg;
wire wire_cal_blk0_nonusertocmu;
wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
wire [1:0] wire_ch_clk_div0_analogrefclkout;
wire wire_ch_clk_div0_analogrefclkpulse;
wire [99:0] wire_ch_clk_div0_dprioout;
wire [599:0] wire_cent_unit0_cmudividerdprioout;
wire [1799:0] wire_cent_unit0_cmuplldprioout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire [1799:0] wire_cent_unit0_rxpmadprioout;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire [1799:0] wire_cent_unit0_txpmadprioout;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire [299:0] wire_rx_cdr_pll0_dprioout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire [299:0] wire_tx_pll0_dprioout;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_clkout;
wire [3:0] wire_receive_pcs0_ctrldetect;
wire [39:0] wire_receive_pcs0_dataout;
wire [3:0] wire_receive_pcs0_disperr;
wire [399:0] wire_receive_pcs0_dprioout;
wire [3:0] wire_receive_pcs0_errdetect;
wire [3:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_rlv;
wire [3:0] wire_receive_pcs0_rmfifodatadeleted;
wire [3:0] wire_receive_pcs0_rmfifodatainserted;
wire [3:0] wire_receive_pcs0_runningdisp;
wire [3:0] wire_receive_pcs0_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire wire_transmit_pcs0_clkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_seriallpbkout;
wire [1:0] analogfastrefclkout;
wire [1:0] analogrefclkout;
wire [0:0] analogrefclkpulse;
wire cal_blk_powerdown;
wire [599:0] cent_unit_cmudividerdprioout;
wire [1799:0] cent_unit_cmuplldprioout;
wire [1:0] cent_unit_pllpowerdn;
wire [1:0] cent_unit_pllresetout;
wire [0:0] cent_unit_quadresetout;
wire [5:0] cent_unit_rxcrupowerdn;
wire [5:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1799:0] cent_unit_rxpmadprioin;
wire [1799:0] cent_unit_rxpmadprioout;
wire [1199:0] cent_unit_tx_dprioin;
wire [31:0] cent_unit_tx_xgmdataout;
wire [3:0] cent_unit_txctrlout;
wire [5:0] cent_unit_txdetectrxpowerdn;
wire [599:0] cent_unit_txdprioout;
wire [5:0] cent_unit_txobpowerdn;
wire [1799:0] cent_unit_txpmadprioin;
wire [1799:0] cent_unit_txpmadprioout;
wire [599:0] clk_div_cmudividerdprioin;
wire [5:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [5:0] fixedclk_in;
wire [0:0] fixedclk_sel;
wire [5:0] fixedclk_to_cmu;
wire [0:0] nonusertocmu_out;
wire [9:0] pll0_clkin;
wire [299:0] pll0_dprioin;
wire [299:0] pll0_dprioout;
wire [3:0] pll0_out;
wire [1:0] pll_ch_dataout_wire;
wire [299:0] pll_ch_dprioout;
wire [1799:0] pll_cmuplldprioout;
wire [0:0] pll_inclk_wire;
wire [0:0] pll_locked_out;
wire [1:0] pllpowerdn_in;
wire [1:0] pllreset_in;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [5:0] rx_analogreset_in;
wire [5:0] rx_analogreset_out;
wire [0:0] rx_clkout_wire;
wire [0:0] rx_coreclk_in;
wire [9:0] rx_cruclk_in;
wire [3:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [0:0] rx_enapatternalign;
wire [0:0] rx_freqlocked_wire;
wire [0:0] rx_locktodata;
wire [0:0] rx_locktodata_wire;
wire [0:0] rx_locktorefclk;
wire [0:0] rx_locktorefclk_wire;
wire [7:0] rx_out_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [0:0] rx_phfifordenable;
wire [0:0] rx_phfiforeset;
wire [0:0] rx_phfifowrdisable;
wire [0:0] rx_pldcruclk_in;
wire [3:0] rx_pll_clkout;
wire [0:0] rx_pll_pfdrefclkout_wire;
wire [0:0] rx_plllocked_wire;
wire [16:0] rx_pma_analogtestbus;
wire [0:0] rx_pma_clockout;
wire [0:0] rx_pma_dataout;
wire [0:0] rx_pma_locktorefout;
wire [19:0] rx_pma_recoverdataout_wire;
wire [1799:0] rx_pmadprioin_wire;
wire [1799:0] rx_pmadprioout;
wire [0:0] rx_powerdown;
wire [5:0] rx_powerdown_in;
wire [0:0] rx_prbscidenable;
wire [0:0] rx_rmfiforeset;
wire [5:0] rx_rxcruresetout;
wire [1799:0] rxpll_dprioin;
wire [5:0] tx_analogreset_out;
wire [0:0] tx_clkout_int_wire;
wire [0:0] tx_core_clkout_wire;
wire [0:0] tx_coreclk_in;
wire [7:0] tx_datain_wire;
wire [19:0] tx_dataout_pcs_to_pma;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [1199:0] tx_dprioin_wire;
wire [0:0] tx_forcedisp_wire;
wire [0:0] tx_invpolarity;
wire [0:0] tx_localrefclk;
wire [0:0] tx_phfiforeset;
wire [1799:0] tx_pmadprioin_wire;
wire [1799:0] tx_pmadprioout;
wire [0:0] tx_serialloopbackout;
wire [599:0] tx_txdprioout;
wire [0:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
// synopsys translate_off
initial
fixedclk_div0quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div0quad0c_clk)
fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);
assign
wire_fixedclk_div0quad0c_clk = fixedclk_in[0];
// synopsys translate_off
initial
fixedclk_div1quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div1quad0c_clk)
fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);
assign
wire_fixedclk_div1quad0c_clk = fixedclk_in[1];
// synopsys translate_off
initial
fixedclk_div2quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div2quad0c_clk)
fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);
assign
wire_fixedclk_div2quad0c_clk = fixedclk_in[2];
// synopsys translate_off
initial
fixedclk_div3quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div3quad0c_clk)
fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);
assign
wire_fixedclk_div3quad0c_clk = fixedclk_in[3];
// synopsys translate_off
initial
fixedclk_div4quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div4quad0c_clk)
fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);
assign
wire_fixedclk_div4quad0c_clk = fixedclk_in[4];
// synopsys translate_off
initial
fixedclk_div5quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div5quad0c_clk)
fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);
assign
wire_fixedclk_div5quad0c_clk = fixedclk_in[5];
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
stratixiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_clock_divider ch_clk_div0
(
.analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_ch_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(pll0_out[3:0]),
.coreclkout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(cent_unit_cmudividerdprioout[99:0]),
.dprioout(wire_ch_clk_div0_dprioout),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchbaseclock(),
.rateswitchdone(),
.rateswitchout(),
.refclkout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.powerdn(1'b0),
.rateswitch(1'b0),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.refclkin({2{1'b0}}),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
ch_clk_div0.divide_by = 5,
ch_clk_div0.divider_type = "CHANNEL_REGULAR",
ch_clk_div0.effective_data_rate = "1250.0 Mbps",
ch_clk_div0.enable_dynamic_divider = "false",
ch_clk_div0.enable_refclk_out = "false",
ch_clk_div0.inclk_select = 0,
ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
ch_clk_div0.pre_divide_by = 1,
ch_clk_div0.select_local_rate_switch_done = "false",
ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
ch_clk_div0.sim_coreclkout_phase_shift = 0,
ch_clk_div0.sim_refclkout_phase_shift = 0,
ch_clk_div0.use_coreclk_out_post_divider = "false",
ch_clk_div0.use_refclk_post_divider = "false",
ch_clk_div0.use_vco_bypass = "false",
ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(),
.autospdx4rateswitchout(),
.autospdx4spdchg(),
.clkdivpowerdn(),
.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifox4byteselout(),
.rxphfifox4rdenableout(),
.rxphfifox4wrclkout(),
.rxphfifox4wrenableout(),
.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfifox4byteselout(),
.txphfifox4rdclkout(),
.txphfifox4rdenableout(),
.txphfifox4wrenableout(),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.rateswitch(1'b0),
.rateswitchdonein(1'b0),
.rxclk(1'b0),
.rxcoreclk(1'b0),
.rxphfifordenable(1'b1),
.rxphfiforeset(1'b0),
.rxphfifowrdisable(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}}),
.txclk(1'b0),
.txcoreclk(1'b0),
.txphfiforddisable(1'b0),
.txphfiforeset(1'b0),
.txphfifowrenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 0,
cent_unit0.bonded_quad_mode = "none",
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "false",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 249950,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "false",
cent_unit0.rx0_channel_bonding = "none",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "local reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_auto_spd_self_switch_enable = "false",
cent_unit0.tx0_channel_bonding = "none",
cent_unit0.tx0_ph_fifo_reg_mode = "false",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "Auto",
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll0_dprioout),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({rx_cruclk_in[9:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.bandwidth_type = "Medium",
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.dprio_config_mode = 6'h00,
rx_cdr_pll0.effective_data_rate = "1250.0 Mbps",
rx_cdr_pll0.enable_dynamic_divider = "false",
rx_cdr_pll0.fast_lock_control = "false",
rx_cdr_pll0.inclk0_input_period = 8000,
rx_cdr_pll0.input_clock_frequency = "125.0 MHz",
rx_cdr_pll0.m = 5,
rx_cdr_pll0.n = 1,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_post_scale = 4,
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(pll0_dprioin[299:0]),
.dprioout(wire_tx_pll0_dprioout),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datain(1'b0),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tx_pll0.bandwidth_type = "High",
tx_pll0.channel_num = 4,
tx_pll0.dprio_config_mode = 6'h00,
tx_pll0.inclk0_input_period = 8000,
tx_pll0.input_clock_frequency = "125.0 MHz",
tx_pll0.logical_tx_pll_number = 0,
tx_pll0.m = 5,
tx_pll0.n = 1,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pfd_fb_select = "internal",
tx_pll0.pll_type = "CMU",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_post_scale = 4,
tx_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(),
.autospdspdchgout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(wire_receive_pcs0_clkout),
.coreclk(rx_coreclk_in[0]),
.coreclkout(),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(wire_receive_pcs0_disperr),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(wire_receive_pcs0_errdetect),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(tx_localrefclk[0]),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(),
.phfifooverflow(),
.phfifoptrsresetout(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(),
.phfifowrenableout(),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipephydonestatus(),
.pipepowerdown({2{1'b0}}),
.pipepowerstate({4{1'b0}}),
.pipestatetransdoneout(),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(),
.rlv(wire_receive_pcs0_rlv),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
.rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(wire_receive_pcs0_runningdisp),
.rxdetectvalid(1'b0),
.rxfound({2{1'b0}}),
.signaldetect(),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.autospdxnconfigsel({3{1'b0}}),
.autospdxnspdchg({3{1'b0}}),
.bitslip(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.phfifoxnbytesel({3{1'b0}}),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxnrdenable({3{1'b0}}),
.phfifoxnwrclk({3{1'b0}}),
.phfifoxnwrenable({3{1'b0}}),
.pipe8b10binvpolarity(1'b0),
.pipeenrevparallellpbkfromtx(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0),
.refclk(1'b0),
.rxelecidlerateswitch(1'b0),
.signaldetected(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "1111100",
receive_pcs0.align_pattern_length = 7,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "false",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 0,
receive_pcs0.auto_spd_self_switch_enable = "false",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_enable = "false",
receive_pcs0.cdrctrl_rxvalid_mask = "false",
receive_pcs0.channel_bonding = "none",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "local reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "basic",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "false",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "true",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 1,
receive_pcs0.num_align_cons_good_data = 4,
receive_pcs0.num_align_cons_pat = 3,
receive_pcs0.num_align_loss_sync_error = 4,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "none",
receive_pcs0.ph_fifo_xn_select = 1,
receive_pcs0.pipe_auto_speed_nego_enable = "false",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 249950,
receive_pcs0.protocol_hint = "gige",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "true",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "true",
receive_pcs0.rate_match_pattern1 = "10100010010101111100",
receive_pcs0.rate_match_pattern2 = "10101011011010000011",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "false",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 5,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 15,
receive_pcs0.rxstatus_error_report_mode = 0,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pma receive_pma0
(
.adaptdone(),
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(rx_seriallpbken[0]),
.seriallpbkin(tx_serialloopbackout[0]),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.adaptive_equalization_mode = "none",
receive_pma0.allow_serial_loopback = "true",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.eq_dc_gain = 0,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 0,
receive_pma0.eyemon_bandwidth = 0,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppmselect = 32,
receive_pma0.protocol_hint = "gige",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis = 2,
receive_pma0.signal_detect_hysteresis_valid_threshold = 1,
receive_pma0.signal_detect_loss_threshold = 1,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_external_termination = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclk(tx_coreclk_in[0]),
.coreclkout(),
.ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
.datain({{32{1'b0}}, tx_datain_wire[7:0]}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(1'b0),
.digitalreset(tx_digitalreset_out[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(1'b0),
.forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifooverflow(),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(),
.pipeenrevparallellpbkout(),
.pipepowerdownout(),
.pipepowerstateout(),
.pipestatetransdone(1'b0),
.powerdn({2{1'b0}}),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.revparallelfdbk({20{1'b0}}),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.dispval({4{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifobyteserdisable(1'b0),
.phfifoptrsreset(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxnbytesel({3{1'b0}}),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxnrdclk({3{1'b0}}),
.phfifoxnrdenable({3{1'b0}}),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.phfifoxnwrenable({3{1'b0}}),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.pipetxswing(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0),
.refclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "none",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "basic",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "none",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "true",
transmit_pcs0.enable_reverse_parallel_loopback = "false",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "none",
transmit_pcs0.ph_fifo_xn_select = 1,
transmit_pcs0.pipe_auto_speed_nego_enable = "false",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "gige",
transmit_pcs0.refclk_select = "local",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in(analogfastrefclkout[1:0]),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(1'b0),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({analogrefclkout[1:0]}),
.refclk0inpulse(analogrefclkpulse[0]),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(),
.rxfoundout(),
.seriallpbkout(wire_transmit_pma0_seriallpbkout),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "auto",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 0,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.logical_protocol_hint_0 = "gige",
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.physical_clkin0_mapping = "x1",
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 0,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "gige",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "medium",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 1,
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
assign
analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
cal_blk_powerdown = 1'b0,
cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{1500{1'b0}}, rx_pmadprioout[299:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
cent_unit_tx_dprioin = {{1050{1'b0}}, tx_txdprioout[149:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
cent_unit_txpmadprioin = {{1500{1'b0}}, tx_pmadprioout[299:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
clk_div_cmudividerdprioin = {{500{1'b0}}, wire_ch_clk_div0_dprioout},
fixedclk_div_in = {fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c},
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_in = {{5{1'b0}}, fixedclk},
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
pll0_dprioout = {wire_tx_pll0_dprioout},
pll0_out = {wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
pll_ch_dprioout = {wire_rx_cdr_pll0_dprioout},
pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], {900{1'b0}}, pll_ch_dprioout[299:0]},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {wire_tx_pll0_locked},
pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {1'b0, cent_unit_pllresetout[0]},
reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
rx_analogreset_in = {{5{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
rx_clkout = {rx_clkout_wire[0]},
rx_clkout_wire = {wire_receive_pcs0_clkout},
rx_coreclk_in = {tx_core_clkout_wire[0]},
rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
rx_dataout = {rx_out_wire[7:0]},
rx_deserclock_in = {rx_pll_clkout[3:0]},
rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_disperr = {wire_receive_pcs0_disperr[0]},
rx_enapatternalign = 1'b0,
rx_errdetect = {wire_receive_pcs0_errdetect[0]},
rx_freqlocked = {(rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
rx_locktodata = 1'b0,
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])},
rx_locktorefclk = 1'b0,
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
rx_phfifordenable = 1'b1,
rx_phfiforeset = 1'b0,
rx_phfifowrdisable = 1'b0,
rx_pldcruclk_in = {rx_cruclk[0]},
rx_pll_clkout = {wire_rx_cdr_pll0_clk},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
rx_pma_analogtestbus = {{12{1'b0}}, wire_receive_pma0_analogtestbus[5:2], 1'b0},
rx_pma_clockout = {wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_rxpmadprioout[299:0]},
rx_pmadprioout = {{1500{1'b0}}, wire_receive_pma0_dprioout},
rx_powerdown = 1'b0,
rx_powerdown_in = {{5{1'b0}}, rx_powerdown[0]},
rx_prbscidenable = 1'b0,
rx_recovclkout = {rx_pma_clockout[0]},
rx_rlv = {wire_receive_pcs0_rlv},
rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]},
rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]},
rx_rmfiforeset = 1'b0,
rx_runningdisp = {wire_receive_pcs0_runningdisp[0]},
rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
rxpll_dprioin = {{1500{1'b0}}, cent_unit_cmuplldprioout[299:0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
tx_clkout = {tx_core_clkout_wire[0]},
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
tx_coreclk_in = {tx_core_clkout_wire[0]},
tx_datain_wire = {tx_datain[7:0]},
tx_dataout = {wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{1050{1'b0}}, cent_unit_txdprioout[149:0]},
tx_forcedisp_wire = {1'b0},
tx_invpolarity = 1'b0,
tx_localrefclk = {wire_transmit_pma0_clockout},
tx_phfiforeset = 1'b0,
tx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_txpmadprioout[299:0]},
tx_pmadprioout = {{1500{1'b0}}, wire_transmit_pma0_dprioout},
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
txdetectrxout = {wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //altera_tse_alt4gxb_gige_alt4gxb_lnca
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_alt4gxb_gige (
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_inclk,
pll_powerdown,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input pll_inclk;
input [0:0] pll_powerdown;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [16:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [16:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [16:0] reconfig_fromgxb = sub_wire2[16:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
altera_tse_alt4gxb_gige_alt4gxb_lnca altera_tse_alt4gxb_gige_alt4gxb_lnca_component (
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.fixedclk (fixedclk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pll_powerdown (pll_powerdown),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.rx_seriallpbken (rx_seriallpbken),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.fixedclk_fast (fixedclk_fast),
.tx_ctrlenable (tx_ctrlenable),
.pll_inclk (pll_inclk),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt4gxb
clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=125.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=slb;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;preemphasis_ctrl_2ndposttap_inv_setting=false;preemphasis_ctrl_2ndposttap_setting=0;preemphasis_ctrl_pretap_inv_setting=false;preemphasis_ctrl_pretap_setting=0;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=1111100;rx_align_pattern_length=7;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Medium;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=normal;rx_rate_match_pattern1=10100010010101111100;
rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=2;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;gxb_powerdown_width=1;number_of_quads=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cru_m_divider=5;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=4;rx_dwidth_factor=1;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=1;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=5;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=4;tx_use_external_termination=false;" */;
defparam
altera_tse_alt4gxb_gige_alt4gxb_lnca_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: IP_MODE STRING "TSE"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "1111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "7"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "5"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "4"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "5"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "4"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: fixedclk_fast 0 0 6 0 INPUT NODEFVAL "fixedclk_fast[5..0]"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk_fast 0 0 6 0 fixedclk_fast 0 0 6 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_bb.v TRUE
// Retrieval info: LIB_FILE: stratixiv_hssi
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: altera_tse_alt4gxb_gige_wo_rmfifo.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
// stratixiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Internal Build 147 03/05/2012 PN Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" effective_data_rate="1250.0 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="1111100" rx_align_pattern_length=7 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="none" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_seriallpbken rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset
//VERSION_BEGIN 12.0 cbx_alt4gxb 2012:03:05:21:09:17:PN cbx_mgl 2012:03:05:22:13:55:PN cbx_tgx 2012:03:05:21:09:17:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 8 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=c104"} *)
module altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_sgca
(
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_inclk,
pll_locked,
pll_powerdown,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_clkout,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_seriallpbken,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_digitalreset) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input pll_inclk;
output [0:0] pll_locked;
input [0:0] pll_powerdown;
input reconfig_clk;
output [16:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
output [0:0] rx_clkout;
input [0:0] rx_cruclk;
output [0:0] rx_ctrldetect;
input [0:0] rx_datain;
output [7:0] rx_dataout;
input [0:0] rx_digitalreset;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
input [0:0] rx_seriallpbken;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
output [0:0] tx_dataout;
input [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri1 [5:0] fixedclk_fast;
tri0 [0:0] gxb_powerdown;
tri0 pll_inclk;
tri0 [0:0] pll_powerdown;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_cruclk;
tri0 [0:0] rx_digitalreset;
tri0 [0:0] rx_seriallpbken;
tri0 [0:0] tx_ctrlenable;
tri0 [7:0] tx_datain;
tri0 [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
reg fixedclk_div0quad0c;
wire wire_fixedclk_div0quad0c_clk;
reg fixedclk_div1quad0c;
wire wire_fixedclk_div1quad0c_clk;
reg fixedclk_div2quad0c;
wire wire_fixedclk_div2quad0c_clk;
reg fixedclk_div3quad0c;
wire wire_fixedclk_div3quad0c_clk;
reg fixedclk_div4quad0c;
wire wire_fixedclk_div4quad0c_clk;
reg fixedclk_div5quad0c;
wire wire_fixedclk_div5quad0c_clk;
reg [1:0] reconfig_togxb_busy_reg;
wire wire_cal_blk0_nonusertocmu;
wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
wire [1:0] wire_ch_clk_div0_analogrefclkout;
wire wire_ch_clk_div0_analogrefclkpulse;
wire [99:0] wire_ch_clk_div0_dprioout;
wire [599:0] wire_cent_unit0_cmudividerdprioout;
wire [1799:0] wire_cent_unit0_cmuplldprioout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire [1799:0] wire_cent_unit0_rxpmadprioout;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire [1799:0] wire_cent_unit0_txpmadprioout;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire [299:0] wire_rx_cdr_pll0_dprioout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire [299:0] wire_tx_pll0_dprioout;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_clkout;
wire [3:0] wire_receive_pcs0_ctrldetect;
wire [39:0] wire_receive_pcs0_dataout;
wire [3:0] wire_receive_pcs0_disperr;
wire [399:0] wire_receive_pcs0_dprioout;
wire [3:0] wire_receive_pcs0_errdetect;
wire [3:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_rlv;
wire [3:0] wire_receive_pcs0_rmfifodatadeleted;
wire [3:0] wire_receive_pcs0_rmfifodatainserted;
wire [3:0] wire_receive_pcs0_runningdisp;
wire [3:0] wire_receive_pcs0_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire wire_transmit_pcs0_clkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_seriallpbkout;
wire [1:0] analogfastrefclkout;
wire [1:0] analogrefclkout;
wire [0:0] analogrefclkpulse;
wire cal_blk_powerdown;
wire [599:0] cent_unit_cmudividerdprioout;
wire [1799:0] cent_unit_cmuplldprioout;
wire [1:0] cent_unit_pllpowerdn;
wire [1:0] cent_unit_pllresetout;
wire [0:0] cent_unit_quadresetout;
wire [5:0] cent_unit_rxcrupowerdn;
wire [5:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1799:0] cent_unit_rxpmadprioin;
wire [1799:0] cent_unit_rxpmadprioout;
wire [1199:0] cent_unit_tx_dprioin;
wire [31:0] cent_unit_tx_xgmdataout;
wire [3:0] cent_unit_txctrlout;
wire [5:0] cent_unit_txdetectrxpowerdn;
wire [599:0] cent_unit_txdprioout;
wire [5:0] cent_unit_txobpowerdn;
wire [1799:0] cent_unit_txpmadprioin;
wire [1799:0] cent_unit_txpmadprioout;
wire [599:0] clk_div_cmudividerdprioin;
wire [5:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [5:0] fixedclk_in;
wire [0:0] fixedclk_sel;
wire [5:0] fixedclk_to_cmu;
wire [0:0] nonusertocmu_out;
wire [9:0] pll0_clkin;
wire [299:0] pll0_dprioin;
wire [299:0] pll0_dprioout;
wire [3:0] pll0_out;
wire [1:0] pll_ch_dataout_wire;
wire [299:0] pll_ch_dprioout;
wire [1799:0] pll_cmuplldprioout;
wire [0:0] pll_inclk_wire;
wire [0:0] pll_locked_out;
wire [1:0] pllpowerdn_in;
wire [1:0] pllreset_in;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [5:0] rx_analogreset_in;
wire [5:0] rx_analogreset_out;
wire [0:0] rx_clkout_wire;
wire [0:0] rx_coreclk_in;
wire [9:0] rx_cruclk_in;
wire [3:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [0:0] rx_enapatternalign;
wire [0:0] rx_freqlocked_wire;
wire [0:0] rx_locktodata;
wire [0:0] rx_locktodata_wire;
wire [0:0] rx_locktorefclk;
wire [0:0] rx_locktorefclk_wire;
wire [7:0] rx_out_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [0:0] rx_phfifordenable;
wire [0:0] rx_phfiforeset;
wire [0:0] rx_phfifowrdisable;
wire [0:0] rx_pldcruclk_in;
wire [3:0] rx_pll_clkout;
wire [0:0] rx_pll_pfdrefclkout_wire;
wire [0:0] rx_plllocked_wire;
wire [16:0] rx_pma_analogtestbus;
wire [0:0] rx_pma_clockout;
wire [0:0] rx_pma_dataout;
wire [0:0] rx_pma_locktorefout;
wire [19:0] rx_pma_recoverdataout_wire;
wire [1799:0] rx_pmadprioin_wire;
wire [1799:0] rx_pmadprioout;
wire [0:0] rx_powerdown;
wire [5:0] rx_powerdown_in;
wire [0:0] rx_prbscidenable;
wire [5:0] rx_rxcruresetout;
wire [1799:0] rxpll_dprioin;
wire [5:0] tx_analogreset_out;
wire [0:0] tx_clkout_int_wire;
wire [0:0] tx_core_clkout_wire;
wire [0:0] tx_coreclk_in;
wire [7:0] tx_datain_wire;
wire [19:0] tx_dataout_pcs_to_pma;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [1199:0] tx_dprioin_wire;
wire [0:0] tx_forcedisp_wire;
wire [0:0] tx_invpolarity;
wire [0:0] tx_localrefclk;
wire [0:0] tx_phfiforeset;
wire [1799:0] tx_pmadprioin_wire;
wire [1799:0] tx_pmadprioout;
wire [0:0] tx_serialloopbackout;
wire [599:0] tx_txdprioout;
wire [0:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
// synopsys translate_off
initial
fixedclk_div0quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div0quad0c_clk)
fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);
assign
wire_fixedclk_div0quad0c_clk = fixedclk_in[0];
// synopsys translate_off
initial
fixedclk_div1quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div1quad0c_clk)
fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);
assign
wire_fixedclk_div1quad0c_clk = fixedclk_in[1];
// synopsys translate_off
initial
fixedclk_div2quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div2quad0c_clk)
fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);
assign
wire_fixedclk_div2quad0c_clk = fixedclk_in[2];
// synopsys translate_off
initial
fixedclk_div3quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div3quad0c_clk)
fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);
assign
wire_fixedclk_div3quad0c_clk = fixedclk_in[3];
// synopsys translate_off
initial
fixedclk_div4quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div4quad0c_clk)
fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);
assign
wire_fixedclk_div4quad0c_clk = fixedclk_in[4];
// synopsys translate_off
initial
fixedclk_div5quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div5quad0c_clk)
fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);
assign
wire_fixedclk_div5quad0c_clk = fixedclk_in[5];
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
stratixiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_clock_divider ch_clk_div0
(
.analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_ch_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(pll0_out[3:0]),
.coreclkout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(cent_unit_cmudividerdprioout[99:0]),
.dprioout(wire_ch_clk_div0_dprioout),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchbaseclock(),
.rateswitchdone(),
.rateswitchout(),
.refclkout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.powerdn(1'b0),
.rateswitch(1'b0),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.refclkin({2{1'b0}}),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
ch_clk_div0.divide_by = 5,
ch_clk_div0.divider_type = "CHANNEL_REGULAR",
ch_clk_div0.effective_data_rate = "1250.0 Mbps",
ch_clk_div0.enable_dynamic_divider = "false",
ch_clk_div0.enable_refclk_out = "false",
ch_clk_div0.inclk_select = 0,
ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
ch_clk_div0.pre_divide_by = 1,
ch_clk_div0.select_local_rate_switch_done = "false",
ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
ch_clk_div0.sim_coreclkout_phase_shift = 0,
ch_clk_div0.sim_refclkout_phase_shift = 0,
ch_clk_div0.use_coreclk_out_post_divider = "false",
ch_clk_div0.use_refclk_post_divider = "false",
ch_clk_div0.use_vco_bypass = "false",
ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(),
.autospdx4rateswitchout(),
.autospdx4spdchg(),
.clkdivpowerdn(),
.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifox4byteselout(),
.rxphfifox4rdenableout(),
.rxphfifox4wrclkout(),
.rxphfifox4wrenableout(),
.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfifox4byteselout(),
.txphfifox4rdclkout(),
.txphfifox4rdenableout(),
.txphfifox4wrenableout(),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.rateswitch(1'b0),
.rateswitchdonein(1'b0),
.rxclk(1'b0),
.rxcoreclk(1'b0),
.rxphfifordenable(1'b1),
.rxphfiforeset(1'b0),
.rxphfifowrdisable(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}}),
.txclk(1'b0),
.txcoreclk(1'b0),
.txphfiforddisable(1'b0),
.txphfiforeset(1'b0),
.txphfifowrenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 0,
cent_unit0.bonded_quad_mode = "none",
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "false",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 249950,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "false",
cent_unit0.rx0_channel_bonding = "none",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "recovered clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_auto_spd_self_switch_enable = "false",
cent_unit0.tx0_channel_bonding = "none",
cent_unit0.tx0_ph_fifo_reg_mode = "false",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "Auto",
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll0_dprioout),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({rx_cruclk_in[9:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.bandwidth_type = "Medium",
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.dprio_config_mode = 6'h00,
rx_cdr_pll0.effective_data_rate = "1250.0 Mbps",
rx_cdr_pll0.enable_dynamic_divider = "false",
rx_cdr_pll0.fast_lock_control = "false",
rx_cdr_pll0.inclk0_input_period = 8000,
rx_cdr_pll0.input_clock_frequency = "125.0 MHz",
rx_cdr_pll0.m = 5,
rx_cdr_pll0.n = 1,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_post_scale = 4,
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(pll0_dprioin[299:0]),
.dprioout(wire_tx_pll0_dprioout),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datain(1'b0),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tx_pll0.bandwidth_type = "High",
tx_pll0.channel_num = 4,
tx_pll0.dprio_config_mode = 6'h00,
tx_pll0.inclk0_input_period = 8000,
tx_pll0.input_clock_frequency = "125.0 MHz",
tx_pll0.logical_tx_pll_number = 0,
tx_pll0.m = 5,
tx_pll0.n = 1,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pfd_fb_select = "internal",
tx_pll0.pll_type = "CMU",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_post_scale = 4,
tx_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(),
.autospdspdchgout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(wire_receive_pcs0_clkout),
.coreclk(rx_coreclk_in[0]),
.coreclkout(),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(wire_receive_pcs0_disperr),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(wire_receive_pcs0_errdetect),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(),
.phfifooverflow(),
.phfifoptrsresetout(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(),
.phfifowrenableout(),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipephydonestatus(),
.pipepowerdown({2{1'b0}}),
.pipepowerstate({4{1'b0}}),
.pipestatetransdoneout(),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(),
.rlv(wire_receive_pcs0_rlv),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
.rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(1'b0),
.rmfifowrena(1'b0),
.runningdisp(wire_receive_pcs0_runningdisp),
.rxdetectvalid(1'b0),
.rxfound({2{1'b0}}),
.signaldetect(),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.autospdxnconfigsel({3{1'b0}}),
.autospdxnspdchg({3{1'b0}}),
.bitslip(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.phfifoxnbytesel({3{1'b0}}),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxnrdenable({3{1'b0}}),
.phfifoxnwrclk({3{1'b0}}),
.phfifoxnwrenable({3{1'b0}}),
.pipe8b10binvpolarity(1'b0),
.pipeenrevparallellpbkfromtx(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0),
.refclk(1'b0),
.rxelecidlerateswitch(1'b0),
.signaldetected(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "1111100",
receive_pcs0.align_pattern_length = 7,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "false",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 0,
receive_pcs0.auto_spd_self_switch_enable = "false",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_enable = "false",
receive_pcs0.cdrctrl_rxvalid_mask = "false",
receive_pcs0.channel_bonding = "none",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "recovered clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "basic",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "false",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "true",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 1,
receive_pcs0.num_align_cons_good_data = 4,
receive_pcs0.num_align_cons_pat = 3,
receive_pcs0.num_align_loss_sync_error = 4,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "none",
receive_pcs0.ph_fifo_xn_select = 1,
receive_pcs0.pipe_auto_speed_nego_enable = "false",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 249950,
receive_pcs0.protocol_hint = "gige",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "true",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "false",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "true",
receive_pcs0.rate_match_pattern1 = "10100010010101111100",
receive_pcs0.rate_match_pattern2 = "10101011011010000011",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "false",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 5,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 15,
receive_pcs0.rxstatus_error_report_mode = 0,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pma receive_pma0
(
.adaptdone(),
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(rx_seriallpbken[0]),
.seriallpbkin(tx_serialloopbackout[0]),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.adaptive_equalization_mode = "none",
receive_pma0.allow_serial_loopback = "true",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.eq_dc_gain = 0,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 0,
receive_pma0.eyemon_bandwidth = 0,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppmselect = 32,
receive_pma0.protocol_hint = "gige",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis = 2,
receive_pma0.signal_detect_hysteresis_valid_threshold = 1,
receive_pma0.signal_detect_loss_threshold = 1,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_external_termination = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclk(tx_coreclk_in[0]),
.coreclkout(),
.ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
.datain({{32{1'b0}}, tx_datain_wire[7:0]}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(1'b0),
.digitalreset(tx_digitalreset_out[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(1'b0),
.forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifooverflow(),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(),
.pipeenrevparallellpbkout(),
.pipepowerdownout(),
.pipepowerstateout(),
.pipestatetransdone(1'b0),
.powerdn({2{1'b0}}),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.revparallelfdbk({20{1'b0}}),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.dispval({4{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifobyteserdisable(1'b0),
.phfifoptrsreset(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxnbytesel({3{1'b0}}),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxnrdclk({3{1'b0}}),
.phfifoxnrdenable({3{1'b0}}),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.phfifoxnwrenable({3{1'b0}}),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.pipetxswing(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0),
.refclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "none",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "basic",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "none",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "true",
transmit_pcs0.enable_reverse_parallel_loopback = "false",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "none",
transmit_pcs0.ph_fifo_xn_select = 1,
transmit_pcs0.pipe_auto_speed_nego_enable = "false",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "gige",
transmit_pcs0.refclk_select = "local",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in(analogfastrefclkout[1:0]),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(1'b0),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({analogrefclkout[1:0]}),
.refclk0inpulse(analogrefclkpulse[0]),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(),
.rxfoundout(),
.seriallpbkout(wire_transmit_pma0_seriallpbkout),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "auto",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 0,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.logical_protocol_hint_0 = "gige",
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.physical_clkin0_mapping = "x1",
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 0,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "gige",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "medium",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 1,
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
assign
analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
cal_blk_powerdown = 1'b0,
cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{1500{1'b0}}, rx_pmadprioout[299:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
cent_unit_tx_dprioin = {{1050{1'b0}}, tx_txdprioout[149:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
cent_unit_txpmadprioin = {{1500{1'b0}}, tx_pmadprioout[299:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
clk_div_cmudividerdprioin = {{500{1'b0}}, wire_ch_clk_div0_dprioout},
fixedclk_div_in = {fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c},
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_in = {{5{1'b0}}, fixedclk},
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
pll0_dprioout = {wire_tx_pll0_dprioout},
pll0_out = {wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
pll_ch_dprioout = {wire_rx_cdr_pll0_dprioout},
pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], {900{1'b0}}, pll_ch_dprioout[299:0]},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {wire_tx_pll0_locked},
pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {1'b0, cent_unit_pllresetout[0]},
reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
rx_analogreset_in = {{5{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
rx_clkout = {rx_clkout_wire[0]},
rx_clkout_wire = {wire_receive_pcs0_clkout},
rx_coreclk_in = {rx_clkout_wire[0]},
rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
rx_dataout = {rx_out_wire[7:0]},
rx_deserclock_in = {rx_pll_clkout[3:0]},
rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_disperr = {wire_receive_pcs0_disperr[0]},
rx_enapatternalign = 1'b0,
rx_errdetect = {wire_receive_pcs0_errdetect[0]},
rx_freqlocked = {(rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
rx_locktodata = 1'b0,
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])},
rx_locktorefclk = 1'b0,
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
rx_phfifordenable = 1'b1,
rx_phfiforeset = 1'b0,
rx_phfifowrdisable = 1'b0,
rx_pldcruclk_in = {rx_cruclk[0]},
rx_pll_clkout = {wire_rx_cdr_pll0_clk},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
rx_pma_analogtestbus = {{12{1'b0}}, wire_receive_pma0_analogtestbus[5:2], 1'b0},
rx_pma_clockout = {wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_rxpmadprioout[299:0]},
rx_pmadprioout = {{1500{1'b0}}, wire_receive_pma0_dprioout},
rx_powerdown = 1'b0,
rx_powerdown_in = {{5{1'b0}}, rx_powerdown[0]},
rx_prbscidenable = 1'b0,
rx_recovclkout = {rx_pma_clockout[0]},
rx_rlv = {wire_receive_pcs0_rlv},
rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]},
rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]},
rx_runningdisp = {wire_receive_pcs0_runningdisp[0]},
rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
rxpll_dprioin = {{1500{1'b0}}, cent_unit_cmuplldprioout[299:0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
tx_clkout = {tx_core_clkout_wire[0]},
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
tx_coreclk_in = {tx_core_clkout_wire[0]},
tx_datain_wire = {tx_datain[7:0]},
tx_dataout = {wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{1050{1'b0}}, cent_unit_txdprioout[149:0]},
tx_forcedisp_wire = {1'b0},
tx_invpolarity = 1'b0,
tx_localrefclk = {wire_transmit_pma0_clockout},
tx_phfiforeset = 1'b0,
tx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_txpmadprioout[299:0]},
tx_pmadprioout = {{1500{1'b0}}, wire_transmit_pma0_dprioout},
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
txdetectrxout = {wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_sgca
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_alt4gxb_gige_wo_rmfifo (
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_inclk,
pll_powerdown,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input pll_inclk;
input [0:0] pll_powerdown;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [16:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [16:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [16:0] reconfig_fromgxb = sub_wire2[16:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_sgca altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_sgca_component (
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.fixedclk (fixedclk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pll_powerdown (pll_powerdown),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.rx_seriallpbken (rx_seriallpbken),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.fixedclk_fast (fixedclk_fast),
.tx_ctrlenable (tx_ctrlenable),
.pll_inclk (pll_inclk),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt4gxb
clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=125.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=slb;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;preemphasis_ctrl_2ndposttap_inv_setting=false;preemphasis_ctrl_2ndposttap_setting=0;preemphasis_ctrl_pretap_inv_setting=false;preemphasis_ctrl_pretap_setting=0;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=1111100;rx_align_pattern_length=7;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Medium;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=none;rx_rate_match_pattern1=10100010010101111100;
rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=2;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;gxb_powerdown_width=1;number_of_quads=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cru_m_divider=5;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=4;rx_dwidth_factor=1;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=1;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=5;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=4;tx_use_external_termination=false;" */;
defparam
altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_sgca_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: IP_MODE STRING "TSE"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "1111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "7"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "none"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "5"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "4"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "5"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "4"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: fixedclk_fast 0 0 6 0 INPUT NODEFVAL "fixedclk_fast[5..0]"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk_fast 0 0 6 0 fixedclk_fast 0 0 6 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo_bb.v TRUE
// Retrieval info: LIB_FILE: stratixiv_hssi
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb
// ============================================================
// File Name: altera_tse_altgx_civgx_gige.v
// Megafunction Name(s):
// alt_c3gxb
//
// Simulation Library Files(s):
// altera_mf;cycloneiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Internal Build 147 03/05/2012 PN Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="1111100" rx_align_pattern_length=7 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altera_tse_altgx_civgx_gige" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_areset pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX"
//VERSION_BEGIN 12.0 cbx_alt_c3gxb 2012:03:05:21:09:17:PN cbx_altclkbuf 2012:03:05:21:09:17:PN cbx_altiobuf_bidir 2012:03:05:21:09:17:PN cbx_altiobuf_in 2012:03:05:21:09:17:PN cbx_altiobuf_out 2012:03:05:21:09:17:PN cbx_altpll 2012:03:05:21:09:17:PN cbx_cycloneii 2012:03:05:21:09:17:PN cbx_lpm_add_sub 2012:03:05:21:09:17:PN cbx_lpm_compare 2012:03:05:21:09:17:PN cbx_lpm_counter 2012:03:05:21:09:17:PN cbx_lpm_decode 2012:03:05:21:09:17:PN cbx_lpm_mux 2012:03:05:21:09:17:PN cbx_mgl 2012:03:05:22:13:55:PN cbx_stingray 2012:03:05:21:09:16:PN cbx_stratix 2012:03:05:21:09:18:PN cbx_stratixii 2012:03:05:21:09:18:PN cbx_stratixiii 2012:03:05:21:09:18:PN cbx_stratixv 2012:03:05:21:09:18:PN cbx_util_mgl 2012:03:05:21:09:17:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module altera_tse_altgx_civgx_gige_alt_c3gxb_g308
(
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_areset,
pll_inclk,
pll_locked,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_clkout,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_digitalreset) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
input fixedclk;
input [3:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input [0:0] pll_areset;
input [0:0] pll_inclk;
output [0:0] pll_locked;
input reconfig_clk;
output [4:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
output [0:0] rx_clkout;
output [0:0] rx_ctrldetect;
input [0:0] rx_datain;
output [7:0] rx_dataout;
input [0:0] rx_digitalreset;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
output [0:0] tx_dataout;
input [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri1 [3:0] fixedclk_fast;
tri0 [0:0] gxb_powerdown;
tri0 [0:0] pll_areset;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_digitalreset;
tri0 [0:0] tx_ctrlenable;
tri0 [7:0] tx_datain;
tri0 [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [5:0] wire_pll0_clk;
wire wire_pll0_fref;
wire wire_pll0_icdrclk;
wire wire_pll0_locked;
wire wire_cal_blk0_nonusertocmu;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_quadresetout;
wire [3:0] wire_cent_unit0_rxanalogresetout;
wire [3:0] wire_cent_unit0_rxcrupowerdown;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [3:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire [1199:0] wire_cent_unit0_rxpmadprioout;
wire [3:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [3:0] wire_cent_unit0_txdividerpowerdown;
wire [3:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire [1199:0] wire_cent_unit0_txpmadprioout;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_clkout;
wire [1:0] wire_receive_pcs0_ctrldetect;
wire [19:0] wire_receive_pcs0_dataout;
wire [1:0] wire_receive_pcs0_disperr;
wire [399:0] wire_receive_pcs0_dprioout;
wire [1:0] wire_receive_pcs0_errdetect;
wire [1:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_rlv;
wire [1:0] wire_receive_pcs0_rmfifodatadeleted;
wire [1:0] wire_receive_pcs0_rmfifodatainserted;
wire [1:0] wire_receive_pcs0_runningdisp;
wire [1:0] wire_receive_pcs0_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_diagnosticlpbkout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_freqlocked;
wire wire_receive_pma0_locktorefout;
wire [9:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_reverselpbkout;
wire wire_receive_pma0_signaldetect;
wire wire_transmit_pcs0_clkout;
wire [9:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_seriallpbkout;
reg [0:0] fixedclk_div;
reg [1:0] reconfig_togxb_busy_reg;
wire cal_blk_powerdown;
wire [0:0] cent_unit_quadresetout;
wire [3:0] cent_unit_rxcrupowerdn;
wire [3:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1199:0] cent_unit_rxpmadprioin;
wire [1199:0] cent_unit_rxpmadprioout;
wire [599:0] cent_unit_tx_dprioin;
wire [3:0] cent_unit_txdetectrxpowerdn;
wire [3:0] cent_unit_txdividerpowerdown;
wire [599:0] cent_unit_txdprioout;
wire [3:0] cent_unit_txobpowerdn;
wire [1199:0] cent_unit_txpmadprioin;
wire [1199:0] cent_unit_txpmadprioout;
wire [0:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [0:0] fixedclk_sel;
wire [3:0] fixedclk_to_cmu;
wire [0:0] nonusertocmu_out;
wire [0:0] pll_powerdown;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [3:0] rx_analogreset_in;
wire [3:0] rx_analogreset_out;
wire [0:0] rx_clkout_wire;
wire [0:0] rx_coreclk_in;
wire [0:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [0:0] rx_enapatternalign;
wire [0:0] rx_locktodata;
wire [0:0] rx_locktorefclk;
wire [0:0] rx_locktorefclk_wire;
wire [7:0] rx_out_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [0:0] rx_phfifordenable;
wire [0:0] rx_phfiforeset;
wire [0:0] rx_phfifowrdisable;
wire [0:0] rx_pll_pfdrefclkout_wire;
wire [4:0] rx_pma_analogtestbus;
wire [0:0] rx_pma_clockout;
wire [9:0] rx_pma_recoverdataout_wire;
wire [1199:0] rx_pmadprioin_wire;
wire [1199:0] rx_pmadprioout;
wire [0:0] rx_powerdown;
wire [3:0] rx_powerdown_in;
wire [0:0] rx_prbscidenable;
wire [0:0] rx_reverselpbkout;
wire [0:0] rx_rmfiforeset;
wire [0:0] rx_signaldetect_wire;
wire [3:0] tx_analogreset_out;
wire [0:0] tx_clkout_int_wire;
wire [0:0] tx_core_clkout_wire;
wire [0:0] tx_coreclk_in;
wire [7:0] tx_datain_wire;
wire [9:0] tx_dataout_pcs_to_pma;
wire [0:0] tx_diagnosticlpbkin;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [599:0] tx_dprioin_wire;
wire [0:0] tx_forcedisp_wire;
wire [0:0] tx_invpolarity;
wire [0:0] tx_localrefclk;
wire [0:0] tx_phfiforeset;
wire [0:0] tx_pma_fastrefclk0in;
wire [0:0] tx_pma_refclk0in;
wire [0:0] tx_pma_refclk0inpulse;
wire [1199:0] tx_pmadprioin_wire;
wire [1199:0] tx_pmadprioout;
wire [0:0] tx_serialloopbackout;
wire [599:0] tx_txdprioout;
wire [0:0] txdataout;
wire [0:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
altpll pll0
(
.activeclock(),
.areset((pll_areset[0] | pll_powerdown[0])),
.clk(wire_pll0_clk),
.clkbad(),
.clkloss(),
.enable0(),
.enable1(),
.extclk(),
.fbout(),
.fref(wire_pll0_fref),
.icdrclk(wire_pll0_icdrclk),
.inclk({{1{1'b0}}, pll_inclk[0]}),
.locked(wire_pll0_locked),
.phasedone(),
.scandataout(),
.scandone(),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkena({6{1'b1}}),
.clkswitch(1'b0),
.configupdate(1'b0),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scanread(1'b0),
.scanwrite(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll0.bandwidth_type = "HIGH",
pll0.clk0_divide_by = 1,
pll0.clk0_multiply_by = 5,
pll0.clk1_divide_by = 5,
pll0.clk1_multiply_by = 5,
pll0.clk2_divide_by = 5,
pll0.clk2_duty_cycle = 20,
pll0.clk2_multiply_by = 5,
pll0.dpa_divide_by = 1,
pll0.dpa_multiply_by = 5,
pll0.inclk0_input_frequency = 8000,
pll0.operation_mode = "no_compensation",
pll0.intended_device_family = "Cyclone IV GX",
pll0.lpm_type = "altpll";
cycloneiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
cycloneiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.coreclkout(),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.fiforesetrd(),
.fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}),
.nonuserfromcal(nonusertocmu_out[0]),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkout(),
.rxanalogreset({rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifox4byteselout(),
.rxphfifox4rdenableout(),
.rxphfifox4wrclkout(),
.rxphfifox4wrenableout(),
.rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txctrl({4{1'b0}}),
.txctrlout(),
.txdatain({32{1'b0}}),
.txdataout(),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfifox4byteselout(),
.txphfifox4rdclkout(),
.txphfifox4rdenableout(),
.txphfifox4wrenableout(),
.txpmadprioin({cent_unit_txpmadprioin[1199:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.pmacramtest(1'b0),
.refclkdig(1'b0),
.rxcoreclk(1'b0),
.rxphfifordenable(1'b1),
.rxphfiforeset(1'b0),
.rxphfifowrdisable(1'b0),
.scanclk(1'b0),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({2000{1'b0}}),
.txclk(1'b0),
.txcoreclk(1'b0),
.txphfiforddisable(1'b0),
.txphfiforeset(1'b0),
.txphfifowrenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 0,
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.dprio_config_mode = 6'h01,
cent_unit0.in_xaui_mode = "false",
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_channel_bonding = "none",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "local reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_channel_bonding = "none",
cent_unit0.tx0_rd_clk_mux_select = "central",
cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_coreclk_out_post_divider = "false",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
cycloneiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(wire_receive_pcs0_clkout),
.coreclk(rx_coreclk_in[0]),
.coreclkout(),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[9:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.disperr(wire_receive_pcs0_disperr),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(wire_receive_pcs0_errdetect),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.k1detect(),
.k2detect(),
.localrefclk(tx_localrefclk[0]),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifooverflow(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipephydonestatus(),
.pipepowerdown({2{1'b0}}),
.pipepowerstate({4{1'b0}}),
.pipestatetransdoneout(),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.revbitorderwa(1'b0),
.revparallelfdbkdata(),
.rlv(wire_receive_pcs0_rlv),
.rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
.rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(wire_receive_pcs0_runningdisp),
.rxdetectvalid(1'b0),
.rxfound({2{1'b0}}),
.signaldetect(),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pipeenrevparallellpbkfromtx(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.refclk(1'b0),
.revbyteorderwa(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "1111100",
receive_pcs0.align_pattern_length = 7,
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "false",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 0,
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_enable = "false",
receive_pcs0.cdrctrl_mask_cycle = 800,
receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs0.cdrctrl_rxvalid_mask = "false",
receive_pcs0.channel_bonding = "none",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "local reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "basic",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "true",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.num_align_code_groups_in_ordered_set = 1,
receive_pcs0.num_align_cons_good_data = 4,
receive_pcs0.num_align_cons_pat = 3,
receive_pcs0.num_align_loss_sync_error = 4,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.protocol_hint = "gige",
receive_pcs0.rate_match_back_to_back = "true",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "true",
receive_pcs0.rate_match_pattern1 = "10100010010101111100",
receive_pcs0.rate_match_pattern2 = "10101011011010000011",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "false",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 5,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 15,
receive_pcs0.rxstatus_error_report_mode = 0,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
cycloneiv_hssi_rx_pma receive_pma0
(
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.crupowerdn(cent_unit_rxcrupowerdn[0]),
.datain(rx_datain[0]),
.datastrobeout(),
.deserclock(rx_deserclock_in[0]),
.diagnosticlpbkout(wire_receive_pma0_diagnosticlpbkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlocked(wire_receive_pma0_freqlocked),
.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(wire_receive_pma0_reverselpbkout),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbkin(tx_serialloopbackout[0]),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dpashift(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.effective_data_rate = "1250.0 Mbps",
receive_pma0.enable_local_divider = "false",
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.enable_second_order_loop = "false",
receive_pma0.eq_dc_gain = 0,
receive_pma0.eq_setting = 1,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.loop_1_digital_filter = 8,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppm_gen1_2_xcnt_en = 1,
receive_pma0.ppm_post_eidle = 0,
receive_pma0.ppmselect = 8,
receive_pma0.protocol_hint = "gige",
receive_pma0.signal_detect_hysteresis = 8,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 1,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_external_termination = "false",
receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
cycloneiv_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclk(tx_coreclk_in[0]),
.coreclkout(),
.ctrlenable({{1{1'b0}}, tx_ctrlenable[0]}),
.datain({{12{1'b0}}, tx_datain_wire[7:0]}),
.datainfull({22{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(1'b0),
.digitalreset(tx_digitalreset_out[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(1'b0),
.forcedisp({{1{1'b0}}, tx_forcedisp_wire[0]}),
.forceelecidleout(),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifooverflow(),
.phfiforddisable(1'b0),
.phfiforddisableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(),
.pipeenrevparallellpbkout(),
.pipepowerdownout(),
.pipepowerstateout(),
.pipestatetransdone(1'b0),
.powerdn({2{1'b0}}),
.quadreset(cent_unit_quadresetout[0]),
.rdenablesync(),
.revparallelfdbk({20{1'b0}}),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrlenable(),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.dispval({2{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.pipetxswing(1'b0),
.prbscidenable(1'b0),
.refclk(1'b0),
.xgmctrl(1'b0),
.xgmdatain({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "none",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "basic",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "none",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "true",
transmit_pcs0.enable_reverse_parallel_loopback = "false",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "gige",
transmit_pcs0.refclk_select = "local",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
cycloneiv_hssi_tx_pma transmit_pma0
(
.cgbpowerdn(cent_unit_txdividerpowerdown[0]),
.clockout(wire_transmit_pma0_clockout),
.datain({tx_dataout_pcs_to_pma[9:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.diagnosticlpbkin(tx_diagnosticlpbkin[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in(tx_pma_fastrefclk0in[0]),
.forceelecidle(1'b0),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in(tx_pma_refclk0in[0]),
.refclk0inpulse(tx_pma_refclk0inpulse[0]),
.reverselpbkin(rx_reverselpbkout[0]),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(),
.rxfoundout(),
.seriallpbkout(wire_transmit_pma0_seriallpbkout),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.effective_data_rate = "1250.0 Mbps",
transmit_pma0.enable_diagnostic_loopback = "false",
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.preemp_tap_1 = 1,
transmit_pma0.protocol_hint = "gige",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "medium",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_rx_detect = "false",
transmit_pma0.vod_selection = 1,
transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
// synopsys translate_off
initial
fixedclk_div = 0;
// synopsys translate_on
always @ ( posedge fixedclk)
fixedclk_div <= (~ fixedclk_div_in);
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
assign
cal_blk_powerdown = 1'b0,
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{900{1'b0}}, rx_pmadprioout[299:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]},
cent_unit_tx_dprioin = {{450{1'b0}}, tx_txdprioout[149:0]},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
cent_unit_txpmadprioin = {{900{1'b0}}, tx_pmadprioout[299:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]},
fixedclk_div_in = fixedclk_div,
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk))},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pll_locked = {wire_pll0_locked},
pll_powerdown = 1'b0,
reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
rx_clkout = {rx_clkout_wire[0]},
rx_clkout_wire = {wire_receive_pcs0_clkout},
rx_coreclk_in = {tx_core_clkout_wire[0]},
rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
rx_dataout = {rx_out_wire[7:0]},
rx_deserclock_in = {wire_pll0_icdrclk},
rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_disperr = {wire_receive_pcs0_disperr[0]},
rx_enapatternalign = 1'b0,
rx_errdetect = {wire_receive_pcs0_errdetect[0]},
rx_freqlocked = {(wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
rx_locktodata = 1'b0,
rx_locktorefclk = 1'b0,
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
rx_phfifordenable = 1'b1,
rx_phfiforeset = 1'b0,
rx_phfifowrdisable = 1'b0,
rx_pll_pfdrefclkout_wire = {wire_pll0_fref},
rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]},
rx_pma_clockout = {wire_receive_pma0_clockout},
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]},
rx_pmadprioin_wire = {{900{1'b0}}, cent_unit_rxpmadprioout[299:0]},
rx_pmadprioout = {{900{1'b0}}, wire_receive_pma0_dprioout},
rx_powerdown = 1'b0,
rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]},
rx_prbscidenable = 1'b0,
rx_recovclkout = {rx_pma_clockout[0]},
rx_reverselpbkout = {wire_receive_pma0_reverselpbkout},
rx_rlv = {wire_receive_pcs0_rlv},
rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]},
rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]},
rx_rmfiforeset = 1'b0,
rx_runningdisp = {wire_receive_pcs0_runningdisp[0]},
rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
tx_clkout = {tx_core_clkout_wire[0]},
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
tx_coreclk_in = {tx_clkout_int_wire[0]},
tx_datain_wire = {tx_datain[7:0]},
tx_dataout = {txdataout[0]},
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]},
tx_diagnosticlpbkin = {wire_receive_pma0_diagnosticlpbkout},
tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{450{1'b0}}, cent_unit_txdprioout[149:0]},
tx_forcedisp_wire = {1'b0},
tx_invpolarity = 1'b0,
tx_localrefclk = {wire_transmit_pma0_clockout},
tx_phfiforeset = 1'b0,
tx_pma_fastrefclk0in = {wire_pll0_clk[0]},
tx_pma_refclk0in = {wire_pll0_clk[1]},
tx_pma_refclk0inpulse = {wire_pll0_clk[2]},
tx_pmadprioin_wire = {{900{1'b0}}, cent_unit_txpmadprioout[299:0]},
tx_pmadprioout = {{900{1'b0}}, wire_transmit_pma0_dprioout},
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
txdataout = {wire_transmit_pma0_dataout},
txdetectrxout = {wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //altera_tse_altgx_civgx_gige_alt_c3gxb_g308
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_altgx_civgx_gige (
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_areset,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input [0:0] pll_areset;
input [0:0] pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [4:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
parameter starting_channel_number = 0;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [4:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [4:0] reconfig_fromgxb = sub_wire2[4:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
altera_tse_altgx_civgx_gige_alt_c3gxb_g308 altera_tse_altgx_civgx_gige_alt_c3gxb_g308_component (
.pll_inclk (pll_inclk),
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.fixedclk (fixedclk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pll_areset (pll_areset),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.fixedclk_fast (fixedclk_fast),
.tx_ctrlenable (tx_ctrlenable),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt_c3gxb
clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=125.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=High;pll_control_width=1;pll_inclk_period=8000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=1;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=1111100;rx_align_pattern_length=7;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=normal;rx_rate_match_pattern1=10100010010101111100;rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=8;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;
rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;equalization_setting=1;gxb_powerdown_width=1;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=1;pll_multiply_by=5;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_deskew_pattern=0;rx_dwidth_factor=1;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=altera_tse_altgx_civgx_gige;tx_bitslip_enable=FALSE;tx_dwidth_factor=1;tx_use_external_termination=false;" */;
defparam
altera_tse_altgx_civgx_gige_alt_c3gxb_g308_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: IP_MODE STRING "TSE"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "62.5 125.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "1111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "7"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "8"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: pll_divide_by STRING "1"
// Retrieval info: CONSTANT: pll_multiply_by STRING "5"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false"
// Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: top_module_name STRING "altera_tse_altgx_civgx_gige"
// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: fixedclk_fast 0 0 6 0 INPUT NODEFVAL "fixedclk_fast[5..0]"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk_fast 0 0 6 0 fixedclk_fast 0 0 6 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cycloneiv_hssi
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb
// ============================================================
// File Name: altera_tse_altgx_civgx_gige_wo_rmfifo.v
// Megafunction Name(s):
// alt_c3gxb
//
// Simulation Library Files(s):
// altera_mf;cycloneiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Internal Build 147 03/05/2012 PN Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="1111100" rx_align_pattern_length=7 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="none" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altera_tse_altgx_civgx_gige_wo_rmfifo" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_areset pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX"
//VERSION_BEGIN 12.0 cbx_alt_c3gxb 2012:03:05:21:09:17:PN cbx_altclkbuf 2012:03:05:21:09:17:PN cbx_altiobuf_bidir 2012:03:05:21:09:17:PN cbx_altiobuf_in 2012:03:05:21:09:17:PN cbx_altiobuf_out 2012:03:05:21:09:17:PN cbx_altpll 2012:03:05:21:09:17:PN cbx_cycloneii 2012:03:05:21:09:17:PN cbx_lpm_add_sub 2012:03:05:21:09:17:PN cbx_lpm_compare 2012:03:05:21:09:17:PN cbx_lpm_counter 2012:03:05:21:09:17:PN cbx_lpm_decode 2012:03:05:21:09:17:PN cbx_lpm_mux 2012:03:05:21:09:17:PN cbx_mgl 2012:03:05:22:13:55:PN cbx_stingray 2012:03:05:21:09:16:PN cbx_stratix 2012:03:05:21:09:18:PN cbx_stratixii 2012:03:05:21:09:18:PN cbx_stratixiii 2012:03:05:21:09:18:PN cbx_stratixv 2012:03:05:21:09:18:PN cbx_util_mgl 2012:03:05:21:09:17:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08
(
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_areset,
pll_inclk,
pll_locked,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_clkout,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_digitalreset) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
input fixedclk;
input [3:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input [0:0] pll_areset;
input [0:0] pll_inclk;
output [0:0] pll_locked;
input reconfig_clk;
output [4:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
output [0:0] rx_clkout;
output [0:0] rx_ctrldetect;
input [0:0] rx_datain;
output [7:0] rx_dataout;
input [0:0] rx_digitalreset;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
output [0:0] tx_dataout;
input [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri1 [3:0] fixedclk_fast;
tri0 [0:0] gxb_powerdown;
tri0 [0:0] pll_areset;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_digitalreset;
tri0 [0:0] tx_ctrlenable;
tri0 [7:0] tx_datain;
tri0 [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [5:0] wire_pll0_clk;
wire wire_pll0_fref;
wire wire_pll0_icdrclk;
wire wire_pll0_locked;
wire wire_cal_blk0_nonusertocmu;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_quadresetout;
wire [3:0] wire_cent_unit0_rxanalogresetout;
wire [3:0] wire_cent_unit0_rxcrupowerdown;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [3:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire [1199:0] wire_cent_unit0_rxpmadprioout;
wire [3:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [3:0] wire_cent_unit0_txdividerpowerdown;
wire [3:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire [1199:0] wire_cent_unit0_txpmadprioout;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_clkout;
wire [1:0] wire_receive_pcs0_ctrldetect;
wire [19:0] wire_receive_pcs0_dataout;
wire [1:0] wire_receive_pcs0_disperr;
wire [399:0] wire_receive_pcs0_dprioout;
wire [1:0] wire_receive_pcs0_errdetect;
wire [1:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_rlv;
wire [1:0] wire_receive_pcs0_rmfifodatadeleted;
wire [1:0] wire_receive_pcs0_rmfifodatainserted;
wire [1:0] wire_receive_pcs0_runningdisp;
wire [1:0] wire_receive_pcs0_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_diagnosticlpbkout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_freqlocked;
wire wire_receive_pma0_locktorefout;
wire [9:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_reverselpbkout;
wire wire_receive_pma0_signaldetect;
wire wire_transmit_pcs0_clkout;
wire [9:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_seriallpbkout;
reg [0:0] fixedclk_div;
reg [1:0] reconfig_togxb_busy_reg;
wire cal_blk_powerdown;
wire [0:0] cent_unit_quadresetout;
wire [3:0] cent_unit_rxcrupowerdn;
wire [3:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1199:0] cent_unit_rxpmadprioin;
wire [1199:0] cent_unit_rxpmadprioout;
wire [599:0] cent_unit_tx_dprioin;
wire [3:0] cent_unit_txdetectrxpowerdn;
wire [3:0] cent_unit_txdividerpowerdown;
wire [599:0] cent_unit_txdprioout;
wire [3:0] cent_unit_txobpowerdn;
wire [1199:0] cent_unit_txpmadprioin;
wire [1199:0] cent_unit_txpmadprioout;
wire [0:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [0:0] fixedclk_sel;
wire [3:0] fixedclk_to_cmu;
wire [0:0] nonusertocmu_out;
wire [0:0] pll_powerdown;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [3:0] rx_analogreset_in;
wire [3:0] rx_analogreset_out;
wire [0:0] rx_clkout_wire;
wire [0:0] rx_coreclk_in;
wire [0:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [0:0] rx_enapatternalign;
wire [0:0] rx_locktodata;
wire [0:0] rx_locktorefclk;
wire [0:0] rx_locktorefclk_wire;
wire [7:0] rx_out_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [0:0] rx_phfifordenable;
wire [0:0] rx_phfiforeset;
wire [0:0] rx_phfifowrdisable;
wire [0:0] rx_pll_pfdrefclkout_wire;
wire [4:0] rx_pma_analogtestbus;
wire [0:0] rx_pma_clockout;
wire [9:0] rx_pma_recoverdataout_wire;
wire [1199:0] rx_pmadprioin_wire;
wire [1199:0] rx_pmadprioout;
wire [0:0] rx_powerdown;
wire [3:0] rx_powerdown_in;
wire [0:0] rx_prbscidenable;
wire [0:0] rx_reverselpbkout;
wire [0:0] rx_signaldetect_wire;
wire [3:0] tx_analogreset_out;
wire [0:0] tx_clkout_int_wire;
wire [0:0] tx_core_clkout_wire;
wire [0:0] tx_coreclk_in;
wire [7:0] tx_datain_wire;
wire [9:0] tx_dataout_pcs_to_pma;
wire [0:0] tx_diagnosticlpbkin;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [599:0] tx_dprioin_wire;
wire [0:0] tx_forcedisp_wire;
wire [0:0] tx_invpolarity;
wire [0:0] tx_localrefclk;
wire [0:0] tx_phfiforeset;
wire [0:0] tx_pma_fastrefclk0in;
wire [0:0] tx_pma_refclk0in;
wire [0:0] tx_pma_refclk0inpulse;
wire [1199:0] tx_pmadprioin_wire;
wire [1199:0] tx_pmadprioout;
wire [0:0] tx_serialloopbackout;
wire [599:0] tx_txdprioout;
wire [0:0] txdataout;
wire [0:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
altpll pll0
(
.activeclock(),
.areset((pll_areset[0] | pll_powerdown[0])),
.clk(wire_pll0_clk),
.clkbad(),
.clkloss(),
.enable0(),
.enable1(),
.extclk(),
.fbout(),
.fref(wire_pll0_fref),
.icdrclk(wire_pll0_icdrclk),
.inclk({{1{1'b0}}, pll_inclk[0]}),
.locked(wire_pll0_locked),
.phasedone(),
.scandataout(),
.scandone(),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkena({6{1'b1}}),
.clkswitch(1'b0),
.configupdate(1'b0),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scanread(1'b0),
.scanwrite(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll0.bandwidth_type = "HIGH",
pll0.clk0_divide_by = 1,
pll0.clk0_multiply_by = 5,
pll0.clk1_divide_by = 5,
pll0.clk1_multiply_by = 5,
pll0.clk2_divide_by = 5,
pll0.clk2_duty_cycle = 20,
pll0.clk2_multiply_by = 5,
pll0.dpa_divide_by = 1,
pll0.dpa_multiply_by = 5,
pll0.inclk0_input_frequency = 8000,
pll0.operation_mode = "no_compensation",
pll0.intended_device_family = "Cyclone IV GX",
pll0.lpm_type = "altpll";
cycloneiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
cycloneiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.coreclkout(),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.fiforesetrd(),
.fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}),
.nonuserfromcal(nonusertocmu_out[0]),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkout(),
.rxanalogreset({rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifox4byteselout(),
.rxphfifox4rdenableout(),
.rxphfifox4wrclkout(),
.rxphfifox4wrenableout(),
.rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txctrl({4{1'b0}}),
.txctrlout(),
.txdatain({32{1'b0}}),
.txdataout(),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfifox4byteselout(),
.txphfifox4rdclkout(),
.txphfifox4rdenableout(),
.txphfifox4wrenableout(),
.txpmadprioin({cent_unit_txpmadprioin[1199:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.pmacramtest(1'b0),
.refclkdig(1'b0),
.rxcoreclk(1'b0),
.rxphfifordenable(1'b1),
.rxphfiforeset(1'b0),
.rxphfifowrdisable(1'b0),
.scanclk(1'b0),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({2000{1'b0}}),
.txclk(1'b0),
.txcoreclk(1'b0),
.txphfiforddisable(1'b0),
.txphfiforeset(1'b0),
.txphfifowrenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 0,
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.dprio_config_mode = 6'h01,
cent_unit0.in_xaui_mode = "false",
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_channel_bonding = "none",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "recovered clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_channel_bonding = "none",
cent_unit0.tx0_rd_clk_mux_select = "central",
cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_coreclk_out_post_divider = "false",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
cycloneiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(wire_receive_pcs0_clkout),
.coreclk(rx_coreclk_in[0]),
.coreclkout(),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[9:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.disperr(wire_receive_pcs0_disperr),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(wire_receive_pcs0_errdetect),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.k1detect(),
.k2detect(),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifooverflow(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipephydonestatus(),
.pipepowerdown({2{1'b0}}),
.pipepowerstate({4{1'b0}}),
.pipestatetransdoneout(),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.revbitorderwa(1'b0),
.revparallelfdbkdata(),
.rlv(wire_receive_pcs0_rlv),
.rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
.rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(1'b0),
.rmfifowrena(1'b0),
.runningdisp(wire_receive_pcs0_runningdisp),
.rxdetectvalid(1'b0),
.rxfound({2{1'b0}}),
.signaldetect(),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.localrefclk(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pipeenrevparallellpbkfromtx(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.refclk(1'b0),
.revbyteorderwa(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "1111100",
receive_pcs0.align_pattern_length = 7,
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "false",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 0,
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_enable = "false",
receive_pcs0.cdrctrl_mask_cycle = 800,
receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs0.cdrctrl_rxvalid_mask = "false",
receive_pcs0.channel_bonding = "none",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "recovered clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "basic",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "true",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.num_align_code_groups_in_ordered_set = 1,
receive_pcs0.num_align_cons_good_data = 4,
receive_pcs0.num_align_cons_pat = 3,
receive_pcs0.num_align_loss_sync_error = 4,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.protocol_hint = "gige",
receive_pcs0.rate_match_back_to_back = "true",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "false",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "true",
receive_pcs0.rate_match_pattern1 = "10100010010101111100",
receive_pcs0.rate_match_pattern2 = "10101011011010000011",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "false",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 5,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 15,
receive_pcs0.rxstatus_error_report_mode = 0,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
cycloneiv_hssi_rx_pma receive_pma0
(
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.crupowerdn(cent_unit_rxcrupowerdn[0]),
.datain(rx_datain[0]),
.datastrobeout(),
.deserclock(rx_deserclock_in[0]),
.diagnosticlpbkout(wire_receive_pma0_diagnosticlpbkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlocked(wire_receive_pma0_freqlocked),
.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(wire_receive_pma0_reverselpbkout),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbkin(tx_serialloopbackout[0]),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dpashift(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.effective_data_rate = "1250.0 Mbps",
receive_pma0.enable_local_divider = "false",
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.enable_second_order_loop = "false",
receive_pma0.eq_dc_gain = 0,
receive_pma0.eq_setting = 1,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.loop_1_digital_filter = 8,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppm_gen1_2_xcnt_en = 1,
receive_pma0.ppm_post_eidle = 0,
receive_pma0.ppmselect = 8,
receive_pma0.protocol_hint = "gige",
receive_pma0.signal_detect_hysteresis = 8,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 1,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_external_termination = "false",
receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
cycloneiv_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclk(tx_coreclk_in[0]),
.coreclkout(),
.ctrlenable({{1{1'b0}}, tx_ctrlenable[0]}),
.datain({{12{1'b0}}, tx_datain_wire[7:0]}),
.datainfull({22{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(1'b0),
.digitalreset(tx_digitalreset_out[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(1'b0),
.forcedisp({{1{1'b0}}, tx_forcedisp_wire[0]}),
.forceelecidleout(),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifooverflow(),
.phfiforddisable(1'b0),
.phfiforddisableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(),
.pipeenrevparallellpbkout(),
.pipepowerdownout(),
.pipepowerstateout(),
.pipestatetransdone(1'b0),
.powerdn({2{1'b0}}),
.quadreset(cent_unit_quadresetout[0]),
.rdenablesync(),
.revparallelfdbk({20{1'b0}}),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrlenable(),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.dispval({2{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.pipetxswing(1'b0),
.prbscidenable(1'b0),
.refclk(1'b0),
.xgmctrl(1'b0),
.xgmdatain({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "none",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "basic",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "none",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "true",
transmit_pcs0.enable_reverse_parallel_loopback = "false",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "gige",
transmit_pcs0.refclk_select = "local",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
cycloneiv_hssi_tx_pma transmit_pma0
(
.cgbpowerdn(cent_unit_txdividerpowerdown[0]),
.clockout(wire_transmit_pma0_clockout),
.datain({tx_dataout_pcs_to_pma[9:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.diagnosticlpbkin(tx_diagnosticlpbkin[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in(tx_pma_fastrefclk0in[0]),
.forceelecidle(1'b0),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in(tx_pma_refclk0in[0]),
.refclk0inpulse(tx_pma_refclk0inpulse[0]),
.reverselpbkin(rx_reverselpbkout[0]),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(),
.rxfoundout(),
.seriallpbkout(wire_transmit_pma0_seriallpbkout),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.effective_data_rate = "1250.0 Mbps",
transmit_pma0.enable_diagnostic_loopback = "false",
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.preemp_tap_1 = 1,
transmit_pma0.protocol_hint = "gige",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "medium",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_rx_detect = "false",
transmit_pma0.vod_selection = 1,
transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
// synopsys translate_off
initial
fixedclk_div = 0;
// synopsys translate_on
always @ ( posedge fixedclk)
fixedclk_div <= (~ fixedclk_div_in);
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
assign
cal_blk_powerdown = 1'b0,
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{900{1'b0}}, rx_pmadprioout[299:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]},
cent_unit_tx_dprioin = {{450{1'b0}}, tx_txdprioout[149:0]},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
cent_unit_txpmadprioin = {{900{1'b0}}, tx_pmadprioout[299:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]},
fixedclk_div_in = fixedclk_div,
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk))},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pll_locked = {wire_pll0_locked},
pll_powerdown = 1'b0,
reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
rx_clkout = {rx_clkout_wire[0]},
rx_clkout_wire = {wire_receive_pcs0_clkout},
rx_coreclk_in = {rx_clkout_wire[0]},
rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
rx_dataout = {rx_out_wire[7:0]},
rx_deserclock_in = {wire_pll0_icdrclk},
rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_disperr = {wire_receive_pcs0_disperr[0]},
rx_enapatternalign = 1'b0,
rx_errdetect = {wire_receive_pcs0_errdetect[0]},
rx_freqlocked = {(wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
rx_locktodata = 1'b0,
rx_locktorefclk = 1'b0,
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
rx_phfifordenable = 1'b1,
rx_phfiforeset = 1'b0,
rx_phfifowrdisable = 1'b0,
rx_pll_pfdrefclkout_wire = {wire_pll0_fref},
rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]},
rx_pma_clockout = {wire_receive_pma0_clockout},
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]},
rx_pmadprioin_wire = {{900{1'b0}}, cent_unit_rxpmadprioout[299:0]},
rx_pmadprioout = {{900{1'b0}}, wire_receive_pma0_dprioout},
rx_powerdown = 1'b0,
rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]},
rx_prbscidenable = 1'b0,
rx_recovclkout = {rx_pma_clockout[0]},
rx_reverselpbkout = {wire_receive_pma0_reverselpbkout},
rx_rlv = {wire_receive_pcs0_rlv},
rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]},
rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]},
rx_runningdisp = {wire_receive_pcs0_runningdisp[0]},
rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
tx_clkout = {tx_core_clkout_wire[0]},
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
tx_coreclk_in = {tx_clkout_int_wire[0]},
tx_datain_wire = {tx_datain[7:0]},
tx_dataout = {txdataout[0]},
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]},
tx_diagnosticlpbkin = {wire_receive_pma0_diagnosticlpbkout},
tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{450{1'b0}}, cent_unit_txdprioout[149:0]},
tx_forcedisp_wire = {1'b0},
tx_invpolarity = 1'b0,
tx_localrefclk = {wire_transmit_pma0_clockout},
tx_phfiforeset = 1'b0,
tx_pma_fastrefclk0in = {wire_pll0_clk[0]},
tx_pma_refclk0in = {wire_pll0_clk[1]},
tx_pma_refclk0inpulse = {wire_pll0_clk[2]},
tx_pmadprioin_wire = {{900{1'b0}}, cent_unit_txpmadprioout[299:0]},
tx_pmadprioout = {{900{1'b0}}, wire_transmit_pma0_dprioout},
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
txdataout = {wire_transmit_pma0_dataout},
txdetectrxout = {wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_altgx_civgx_gige_wo_rmfifo (
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_areset,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input [0:0] pll_areset;
input [0:0] pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [4:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
parameter starting_channel_number = 0;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [4:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [4:0] reconfig_fromgxb = sub_wire2[4:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08 altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08_component (
.pll_inclk (pll_inclk),
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.fixedclk (fixedclk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pll_areset (pll_areset),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.fixedclk_fast (fixedclk_fast),
.tx_ctrlenable (tx_ctrlenable),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt_c3gxb
clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=125.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=High;pll_control_width=1;pll_inclk_period=8000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=1;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=1111100;rx_align_pattern_length=7;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=none;rx_rate_match_pattern1=10100010010101111100;rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=8;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;
rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;equalization_setting=1;gxb_powerdown_width=1;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=1;pll_multiply_by=5;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_deskew_pattern=0;rx_dwidth_factor=1;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=altera_tse_altgx_civgx_gige_wo_rmfifo;tx_bitslip_enable=FALSE;tx_dwidth_factor=1;tx_use_external_termination=false;" */;
defparam
altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: IP_MODE STRING "TSE"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "62.5 125.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "1111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "7"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "none"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "8"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: pll_divide_by STRING "1"
// Retrieval info: CONSTANT: pll_multiply_by STRING "5"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false"
// Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: top_module_name STRING "altera_tse_altgx_civgx_gige_wo_rmfifo"
// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: fixedclk_fast 0 0 6 0 INPUT NODEFVAL "fixedclk_fast[5..0]"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk_fast 0 0 6 0 fixedclk_fast 0 0 6 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_wo_rmfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_wo_rmfifo.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_wo_rmfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_wo_rmfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_wo_rmfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_wo_rmfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_wo_rmfifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cycloneiv_hssi
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Siew Kong NG
//
// Project : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description :
//
// RX_SYNC alignment for Alt2gxb, Alt4gxb
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
module altera_tse_gxb_aligned_rxsync (
input clk,
input reset,
input [7:0] alt_dataout,
input alt_sync,
input alt_disperr,
input alt_ctrldetect,
input alt_errdetect,
input alt_rmfifodatadeleted,
input alt_rmfifodatainserted,
input alt_runlengthviolation,
input alt_patterndetect,
input alt_runningdisp,
output reg [7:0] altpcs_dataout,
output altpcs_sync,
output reg altpcs_disperr,
output reg altpcs_ctrldetect,
output reg altpcs_errdetect,
output reg altpcs_rmfifodatadeleted,
output reg altpcs_rmfifodatainserted,
output reg altpcs_carrierdetect) ;
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
//-------------------------------------------------------------------------------
// intermediate wires
//reg altpcs_dataout
// pipelined 1
reg [7:0] alt_dataout_reg1;
reg alt_sync_reg1;
reg alt_sync_reg2;
reg alt_disperr_reg1;
reg alt_ctrldetect_reg1;
reg alt_errdetect_reg1;
reg alt_rmfifodatadeleted_reg1;
reg alt_rmfifodatainserted_reg1;
reg alt_patterndetect_reg1;
reg alt_runningdisp_reg1;
reg alt_runlengthviolation_latched;
//-------------------------------------------------------------------------------
always @(posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
// pipelined 1
alt_dataout_reg1 <= 8'h0;
alt_sync_reg1 <= 1'b0;
alt_disperr_reg1 <= 1'b0;
alt_ctrldetect_reg1 <= 1'b0;
alt_errdetect_reg1 <= 1'b0;
alt_rmfifodatadeleted_reg1 <= 1'b0;
alt_rmfifodatainserted_reg1 <= 1'b0;
alt_patterndetect_reg1 <= 1'b0;
alt_runningdisp_reg1 <= 1'b0;
end
else
begin
// pipelined 1
alt_dataout_reg1 <= alt_dataout;
alt_sync_reg1 <= alt_sync;
alt_disperr_reg1 <= alt_disperr;
alt_ctrldetect_reg1 <= alt_ctrldetect;
alt_errdetect_reg1 <= alt_errdetect;
alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;
alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
alt_patterndetect_reg1 <= alt_patterndetect;
alt_runningdisp_reg1 <= alt_runningdisp;
end
end
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX" )
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
else
begin
if (alt_sync == 1'b1 )
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
end
else
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
end
end
assign altpcs_sync = alt_sync_reg1;
end
else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGZ" || DEVICE_FAMILY == "STRATIXV" || DEVICE_FAMILY == "ARRIAV" || DEVICE_FAMILY == "ARRIAVGZ" || DEVICE_FAMILY == "CYCLONEV")
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
alt_sync_reg2 <= 1'b0;
end
else
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
alt_sync_reg2 <= alt_sync_reg1 ;
end
end
assign altpcs_sync = alt_sync_reg2;
end
endgenerate
//latched runlength violation assertion for "carrier_detect" signal generation block
//reset the latch value after carrier_detect goes de-asserted
// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
// begin
// if (altpcs_carrierdetect == 1'b0)
// begin
// alt_runlengthviolation_latched <= 1'b0;
// end
// else
// begin
// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
// begin
// alt_runlengthviolation_latched <= 1'b1;
// end
// end
// end
// always @ (posedge reset or posedge clk)
// begin
// if (reset == 1'b1)
// begin
// alt_runlengthviolation_latched_reg <= 1'b0;
// end
// else
// begin
// alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;
// end
// end
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
begin
alt_runlengthviolation_latched <= 1'b1;
end
end
end
end
// carrier_detect signal generation
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_carrierdetect <= 1'b1;
end
else
// This portion of code is to workaround the issue with PHYIP (hard PCS) for not implementing the carrier_detect,
// which suppose to be implemented based on 10b character, not 8b.
//
// The real challenge is to detect the /INVALID/ 10b code group
//
// This is the Table 36.3.2.1 in UNH test plan
// =====================================================
// RD- code-group RD+ code-group
// =====================================================
// 001111 1010 /K28.5/ 110000 0101 /K28.5/
// 001111 1011 /INVALID/ 110000 0100 /INVALID/
// 001111 1000 /K28.7/ 110000 0111 /K28.7/
// 001111 1110 /INVALID/ 110000 0001 /INVALID/
// 001111 0010 /K28.4/ 110000 1101 /K28.4/
// 001110 1010 /D28.5/ 110001 0101 /D3.2/
// 001101 1010 /D12.5/ 110010 0101 /D19.2/
// 001011 1010 /D20.5/ 110100 0101 /D11.2/
// 000111 1010 /D7.5/ 111000 0101 /D7.2/
// 011111 1010 /INVALID/ 100000 0101 /INVALID/
// 101111 1010 /INVALID/ 010000 0101 /INVALID/
begin
if ( (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
& alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
& alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
)
begin
altpcs_carrierdetect <= 1'b0;
end
else
begin
altpcs_carrierdetect <= 1'b1;
end
end
end
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_gxb_gige_inst.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_gxb_gige_inst.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Siew Kong NG
//
// Project : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description :
//
// Instantiation for Alt2gxb, Alt4gxb
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module altera_tse_gxb_gige_inst (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_powerdown,
pll_locked,
rx_freqlocked,
reconfig_fromgxb,
rx_ctrldetect,
rx_clkout,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_syncstatus,
tx_clkout,
tx_dataout,
rx_recovclkout,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp
);
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter STARTING_CHANNEL_NUMBER = 0;
parameter ENABLE_ALT_RECONFIG = 0;
parameter ENABLE_SGMII = 1; // Use to determine rate match FIFO in ALTGX GIGE mode
input cal_blk_clk;
input gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input rx_analogreset;
input rx_cruclk;
input rx_datain;
input rx_digitalreset;
input rx_seriallpbken;
input tx_ctrlenable;
input [7:0] tx_datain;
input tx_digitalreset;
input pll_powerdown;
output pll_locked;
output rx_freqlocked;
output [16:0] reconfig_fromgxb;
output rx_ctrldetect;
output rx_clkout;
output [7:0] rx_dataout;
output rx_disperr;
output rx_errdetect;
output rx_patterndetect;
output rx_rlv;
output rx_syncstatus;
output tx_clkout;
output tx_dataout;
output rx_recovclkout;
output rx_rmfifodatadeleted;
output rx_rmfifodatainserted;
output rx_runningdisp;
wire [16:0] reconfig_fromgxb;
wire [2:0] reconfig_togxb_alt2gxb;
wire reconfig_fromgxb_alt2gxb;
wire wire_reconfig_clk;
wire [3:0] wire_reconfig_togxb;
(* altera_attribute = "-name MESSAGE_DISABLE 10036" *)
wire [16:0] wire_reconfig_fromgxb;
generate if (ENABLE_ALT_RECONFIG == 0)
begin
assign wire_reconfig_clk = 1'b0;
assign wire_reconfig_togxb = 4'b0010;
assign reconfig_fromgxb = {17{1'b0}};
end
else
begin
assign wire_reconfig_clk = reconfig_clk;
assign wire_reconfig_togxb = reconfig_togxb;
assign reconfig_fromgxb = wire_reconfig_fromgxb;
end
endgenerate
generate if ((DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX") && (ENABLE_SGMII == 0))
begin
altera_tse_alt2gxb_gige the_altera_tse_alt2gxb_gige
(
.cal_blk_clk (cal_blk_clk),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(reconfig_togxb_alt2gxb),
.reconfig_fromgxb(reconfig_fromgxb_alt2gxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp),
.rx_freqlocked(rx_freqlocked),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_alt2gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER,
the_altera_tse_alt2gxb_gige.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG;
assign reconfig_togxb_alt2gxb = wire_reconfig_togxb[2:0];
assign wire_reconfig_fromgxb = {{16{1'b0}}, reconfig_fromgxb_alt2gxb};
assign rx_clkout = tx_clkout;
end
endgenerate
generate if ((DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX") && (ENABLE_SGMII == 1))
begin
altera_tse_alt2gxb_gige_wo_rmfifo the_altera_tse_alt2gxb_gige_wo_rmfifo
(
.cal_blk_clk (cal_blk_clk),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(reconfig_togxb_alt2gxb),
.reconfig_fromgxb(reconfig_fromgxb_alt2gxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_clkout (rx_clkout),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(),
.rx_rmfifodatainserted(),
.rx_runningdisp(rx_runningdisp),
.rx_freqlocked(rx_freqlocked),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_alt2gxb_gige_wo_rmfifo.starting_channel_number = STARTING_CHANNEL_NUMBER,
the_altera_tse_alt2gxb_gige_wo_rmfifo.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG;
assign reconfig_togxb_alt2gxb = wire_reconfig_togxb[2:0];
assign wire_reconfig_fromgxb = {{16{1'b0}}, reconfig_fromgxb_alt2gxb};
assign rx_rmfifodatadeleted = 1'b0;
assign rx_rmfifodatainserted = 1'b0;
end
endgenerate
generate if ((DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "ARRIAIIGZ") && (ENABLE_SGMII == 0))
begin
altera_tse_alt4gxb_gige the_altera_tse_alt4gxb_gige
(
.cal_blk_clk (cal_blk_clk),
.fixedclk(wire_reconfig_clk),
.fixedclk_fast(6'b0),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.reconfig_fromgxb(wire_reconfig_fromgxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp),
.pll_powerdown(pll_powerdown),
.rx_freqlocked(rx_freqlocked),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_alt4gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER;
assign rx_clkout = tx_clkout;
end
endgenerate
generate if ((DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "ARRIAIIGZ" ) && (ENABLE_SGMII == 1))
begin
altera_tse_alt4gxb_gige_wo_rmfifo the_altera_tse_alt4gxb_gige_wo_rmfifo
(
.cal_blk_clk (cal_blk_clk),
.fixedclk(wire_reconfig_clk),
.fixedclk_fast(6'b0),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.reconfig_fromgxb(wire_reconfig_fromgxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_clkout (rx_clkout),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(),
.rx_rmfifodatainserted(),
.rx_runningdisp(rx_runningdisp),
.pll_powerdown(pll_powerdown),
.rx_freqlocked(rx_freqlocked),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_alt4gxb_gige_wo_rmfifo.starting_channel_number = STARTING_CHANNEL_NUMBER;
assign rx_rmfifodatadeleted = 1'b0;
assign rx_rmfifodatainserted = 1'b0;
end
endgenerate
generate if ((DEVICE_FAMILY == "CYCLONEIVGX") && (ENABLE_SGMII == 0))
begin
altera_tse_altgx_civgx_gige the_altera_tse_alt_gx_civgx
(
.cal_blk_clk (cal_blk_clk),
.fixedclk(wire_reconfig_clk),
.fixedclk_fast(1'b0),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.rx_analogreset (rx_analogreset),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.reconfig_fromgxb(wire_reconfig_fromgxb[4:0]),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp),
.pll_areset(pll_powerdown),
.rx_freqlocked(rx_freqlocked),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_alt_gx_civgx.starting_channel_number = STARTING_CHANNEL_NUMBER;
assign rx_clkout = tx_clkout;
end
endgenerate
generate if ((DEVICE_FAMILY == "CYCLONEIVGX") && (ENABLE_SGMII == 1))
begin
altera_tse_altgx_civgx_gige_wo_rmfifo the_altera_tse_alt_gx_civgx_wo_rmfifo
(
.cal_blk_clk (cal_blk_clk),
.fixedclk(wire_reconfig_clk),
.fixedclk_fast(1'b0),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.rx_analogreset (rx_analogreset),
.rx_ctrldetect (rx_ctrldetect),
.rx_clkout (rx_clkout),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.reconfig_fromgxb(wire_reconfig_fromgxb[4:0]),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(),
.rx_rmfifodatainserted(),
.rx_runningdisp(rx_runningdisp),
.pll_areset(pll_powerdown),
.rx_freqlocked(rx_freqlocked),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_alt_gx_civgx_wo_rmfifo.starting_channel_number = STARTING_CHANNEL_NUMBER;
assign rx_rmfifodatadeleted = 1'b0;
assign rx_rmfifodatainserted = 1'b0;
end
endgenerate
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_gxb_gige_inst.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_gxb_gige_phyip_inst.v,v $
//
// $Revision: #23 $
// $Date: 2010/09/05 $
// Check in by : $Author: sxsaw $
// Author : Siew Kong NG
//
// Project : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description :
//
// Instantiation for Alt2gxb, Alt4gxb
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module altera_tse_gxb_gige_phyip_inst (
phy_mgmt_clk,
phy_mgmt_clk_reset,
phy_mgmt_address,
phy_mgmt_read,
phy_mgmt_readdata,
phy_mgmt_waitrequest,
phy_mgmt_write,
phy_mgmt_writedata,
tx_ready,
rx_ready,
pll_ref_clk,
pll_locked,
tx_serial_data,
rx_serial_data,
rx_runningdisp,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_syncstatus,
tx_clkout,
rx_clkout,
tx_parallel_data,
tx_datak,
rx_parallel_data,
rx_datak,
rx_rlv,
rx_recovclkout,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
reconfig_togxb,
reconfig_fromgxb,
wa_boundary
);
parameter DEVICE_FAMILY = "STRATIXV"; // The device family the the core is targetted for.
parameter ENABLE_ALT_RECONFIG = 0;
parameter ENABLE_SGMII = 1; // Use to determine rate match FIFO in ALTGX GIGE mode
input phy_mgmt_clk;
input phy_mgmt_clk_reset;
input [8:0]phy_mgmt_address;
input phy_mgmt_read;
output [31:0]phy_mgmt_readdata;
output phy_mgmt_waitrequest;
input phy_mgmt_write;
input [31:0]phy_mgmt_writedata;
output tx_ready;
output rx_ready;
input pll_ref_clk;
output pll_locked;
output tx_serial_data;
input rx_serial_data;
output rx_runningdisp;
output rx_disperr;
output rx_errdetect;
output rx_patterndetect;
output rx_syncstatus;
output tx_clkout;
output rx_clkout;
input [7:0] tx_parallel_data;
input tx_datak;
output [7:0] rx_parallel_data;
output rx_datak;
output rx_rlv;
output rx_recovclkout;
output rx_rmfifodatadeleted;
output rx_rmfifodatainserted;
input [139:0]reconfig_togxb;
output [91:0]reconfig_fromgxb;
output wire [4:0] wa_boundary;
wire [91:0] reconfig_fromgxb;
wire [139:0] wire_reconfig_togxb;
(* altera_attribute = "-name MESSAGE_DISABLE 10036" *)
wire [91:0] wire_reconfig_fromgxb;
generate if (ENABLE_ALT_RECONFIG == 0)
begin
assign wire_reconfig_togxb = 140'd0;
assign reconfig_fromgxb = 92'd0;
end
else
begin
assign wire_reconfig_togxb = reconfig_togxb;
assign reconfig_fromgxb = wire_reconfig_fromgxb;
end
endgenerate
generate if (ENABLE_SGMII == 0)
begin
altera_tse_phyip_gxb the_altera_tse_phyip_gxb (
.phy_mgmt_clk(phy_mgmt_clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset(phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
.phy_mgmt_read(phy_mgmt_read), // .read
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
.phy_mgmt_write(phy_mgmt_write), // .write
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
.tx_ready(tx_ready), // tx_ready.export
.rx_ready(rx_ready), // rx_ready.export
.pll_ref_clk(pll_ref_clk), // pll_ref_clk.clk
.pll_locked(pll_locked), // pll_locked.export
.tx_serial_data(tx_serial_data), // tx_serial_data.export
.rx_serial_data(rx_serial_data), // rx_serial_data.export
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
.rx_disperr(rx_disperr), // rx_disperr.export
.rx_errdetect(rx_errdetect), // rx_errdetect.export
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
.tx_clkout(tx_clkout), // tx_clkout.clk
.tx_parallel_data(tx_parallel_data), // tx_parallel_data.data
.tx_datak(tx_datak), // tx_datak.data
.rx_parallel_data(rx_parallel_data), // rx_parallel_data.data
.rx_datak(rx_datak), // rx_datak.data
.rx_rlv(rx_rlv),
.rx_recovered_clk(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.reconfig_to_xcvr(wire_reconfig_togxb),
.reconfig_from_xcvr(wire_reconfig_fromgxb)
);
assign rx_clkout = tx_clkout;
end
endgenerate
generate if (ENABLE_SGMII == 1)
begin
altera_tse_phyip_gxb_wo_rmfifo the_altera_tse_phyip_gxb_wo_rmfifo (
.phy_mgmt_clk(phy_mgmt_clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset(phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
.phy_mgmt_read(phy_mgmt_read), // .read
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
.phy_mgmt_write(phy_mgmt_write), // .write
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
.tx_ready(tx_ready), // tx_ready.export
.rx_ready(rx_ready), // rx_ready.export
.pll_ref_clk(pll_ref_clk), // pll_ref_clk.clk
.pll_locked(pll_locked), // pll_locked.export
.tx_serial_data(tx_serial_data), // tx_serial_data.export
.rx_serial_data(rx_serial_data), // rx_serial_data.export
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
.rx_disperr(rx_disperr), // rx_disperr.export
.rx_errdetect(rx_errdetect), // rx_errdetect.export
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
.tx_clkout(tx_clkout), // tx_clkout.clk
.rx_clkout(rx_clkout), // rx_clkout.clk
.tx_parallel_data(tx_parallel_data), // tx_parallel_data.data
.tx_datak(tx_datak), // tx_datak.data
.rx_parallel_data(rx_parallel_data), // rx_parallel_data.data
.rx_datak(rx_datak), // rx_datak.data
.rx_rlv(rx_rlv),
.rx_recovered_clk(rx_recovclkout),
.reconfig_to_xcvr(wire_reconfig_togxb),
.reconfig_from_xcvr(wire_reconfig_fromgxb),
.rx_bitslipboundaryselectout(wa_boundary) // output needed by IEEE1588 to determine latency across word aligner
);
assign rx_rmfifodatadeleted = 1'b0;
assign rx_rmfifodatainserted = 1'b0;
end
endgenerate
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
module altera_tse_lvds_reset_sequencer (
clk,
reset,
rx_locked,
rx_channel_data_align,
pll_areset,
rx_reset,
rx_cda_reset,
rx_reset_sequence_done,
);
input clk;
input reset;
input rx_locked;
output rx_channel_data_align;
output pll_areset;
output rx_reset;
output rx_cda_reset;
output rx_reset_sequence_done;
reg rx_channel_data_align;
reg pll_areset;
reg rx_reset;
reg rx_cda_reset;
reg rx_reset_sequence_done;
wire rx_locked_sync;
reg rx_locked_sync_d1;
reg rx_locked_sync_d2;
reg rx_locked_sync_d3;
reg rx_locked_stable;
reg [2:0] pulse_count;
reg [2:0] state;
reg [2:0] nextstate;
// State Definitions
parameter [2:0] stm_idle = 3'b000; //0
parameter [2:0] stm_pll_areset = 3'b001; //1
parameter [2:0] stm_rx_reset = 3'b010; //2
parameter [2:0] stm_rx_cda_reset = 3'b011; //3
parameter [2:0] stm_word_alignment = 3'b100; //4
altera_std_synchronizer #(2) rx_locked_altera_std_synchronizer (
.clk ( clk ),
.reset_n ( ~reset ),
.din ( rx_locked ),
.dout ( rx_locked_sync )
);
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
rx_reset_sequence_done <= 1'b0;
end
else begin
if (state == stm_idle)
begin
rx_reset_sequence_done <= 1'b1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
rx_locked_sync_d1 <= 1'b0;
rx_locked_sync_d2 <= 1'b0;
rx_locked_sync_d3 <= 1'b0;
end
else begin
rx_locked_sync_d1 <= rx_locked_sync;
rx_locked_sync_d2 <= rx_locked_sync_d1;
rx_locked_sync_d3 <= rx_locked_sync_d2;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
rx_locked_stable <= 1'b0;
end
else begin
rx_locked_stable <= rx_locked_sync & rx_locked_sync_d1 & rx_locked_sync_d2 & rx_locked_sync_d3;
end
end
// FSM
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
state <= stm_pll_areset;
end
else begin
state <= nextstate;
end
end
always @ (*)
begin
case (state)
stm_idle:
if (reset == 1'b1) begin
nextstate = stm_pll_areset;
end
else begin
nextstate = stm_idle;
end
stm_pll_areset:
begin
nextstate = stm_rx_reset;
end
stm_rx_reset:
if (rx_locked_stable == 1'b0) begin
nextstate = stm_rx_reset;
end
else begin
nextstate = stm_rx_cda_reset;
end
stm_rx_cda_reset:
begin
nextstate = stm_word_alignment;
end
stm_word_alignment:
if (pulse_count == 4) begin
nextstate = stm_idle;
end
else begin
nextstate = stm_word_alignment;
end
default:
begin
nextstate = stm_idle;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
pll_areset <= 1'b1;
rx_reset <= 1'b1;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
else begin
case (nextstate)
stm_idle:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_pll_areset:
begin
pll_areset <= 1'b1;
rx_reset <= 1'b1;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_rx_reset:
begin
pll_areset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_rx_cda_reset:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b1;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_word_alignment:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= ~rx_channel_data_align;
pulse_count <= pulse_count +1'b1;
end
default:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
endcase
end
end
endmodule
|
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module altera_tse_lvds_reverse_loopback
(
input reset_wclk,
input reset_rclk,
input wclk,
input rclk,
input [9:0] tbi_rx_clk,
output [9:0] tbi_tx_clk
);
localparam COMMAP = 7'b 1111100;
localparam COMMAN = 7'b 0000011;
localparam D16_2P = 10'b 1010110110;
localparam D16_2N = 10'b 1010001001;
wire [9:0] tbi_rx_clk_aligned;
reg [9:0] tbi_rx_clk_aligned_reg_0;
reg [9:0] tbi_rx_clk_aligned_reg_1;
wire [9:0] tbi_tx_clk_reg_in;
reg [9:0] tbi_tx_clk_reg_0;
reg [9:0] tbi_tx_clk_reg_1;
wire [9:0] tbi_rx_clk_flipped;
wire [9:0] tbi_din;
wire [9:0] tbi_dout;
wire ff_wren;
wire ff_rden;
wire ff_afull;
wire ff_aempty;
wire rm_insert;
reg rm_insert_d0;
reg rm_insert_d1;
wire rm_delete;
reg rm_delete_d;
wire tx_idle_detect;
wire rx_idle_detect;
// /I2/ detect for rate-match implementation
assign tx_idle_detect =
(tbi_tx_clk_reg_1[6:0] == COMMAP && tbi_tx_clk_reg_0 == D16_2N) ||
(tbi_tx_clk_reg_1[6:0] == COMMAN && tbi_tx_clk_reg_0 == D16_2P);
assign rx_idle_detect =
(tbi_rx_clk_aligned_reg_1[6:0] == COMMAP && tbi_rx_clk_aligned_reg_0 == D16_2N) ||
(tbi_rx_clk_aligned_reg_1[6:0] == COMMAN && tbi_rx_clk_aligned_reg_0 == D16_2P);
// Rate-match insert and delete equation
assign rm_delete = ff_afull & rx_idle_detect;
assign rm_insert = ff_aempty & tx_idle_detect;
always @(posedge reset_wclk or posedge wclk)
begin
if (reset_wclk == 1'b 1)
rm_delete_d <= 1'b0;
else
rm_delete_d <= rm_delete;
end
always @(posedge reset_rclk or posedge rclk)
begin
if (reset_rclk == 1'b 1)
begin
rm_insert_d0 <= 1'b0;
rm_insert_d1 <= 1'b0;
end
else
begin
rm_insert_d0 <= rm_insert;
rm_insert_d1 <= rm_insert_d0;
end
end
// Don't write to FIFO if rate-match delete happened (2 clock cycles for /I2/ order set)
assign ff_wren = ~ (rm_delete_d | rm_delete);
// Don't read from FIFO if rate-match insert happened (2 clock cycles for /I2/ order set)
assign ff_rden = ~ (rm_insert_d0 | rm_insert);
// If rate-match insert happended, duplicated the /I2/ order set by loopback tbi_tx_clk_reg_1 to tbi_tx_clk_reg_0
// for 2 clock cycles.
assign tbi_tx_clk_reg_in = (rm_insert_d0 | rm_insert_d1) ? tbi_tx_clk_reg_1: tbi_dout;
assign tbi_din = tbi_rx_clk_aligned_reg_1;
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm
assign tbi_rx_clk_flipped = {
tbi_rx_clk[0],
tbi_rx_clk[1],
tbi_rx_clk[2],
tbi_rx_clk[3],
tbi_rx_clk[4],
tbi_rx_clk[5],
tbi_rx_clk[6],
tbi_rx_clk[7],
tbi_rx_clk[8],
tbi_rx_clk[9]
};
assign tbi_tx_clk = {
tbi_tx_clk_reg_1[0],
tbi_tx_clk_reg_1[1],
tbi_tx_clk_reg_1[2],
tbi_tx_clk_reg_1[3],
tbi_tx_clk_reg_1[4],
tbi_tx_clk_reg_1[5],
tbi_tx_clk_reg_1[6],
tbi_tx_clk_reg_1[7],
tbi_tx_clk_reg_1[8],
tbi_tx_clk_reg_1[9]
};
// Align the 10 bit rx data to COMMA
altera_tse_align_sync
U_TBI_ALIGN (
.rst_align (reset_wclk),
.din (tbi_rx_clk_flipped),
.dout (tbi_rx_clk_aligned),
.sync (), // UNUSED
.ce (1'b1),
.clk (wclk),
.sw_reset (1'b0),
.rst (reset_wclk)
);
// Flop the aligned rx data
always @(posedge reset_wclk or posedge wclk)
begin
if (reset_wclk == 1'b 1)
begin
tbi_rx_clk_aligned_reg_0 <= 10'b0;
tbi_rx_clk_aligned_reg_1 <= 10'b0;
end
else
begin
tbi_rx_clk_aligned_reg_0 <= tbi_rx_clk_aligned;
tbi_rx_clk_aligned_reg_1 <= tbi_rx_clk_aligned_reg_0;
end
end
// Flop the tx data
always @(posedge reset_rclk or posedge rclk)
begin
if (reset_rclk == 1'b 1)
begin
tbi_tx_clk_reg_0 <= 10'b0;
tbi_tx_clk_reg_1 <= 10'b0;
end
else
begin
tbi_tx_clk_reg_0 <= tbi_tx_clk_reg_in;
tbi_tx_clk_reg_1 <= tbi_tx_clk_reg_0;
end
end
// DC FIFO for rate-match
altera_tse_a_fifo_24
#( .FF_WIDTH(10),
.ADDR_WIDTH(4),
.DEPTH(16),
.SAMPLE_SIZE(0)
)
U_REV_LOOPBACK_FIFO (
.reset_wclk(reset_wclk),
.reset_rclk(reset_rclk),
.wclk(wclk),
.wclk_ena(1'b1),
.wren(ff_wren),
.din(tbi_din),
.rclk(rclk),
.rclk_ena(1'b1),
.rden(ff_rden),
.dout(tbi_dout),
.afull(ff_afull),
.aempty(ff_aempty),
.af_threshold(4'd4),
.ae_threshold(4'd4),
// These ports are not used
.calc_clk(1'b0),
.clk_125(1'b0),
.latadj() // UNUSED
);
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet MAC
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // AtlanticII source - component_specific_signal(data)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // AtlanticII source - component_specific_signal(data)
tx_ff_uflow, // AtlanticII source - component_specific_signal(data)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
rx_clk,
tx_clk,
gm_rx_d,
gm_rx_dv,
gm_rx_err,
gm_tx_d,
gm_tx_en,
gm_tx_err,
m_rx_d,
m_rx_en,
m_rx_err,
m_tx_d,
m_tx_en,
m_tx_err,
m_rx_crs,
m_rx_col,
eth_mode,
ena_10,
set_10,
set_1000,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tx_control,
rx_control,
rgmii_in,
rgmii_out
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
input rx_clk; // Receive Clock
input tx_clk; // Transmit Clock
input [7:0] gm_rx_d; // GMII Receive Data
input gm_rx_dv; // GMII Receive Frame Enable
input gm_rx_err; // GMII Receive Frame Error
output [7:0] gm_tx_d; // GMII Transmit Data
output gm_tx_en; // GMII Transmit Frame Enable
output gm_tx_err; // GMII Transmit Frame Error
input [3:0] m_rx_d; // MII Receive Data
input m_rx_en; // MII Receive Frame Enable
input m_rx_err; // MII Receive Drame Error
output [3:0] m_tx_d; // MII Transmit Data
output m_tx_en; // MII Transmit Frame Enable
output m_tx_err; // MII Transmit Frame Error
input m_rx_crs; // Carrier Sense
input m_rx_col; // Collition
output eth_mode; // Ethernet Mode
output ena_10; // Enable 10Mbps Mode
input set_1000; // Gigabit Mode Enable
input set_10; // 10Mbps Mode Enable
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
output tx_control;
output [3:0] rgmii_out;
input [3:0] rgmii_in;
input rx_control;
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire [7:0] gm_tx_d;
wire gm_tx_en;
wire gm_tx_err;
wire [3:0] m_tx_d;
wire m_tx_en;
wire m_tx_err;
wire eth_mode;
wire ena_10;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire tx_control;
wire [3:0] rgmii_out;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
altera_tse_reset_synchronizer reset_sync_0 (
.clk(rx_clk),
.reset_in(reset),
.reset_out(reset_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_1 (
.clk(tx_clk),
.reset_in(reset),
.reset_out(reset_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_2 (
.clk(ff_rx_clk),
.reset_in(reset),
.reset_out(reset_ff_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_3 (
.clk(ff_tx_clk),
.reset_in(reset),
.reset_out(reset_ff_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_4 (
.clk(clk),
.reset_in(reset),
.reset_out(reset_reg_clk_int)
);
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(1'b1),
.tx_clkena(1'b1),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_en),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read),
.reg_wr(write),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(eth_mode),
.ena_10(ena_10),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata),
.reg_busy(waitrequest),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen),
.tx_control(tx_control),
.rgmii_out(rgmii_out),
.rgmii_in(rgmii_in),
.rx_control(rx_control));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE, //1,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE, //1,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE, //1,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE, //1,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE, //0,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet MAC + PCS
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // Will not exists in SoPC Model (leave unconnected)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // Will not exists in SoPC Model (leave unconnected)
tx_ff_uflow, // Will not exists in SoPC Model (leave unconnected)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
output led_crs; // Carrier Sense
output led_link; // Valid Link
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire led_crs;
wire led_link;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire [7:0] gm_rx_d; // GMII Receive Data
wire gm_rx_dv; // GMII Receive Frame Enable
wire gm_rx_err; // GMII Receive Frame Error
wire [7:0] gm_tx_d; // GMII Transmit Data
wire gm_tx_en; // GMII Transmit Frame Enable
wire gm_tx_err; // GMII Transmit Frame Error
wire [3:0] m_rx_d; // MII Receive Data
wire m_rx_dv; // MII Receive Frame Enable
wire m_rx_err; // MII Receive Drame Error
wire [3:0] m_tx_d; // MII Transmit Data
wire m_tx_en; // MII Transmit Frame Enable
wire m_tx_err; // MII Transmit Frame Error
wire m_rx_crs; // Carrier Sense
wire m_rx_col; // Collition
wire set_1000; // Gigabit Mode Enable
wire set_10; // 10Mbps Mode Enable
wire pcs_en;
wire [31:0]readdata_mac;
wire waitrequest_mac;
wire [31:0]readdata_pcs;
wire waitrequest_pcs;
wire write_pcs;
wire read_pcs;
wire write_mac;
wire read_mac;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// This is done because the PCS address space is from 0x80 to 0x9F
// ---------------------------------------------------------------
assign pcs_en = address[7] & !address[6] & !address[5];
assign write_pcs = pcs_en? write : 1'b0;
assign read_pcs = pcs_en? read : 1'b0;
assign write_mac = pcs_en? 1'b0 : write;
assign read_mac = pcs_en? 1'b0 : read;
assign readdata = pcs_en? readdata_pcs : readdata_mac;
assign waitrequest = pcs_en? waitrequest_pcs : waitrequest_mac;
assign readdata_pcs[31:16] = {16{1'b0}};
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
altera_tse_reset_synchronizer reset_sync_0 (
.clk(rx_clk),
.reset_in(reset),
.reset_out(reset_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_1 (
.clk(tx_clk),
.reset_in(reset),
.reset_out(reset_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_2 (
.clk(ff_rx_clk),
.reset_in(reset),
.reset_out(reset_ff_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_3 (
.clk(ff_tx_clk),
.reset_in(reset),
.reset_out(reset_ff_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_4 (
.clk(clk),
.reset_in(reset),
.reset_out(reset_reg_clk_int)
);
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_dv),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read_mac),
.reg_wr(write_mac),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(),
.ena_10(),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata_mac),
.reg_busy(waitrequest_mac),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gm_rx_dv),
.gmii_rx_d(gm_rx_d),
.gmii_rx_err(gm_rx_err),
.gmii_tx_en(gm_tx_en),
.gmii_tx_d(gm_tx_d),
.gmii_tx_err(gm_tx_err),
.mii_rx_dv(m_rx_dv),
.mii_rx_d(m_rx_d),
.mii_rx_err(m_rx_err),
.mii_tx_en(m_tx_en),
.mii_tx_d(m_tx_d),
.mii_tx_err(m_tx_err),
.mii_col(m_rx_col),
.mii_crs(m_rx_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(clk),
.reg_rd(read_pcs),
.reg_wr(write_pcs),
.reg_addr(address[4:0]),
.reg_data_in(writedata[15:0]),
.reg_data_out(readdata_pcs[15:0]),
.reg_busy(waitrequest_pcs),
.powerdown(powerdown),
.set_10(set_10),
.set_100(),
.set_1000(set_1000),
.hd_ena(),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma.v,v $
//
// $Revision: #2 $
// $Date: 2012/08/15 $
// Check in by : $Author: ksting $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,C105\"" */ (
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
rx_recovclkout,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
parameter ENABLE_REV_LOOPBACK = 0; // Enable PHY Reverse Loopback
//Dummy parameter from IEEE1588
parameter TSTAMP_FP_WIDTH = 4;
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output rx_recovclkout;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire led_an;
wire led_char_err;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire [5:0] rx_err;
wire [17: 0] rx_err_stat;
wire [3:0] rx_frm_type;
wire sd_loopback;
wire rev_loopback_ena;
wire rev_loopback_ena_ref_clk;
wire tbi_rx_clk;
wire [9:0] tbi_rx_d;
wire tbi_tx_clk;
wire [9:0] tbi_tx_d;
wire tx_ff_uflow;
wire txp;
wire waitrequest;
wire [9:0] tbi_rx_d_lvds;
reg [9:0] tbi_rx_d_flip;
reg [9:0] tbi_tx_d_flip;
wire [9:0] tbi_tx_d_muxed;
wire [9:0] tbi_tx_d_loopback;
wire reset_ref_clk_int;
wire reset_tbi_rx_clk_int;
wire pll_areset,rx_cda_reset,rx_channel_data_align,rx_locked,rx_reset_sequence_done;
wire rx_reset;
// Export recovered clock
assign rx_recovclkout = tbi_rx_clk;
// Assign the digital reset of the PMA to the MAC_PCS logic
// --------------------------------------------------------
assign MAC_PCS_reset = rx_reset;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_ena altera_tse_mac_pcs_pma_ena_inst
(
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err),
.led_col (led_col),
.led_crs (led_crs),
.led_disp_err (led_disp_err),
.led_link (led_link),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (MAC_PCS_reset),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.sd_loopback (sd_loopback),
.rev_loopback_ena (rev_loopback_ena),
.tbi_rx_clk (tbi_rx_clk),
.tbi_rx_d (tbi_rx_d),
.tbi_tx_clk (tbi_tx_clk),
.tbi_tx_d (tbi_tx_d),
.tx_ff_uflow (tx_ff_uflow),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the Alt2gxb block as the PMA for devices other than ArriaGX
// ----------------------------------------------------------------------------
// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
// ----------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
begin
assign tbi_tx_clk = ref_clk;
assign tbi_rx_d = tbi_rx_d_flip;
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena), //INPUT
.dout(rev_loopback_ena_ref_clk));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK (
.reset_wclk(reset_tbi_rx_clk_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds),
.tbi_tx_clk (tbi_tx_d_loopback)
);
assign tbi_tx_d_muxed = rev_loopback_ena_ref_clk ? tbi_tx_d_loopback: tbi_tx_d_flip;
end
else
begin
assign tbi_tx_d_muxed = tbi_tx_d_flip;
// Unused wires
assign tbi_tx_d_loopback = 10'd0;
assign rev_loopback_ena_ref_clk = 1'b0;
end
altera_tse_reset_synchronizer reset_sync_0 (
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_ref_clk_int)
);
altera_tse_reset_synchronizer reset_sync_1 (
.clk(tbi_rx_clk),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_int)
);
always @(posedge tbi_rx_clk or posedge reset_tbi_rx_clk_int)
begin
if (reset_tbi_rx_clk_int == 1)
tbi_rx_d_flip <= 0;
else
begin
if (rx_reset_sequence_done == 1)
begin
tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip <= 0;
else
begin
tbi_tx_d_flip[0] <= tbi_tx_d[9];
tbi_tx_d_flip[1] <= tbi_tx_d[8];
tbi_tx_d_flip[2] <= tbi_tx_d[7];
tbi_tx_d_flip[3] <= tbi_tx_d[6];
tbi_tx_d_flip[4] <= tbi_tx_d[5];
tbi_tx_d_flip[5] <= tbi_tx_d[4];
tbi_tx_d_flip[6] <= tbi_tx_d[3];
tbi_tx_d_flip[7] <= tbi_tx_d[2];
tbi_tx_d_flip[8] <= tbi_tx_d[1];
tbi_tx_d_flip[9] <= tbi_tx_d[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align ),
.rx_locked ( rx_locked ),
.rx_divfwdclk (tbi_rx_clk),
.rx_in (rxp),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds),
.rx_outclock (),
.rx_reset (rx_reset)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset ),
.rx_channel_data_align ( rx_channel_data_align ),
.rx_locked ( rx_locked ),
.rx_divfwdclk (tbi_rx_clk),
.rx_in (rxp),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds),
.rx_outclock (),
.rx_reset (rx_reset)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer (
.clk ( clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked ),
.rx_channel_data_align ( rx_channel_data_align ),
.pll_areset ( pll_areset ),
.rx_reset (rx_reset),
.rx_cda_reset ( rx_cda_reset ),
.rx_reset_sequence_done ( rx_reset_sequence_done )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
(
.tx_in (tbi_tx_d_muxed),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp)
);
end
endgenerate
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma_gige.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
reconfig_clk,
reconfig_togxb,
reconfig_busy,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
reconfig_fromgxb,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
rx_recovclkout,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
//Dummy parameter from IEEE1588
parameter TSTAMP_FP_WIDTH = 4;
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [16:0] reconfig_fromgxb;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output rx_recovclkout;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input reconfig_clk;
input [3:0] reconfig_togxb;
input reconfig_busy;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire gige_pma_reset;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire rx_pcs_clk;
wire tx_pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire rx_char_err_gx;
wire rx_disp_err;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire sd_loopback;
wire tx_ff_uflow;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire rx_recovclkout;
wire waitrequest;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
wire [16:0] reconfig_fromgxb;
wire reset_ref_clk;
wire reset_rx_pcs_clk_int;
wire pll_powerdown_sqcnr,tx_digitalreset_sqcnr,rx_analogreset_sqcnr,rx_digitalreset_sqcnr,gxb_powerdown_sqcnr,pll_locked;
wire locked_signal;
wire rx_freqlocked;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (reset),
.rx_clkout (rx_pcs_clk),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frame (pcs_rx_frame),
.rx_frm_type (rx_frm_type),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.tx_clkout (tx_pcs_clk),
.tx_ff_uflow (tx_ff_uflow),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Based on PHYIP , when user assert reset - it hold the reset sequencer block in reset.
// , reset sequencing only start then reset_sequnece end.
wire reset_sync;
reg reset_start;
altera_tse_reset_synchronizer reset_sync_u0 (
.clk(clk),
.reset_in(reset),
.reset_out(reset_sync)
);
always@(posedge clk or posedge reset_sync) begin
if (reset_sync) begin
reset_start <= 1'b1;
end
else begin
reset_start <= 1'b0;
end
end
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_d1, gxb_pwrdn_in_sig_clk;
generate if (EXPORT_PWRDN == 1)
begin
always @(posedge clk or posedge gxb_pwrdn_in)
begin
if (gxb_pwrdn_in == 1) begin
data_in_d1 <= 1;
gxb_pwrdn_in_sig_clk <= 1;
end else begin
data_in_d1 <= 1'b0;
gxb_pwrdn_in_sig_clk <= data_in_d1;
end
end
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk = gxb_pwrdn_in_sig;
end
end
endgenerate
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr),// output
.tx_digitalreset(tx_digitalreset_sqcnr),// output
.rx_analogreset(rx_analogreset_sqcnr),// output
.rx_digitalreset(rx_digitalreset_sqcnr),// output
.gxb_powerdown(gxb_powerdown_sqcnr),// output
.pll_is_locked(locked_signal),
.rx_is_lockedtodata(rx_freqlocked),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy)
);
assign locked_signal = (reset? 1'b0: pll_locked);
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk),
.reset_in(rx_digitalreset_sqcnr),
.reset_out(reset_rx_pcs_clk_int)
);
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(rx_pcs_clk),
.reset(reset_rx_pcs_clk_int),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb),
.rx_analogreset (rx_analogreset_sqcnr),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar),
.rx_clkout (rx_pcs_clk),
.rx_datain (rxp),
.rx_dataout (rx_frame),
.rx_digitalreset (rx_digitalreset_sqcnr),
.rx_disperr (rx_disp_err),
.rx_errdetect (rx_char_err_gx),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_runlengthviolation),
.rx_seriallpbken (sd_loopback),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_pcs_clk),
.tx_ctrlenable (tx_kchar),
.tx_datain (tx_frame),
.rx_freqlocked (rx_freqlocked),
.tx_dataout (txp),
.tx_digitalreset (tx_digitalreset_sqcnr),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp),
.pll_powerdown(gxb_pwrdn_in_sig),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY,
the_altera_tse_gxb_gige_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma_gige_phyip.v,v $
//
// $Revision: #17 $
// $Date: 2010/10/07 $
// Check in by : $Author: aishak $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma_gige_phyip /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
magic_sleep_n,
mdio_in,
read,
reconfig_togxb,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
readdata,
reconfig_fromgxb,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
rx_recovclkout,
waitrequest,
// phy_mgmt_interface
phy_mgmt_address,
phy_mgmt_read,
phy_mgmt_readdata,
phy_mgmt_waitrequest,
phy_mgmt_write,
phy_mgmt_writedata
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
//Dummy parameter from IEEE1588
parameter TSTAMP_FP_WIDTH = 4;
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output [31: 0] readdata;
output [91:0] reconfig_fromgxb;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output rx_recovclkout;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input magic_sleep_n;
input mdio_in;
input read;
input [139:0] reconfig_togxb;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
input [8:0] phy_mgmt_address;
input phy_mgmt_read;
output [31:0] phy_mgmt_readdata;
output phy_mgmt_waitrequest;
input phy_mgmt_write;
input [31:0]phy_mgmt_writedata;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire gige_pma_reset;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire rx_pcs_clk;
wire tx_pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire rx_char_err_gx;
wire rx_disp_err;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire sd_loopback;
wire tx_ff_uflow;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire rx_recovclkout;
wire waitrequest;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
wire [91:0] reconfig_fromgxb;
wire reset_ref_clk;
wire reset_rx_pcs_clk_int;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (reset),
.rx_clkout (rx_pcs_clk),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frame (pcs_rx_frame),
.rx_frm_type (rx_frm_type),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.tx_clkout (tx_pcs_clk),
.tx_ff_uflow (tx_ff_uflow),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_int)
);
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(rx_pcs_clk),
.reset(reset_rx_pcs_clk_int),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Custom PhyIP
// ------------------------------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst(
.phy_mgmt_clk(clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset(reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
.phy_mgmt_read(phy_mgmt_read), // .read
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
.phy_mgmt_write(phy_mgmt_write), // .write
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
.tx_ready(), // tx_ready.export
.rx_ready(), // rx_ready.export
.pll_ref_clk(ref_clk), // pll_ref_clk.clk
.pll_locked(), // pll_locked.export
.tx_serial_data(txp), // tx_serial_data.export
.rx_serial_data(rxp), // rx_serial_data.export
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
.rx_disperr(rx_disp_err), // rx_disperr.export
.rx_errdetect(rx_char_err_gx), // rx_errdetect.export
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
.tx_clkout(tx_pcs_clk), // tx_clkout0.clk
.rx_clkout(rx_pcs_clk), // rx_clkout0.clk
.tx_parallel_data(tx_frame), // tx_parallel_data0.data
.tx_datak(tx_kchar), // tx_datak0.data
.rx_parallel_data(rx_frame), // rx_parallel_data0.data
.rx_datak(rx_kchar), // rx_datak0.data
.rx_rlv(rx_runlengthviolation),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb)
);
defparam
the_altera_tse_gxb_gige_phyip_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst.DEVICE_FAMILY = DEVICE_FAMILY,
the_altera_tse_gxb_gige_phyip_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_multi_mac
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 1, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// SHARED CLK SIGNALS
input wire rx_clk, // Receive Clock
input wire tx_clk, // Transmit Clock
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clock
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_0, // Carrier Sense
input wire m_rx_col_0, // Collition
input wire rx_clk_0, // Receive Clock
input wire tx_clk_0, // Transmit Clock
input wire [7:0] gm_rx_d_0, // GMII Receive Data
input wire gm_rx_dv_0, // GMII Receive Frame Enable
input wire gm_rx_err_0, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_0, // GMII Transmit Data
output wire gm_tx_en_0, // GMII Transmit Frame Enable
output wire gm_tx_err_0, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_0, // MII Receive Data
input wire m_rx_en_0, // MII Receive Frame Enable
input wire m_rx_err_0, // MII Receive Drame Error
output wire [3:0] m_tx_d_0, // MII Transmit Data
output wire m_tx_en_0, // MII Transmit Frame Enable
output wire m_tx_err_0, // MII Transmit Frame Error
output wire tx_control_0,
output wire [3:0] rgmii_out_0,
input wire [3:0] rgmii_in_0,
input wire rx_control_0,
output wire eth_mode_0, // Ethernet Mode
output wire ena_10_0, // Enable 10Mbps Mode
input wire set_1000_0, // Gigabit Mode Enable
input wire set_10_0, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// CHANNEL 1
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_1, // Carrier Sense
input wire m_rx_col_1, // Collition
input wire rx_clk_1, // Receive Clock
input wire tx_clk_1, // Transmit Clock
input wire [7:0] gm_rx_d_1, // GMII Receive Data
input wire gm_rx_dv_1, // GMII Receive Frame Enable
input wire gm_rx_err_1, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_1, // GMII Transmit Data
output wire gm_tx_en_1, // GMII Transmit Frame Enable
output wire gm_tx_err_1, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_1, // MII Receive Data
input wire m_rx_en_1, // MII Receive Frame Enable
input wire m_rx_err_1, // MII Receive Drame Error
output wire [3:0] m_tx_d_1, // MII Transmit Data
output wire m_tx_en_1, // MII Transmit Frame Enable
output wire m_tx_err_1, // MII Transmit Frame Error
output wire tx_control_1,
output wire [3:0] rgmii_out_1,
input wire [3:0] rgmii_in_1,
input wire rx_control_1,
output wire eth_mode_1, // Ethernet Mode
output wire ena_10_1, // Enable 10Mbps Mode
input wire set_1000_1, // Gigabit Mode Enable
input wire set_10_1, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// CHANNEL 2
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_2, // Carrier Sense
input wire m_rx_col_2, // Collition
input wire rx_clk_2, // Receive Clock
input wire tx_clk_2, // Transmit Clock
input wire [7:0] gm_rx_d_2, // GMII Receive Data
input wire gm_rx_dv_2, // GMII Receive Frame Enable
input wire gm_rx_err_2, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_2, // GMII Transmit Data
output wire gm_tx_en_2, // GMII Transmit Frame Enable
output wire gm_tx_err_2, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_2, // MII Receive Data
input wire m_rx_en_2, // MII Receive Frame Enable
input wire m_rx_err_2, // MII Receive Drame Error
output wire [3:0] m_tx_d_2, // MII Transmit Data
output wire m_tx_en_2, // MII Transmit Frame Enable
output wire m_tx_err_2, // MII Transmit Frame Error
output wire tx_control_2,
output wire [3:0] rgmii_out_2,
input wire [3:0] rgmii_in_2,
input wire rx_control_2,
output wire eth_mode_2, // Ethernet Mode
output wire ena_10_2, // Enable 10Mbps Mode
input wire set_1000_2, // Gigabit Mode Enable
input wire set_10_2, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// CHANNEL 3
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_3, // Carrier Sense
input wire m_rx_col_3, // Collition
input wire rx_clk_3, // Receive Clock
input wire tx_clk_3, // Transmit Clock
input wire [7:0] gm_rx_d_3, // GMII Receive Data
input wire gm_rx_dv_3, // GMII Receive Frame Enable
input wire gm_rx_err_3, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_3, // GMII Transmit Data
output wire gm_tx_en_3, // GMII Transmit Frame Enable
output wire gm_tx_err_3, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_3, // MII Receive Data
input wire m_rx_en_3, // MII Receive Frame Enable
input wire m_rx_err_3, // MII Receive Drame Error
output wire [3:0] m_tx_d_3, // MII Transmit Data
output wire m_tx_en_3, // MII Transmit Frame Enable
output wire m_tx_err_3, // MII Transmit Frame Error
output wire tx_control_3,
output wire [3:0] rgmii_out_3,
input wire [3:0] rgmii_in_3,
input wire rx_control_3,
output wire eth_mode_3, // Ethernet Mode
output wire ena_10_3, // Enable 10Mbps Mode
input wire set_1000_3, // Gigabit Mode Enable
input wire set_10_3, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// CHANNEL 4
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_4, // Carrier Sense
input wire m_rx_col_4, // Collition
input wire rx_clk_4, // Receive Clock
input wire tx_clk_4, // Transmit Clock
input wire [7:0] gm_rx_d_4, // GMII Receive Data
input wire gm_rx_dv_4, // GMII Receive Frame Enable
input wire gm_rx_err_4, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_4, // GMII Transmit Data
output wire gm_tx_en_4, // GMII Transmit Frame Enable
output wire gm_tx_err_4, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_4, // MII Receive Data
input wire m_rx_en_4, // MII Receive Frame Enable
input wire m_rx_err_4, // MII Receive Drame Error
output wire [3:0] m_tx_d_4, // MII Transmit Data
output wire m_tx_en_4, // MII Transmit Frame Enable
output wire m_tx_err_4, // MII Transmit Frame Error
output wire tx_control_4,
output wire [3:0] rgmii_out_4,
input wire [3:0] rgmii_in_4,
input wire rx_control_4,
output wire eth_mode_4, // Ethernet Mode
output wire ena_10_4, // Enable 10Mbps Mode
input wire set_1000_4, // Gigabit Mode Enable
input wire set_10_4, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// CHANNEL 5
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_5, // Carrier Sense
input wire m_rx_col_5, // Collition
input wire rx_clk_5, // Receive Clock
input wire tx_clk_5, // Transmit Clock
input wire [7:0] gm_rx_d_5, // GMII Receive Data
input wire gm_rx_dv_5, // GMII Receive Frame Enable
input wire gm_rx_err_5, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_5, // GMII Transmit Data
output wire gm_tx_en_5, // GMII Transmit Frame Enable
output wire gm_tx_err_5, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_5, // MII Receive Data
input wire m_rx_en_5, // MII Receive Frame Enable
input wire m_rx_err_5, // MII Receive Drame Error
output wire [3:0] m_tx_d_5, // MII Transmit Data
output wire m_tx_en_5, // MII Transmit Frame Enable
output wire m_tx_err_5, // MII Transmit Frame Error
output wire tx_control_5,
output wire [3:0] rgmii_out_5,
input wire [3:0] rgmii_in_5,
input wire rx_control_5,
output wire eth_mode_5, // Ethernet Mode
output wire ena_10_5, // Enable 10Mbps Mode
input wire set_1000_5, // Gigabit Mode Enable
input wire set_10_5, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// CHANNEL 6
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_6, // Carrier Sense
input wire m_rx_col_6, // Collition
input wire rx_clk_6, // Receive Clock
input wire tx_clk_6, // Transmit Clock
input wire [7:0] gm_rx_d_6, // GMII Receive Data
input wire gm_rx_dv_6, // GMII Receive Frame Enable
input wire gm_rx_err_6, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_6, // GMII Transmit Data
output wire gm_tx_en_6, // GMII Transmit Frame Enable
output wire gm_tx_err_6, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_6, // MII Receive Data
input wire m_rx_en_6, // MII Receive Frame Enable
input wire m_rx_err_6, // MII Receive Drame Error
output wire [3:0] m_tx_d_6, // MII Transmit Data
output wire m_tx_en_6, // MII Transmit Frame Enable
output wire m_tx_err_6, // MII Transmit Frame Error
output wire tx_control_6,
output wire [3:0] rgmii_out_6,
input wire [3:0] rgmii_in_6,
input wire rx_control_6,
output wire eth_mode_6, // Ethernet Mode
output wire ena_10_6, // Enable 10Mbps Mode
input wire set_1000_6, // Gigabit Mode Enable
input wire set_10_6, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// CHANNEL 7
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_7, // Carrier Sense
input wire m_rx_col_7, // Collition
input wire rx_clk_7, // Receive Clock
input wire tx_clk_7, // Transmit Clock
input wire [7:0] gm_rx_d_7, // GMII Receive Data
input wire gm_rx_dv_7, // GMII Receive Frame Enable
input wire gm_rx_err_7, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_7, // GMII Transmit Data
output wire gm_tx_en_7, // GMII Transmit Frame Enable
output wire gm_tx_err_7, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_7, // MII Receive Data
input wire m_rx_en_7, // MII Receive Frame Enable
input wire m_rx_err_7, // MII Receive Drame Error
output wire [3:0] m_tx_d_7, // MII Transmit Data
output wire m_tx_en_7, // MII Transmit Frame Enable
output wire m_tx_err_7, // MII Transmit Frame Error
output wire tx_control_7,
output wire [3:0] rgmii_out_7,
input wire [3:0] rgmii_in_7,
input wire rx_control_7,
output wire eth_mode_7, // Ethernet Mode
output wire ena_10_7, // Enable 10Mbps Mode
input wire set_1000_7, // Gigabit Mode Enable
input wire set_10_7, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// CHANNEL 8
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_8, // Carrier Sense
input wire m_rx_col_8, // Collition
input wire rx_clk_8, // Receive Clock
input wire tx_clk_8, // Transmit Clock
input wire [7:0] gm_rx_d_8, // GMII Receive Data
input wire gm_rx_dv_8, // GMII Receive Frame Enable
input wire gm_rx_err_8, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_8, // GMII Transmit Data
output wire gm_tx_en_8, // GMII Transmit Frame Enable
output wire gm_tx_err_8, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_8, // MII Receive Data
input wire m_rx_en_8, // MII Receive Frame Enable
input wire m_rx_err_8, // MII Receive Drame Error
output wire [3:0] m_tx_d_8, // MII Transmit Data
output wire m_tx_en_8, // MII Transmit Frame Enable
output wire m_tx_err_8, // MII Transmit Frame Error
output wire tx_control_8,
output wire [3:0] rgmii_out_8,
input wire [3:0] rgmii_in_8,
input wire rx_control_8,
output wire eth_mode_8, // Ethernet Mode
output wire ena_10_8, // Enable 10Mbps Mode
input wire set_1000_8, // Gigabit Mode Enable
input wire set_10_8, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// CHANNEL 9
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_9, // Carrier Sense
input wire m_rx_col_9, // Collition
input wire rx_clk_9, // Receive Clock
input wire tx_clk_9, // Transmit Clock
input wire [7:0] gm_rx_d_9, // GMII Receive Data
input wire gm_rx_dv_9, // GMII Receive Frame Enable
input wire gm_rx_err_9, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_9, // GMII Transmit Data
output wire gm_tx_en_9, // GMII Transmit Frame Enable
output wire gm_tx_err_9, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_9, // MII Receive Data
input wire m_rx_en_9, // MII Receive Frame Enable
input wire m_rx_err_9, // MII Receive Drame Error
output wire [3:0] m_tx_d_9, // MII Transmit Data
output wire m_tx_en_9, // MII Transmit Frame Enable
output wire m_tx_err_9, // MII Transmit Frame Error
output wire tx_control_9,
output wire [3:0] rgmii_out_9,
input wire [3:0] rgmii_in_9,
input wire rx_control_9,
output wire eth_mode_9, // Ethernet Mode
output wire ena_10_9, // Enable 10Mbps Mode
input wire set_1000_9, // Gigabit Mode Enable
input wire set_10_9, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// CHANNEL 10
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_10, // Carrier Sense
input wire m_rx_col_10, // Collition
input wire rx_clk_10, // Receive Clock
input wire tx_clk_10, // Transmit Clock
input wire [7:0] gm_rx_d_10, // GMII Receive Data
input wire gm_rx_dv_10, // GMII Receive Frame Enable
input wire gm_rx_err_10, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_10, // GMII Transmit Data
output wire gm_tx_en_10, // GMII Transmit Frame Enable
output wire gm_tx_err_10, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_10, // MII Receive Data
input wire m_rx_en_10, // MII Receive Frame Enable
input wire m_rx_err_10, // MII Receive Drame Error
output wire [3:0] m_tx_d_10, // MII Transmit Data
output wire m_tx_en_10, // MII Transmit Frame Enable
output wire m_tx_err_10, // MII Transmit Frame Error
output wire tx_control_10,
output wire [3:0] rgmii_out_10,
input wire [3:0] rgmii_in_10,
input wire rx_control_10,
output wire eth_mode_10, // Ethernet Mode
output wire ena_10_10, // Enable 10Mbps Mode
input wire set_1000_10, // Gigabit Mode Enable
input wire set_10_10, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// CHANNEL 11
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_11, // Carrier Sense
input wire m_rx_col_11, // Collition
input wire rx_clk_11, // Receive Clock
input wire tx_clk_11, // Transmit Clock
input wire [7:0] gm_rx_d_11, // GMII Receive Data
input wire gm_rx_dv_11, // GMII Receive Frame Enable
input wire gm_rx_err_11, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_11, // GMII Transmit Data
output wire gm_tx_en_11, // GMII Transmit Frame Enable
output wire gm_tx_err_11, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_11, // MII Receive Data
input wire m_rx_en_11, // MII Receive Frame Enable
input wire m_rx_err_11, // MII Receive Drame Error
output wire [3:0] m_tx_d_11, // MII Transmit Data
output wire m_tx_en_11, // MII Transmit Frame Enable
output wire m_tx_err_11, // MII Transmit Frame Error
output wire tx_control_11,
output wire [3:0] rgmii_out_11,
input wire [3:0] rgmii_in_11,
input wire rx_control_11,
output wire eth_mode_11, // Ethernet Mode
output wire ena_10_11, // Enable 10Mbps Mode
input wire set_1000_11, // Gigabit Mode Enable
input wire set_10_11, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// CHANNEL 12
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_12, // Carrier Sense
input wire m_rx_col_12, // Collition
input wire rx_clk_12, // Receive Clock
input wire tx_clk_12, // Transmit Clock
input wire [7:0] gm_rx_d_12, // GMII Receive Data
input wire gm_rx_dv_12, // GMII Receive Frame Enable
input wire gm_rx_err_12, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_12, // GMII Transmit Data
output wire gm_tx_en_12, // GMII Transmit Frame Enable
output wire gm_tx_err_12, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_12, // MII Receive Data
input wire m_rx_en_12, // MII Receive Frame Enable
input wire m_rx_err_12, // MII Receive Drame Error
output wire [3:0] m_tx_d_12, // MII Transmit Data
output wire m_tx_en_12, // MII Transmit Frame Enable
output wire m_tx_err_12, // MII Transmit Frame Error
output wire tx_control_12,
output wire [3:0] rgmii_out_12,
input wire [3:0] rgmii_in_12,
input wire rx_control_12,
output wire eth_mode_12, // Ethernet Mode
output wire ena_10_12, // Enable 10Mbps Mode
input wire set_1000_12, // Gigabit Mode Enable
input wire set_10_12, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// CHANNEL 13
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_13, // Carrier Sense
input wire m_rx_col_13, // Collition
input wire rx_clk_13, // Receive Clock
input wire tx_clk_13, // Transmit Clock
input wire [7:0] gm_rx_d_13, // GMII Receive Data
input wire gm_rx_dv_13, // GMII Receive Frame Enable
input wire gm_rx_err_13, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_13, // GMII Transmit Data
output wire gm_tx_en_13, // GMII Transmit Frame Enable
output wire gm_tx_err_13, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_13, // MII Receive Data
input wire m_rx_en_13, // MII Receive Frame Enable
input wire m_rx_err_13, // MII Receive Drame Error
output wire [3:0] m_tx_d_13, // MII Transmit Data
output wire m_tx_en_13, // MII Transmit Frame Enable
output wire m_tx_err_13, // MII Transmit Frame Error
output wire tx_control_13,
output wire [3:0] rgmii_out_13,
input wire [3:0] rgmii_in_13,
input wire rx_control_13,
output wire eth_mode_13, // Ethernet Mode
output wire ena_10_13, // Enable 10Mbps Mode
input wire set_1000_13, // Gigabit Mode Enable
input wire set_10_13, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// CHANNEL 14
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_14, // Carrier Sense
input wire m_rx_col_14, // Collition
input wire rx_clk_14, // Receive Clock
input wire tx_clk_14, // Transmit Clock
input wire [7:0] gm_rx_d_14, // GMII Receive Data
input wire gm_rx_dv_14, // GMII Receive Frame Enable
input wire gm_rx_err_14, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_14, // GMII Transmit Data
output wire gm_tx_en_14, // GMII Transmit Frame Enable
output wire gm_tx_err_14, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_14, // MII Receive Data
input wire m_rx_en_14, // MII Receive Frame Enable
input wire m_rx_err_14, // MII Receive Drame Error
output wire [3:0] m_tx_d_14, // MII Transmit Data
output wire m_tx_en_14, // MII Transmit Frame Enable
output wire m_tx_err_14, // MII Transmit Frame Error
output wire tx_control_14,
output wire [3:0] rgmii_out_14,
input wire [3:0] rgmii_in_14,
input wire rx_control_14,
output wire eth_mode_14, // Ethernet Mode
output wire ena_10_14, // Enable 10Mbps Mode
input wire set_1000_14, // Gigabit Mode Enable
input wire set_10_14, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// CHANNEL 15
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_15, // Carrier Sense
input wire m_rx_col_15, // Collition
input wire rx_clk_15, // Receive Clock
input wire tx_clk_15, // Transmit Clock
input wire [7:0] gm_rx_d_15, // GMII Receive Data
input wire gm_rx_dv_15, // GMII Receive Frame Enable
input wire gm_rx_err_15, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_15, // GMII Transmit Data
output wire gm_tx_en_15, // GMII Transmit Frame Enable
output wire gm_tx_err_15, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_15, // MII Receive Data
input wire m_rx_en_15, // MII Receive Frame Enable
input wire m_rx_err_15, // MII Receive Drame Error
output wire [3:0] m_tx_d_15, // MII Transmit Data
output wire m_tx_en_15, // MII Transmit Frame Enable
output wire m_tx_err_15, // MII Transmit Frame Error
output wire tx_control_15,
output wire [3:0] rgmii_out_15,
input wire [3:0] rgmii_in_15,
input wire rx_control_15,
output wire eth_mode_15, // Ethernet Mode
output wire ena_10_15, // Enable 10Mbps Mode
input wire set_1000_15, // Gigabit Mode Enable
input wire set_10_15, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// CHANNEL 16
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_16, // Carrier Sense
input wire m_rx_col_16, // Collition
input wire rx_clk_16, // Receive Clock
input wire tx_clk_16, // Transmit Clock
input wire [7:0] gm_rx_d_16, // GMII Receive Data
input wire gm_rx_dv_16, // GMII Receive Frame Enable
input wire gm_rx_err_16, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_16, // GMII Transmit Data
output wire gm_tx_en_16, // GMII Transmit Frame Enable
output wire gm_tx_err_16, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_16, // MII Receive Data
input wire m_rx_en_16, // MII Receive Frame Enable
input wire m_rx_err_16, // MII Receive Drame Error
output wire [3:0] m_tx_d_16, // MII Transmit Data
output wire m_tx_en_16, // MII Transmit Frame Enable
output wire m_tx_err_16, // MII Transmit Frame Error
output wire tx_control_16,
output wire [3:0] rgmii_out_16,
input wire [3:0] rgmii_in_16,
input wire rx_control_16,
output wire eth_mode_16, // Ethernet Mode
output wire ena_10_16, // Enable 10Mbps Mode
input wire set_1000_16, // Gigabit Mode Enable
input wire set_10_16, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// CHANNEL 17
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_17, // Carrier Sense
input wire m_rx_col_17, // Collition
input wire rx_clk_17, // Receive Clock
input wire tx_clk_17, // Transmit Clock
input wire [7:0] gm_rx_d_17, // GMII Receive Data
input wire gm_rx_dv_17, // GMII Receive Frame Enable
input wire gm_rx_err_17, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_17, // GMII Transmit Data
output wire gm_tx_en_17, // GMII Transmit Frame Enable
output wire gm_tx_err_17, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_17, // MII Receive Data
input wire m_rx_en_17, // MII Receive Frame Enable
input wire m_rx_err_17, // MII Receive Drame Error
output wire [3:0] m_tx_d_17, // MII Transmit Data
output wire m_tx_en_17, // MII Transmit Frame Enable
output wire m_tx_err_17, // MII Transmit Frame Error
output wire tx_control_17,
output wire [3:0] rgmii_out_17,
input wire [3:0] rgmii_in_17,
input wire rx_control_17,
output wire eth_mode_17, // Ethernet Mode
output wire ena_10_17, // Enable 10Mbps Mode
input wire set_1000_17, // Gigabit Mode Enable
input wire set_10_17, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// CHANNEL 18
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_18, // Carrier Sense
input wire m_rx_col_18, // Collition
input wire rx_clk_18, // Receive Clock
input wire tx_clk_18, // Transmit Clock
input wire [7:0] gm_rx_d_18, // GMII Receive Data
input wire gm_rx_dv_18, // GMII Receive Frame Enable
input wire gm_rx_err_18, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_18, // GMII Transmit Data
output wire gm_tx_en_18, // GMII Transmit Frame Enable
output wire gm_tx_err_18, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_18, // MII Receive Data
input wire m_rx_en_18, // MII Receive Frame Enable
input wire m_rx_err_18, // MII Receive Drame Error
output wire [3:0] m_tx_d_18, // MII Transmit Data
output wire m_tx_en_18, // MII Transmit Frame Enable
output wire m_tx_err_18, // MII Transmit Frame Error
output wire tx_control_18,
output wire [3:0] rgmii_out_18,
input wire [3:0] rgmii_in_18,
input wire rx_control_18,
output wire eth_mode_18, // Ethernet Mode
output wire ena_10_18, // Enable 10Mbps Mode
input wire set_1000_18, // Gigabit Mode Enable
input wire set_10_18, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// CHANNEL 19
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_19, // Carrier Sense
input wire m_rx_col_19, // Collition
input wire rx_clk_19, // Receive Clock
input wire tx_clk_19, // Transmit Clock
input wire [7:0] gm_rx_d_19, // GMII Receive Data
input wire gm_rx_dv_19, // GMII Receive Frame Enable
input wire gm_rx_err_19, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_19, // GMII Transmit Data
output wire gm_tx_en_19, // GMII Transmit Frame Enable
output wire gm_tx_err_19, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_19, // MII Receive Data
input wire m_rx_en_19, // MII Receive Frame Enable
input wire m_rx_err_19, // MII Receive Drame Error
output wire [3:0] m_tx_d_19, // MII Transmit Data
output wire m_tx_en_19, // MII Transmit Frame Enable
output wire m_tx_err_19, // MII Transmit Frame Error
output wire tx_control_19,
output wire [3:0] rgmii_out_19,
input wire [3:0] rgmii_in_19,
input wire rx_control_19,
output wire eth_mode_19, // Ethernet Mode
output wire ena_10_19, // Enable 10Mbps Mode
input wire set_1000_19, // Gigabit Mode Enable
input wire set_10_19, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// CHANNEL 20
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_20, // Carrier Sense
input wire m_rx_col_20, // Collition
input wire rx_clk_20, // Receive Clock
input wire tx_clk_20, // Transmit Clock
input wire [7:0] gm_rx_d_20, // GMII Receive Data
input wire gm_rx_dv_20, // GMII Receive Frame Enable
input wire gm_rx_err_20, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_20, // GMII Transmit Data
output wire gm_tx_en_20, // GMII Transmit Frame Enable
output wire gm_tx_err_20, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_20, // MII Receive Data
input wire m_rx_en_20, // MII Receive Frame Enable
input wire m_rx_err_20, // MII Receive Drame Error
output wire [3:0] m_tx_d_20, // MII Transmit Data
output wire m_tx_en_20, // MII Transmit Frame Enable
output wire m_tx_err_20, // MII Transmit Frame Error
output wire tx_control_20,
output wire [3:0] rgmii_out_20,
input wire [3:0] rgmii_in_20,
input wire rx_control_20,
output wire eth_mode_20, // Ethernet Mode
output wire ena_10_20, // Enable 10Mbps Mode
input wire set_1000_20, // Gigabit Mode Enable
input wire set_10_20, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// CHANNEL 21
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_21, // Carrier Sense
input wire m_rx_col_21, // Collition
input wire rx_clk_21, // Receive Clock
input wire tx_clk_21, // Transmit Clock
input wire [7:0] gm_rx_d_21, // GMII Receive Data
input wire gm_rx_dv_21, // GMII Receive Frame Enable
input wire gm_rx_err_21, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_21, // GMII Transmit Data
output wire gm_tx_en_21, // GMII Transmit Frame Enable
output wire gm_tx_err_21, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_21, // MII Receive Data
input wire m_rx_en_21, // MII Receive Frame Enable
input wire m_rx_err_21, // MII Receive Drame Error
output wire [3:0] m_tx_d_21, // MII Transmit Data
output wire m_tx_en_21, // MII Transmit Frame Enable
output wire m_tx_err_21, // MII Transmit Frame Error
output wire tx_control_21,
output wire [3:0] rgmii_out_21,
input wire [3:0] rgmii_in_21,
input wire rx_control_21,
output wire eth_mode_21, // Ethernet Mode
output wire ena_10_21, // Enable 10Mbps Mode
input wire set_1000_21, // Gigabit Mode Enable
input wire set_10_21, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// CHANNEL 22
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_22, // Carrier Sense
input wire m_rx_col_22, // Collition
input wire rx_clk_22, // Receive Clock
input wire tx_clk_22, // Transmit Clock
input wire [7:0] gm_rx_d_22, // GMII Receive Data
input wire gm_rx_dv_22, // GMII Receive Frame Enable
input wire gm_rx_err_22, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_22, // GMII Transmit Data
output wire gm_tx_en_22, // GMII Transmit Frame Enable
output wire gm_tx_err_22, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_22, // MII Receive Data
input wire m_rx_en_22, // MII Receive Frame Enable
input wire m_rx_err_22, // MII Receive Drame Error
output wire [3:0] m_tx_d_22, // MII Transmit Data
output wire m_tx_en_22, // MII Transmit Frame Enable
output wire m_tx_err_22, // MII Transmit Frame Error
output wire tx_control_22,
output wire [3:0] rgmii_out_22,
input wire [3:0] rgmii_in_22,
input wire rx_control_22,
output wire eth_mode_22, // Ethernet Mode
output wire ena_10_22, // Enable 10Mbps Mode
input wire set_1000_22, // Gigabit Mode Enable
input wire set_10_22, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// CHANNEL 23
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_23, // Carrier Sense
input wire m_rx_col_23, // Collition
input wire rx_clk_23, // Receive Clock
input wire tx_clk_23, // Transmit Clock
input wire [7:0] gm_rx_d_23, // GMII Receive Data
input wire gm_rx_dv_23, // GMII Receive Frame Enable
input wire gm_rx_err_23, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_23, // GMII Transmit Data
output wire gm_tx_en_23, // GMII Transmit Frame Enable
output wire gm_tx_err_23, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_23, // MII Receive Data
input wire m_rx_en_23, // MII Receive Frame Enable
input wire m_rx_err_23, // MII Receive Drame Error
output wire [3:0] m_tx_d_23, // MII Transmit Data
output wire m_tx_en_23, // MII Transmit Frame Enable
output wire m_tx_err_23, // MII Transmit Frame Error
output wire tx_control_23,
output wire [3:0] rgmii_out_23,
input wire [3:0] rgmii_in_23,
input wire rx_control_23,
output wire eth_mode_23, // Ethernet Mode
output wire ena_10_23, // Enable 10Mbps Mode
input wire set_1000_23, // Gigabit Mode Enable
input wire set_10_23, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23); // Wake Up Request
altera_tse_top_multi_mac U_TOP_MULTI_MAC(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.rx_clk(rx_clk), //INPUT : MAC RX CLK
.tx_clk(tx_clk), //INPUT : MAC TX CLK
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.rx_clk_0(rx_clk_0), //INPUT : MAC RX CLK
.tx_clk_0(tx_clk_0), //INPUT : MAC TX CLK
.gm_rx_d_0(gm_rx_d_0), //INPUT : GMII RX DATA
.gm_rx_dv_0(gm_rx_dv_0), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_0(gm_rx_err_0), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_0(gm_tx_d_0), //OUTPUT : GMII TX DATA
.gm_tx_en_0(gm_tx_en_0), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_0(gm_tx_err_0), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_0(m_rx_crs_0), //INPUT : MII RX CARRIER SENSE
.m_rx_col_0(m_rx_col_0), //INPUT : MII RX COLLISION
.m_rx_d_0(m_rx_d_0), //INPUT : MII RX DATA
.m_rx_en_0(m_rx_en_0), //INPUT : MII RX VALID INDICATION
.m_rx_err_0(m_rx_err_0), //INPUT : MII RX ERROR INDICATION
.m_tx_d_0(m_tx_d_0), //OUTPUT : MII TX DATA
.m_tx_en_0(m_tx_en_0), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_0(m_tx_err_0), //OUTPUT : MII TX ERROR INDICATION
.rx_control_0(rx_control_0), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_0(rgmii_in_0), //INPUT : RGMII RX DATA INDICATION
.tx_control_0(tx_control_0), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_0(rgmii_out_0), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_0(eth_mode_0), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_0(ena_10_0), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_0(set_10_0), //INPUT : SPEED 10 MBPS
.set_1000_0(set_1000_0), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_clk_1(rx_clk_1), //INPUT : MAC RX CLK
.tx_clk_1(tx_clk_1), //INPUT : MAC TX CLK
.gm_rx_d_1(gm_rx_d_1), //INPUT : GMII RX DATA
.gm_rx_dv_1(gm_rx_dv_1), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_1(gm_rx_err_1), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_1(gm_tx_d_1), //OUTPUT : GMII TX DATA
.gm_tx_en_1(gm_tx_en_1), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_1(gm_tx_err_1), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_1(m_rx_crs_1), //INPUT : MII RX CARRIER SENSE
.m_rx_col_1(m_rx_col_1), //INPUT : MII RX COLLISION
.m_rx_d_1(m_rx_d_1), //INPUT : MII RX DATA
.m_rx_en_1(m_rx_en_1), //INPUT : MII RX VALID INDICATION
.m_rx_err_1(m_rx_err_1), //INPUT : MII RX ERROR INDICATION
.m_tx_d_1(m_tx_d_1), //OUTPUT : MII TX DATA
.m_tx_en_1(m_tx_en_1), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_1(m_tx_err_1), //OUTPUT : MII TX ERROR INDICATION
.rx_control_1(rx_control_1), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_1(rgmii_in_1), //INPUT : RGMII RX DATA INDICATION
.tx_control_1(tx_control_1), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_1(rgmii_out_1), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_1(eth_mode_1), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_1(ena_10_1), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_1(set_10_1), //INPUT : SPEED 10 MBPS
.set_1000_1(set_1000_1), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_clk_2(rx_clk_2), //INPUT : MAC RX CLK
.tx_clk_2(tx_clk_2), //INPUT : MAC TX CLK
.gm_rx_d_2(gm_rx_d_2), //INPUT : GMII RX DATA
.gm_rx_dv_2(gm_rx_dv_2), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_2(gm_rx_err_2), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_2(gm_tx_d_2), //OUTPUT : GMII TX DATA
.gm_tx_en_2(gm_tx_en_2), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_2(gm_tx_err_2), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_2(m_rx_crs_2), //INPUT : MII RX CARRIER SENSE
.m_rx_col_2(m_rx_col_2), //INPUT : MII RX COLLISION
.m_rx_d_2(m_rx_d_2), //INPUT : MII RX DATA
.m_rx_en_2(m_rx_en_2), //INPUT : MII RX VALID INDICATION
.m_rx_err_2(m_rx_err_2), //INPUT : MII RX ERROR INDICATION
.m_tx_d_2(m_tx_d_2), //OUTPUT : MII TX DATA
.m_tx_en_2(m_tx_en_2), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_2(m_tx_err_2), //OUTPUT : MII TX ERROR INDICATION
.rx_control_2(rx_control_2), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_2(rgmii_in_2), //INPUT : RGMII RX DATA INDICATION
.tx_control_2(tx_control_2), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_2(rgmii_out_2), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_2(eth_mode_2), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_2(ena_10_2), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_2(set_10_2), //INPUT : SPEED 10 MBPS
.set_1000_2(set_1000_2), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_clk_3(rx_clk_3), //INPUT : MAC RX CLK
.tx_clk_3(tx_clk_3), //INPUT : MAC TX CLK
.gm_rx_d_3(gm_rx_d_3), //INPUT : GMII RX DATA
.gm_rx_dv_3(gm_rx_dv_3), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_3(gm_rx_err_3), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_3(gm_tx_d_3), //OUTPUT : GMII TX DATA
.gm_tx_en_3(gm_tx_en_3), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_3(gm_tx_err_3), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_3(m_rx_crs_3), //INPUT : MII RX CARRIER SENSE
.m_rx_col_3(m_rx_col_3), //INPUT : MII RX COLLISION
.m_rx_d_3(m_rx_d_3), //INPUT : MII RX DATA
.m_rx_en_3(m_rx_en_3), //INPUT : MII RX VALID INDICATION
.m_rx_err_3(m_rx_err_3), //INPUT : MII RX ERROR INDICATION
.m_tx_d_3(m_tx_d_3), //OUTPUT : MII TX DATA
.m_tx_en_3(m_tx_en_3), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_3(m_tx_err_3), //OUTPUT : MII TX ERROR INDICATION
.rx_control_3(rx_control_3), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_3(rgmii_in_3), //INPUT : RGMII RX DATA INDICATION
.tx_control_3(tx_control_3), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_3(rgmii_out_3), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_3(eth_mode_3), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_3(ena_10_3), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_3(set_10_3), //INPUT : SPEED 10 MBPS
.set_1000_3(set_1000_3), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_clk_4(rx_clk_4), //INPUT : MAC RX CLK
.tx_clk_4(tx_clk_4), //INPUT : MAC TX CLK
.gm_rx_d_4(gm_rx_d_4), //INPUT : GMII RX DATA
.gm_rx_dv_4(gm_rx_dv_4), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_4(gm_rx_err_4), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_4(gm_tx_d_4), //OUTPUT : GMII TX DATA
.gm_tx_en_4(gm_tx_en_4), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_4(gm_tx_err_4), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_4(m_rx_crs_4), //INPUT : MII RX CARRIER SENSE
.m_rx_col_4(m_rx_col_4), //INPUT : MII RX COLLISION
.m_rx_d_4(m_rx_d_4), //INPUT : MII RX DATA
.m_rx_en_4(m_rx_en_4), //INPUT : MII RX VALID INDICATION
.m_rx_err_4(m_rx_err_4), //INPUT : MII RX ERROR INDICATION
.m_tx_d_4(m_tx_d_4), //OUTPUT : MII TX DATA
.m_tx_en_4(m_tx_en_4), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_4(m_tx_err_4), //OUTPUT : MII TX ERROR INDICATION
.rx_control_4(rx_control_4), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_4(rgmii_in_4), //INPUT : RGMII RX DATA INDICATION
.tx_control_4(tx_control_4), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_4(rgmii_out_4), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_4(eth_mode_4), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_4(ena_10_4), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_4(set_10_4), //INPUT : SPEED 10 MBPS
.set_1000_4(set_1000_4), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_clk_5(rx_clk_5), //INPUT : MAC RX CLK
.tx_clk_5(tx_clk_5), //INPUT : MAC TX CLK
.gm_rx_d_5(gm_rx_d_5), //INPUT : GMII RX DATA
.gm_rx_dv_5(gm_rx_dv_5), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_5(gm_rx_err_5), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_5(gm_tx_d_5), //OUTPUT : GMII TX DATA
.gm_tx_en_5(gm_tx_en_5), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_5(gm_tx_err_5), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_5(m_rx_crs_5), //INPUT : MII RX CARRIER SENSE
.m_rx_col_5(m_rx_col_5), //INPUT : MII RX COLLISION
.m_rx_d_5(m_rx_d_5), //INPUT : MII RX DATA
.m_rx_en_5(m_rx_en_5), //INPUT : MII RX VALID INDICATION
.m_rx_err_5(m_rx_err_5), //INPUT : MII RX ERROR INDICATION
.m_tx_d_5(m_tx_d_5), //OUTPUT : MII TX DATA
.m_tx_en_5(m_tx_en_5), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_5(m_tx_err_5), //OUTPUT : MII TX ERROR INDICATION
.rx_control_5(rx_control_5), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_5(rgmii_in_5), //INPUT : RGMII RX DATA INDICATION
.tx_control_5(tx_control_5), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_5(rgmii_out_5), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_5(eth_mode_5), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_5(ena_10_5), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_5(set_10_5), //INPUT : SPEED 10 MBPS
.set_1000_5(set_1000_5), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_clk_6(rx_clk_6), //INPUT : MAC RX CLK
.tx_clk_6(tx_clk_6), //INPUT : MAC TX CLK
.gm_rx_d_6(gm_rx_d_6), //INPUT : GMII RX DATA
.gm_rx_dv_6(gm_rx_dv_6), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_6(gm_rx_err_6), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_6(gm_tx_d_6), //OUTPUT : GMII TX DATA
.gm_tx_en_6(gm_tx_en_6), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_6(gm_tx_err_6), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_6(m_rx_crs_6), //INPUT : MII RX CARRIER SENSE
.m_rx_col_6(m_rx_col_6), //INPUT : MII RX COLLISION
.m_rx_d_6(m_rx_d_6), //INPUT : MII RX DATA
.m_rx_en_6(m_rx_en_6), //INPUT : MII RX VALID INDICATION
.m_rx_err_6(m_rx_err_6), //INPUT : MII RX ERROR INDICATION
.m_tx_d_6(m_tx_d_6), //OUTPUT : MII TX DATA
.m_tx_en_6(m_tx_en_6), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_6(m_tx_err_6), //OUTPUT : MII TX ERROR INDICATION
.rx_control_6(rx_control_6), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_6(rgmii_in_6), //INPUT : RGMII RX DATA INDICATION
.tx_control_6(tx_control_6), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_6(rgmii_out_6), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_6(eth_mode_6), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_6(ena_10_6), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_6(set_10_6), //INPUT : SPEED 10 MBPS
.set_1000_6(set_1000_6), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_clk_7(rx_clk_7), //INPUT : MAC RX CLK
.tx_clk_7(tx_clk_7), //INPUT : MAC TX CLK
.gm_rx_d_7(gm_rx_d_7), //INPUT : GMII RX DATA
.gm_rx_dv_7(gm_rx_dv_7), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_7(gm_rx_err_7), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_7(gm_tx_d_7), //OUTPUT : GMII TX DATA
.gm_tx_en_7(gm_tx_en_7), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_7(gm_tx_err_7), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_7(m_rx_crs_7), //INPUT : MII RX CARRIER SENSE
.m_rx_col_7(m_rx_col_7), //INPUT : MII RX COLLISION
.m_rx_d_7(m_rx_d_7), //INPUT : MII RX DATA
.m_rx_en_7(m_rx_en_7), //INPUT : MII RX VALID INDICATION
.m_rx_err_7(m_rx_err_7), //INPUT : MII RX ERROR INDICATION
.m_tx_d_7(m_tx_d_7), //OUTPUT : MII TX DATA
.m_tx_en_7(m_tx_en_7), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_7(m_tx_err_7), //OUTPUT : MII TX ERROR INDICATION
.rx_control_7(rx_control_7), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_7(rgmii_in_7), //INPUT : RGMII RX DATA INDICATION
.tx_control_7(tx_control_7), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_7(rgmii_out_7), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_7(eth_mode_7), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_7(ena_10_7), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_7(set_10_7), //INPUT : SPEED 10 MBPS
.set_1000_7(set_1000_7), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_clk_8(rx_clk_8), //INPUT : MAC RX CLK
.tx_clk_8(tx_clk_8), //INPUT : MAC TX CLK
.gm_rx_d_8(gm_rx_d_8), //INPUT : GMII RX DATA
.gm_rx_dv_8(gm_rx_dv_8), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_8(gm_rx_err_8), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_8(gm_tx_d_8), //OUTPUT : GMII TX DATA
.gm_tx_en_8(gm_tx_en_8), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_8(gm_tx_err_8), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_8(m_rx_crs_8), //INPUT : MII RX CARRIER SENSE
.m_rx_col_8(m_rx_col_8), //INPUT : MII RX COLLISION
.m_rx_d_8(m_rx_d_8), //INPUT : MII RX DATA
.m_rx_en_8(m_rx_en_8), //INPUT : MII RX VALID INDICATION
.m_rx_err_8(m_rx_err_8), //INPUT : MII RX ERROR INDICATION
.m_tx_d_8(m_tx_d_8), //OUTPUT : MII TX DATA
.m_tx_en_8(m_tx_en_8), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_8(m_tx_err_8), //OUTPUT : MII TX ERROR INDICATION
.rx_control_8(rx_control_8), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_8(rgmii_in_8), //INPUT : RGMII RX DATA INDICATION
.tx_control_8(tx_control_8), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_8(rgmii_out_8), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_8(eth_mode_8), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_8(ena_10_8), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_8(set_10_8), //INPUT : SPEED 10 MBPS
.set_1000_8(set_1000_8), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_clk_9(rx_clk_9), //INPUT : MAC RX CLK
.tx_clk_9(tx_clk_9), //INPUT : MAC TX CLK
.gm_rx_d_9(gm_rx_d_9), //INPUT : GMII RX DATA
.gm_rx_dv_9(gm_rx_dv_9), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_9(gm_rx_err_9), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_9(gm_tx_d_9), //OUTPUT : GMII TX DATA
.gm_tx_en_9(gm_tx_en_9), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_9(gm_tx_err_9), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_9(m_rx_crs_9), //INPUT : MII RX CARRIER SENSE
.m_rx_col_9(m_rx_col_9), //INPUT : MII RX COLLISION
.m_rx_d_9(m_rx_d_9), //INPUT : MII RX DATA
.m_rx_en_9(m_rx_en_9), //INPUT : MII RX VALID INDICATION
.m_rx_err_9(m_rx_err_9), //INPUT : MII RX ERROR INDICATION
.m_tx_d_9(m_tx_d_9), //OUTPUT : MII TX DATA
.m_tx_en_9(m_tx_en_9), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_9(m_tx_err_9), //OUTPUT : MII TX ERROR INDICATION
.rx_control_9(rx_control_9), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_9(rgmii_in_9), //INPUT : RGMII RX DATA INDICATION
.tx_control_9(tx_control_9), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_9(rgmii_out_9), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_9(eth_mode_9), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_9(ena_10_9), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_9(set_10_9), //INPUT : SPEED 10 MBPS
.set_1000_9(set_1000_9), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_clk_10(rx_clk_10), //INPUT : MAC RX CLK
.tx_clk_10(tx_clk_10), //INPUT : MAC TX CLK
.gm_rx_d_10(gm_rx_d_10), //INPUT : GMII RX DATA
.gm_rx_dv_10(gm_rx_dv_10), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_10(gm_rx_err_10), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_10(gm_tx_d_10), //OUTPUT : GMII TX DATA
.gm_tx_en_10(gm_tx_en_10), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_10(gm_tx_err_10), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_10(m_rx_crs_10), //INPUT : MII RX CARRIER SENSE
.m_rx_col_10(m_rx_col_10), //INPUT : MII RX COLLISION
.m_rx_d_10(m_rx_d_10), //INPUT : MII RX DATA
.m_rx_en_10(m_rx_en_10), //INPUT : MII RX VALID INDICATION
.m_rx_err_10(m_rx_err_10), //INPUT : MII RX ERROR INDICATION
.m_tx_d_10(m_tx_d_10), //OUTPUT : MII TX DATA
.m_tx_en_10(m_tx_en_10), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_10(m_tx_err_10), //OUTPUT : MII TX ERROR INDICATION
.rx_control_10(rx_control_10), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_10(rgmii_in_10), //INPUT : RGMII RX DATA INDICATION
.tx_control_10(tx_control_10), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_10(rgmii_out_10), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_10(eth_mode_10), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_10(ena_10_10), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_10(set_10_10), //INPUT : SPEED 10 MBPS
.set_1000_10(set_1000_10), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_clk_11(rx_clk_11), //INPUT : MAC RX CLK
.tx_clk_11(tx_clk_11), //INPUT : MAC TX CLK
.gm_rx_d_11(gm_rx_d_11), //INPUT : GMII RX DATA
.gm_rx_dv_11(gm_rx_dv_11), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_11(gm_rx_err_11), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_11(gm_tx_d_11), //OUTPUT : GMII TX DATA
.gm_tx_en_11(gm_tx_en_11), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_11(gm_tx_err_11), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_11(m_rx_crs_11), //INPUT : MII RX CARRIER SENSE
.m_rx_col_11(m_rx_col_11), //INPUT : MII RX COLLISION
.m_rx_d_11(m_rx_d_11), //INPUT : MII RX DATA
.m_rx_en_11(m_rx_en_11), //INPUT : MII RX VALID INDICATION
.m_rx_err_11(m_rx_err_11), //INPUT : MII RX ERROR INDICATION
.m_tx_d_11(m_tx_d_11), //OUTPUT : MII TX DATA
.m_tx_en_11(m_tx_en_11), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_11(m_tx_err_11), //OUTPUT : MII TX ERROR INDICATION
.rx_control_11(rx_control_11), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_11(rgmii_in_11), //INPUT : RGMII RX DATA INDICATION
.tx_control_11(tx_control_11), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_11(rgmii_out_11), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_11(eth_mode_11), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_11(ena_10_11), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_11(set_10_11), //INPUT : SPEED 10 MBPS
.set_1000_11(set_1000_11), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_clk_12(rx_clk_12), //INPUT : MAC RX CLK
.tx_clk_12(tx_clk_12), //INPUT : MAC TX CLK
.gm_rx_d_12(gm_rx_d_12), //INPUT : GMII RX DATA
.gm_rx_dv_12(gm_rx_dv_12), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_12(gm_rx_err_12), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_12(gm_tx_d_12), //OUTPUT : GMII TX DATA
.gm_tx_en_12(gm_tx_en_12), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_12(gm_tx_err_12), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_12(m_rx_crs_12), //INPUT : MII RX CARRIER SENSE
.m_rx_col_12(m_rx_col_12), //INPUT : MII RX COLLISION
.m_rx_d_12(m_rx_d_12), //INPUT : MII RX DATA
.m_rx_en_12(m_rx_en_12), //INPUT : MII RX VALID INDICATION
.m_rx_err_12(m_rx_err_12), //INPUT : MII RX ERROR INDICATION
.m_tx_d_12(m_tx_d_12), //OUTPUT : MII TX DATA
.m_tx_en_12(m_tx_en_12), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_12(m_tx_err_12), //OUTPUT : MII TX ERROR INDICATION
.rx_control_12(rx_control_12), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_12(rgmii_in_12), //INPUT : RGMII RX DATA INDICATION
.tx_control_12(tx_control_12), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_12(rgmii_out_12), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_12(eth_mode_12), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_12(ena_10_12), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_12(set_10_12), //INPUT : SPEED 10 MBPS
.set_1000_12(set_1000_12), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_clk_13(rx_clk_13), //INPUT : MAC RX CLK
.tx_clk_13(tx_clk_13), //INPUT : MAC TX CLK
.gm_rx_d_13(gm_rx_d_13), //INPUT : GMII RX DATA
.gm_rx_dv_13(gm_rx_dv_13), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_13(gm_rx_err_13), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_13(gm_tx_d_13), //OUTPUT : GMII TX DATA
.gm_tx_en_13(gm_tx_en_13), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_13(gm_tx_err_13), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_13(m_rx_crs_13), //INPUT : MII RX CARRIER SENSE
.m_rx_col_13(m_rx_col_13), //INPUT : MII RX COLLISION
.m_rx_d_13(m_rx_d_13), //INPUT : MII RX DATA
.m_rx_en_13(m_rx_en_13), //INPUT : MII RX VALID INDICATION
.m_rx_err_13(m_rx_err_13), //INPUT : MII RX ERROR INDICATION
.m_tx_d_13(m_tx_d_13), //OUTPUT : MII TX DATA
.m_tx_en_13(m_tx_en_13), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_13(m_tx_err_13), //OUTPUT : MII TX ERROR INDICATION
.rx_control_13(rx_control_13), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_13(rgmii_in_13), //INPUT : RGMII RX DATA INDICATION
.tx_control_13(tx_control_13), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_13(rgmii_out_13), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_13(eth_mode_13), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_13(ena_10_13), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_13(set_10_13), //INPUT : SPEED 10 MBPS
.set_1000_13(set_1000_13), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_clk_14(rx_clk_14), //INPUT : MAC RX CLK
.tx_clk_14(tx_clk_14), //INPUT : MAC TX CLK
.gm_rx_d_14(gm_rx_d_14), //INPUT : GMII RX DATA
.gm_rx_dv_14(gm_rx_dv_14), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_14(gm_rx_err_14), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_14(gm_tx_d_14), //OUTPUT : GMII TX DATA
.gm_tx_en_14(gm_tx_en_14), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_14(gm_tx_err_14), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_14(m_rx_crs_14), //INPUT : MII RX CARRIER SENSE
.m_rx_col_14(m_rx_col_14), //INPUT : MII RX COLLISION
.m_rx_d_14(m_rx_d_14), //INPUT : MII RX DATA
.m_rx_en_14(m_rx_en_14), //INPUT : MII RX VALID INDICATION
.m_rx_err_14(m_rx_err_14), //INPUT : MII RX ERROR INDICATION
.m_tx_d_14(m_tx_d_14), //OUTPUT : MII TX DATA
.m_tx_en_14(m_tx_en_14), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_14(m_tx_err_14), //OUTPUT : MII TX ERROR INDICATION
.rx_control_14(rx_control_14), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_14(rgmii_in_14), //INPUT : RGMII RX DATA INDICATION
.tx_control_14(tx_control_14), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_14(rgmii_out_14), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_14(eth_mode_14), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_14(ena_10_14), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_14(set_10_14), //INPUT : SPEED 10 MBPS
.set_1000_14(set_1000_14), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_clk_15(rx_clk_15), //INPUT : MAC RX CLK
.tx_clk_15(tx_clk_15), //INPUT : MAC TX CLK
.gm_rx_d_15(gm_rx_d_15), //INPUT : GMII RX DATA
.gm_rx_dv_15(gm_rx_dv_15), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_15(gm_rx_err_15), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_15(gm_tx_d_15), //OUTPUT : GMII TX DATA
.gm_tx_en_15(gm_tx_en_15), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_15(gm_tx_err_15), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_15(m_rx_crs_15), //INPUT : MII RX CARRIER SENSE
.m_rx_col_15(m_rx_col_15), //INPUT : MII RX COLLISION
.m_rx_d_15(m_rx_d_15), //INPUT : MII RX DATA
.m_rx_en_15(m_rx_en_15), //INPUT : MII RX VALID INDICATION
.m_rx_err_15(m_rx_err_15), //INPUT : MII RX ERROR INDICATION
.m_tx_d_15(m_tx_d_15), //OUTPUT : MII TX DATA
.m_tx_en_15(m_tx_en_15), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_15(m_tx_err_15), //OUTPUT : MII TX ERROR INDICATION
.rx_control_15(rx_control_15), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_15(rgmii_in_15), //INPUT : RGMII RX DATA INDICATION
.tx_control_15(tx_control_15), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_15(rgmii_out_15), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_15(eth_mode_15), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_15(ena_10_15), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_15(set_10_15), //INPUT : SPEED 10 MBPS
.set_1000_15(set_1000_15), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_clk_16(rx_clk_16), //INPUT : MAC RX CLK
.tx_clk_16(tx_clk_16), //INPUT : MAC TX CLK
.gm_rx_d_16(gm_rx_d_16), //INPUT : GMII RX DATA
.gm_rx_dv_16(gm_rx_dv_16), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_16(gm_rx_err_16), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_16(gm_tx_d_16), //OUTPUT : GMII TX DATA
.gm_tx_en_16(gm_tx_en_16), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_16(gm_tx_err_16), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_16(m_rx_crs_16), //INPUT : MII RX CARRIER SENSE
.m_rx_col_16(m_rx_col_16), //INPUT : MII RX COLLISION
.m_rx_d_16(m_rx_d_16), //INPUT : MII RX DATA
.m_rx_en_16(m_rx_en_16), //INPUT : MII RX VALID INDICATION
.m_rx_err_16(m_rx_err_16), //INPUT : MII RX ERROR INDICATION
.m_tx_d_16(m_tx_d_16), //OUTPUT : MII TX DATA
.m_tx_en_16(m_tx_en_16), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_16(m_tx_err_16), //OUTPUT : MII TX ERROR INDICATION
.rx_control_16(rx_control_16), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_16(rgmii_in_16), //INPUT : RGMII RX DATA INDICATION
.tx_control_16(tx_control_16), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_16(rgmii_out_16), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_16(eth_mode_16), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_16(ena_10_16), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_16(set_10_16), //INPUT : SPEED 10 MBPS
.set_1000_16(set_1000_16), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_clk_17(rx_clk_17), //INPUT : MAC RX CLK
.tx_clk_17(tx_clk_17), //INPUT : MAC TX CLK
.gm_rx_d_17(gm_rx_d_17), //INPUT : GMII RX DATA
.gm_rx_dv_17(gm_rx_dv_17), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_17(gm_rx_err_17), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_17(gm_tx_d_17), //OUTPUT : GMII TX DATA
.gm_tx_en_17(gm_tx_en_17), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_17(gm_tx_err_17), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_17(m_rx_crs_17), //INPUT : MII RX CARRIER SENSE
.m_rx_col_17(m_rx_col_17), //INPUT : MII RX COLLISION
.m_rx_d_17(m_rx_d_17), //INPUT : MII RX DATA
.m_rx_en_17(m_rx_en_17), //INPUT : MII RX VALID INDICATION
.m_rx_err_17(m_rx_err_17), //INPUT : MII RX ERROR INDICATION
.m_tx_d_17(m_tx_d_17), //OUTPUT : MII TX DATA
.m_tx_en_17(m_tx_en_17), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_17(m_tx_err_17), //OUTPUT : MII TX ERROR INDICATION
.rx_control_17(rx_control_17), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_17(rgmii_in_17), //INPUT : RGMII RX DATA INDICATION
.tx_control_17(tx_control_17), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_17(rgmii_out_17), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_17(eth_mode_17), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_17(ena_10_17), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_17(set_10_17), //INPUT : SPEED 10 MBPS
.set_1000_17(set_1000_17), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_clk_18(rx_clk_18), //INPUT : MAC RX CLK
.tx_clk_18(tx_clk_18), //INPUT : MAC TX CLK
.gm_rx_d_18(gm_rx_d_18), //INPUT : GMII RX DATA
.gm_rx_dv_18(gm_rx_dv_18), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_18(gm_rx_err_18), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_18(gm_tx_d_18), //OUTPUT : GMII TX DATA
.gm_tx_en_18(gm_tx_en_18), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_18(gm_tx_err_18), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_18(m_rx_crs_18), //INPUT : MII RX CARRIER SENSE
.m_rx_col_18(m_rx_col_18), //INPUT : MII RX COLLISION
.m_rx_d_18(m_rx_d_18), //INPUT : MII RX DATA
.m_rx_en_18(m_rx_en_18), //INPUT : MII RX VALID INDICATION
.m_rx_err_18(m_rx_err_18), //INPUT : MII RX ERROR INDICATION
.m_tx_d_18(m_tx_d_18), //OUTPUT : MII TX DATA
.m_tx_en_18(m_tx_en_18), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_18(m_tx_err_18), //OUTPUT : MII TX ERROR INDICATION
.rx_control_18(rx_control_18), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_18(rgmii_in_18), //INPUT : RGMII RX DATA INDICATION
.tx_control_18(tx_control_18), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_18(rgmii_out_18), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_18(eth_mode_18), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_18(ena_10_18), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_18(set_10_18), //INPUT : SPEED 10 MBPS
.set_1000_18(set_1000_18), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_clk_19(rx_clk_19), //INPUT : MAC RX CLK
.tx_clk_19(tx_clk_19), //INPUT : MAC TX CLK
.gm_rx_d_19(gm_rx_d_19), //INPUT : GMII RX DATA
.gm_rx_dv_19(gm_rx_dv_19), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_19(gm_rx_err_19), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_19(gm_tx_d_19), //OUTPUT : GMII TX DATA
.gm_tx_en_19(gm_tx_en_19), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_19(gm_tx_err_19), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_19(m_rx_crs_19), //INPUT : MII RX CARRIER SENSE
.m_rx_col_19(m_rx_col_19), //INPUT : MII RX COLLISION
.m_rx_d_19(m_rx_d_19), //INPUT : MII RX DATA
.m_rx_en_19(m_rx_en_19), //INPUT : MII RX VALID INDICATION
.m_rx_err_19(m_rx_err_19), //INPUT : MII RX ERROR INDICATION
.m_tx_d_19(m_tx_d_19), //OUTPUT : MII TX DATA
.m_tx_en_19(m_tx_en_19), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_19(m_tx_err_19), //OUTPUT : MII TX ERROR INDICATION
.rx_control_19(rx_control_19), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_19(rgmii_in_19), //INPUT : RGMII RX DATA INDICATION
.tx_control_19(tx_control_19), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_19(rgmii_out_19), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_19(eth_mode_19), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_19(ena_10_19), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_19(set_10_19), //INPUT : SPEED 10 MBPS
.set_1000_19(set_1000_19), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_clk_20(rx_clk_20), //INPUT : MAC RX CLK
.tx_clk_20(tx_clk_20), //INPUT : MAC TX CLK
.gm_rx_d_20(gm_rx_d_20), //INPUT : GMII RX DATA
.gm_rx_dv_20(gm_rx_dv_20), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_20(gm_rx_err_20), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_20(gm_tx_d_20), //OUTPUT : GMII TX DATA
.gm_tx_en_20(gm_tx_en_20), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_20(gm_tx_err_20), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_20(m_rx_crs_20), //INPUT : MII RX CARRIER SENSE
.m_rx_col_20(m_rx_col_20), //INPUT : MII RX COLLISION
.m_rx_d_20(m_rx_d_20), //INPUT : MII RX DATA
.m_rx_en_20(m_rx_en_20), //INPUT : MII RX VALID INDICATION
.m_rx_err_20(m_rx_err_20), //INPUT : MII RX ERROR INDICATION
.m_tx_d_20(m_tx_d_20), //OUTPUT : MII TX DATA
.m_tx_en_20(m_tx_en_20), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_20(m_tx_err_20), //OUTPUT : MII TX ERROR INDICATION
.rx_control_20(rx_control_20), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_20(rgmii_in_20), //INPUT : RGMII RX DATA INDICATION
.tx_control_20(tx_control_20), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_20(rgmii_out_20), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_20(eth_mode_20), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_20(ena_10_20), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_20(set_10_20), //INPUT : SPEED 10 MBPS
.set_1000_20(set_1000_20), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_clk_21(rx_clk_21), //INPUT : MAC RX CLK
.tx_clk_21(tx_clk_21), //INPUT : MAC TX CLK
.gm_rx_d_21(gm_rx_d_21), //INPUT : GMII RX DATA
.gm_rx_dv_21(gm_rx_dv_21), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_21(gm_rx_err_21), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_21(gm_tx_d_21), //OUTPUT : GMII TX DATA
.gm_tx_en_21(gm_tx_en_21), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_21(gm_tx_err_21), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_21(m_rx_crs_21), //INPUT : MII RX CARRIER SENSE
.m_rx_col_21(m_rx_col_21), //INPUT : MII RX COLLISION
.m_rx_d_21(m_rx_d_21), //INPUT : MII RX DATA
.m_rx_en_21(m_rx_en_21), //INPUT : MII RX VALID INDICATION
.m_rx_err_21(m_rx_err_21), //INPUT : MII RX ERROR INDICATION
.m_tx_d_21(m_tx_d_21), //OUTPUT : MII TX DATA
.m_tx_en_21(m_tx_en_21), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_21(m_tx_err_21), //OUTPUT : MII TX ERROR INDICATION
.rx_control_21(rx_control_21), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_21(rgmii_in_21), //INPUT : RGMII RX DATA INDICATION
.tx_control_21(tx_control_21), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_21(rgmii_out_21), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_21(eth_mode_21), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_21(ena_10_21), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_21(set_10_21), //INPUT : SPEED 10 MBPS
.set_1000_21(set_1000_21), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_clk_22(rx_clk_22), //INPUT : MAC RX CLK
.tx_clk_22(tx_clk_22), //INPUT : MAC TX CLK
.gm_rx_d_22(gm_rx_d_22), //INPUT : GMII RX DATA
.gm_rx_dv_22(gm_rx_dv_22), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_22(gm_rx_err_22), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_22(gm_tx_d_22), //OUTPUT : GMII TX DATA
.gm_tx_en_22(gm_tx_en_22), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_22(gm_tx_err_22), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_22(m_rx_crs_22), //INPUT : MII RX CARRIER SENSE
.m_rx_col_22(m_rx_col_22), //INPUT : MII RX COLLISION
.m_rx_d_22(m_rx_d_22), //INPUT : MII RX DATA
.m_rx_en_22(m_rx_en_22), //INPUT : MII RX VALID INDICATION
.m_rx_err_22(m_rx_err_22), //INPUT : MII RX ERROR INDICATION
.m_tx_d_22(m_tx_d_22), //OUTPUT : MII TX DATA
.m_tx_en_22(m_tx_en_22), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_22(m_tx_err_22), //OUTPUT : MII TX ERROR INDICATION
.rx_control_22(rx_control_22), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_22(rgmii_in_22), //INPUT : RGMII RX DATA INDICATION
.tx_control_22(tx_control_22), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_22(rgmii_out_22), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_22(eth_mode_22), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_22(ena_10_22), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_22(set_10_22), //INPUT : SPEED 10 MBPS
.set_1000_22(set_1000_22), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_clk_23(rx_clk_23), //INPUT : MAC RX CLK
.tx_clk_23(tx_clk_23), //INPUT : MAC TX CLK
.gm_rx_d_23(gm_rx_d_23), //INPUT : GMII RX DATA
.gm_rx_dv_23(gm_rx_dv_23), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_23(gm_rx_err_23), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_23(gm_tx_d_23), //OUTPUT : GMII TX DATA
.gm_tx_en_23(gm_tx_en_23), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_23(gm_tx_err_23), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_23(m_rx_crs_23), //INPUT : MII RX CARRIER SENSE
.m_rx_col_23(m_rx_col_23), //INPUT : MII RX COLLISION
.m_rx_d_23(m_rx_d_23), //INPUT : MII RX DATA
.m_rx_en_23(m_rx_en_23), //INPUT : MII RX VALID INDICATION
.m_rx_err_23(m_rx_err_23), //INPUT : MII RX ERROR INDICATION
.m_tx_d_23(m_tx_d_23), //OUTPUT : MII TX DATA
.m_tx_en_23(m_tx_en_23), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_23(m_tx_err_23), //OUTPUT : MII TX ERROR INDICATION
.rx_control_23(rx_control_23), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_23(rgmii_in_23), //INPUT : RGMII RX DATA INDICATION
.tx_control_23(tx_control_23), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_23(rgmii_out_23), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_23(eth_mode_23), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_23(ena_10_23), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_23(set_10_23), //INPUT : SPEED 10 MBPS
.set_1000_23(set_1000_23), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_TOP_MULTI_MAC.USE_SYNC_RESET = USE_SYNC_RESET,
U_TOP_MULTI_MAC.RESET_LEVEL = RESET_LEVEL,
U_TOP_MULTI_MAC.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_TOP_MULTI_MAC.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_TOP_MULTI_MAC.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_TOP_MULTI_MAC.ENA_HASH = ENA_HASH,
U_TOP_MULTI_MAC.STAT_CNT_ENA = STAT_CNT_ENA,
U_TOP_MULTI_MAC.CORE_VERSION = CORE_VERSION,
U_TOP_MULTI_MAC.CUST_VERSION = CUST_VERSION,
U_TOP_MULTI_MAC.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_TOP_MULTI_MAC.ENABLE_MDIO = ENABLE_MDIO,
U_TOP_MULTI_MAC.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_TOP_MULTI_MAC.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_TOP_MULTI_MAC.CRC32DWIDTH = CRC32DWIDTH,
U_TOP_MULTI_MAC.CRC32GENDELAY = CRC32GENDELAY,
U_TOP_MULTI_MAC.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_TOP_MULTI_MAC.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_TOP_MULTI_MAC.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_TOP_MULTI_MAC.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_TOP_MULTI_MAC.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_TOP_MULTI_MAC.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_TOP_MULTI_MAC.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_TOP_MULTI_MAC.ADDR_WIDTH = ADDR_WIDTH,
U_TOP_MULTI_MAC.MAX_CHANNELS = MAX_CHANNELS,
U_TOP_MULTI_MAC.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_TOP_MULTI_MAC.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_TOP_MULTI_MAC.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_TOP_MULTI_MAC.ENABLE_REG_SHARING = ENABLE_REG_SHARING,
U_TOP_MULTI_MAC.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
U_TOP_MULTI_MAC.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING;
endmodule // module altera_tse_multi_mac
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_multi_mac_pcs
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,C105\"" */
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
input wire ref_clk, // Reference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_0, // 125MHz Recoved Clock
input wire tbi_tx_clk_0, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_0, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_0, // Transmit TBI Interface
output wire sd_loopback_0, // SERDES Loopback Enable
output wire powerdown_0, // Powerdown Enable
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_1, // 125MHz Recoved Clock
input wire tbi_tx_clk_1, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_1, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_1, // Transmit TBI Interface
output wire sd_loopback_1, // SERDES Loopback Enable
output wire powerdown_1, // Powerdown Enable
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_2, // 125MHz Recoved Clock
input wire tbi_tx_clk_2, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_2, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_2, // Transmit TBI Interface
output wire sd_loopback_2, // SERDES Loopback Enable
output wire powerdown_2, // Powerdown Enable
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_3, // 125MHz Recoved Clock
input wire tbi_tx_clk_3, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_3, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_3, // Transmit TBI Interface
output wire sd_loopback_3, // SERDES Loopback Enable
output wire powerdown_3, // Powerdown Enable
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_4, // 125MHz Recoved Clock
input wire tbi_tx_clk_4, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_4, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_4, // Transmit TBI Interface
output wire sd_loopback_4, // SERDES Loopback Enable
output wire powerdown_4, // Powerdown Enable
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_5, // 125MHz Recoved Clock
input wire tbi_tx_clk_5, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_5, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_5, // Transmit TBI Interface
output wire sd_loopback_5, // SERDES Loopback Enable
output wire powerdown_5, // Powerdown Enable
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_6, // 125MHz Recoved Clock
input wire tbi_tx_clk_6, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_6, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_6, // Transmit TBI Interface
output wire sd_loopback_6, // SERDES Loopback Enable
output wire powerdown_6, // Powerdown Enable
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_7, // 125MHz Recoved Clock
input wire tbi_tx_clk_7, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_7, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_7, // Transmit TBI Interface
output wire sd_loopback_7, // SERDES Loopback Enable
output wire powerdown_7, // Powerdown Enable
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_8, // 125MHz Recoved Clock
input wire tbi_tx_clk_8, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_8, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_8, // Transmit TBI Interface
output wire sd_loopback_8, // SERDES Loopback Enable
output wire powerdown_8, // Powerdown Enable
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_9, // 125MHz Recoved Clock
input wire tbi_tx_clk_9, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_9, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_9, // Transmit TBI Interface
output wire sd_loopback_9, // SERDES Loopback Enable
output wire powerdown_9, // Powerdown Enable
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_10, // 125MHz Recoved Clock
input wire tbi_tx_clk_10, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_10, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_10, // Transmit TBI Interface
output wire sd_loopback_10, // SERDES Loopback Enable
output wire powerdown_10, // Powerdown Enable
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_11, // 125MHz Recoved Clock
input wire tbi_tx_clk_11, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_11, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_11, // Transmit TBI Interface
output wire sd_loopback_11, // SERDES Loopback Enable
output wire powerdown_11, // Powerdown Enable
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_12, // 125MHz Recoved Clock
input wire tbi_tx_clk_12, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_12, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_12, // Transmit TBI Interface
output wire sd_loopback_12, // SERDES Loopback Enable
output wire powerdown_12, // Powerdown Enable
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_13, // 125MHz Recoved Clock
input wire tbi_tx_clk_13, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_13, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_13, // Transmit TBI Interface
output wire sd_loopback_13, // SERDES Loopback Enable
output wire powerdown_13, // Powerdown Enable
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_14, // 125MHz Recoved Clock
input wire tbi_tx_clk_14, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_14, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_14, // Transmit TBI Interface
output wire sd_loopback_14, // SERDES Loopback Enable
output wire powerdown_14, // Powerdown Enable
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_15, // 125MHz Recoved Clock
input wire tbi_tx_clk_15, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_15, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_15, // Transmit TBI Interface
output wire sd_loopback_15, // SERDES Loopback Enable
output wire powerdown_15, // Powerdown Enable
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_16, // 125MHz Recoved Clock
input wire tbi_tx_clk_16, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_16, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_16, // Transmit TBI Interface
output wire sd_loopback_16, // SERDES Loopback Enable
output wire powerdown_16, // Powerdown Enable
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_17, // 125MHz Recoved Clock
input wire tbi_tx_clk_17, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_17, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_17, // Transmit TBI Interface
output wire sd_loopback_17, // SERDES Loopback Enable
output wire powerdown_17, // Powerdown Enable
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_18, // 125MHz Recoved Clock
input wire tbi_tx_clk_18, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_18, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_18, // Transmit TBI Interface
output wire sd_loopback_18, // SERDES Loopback Enable
output wire powerdown_18, // Powerdown Enable
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_19, // 125MHz Recoved Clock
input wire tbi_tx_clk_19, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_19, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_19, // Transmit TBI Interface
output wire sd_loopback_19, // SERDES Loopback Enable
output wire powerdown_19, // Powerdown Enable
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_20, // 125MHz Recoved Clock
input wire tbi_tx_clk_20, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_20, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_20, // Transmit TBI Interface
output wire sd_loopback_20, // SERDES Loopback Enable
output wire powerdown_20, // Powerdown Enable
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_21, // 125MHz Recoved Clock
input wire tbi_tx_clk_21, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_21, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_21, // Transmit TBI Interface
output wire sd_loopback_21, // SERDES Loopback Enable
output wire powerdown_21, // Powerdown Enable
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_22, // 125MHz Recoved Clock
input wire tbi_tx_clk_22, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_22, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_22, // Transmit TBI Interface
output wire sd_loopback_22, // SERDES Loopback Enable
output wire powerdown_22, // Powerdown Enable
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_23, // 125MHz Recoved Clock
input wire tbi_tx_clk_23, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_23, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_23, // Transmit TBI Interface
output wire sd_loopback_23, // SERDES Loopback Enable
output wire powerdown_23, // Powerdown Enable
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23); // Wake Up Request
// Component instantiation
altera_tse_top_multi_mac_pcs U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.tbi_rx_clk_0(tbi_rx_clk_0), //INPUT : Receive TBI Clock
.tbi_tx_clk_0(tbi_tx_clk_0), //INPUT : Transmit TBI Clock
.tbi_rx_d_0(tbi_rx_d_0), //INPUT : Receive TBI Interface
.tbi_tx_d_0(tbi_tx_d_0), //OUTPUT : Transmit TBI Interface
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(powerdown_0), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_0), //OUTPUT : Character error
.led_disp_err_0(led_disp_err_0), //OUTPUT : Disparity error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(led_link_0), //OUTPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.tbi_rx_clk_1(tbi_rx_clk_1), //INPUT : Receive TBI Clock
.tbi_tx_clk_1(tbi_tx_clk_1), //INPUT : Transmit TBI Clock
.tbi_rx_d_1(tbi_rx_d_1), //INPUT : Receive TBI Interface
.tbi_tx_d_1(tbi_tx_d_1), //OUTPUT : Transmit TBI Interface
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(powerdown_1), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_1), //OUTPUT : Character error
.led_disp_err_1(led_disp_err_1), //OUTPUT : Disparity error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(led_link_1), //OUTPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.tbi_rx_clk_2(tbi_rx_clk_2), //INPUT : Receive TBI Clock
.tbi_tx_clk_2(tbi_tx_clk_2), //INPUT : Transmit TBI Clock
.tbi_rx_d_2(tbi_rx_d_2), //INPUT : Receive TBI Interface
.tbi_tx_d_2(tbi_tx_d_2), //OUTPUT : Transmit TBI Interface
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(powerdown_2), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_2), //OUTPUT : Character error
.led_disp_err_2(led_disp_err_2), //OUTPUT : Disparity error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(led_link_2), //OUTPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.tbi_rx_clk_3(tbi_rx_clk_3), //INPUT : Receive TBI Clock
.tbi_tx_clk_3(tbi_tx_clk_3), //INPUT : Transmit TBI Clock
.tbi_rx_d_3(tbi_rx_d_3), //INPUT : Receive TBI Interface
.tbi_tx_d_3(tbi_tx_d_3), //OUTPUT : Transmit TBI Interface
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(powerdown_3), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_3), //OUTPUT : Character error
.led_disp_err_3(led_disp_err_3), //OUTPUT : Disparity error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(led_link_3), //OUTPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.tbi_rx_clk_4(tbi_rx_clk_4), //INPUT : Receive TBI Clock
.tbi_tx_clk_4(tbi_tx_clk_4), //INPUT : Transmit TBI Clock
.tbi_rx_d_4(tbi_rx_d_4), //INPUT : Receive TBI Interface
.tbi_tx_d_4(tbi_tx_d_4), //OUTPUT : Transmit TBI Interface
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(powerdown_4), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_4), //OUTPUT : Character error
.led_disp_err_4(led_disp_err_4), //OUTPUT : Disparity error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(led_link_4), //OUTPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.tbi_rx_clk_5(tbi_rx_clk_5), //INPUT : Receive TBI Clock
.tbi_tx_clk_5(tbi_tx_clk_5), //INPUT : Transmit TBI Clock
.tbi_rx_d_5(tbi_rx_d_5), //INPUT : Receive TBI Interface
.tbi_tx_d_5(tbi_tx_d_5), //OUTPUT : Transmit TBI Interface
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(powerdown_5), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_5), //OUTPUT : Character error
.led_disp_err_5(led_disp_err_5), //OUTPUT : Disparity error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(led_link_5), //OUTPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.tbi_rx_clk_6(tbi_rx_clk_6), //INPUT : Receive TBI Clock
.tbi_tx_clk_6(tbi_tx_clk_6), //INPUT : Transmit TBI Clock
.tbi_rx_d_6(tbi_rx_d_6), //INPUT : Receive TBI Interface
.tbi_tx_d_6(tbi_tx_d_6), //OUTPUT : Transmit TBI Interface
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(powerdown_6), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_6), //OUTPUT : Character error
.led_disp_err_6(led_disp_err_6), //OUTPUT : Disparity error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(led_link_6), //OUTPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.tbi_rx_clk_7(tbi_rx_clk_7), //INPUT : Receive TBI Clock
.tbi_tx_clk_7(tbi_tx_clk_7), //INPUT : Transmit TBI Clock
.tbi_rx_d_7(tbi_rx_d_7), //INPUT : Receive TBI Interface
.tbi_tx_d_7(tbi_tx_d_7), //OUTPUT : Transmit TBI Interface
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(powerdown_7), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_7), //OUTPUT : Character error
.led_disp_err_7(led_disp_err_7), //OUTPUT : Disparity error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(led_link_7), //OUTPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.tbi_rx_clk_8(tbi_rx_clk_8), //INPUT : Receive TBI Clock
.tbi_tx_clk_8(tbi_tx_clk_8), //INPUT : Transmit TBI Clock
.tbi_rx_d_8(tbi_rx_d_8), //INPUT : Receive TBI Interface
.tbi_tx_d_8(tbi_tx_d_8), //OUTPUT : Transmit TBI Interface
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(powerdown_8), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_8), //OUTPUT : Character error
.led_disp_err_8(led_disp_err_8), //OUTPUT : Disparity error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(led_link_8), //OUTPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.tbi_rx_clk_9(tbi_rx_clk_9), //INPUT : Receive TBI Clock
.tbi_tx_clk_9(tbi_tx_clk_9), //INPUT : Transmit TBI Clock
.tbi_rx_d_9(tbi_rx_d_9), //INPUT : Receive TBI Interface
.tbi_tx_d_9(tbi_tx_d_9), //OUTPUT : Transmit TBI Interface
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(powerdown_9), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_9), //OUTPUT : Character error
.led_disp_err_9(led_disp_err_9), //OUTPUT : Disparity error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(led_link_9), //OUTPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.tbi_rx_clk_10(tbi_rx_clk_10), //INPUT : Receive TBI Clock
.tbi_tx_clk_10(tbi_tx_clk_10), //INPUT : Transmit TBI Clock
.tbi_rx_d_10(tbi_rx_d_10), //INPUT : Receive TBI Interface
.tbi_tx_d_10(tbi_tx_d_10), //OUTPUT : Transmit TBI Interface
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(powerdown_10), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_10), //OUTPUT : Character error
.led_disp_err_10(led_disp_err_10), //OUTPUT : Disparity error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(led_link_10), //OUTPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.tbi_rx_clk_11(tbi_rx_clk_11), //INPUT : Receive TBI Clock
.tbi_tx_clk_11(tbi_tx_clk_11), //INPUT : Transmit TBI Clock
.tbi_rx_d_11(tbi_rx_d_11), //INPUT : Receive TBI Interface
.tbi_tx_d_11(tbi_tx_d_11), //OUTPUT : Transmit TBI Interface
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(powerdown_11), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_11), //OUTPUT : Character error
.led_disp_err_11(led_disp_err_11), //OUTPUT : Disparity error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(led_link_11), //OUTPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.tbi_rx_clk_12(tbi_rx_clk_12), //INPUT : Receive TBI Clock
.tbi_tx_clk_12(tbi_tx_clk_12), //INPUT : Transmit TBI Clock
.tbi_rx_d_12(tbi_rx_d_12), //INPUT : Receive TBI Interface
.tbi_tx_d_12(tbi_tx_d_12), //OUTPUT : Transmit TBI Interface
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(powerdown_12), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_12), //OUTPUT : Character error
.led_disp_err_12(led_disp_err_12), //OUTPUT : Disparity error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(led_link_12), //OUTPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.tbi_rx_clk_13(tbi_rx_clk_13), //INPUT : Receive TBI Clock
.tbi_tx_clk_13(tbi_tx_clk_13), //INPUT : Transmit TBI Clock
.tbi_rx_d_13(tbi_rx_d_13), //INPUT : Receive TBI Interface
.tbi_tx_d_13(tbi_tx_d_13), //OUTPUT : Transmit TBI Interface
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(powerdown_13), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_13), //OUTPUT : Character error
.led_disp_err_13(led_disp_err_13), //OUTPUT : Disparity error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(led_link_13), //OUTPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.tbi_rx_clk_14(tbi_rx_clk_14), //INPUT : Receive TBI Clock
.tbi_tx_clk_14(tbi_tx_clk_14), //INPUT : Transmit TBI Clock
.tbi_rx_d_14(tbi_rx_d_14), //INPUT : Receive TBI Interface
.tbi_tx_d_14(tbi_tx_d_14), //OUTPUT : Transmit TBI Interface
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(powerdown_14), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_14), //OUTPUT : Character error
.led_disp_err_14(led_disp_err_14), //OUTPUT : Disparity error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(led_link_14), //OUTPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.tbi_rx_clk_15(tbi_rx_clk_15), //INPUT : Receive TBI Clock
.tbi_tx_clk_15(tbi_tx_clk_15), //INPUT : Transmit TBI Clock
.tbi_rx_d_15(tbi_rx_d_15), //INPUT : Receive TBI Interface
.tbi_tx_d_15(tbi_tx_d_15), //OUTPUT : Transmit TBI Interface
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(powerdown_15), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_15), //OUTPUT : Character error
.led_disp_err_15(led_disp_err_15), //OUTPUT : Disparity error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(led_link_15), //OUTPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.tbi_rx_clk_16(tbi_rx_clk_16), //INPUT : Receive TBI Clock
.tbi_tx_clk_16(tbi_tx_clk_16), //INPUT : Transmit TBI Clock
.tbi_rx_d_16(tbi_rx_d_16), //INPUT : Receive TBI Interface
.tbi_tx_d_16(tbi_tx_d_16), //OUTPUT : Transmit TBI Interface
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(powerdown_16), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_16), //OUTPUT : Character error
.led_disp_err_16(led_disp_err_16), //OUTPUT : Disparity error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(led_link_16), //OUTPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.tbi_rx_clk_17(tbi_rx_clk_17), //INPUT : Receive TBI Clock
.tbi_tx_clk_17(tbi_tx_clk_17), //INPUT : Transmit TBI Clock
.tbi_rx_d_17(tbi_rx_d_17), //INPUT : Receive TBI Interface
.tbi_tx_d_17(tbi_tx_d_17), //OUTPUT : Transmit TBI Interface
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(powerdown_17), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_17), //OUTPUT : Character error
.led_disp_err_17(led_disp_err_17), //OUTPUT : Disparity error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(led_link_17), //OUTPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.tbi_rx_clk_18(tbi_rx_clk_18), //INPUT : Receive TBI Clock
.tbi_tx_clk_18(tbi_tx_clk_18), //INPUT : Transmit TBI Clock
.tbi_rx_d_18(tbi_rx_d_18), //INPUT : Receive TBI Interface
.tbi_tx_d_18(tbi_tx_d_18), //OUTPUT : Transmit TBI Interface
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(powerdown_18), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_18), //OUTPUT : Character error
.led_disp_err_18(led_disp_err_18), //OUTPUT : Disparity error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(led_link_18), //OUTPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.tbi_rx_clk_19(tbi_rx_clk_19), //INPUT : Receive TBI Clock
.tbi_tx_clk_19(tbi_tx_clk_19), //INPUT : Transmit TBI Clock
.tbi_rx_d_19(tbi_rx_d_19), //INPUT : Receive TBI Interface
.tbi_tx_d_19(tbi_tx_d_19), //OUTPUT : Transmit TBI Interface
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(powerdown_19), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_19), //OUTPUT : Character error
.led_disp_err_19(led_disp_err_19), //OUTPUT : Disparity error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(led_link_19), //OUTPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.tbi_rx_clk_20(tbi_rx_clk_20), //INPUT : Receive TBI Clock
.tbi_tx_clk_20(tbi_tx_clk_20), //INPUT : Transmit TBI Clock
.tbi_rx_d_20(tbi_rx_d_20), //INPUT : Receive TBI Interface
.tbi_tx_d_20(tbi_tx_d_20), //OUTPUT : Transmit TBI Interface
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(powerdown_20), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_20), //OUTPUT : Character error
.led_disp_err_20(led_disp_err_20), //OUTPUT : Disparity error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(led_link_20), //OUTPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.tbi_rx_clk_21(tbi_rx_clk_21), //INPUT : Receive TBI Clock
.tbi_tx_clk_21(tbi_tx_clk_21), //INPUT : Transmit TBI Clock
.tbi_rx_d_21(tbi_rx_d_21), //INPUT : Receive TBI Interface
.tbi_tx_d_21(tbi_tx_d_21), //OUTPUT : Transmit TBI Interface
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(powerdown_21), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_21), //OUTPUT : Character error
.led_disp_err_21(led_disp_err_21), //OUTPUT : Disparity error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(led_link_21), //OUTPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.tbi_rx_clk_22(tbi_rx_clk_22), //INPUT : Receive TBI Clock
.tbi_tx_clk_22(tbi_tx_clk_22), //INPUT : Transmit TBI Clock
.tbi_rx_d_22(tbi_rx_d_22), //INPUT : Receive TBI Interface
.tbi_tx_d_22(tbi_tx_d_22), //OUTPUT : Transmit TBI Interface
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(powerdown_22), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_22), //OUTPUT : Character error
.led_disp_err_22(led_disp_err_22), //OUTPUT : Disparity error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(led_link_22), //OUTPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.tbi_rx_clk_23(tbi_rx_clk_23), //INPUT : Receive TBI Clock
.tbi_tx_clk_23(tbi_tx_clk_23), //INPUT : Transmit TBI Clock
.tbi_rx_d_23(tbi_rx_d_23), //INPUT : Receive TBI Interface
.tbi_tx_d_23(tbi_tx_d_23), //OUTPUT : Transmit TBI Interface
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(powerdown_23), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_23), //OUTPUT : Character error
.led_disp_err_23(led_disp_err_23), //OUTPUT : Disparity error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(led_link_23), //OUTPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
endmodule // module altera_tse_multi_mac_pcs
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs_pma.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma.v,v $
//
// $Revision: #2 $
// $Date: 2012/08/15 $
// Check in by : $Author: ksting $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_multi_mac_pcs_pma
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b1, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0, // Option to have the Alt_Reconfig ports exposed
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
parameter ENABLE_REV_LOOPBACK = 0, // PHY reverse loopback enable
// Internal parameters
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8,
//Dummy parameter from IEEE1588
parameter TSTAMP_FP_WIDTH = 4
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clock
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
input wire gxb_pwrdn_in_0, // Powerdown signal to GXB
output wire pcs_pwrdn_out_0, // Powerdown Enable from PCS
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
output wire rx_recovclkout_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
input wire gxb_pwrdn_in_1, // Powerdown signal to GXB
output wire pcs_pwrdn_out_1, // Powerdown Enable from PCS
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
output wire rx_recovclkout_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
input wire gxb_pwrdn_in_2, // Powerdown signal to GXB
output wire pcs_pwrdn_out_2, // Powerdown Enable from PCS
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
output wire rx_recovclkout_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
input wire gxb_pwrdn_in_3, // Powerdown signal to GXB
output wire pcs_pwrdn_out_3, // Powerdown Enable from PCS
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
output wire rx_recovclkout_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
input wire gxb_pwrdn_in_4, // Powerdown signal to GXB
output wire pcs_pwrdn_out_4, // Powerdown Enable from PCS
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
output wire rx_recovclkout_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
input wire gxb_pwrdn_in_5, // Powerdown signal to GXB
output wire pcs_pwrdn_out_5, // Powerdown Enable from PCS
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
output wire rx_recovclkout_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
input wire gxb_pwrdn_in_6, // Powerdown signal to GXB
output wire pcs_pwrdn_out_6, // Powerdown Enable from PCS
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
output wire rx_recovclkout_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
input wire gxb_pwrdn_in_7, // Powerdown signal to GXB
output wire pcs_pwrdn_out_7, // Powerdown Enable from PCS
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
output wire rx_recovclkout_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
input wire gxb_pwrdn_in_8, // Powerdown signal to GXB
output wire pcs_pwrdn_out_8, // Powerdown Enable from PCS
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
output wire rx_recovclkout_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
input wire gxb_pwrdn_in_9, // Powerdown signal to GXB
output wire pcs_pwrdn_out_9, // Powerdown Enable from PCS
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
output wire rx_recovclkout_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
input wire gxb_pwrdn_in_10, // Powerdown signal to GXB
output wire pcs_pwrdn_out_10, // Powerdown Enable from PCS
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
output wire rx_recovclkout_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
input wire gxb_pwrdn_in_11, // Powerdown signal to GXB
output wire pcs_pwrdn_out_11, // Powerdown Enable from PCS
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
output wire rx_recovclkout_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
input wire gxb_pwrdn_in_12, // Powerdown signal to GXB
output wire pcs_pwrdn_out_12, // Powerdown Enable from PCS
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
output wire rx_recovclkout_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
input wire gxb_pwrdn_in_13, // Powerdown signal to GXB
output wire pcs_pwrdn_out_13, // Powerdown Enable from PCS
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
output wire rx_recovclkout_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
input wire gxb_pwrdn_in_14, // Powerdown signal to GXB
output wire pcs_pwrdn_out_14, // Powerdown Enable from PCS
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
output wire rx_recovclkout_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
input wire gxb_pwrdn_in_15, // Powerdown signal to GXB
output wire pcs_pwrdn_out_15, // Powerdown Enable from PCS
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
output wire rx_recovclkout_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
input wire gxb_pwrdn_in_16, // Powerdown signal to GXB
output wire pcs_pwrdn_out_16, // Powerdown Enable from PCS
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
output wire rx_recovclkout_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
input wire gxb_pwrdn_in_17, // Powerdown signal to GXB
output wire pcs_pwrdn_out_17, // Powerdown Enable from PCS
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
output wire rx_recovclkout_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
input wire gxb_pwrdn_in_18, // Powerdown signal to GXB
output wire pcs_pwrdn_out_18, // Powerdown Enable from PCS
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
output wire rx_recovclkout_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
input wire gxb_pwrdn_in_19, // Powerdown signal to GXB
output wire pcs_pwrdn_out_19, // Powerdown Enable from PCS
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
output wire rx_recovclkout_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
input wire gxb_pwrdn_in_20, // Powerdown signal to GXB
output wire pcs_pwrdn_out_20, // Powerdown Enable from PCS
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
output wire rx_recovclkout_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
input wire gxb_pwrdn_in_21, // Powerdown signal to GXB
output wire pcs_pwrdn_out_21, // Powerdown Enable from PCS
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
output wire rx_recovclkout_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
input wire gxb_pwrdn_in_22, // Powerdown signal to GXB
output wire pcs_pwrdn_out_22, // Powerdown Enable from PCS
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
output wire rx_recovclkout_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
input wire gxb_pwrdn_in_23, // Powerdown signal to GXB
output wire pcs_pwrdn_out_23, // Powerdown Enable from PCS
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
output wire rx_recovclkout_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23); // Wake Up Request
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire reset_ref_clk_int;
wire [9:0] tbi_rx_d_lvds_0;
reg [9:0] tbi_rx_d_flip_0;
reg [9:0] tbi_tx_d_flip_0;
wire [9:0] tbi_rx_d_0;
wire [9:0] tbi_tx_d_0;
wire [9:0] tbi_rx_d_lvds_1;
reg [9:0] tbi_rx_d_flip_1;
reg [9:0] tbi_tx_d_flip_1;
wire [9:0] tbi_rx_d_1;
wire [9:0] tbi_tx_d_1;
wire [9:0] tbi_rx_d_lvds_2;
reg [9:0] tbi_rx_d_flip_2;
reg [9:0] tbi_tx_d_flip_2;
wire [9:0] tbi_rx_d_2;
wire [9:0] tbi_tx_d_2;
wire [9:0] tbi_rx_d_lvds_3;
reg [9:0] tbi_rx_d_flip_3;
reg [9:0] tbi_tx_d_flip_3;
wire [9:0] tbi_rx_d_3;
wire [9:0] tbi_tx_d_3;
wire [9:0] tbi_rx_d_lvds_4;
reg [9:0] tbi_rx_d_flip_4;
reg [9:0] tbi_tx_d_flip_4;
wire [9:0] tbi_rx_d_4;
wire [9:0] tbi_tx_d_4;
wire [9:0] tbi_rx_d_lvds_5;
reg [9:0] tbi_rx_d_flip_5;
reg [9:0] tbi_tx_d_flip_5;
wire [9:0] tbi_rx_d_5;
wire [9:0] tbi_tx_d_5;
wire [9:0] tbi_rx_d_lvds_6;
reg [9:0] tbi_rx_d_flip_6;
reg [9:0] tbi_tx_d_flip_6;
wire [9:0] tbi_rx_d_6;
wire [9:0] tbi_tx_d_6;
wire [9:0] tbi_rx_d_lvds_7;
reg [9:0] tbi_rx_d_flip_7;
reg [9:0] tbi_tx_d_flip_7;
wire [9:0] tbi_rx_d_7;
wire [9:0] tbi_tx_d_7;
wire [9:0] tbi_rx_d_lvds_8;
reg [9:0] tbi_rx_d_flip_8;
reg [9:0] tbi_tx_d_flip_8;
wire [9:0] tbi_rx_d_8;
wire [9:0] tbi_tx_d_8;
wire [9:0] tbi_rx_d_lvds_9;
reg [9:0] tbi_rx_d_flip_9;
reg [9:0] tbi_tx_d_flip_9;
wire [9:0] tbi_rx_d_9;
wire [9:0] tbi_tx_d_9;
wire [9:0] tbi_rx_d_lvds_10;
reg [9:0] tbi_rx_d_flip_10;
reg [9:0] tbi_tx_d_flip_10;
wire [9:0] tbi_rx_d_10;
wire [9:0] tbi_tx_d_10;
wire [9:0] tbi_rx_d_lvds_11;
reg [9:0] tbi_rx_d_flip_11;
reg [9:0] tbi_tx_d_flip_11;
wire [9:0] tbi_rx_d_11;
wire [9:0] tbi_tx_d_11;
wire [9:0] tbi_rx_d_lvds_12;
reg [9:0] tbi_rx_d_flip_12;
reg [9:0] tbi_tx_d_flip_12;
wire [9:0] tbi_rx_d_12;
wire [9:0] tbi_tx_d_12;
wire [9:0] tbi_rx_d_lvds_13;
reg [9:0] tbi_rx_d_flip_13;
reg [9:0] tbi_tx_d_flip_13;
wire [9:0] tbi_rx_d_13;
wire [9:0] tbi_tx_d_13;
wire [9:0] tbi_rx_d_lvds_14;
reg [9:0] tbi_rx_d_flip_14;
reg [9:0] tbi_tx_d_flip_14;
wire [9:0] tbi_rx_d_14;
wire [9:0] tbi_tx_d_14;
wire [9:0] tbi_rx_d_lvds_15;
reg [9:0] tbi_rx_d_flip_15;
reg [9:0] tbi_tx_d_flip_15;
wire [9:0] tbi_rx_d_15;
wire [9:0] tbi_tx_d_15;
wire [9:0] tbi_rx_d_lvds_16;
reg [9:0] tbi_rx_d_flip_16;
reg [9:0] tbi_tx_d_flip_16;
wire [9:0] tbi_rx_d_16;
wire [9:0] tbi_tx_d_16;
wire [9:0] tbi_rx_d_lvds_17;
reg [9:0] tbi_rx_d_flip_17;
reg [9:0] tbi_tx_d_flip_17;
wire [9:0] tbi_rx_d_17;
wire [9:0] tbi_tx_d_17;
wire [9:0] tbi_rx_d_lvds_18;
reg [9:0] tbi_rx_d_flip_18;
reg [9:0] tbi_tx_d_flip_18;
wire [9:0] tbi_rx_d_18;
wire [9:0] tbi_tx_d_18;
wire [9:0] tbi_rx_d_lvds_19;
reg [9:0] tbi_rx_d_flip_19;
reg [9:0] tbi_tx_d_flip_19;
wire [9:0] tbi_rx_d_19;
wire [9:0] tbi_tx_d_19;
wire [9:0] tbi_rx_d_lvds_20;
reg [9:0] tbi_rx_d_flip_20;
reg [9:0] tbi_tx_d_flip_20;
wire [9:0] tbi_rx_d_20;
wire [9:0] tbi_tx_d_20;
wire [9:0] tbi_rx_d_lvds_21;
reg [9:0] tbi_rx_d_flip_21;
reg [9:0] tbi_tx_d_flip_21;
wire [9:0] tbi_rx_d_21;
wire [9:0] tbi_tx_d_21;
wire [9:0] tbi_rx_d_lvds_22;
reg [9:0] tbi_rx_d_flip_22;
reg [9:0] tbi_tx_d_flip_22;
wire [9:0] tbi_rx_d_22;
wire [9:0] tbi_tx_d_22;
wire [9:0] tbi_rx_d_lvds_23;
reg [9:0] tbi_rx_d_flip_23;
reg [9:0] tbi_tx_d_flip_23;
wire [9:0] tbi_rx_d_23;
wire [9:0] tbi_tx_d_23;
wire [9:0] tbi_tx_d_muxed_0;
wire [9:0] tbi_tx_d_muxed_1;
wire [9:0] tbi_tx_d_muxed_2;
wire [9:0] tbi_tx_d_muxed_3;
wire [9:0] tbi_tx_d_muxed_4;
wire [9:0] tbi_tx_d_muxed_5;
wire [9:0] tbi_tx_d_muxed_6;
wire [9:0] tbi_tx_d_muxed_7;
wire [9:0] tbi_tx_d_muxed_8;
wire [9:0] tbi_tx_d_muxed_9;
wire [9:0] tbi_tx_d_muxed_10;
wire [9:0] tbi_tx_d_muxed_11;
wire [9:0] tbi_tx_d_muxed_12;
wire [9:0] tbi_tx_d_muxed_13;
wire [9:0] tbi_tx_d_muxed_14;
wire [9:0] tbi_tx_d_muxed_15;
wire [9:0] tbi_tx_d_muxed_16;
wire [9:0] tbi_tx_d_muxed_17;
wire [9:0] tbi_tx_d_muxed_18;
wire [9:0] tbi_tx_d_muxed_19;
wire [9:0] tbi_tx_d_muxed_20;
wire [9:0] tbi_tx_d_muxed_21;
wire [9:0] tbi_tx_d_muxed_22;
wire [9:0] tbi_tx_d_muxed_23;
wire [9:0] tbi_tx_d_loopback_0;
wire [9:0] tbi_tx_d_loopback_1;
wire [9:0] tbi_tx_d_loopback_2;
wire [9:0] tbi_tx_d_loopback_3;
wire [9:0] tbi_tx_d_loopback_4;
wire [9:0] tbi_tx_d_loopback_5;
wire [9:0] tbi_tx_d_loopback_6;
wire [9:0] tbi_tx_d_loopback_7;
wire [9:0] tbi_tx_d_loopback_8;
wire [9:0] tbi_tx_d_loopback_9;
wire [9:0] tbi_tx_d_loopback_10;
wire [9:0] tbi_tx_d_loopback_11;
wire [9:0] tbi_tx_d_loopback_12;
wire [9:0] tbi_tx_d_loopback_13;
wire [9:0] tbi_tx_d_loopback_14;
wire [9:0] tbi_tx_d_loopback_15;
wire [9:0] tbi_tx_d_loopback_16;
wire [9:0] tbi_tx_d_loopback_17;
wire [9:0] tbi_tx_d_loopback_18;
wire [9:0] tbi_tx_d_loopback_19;
wire [9:0] tbi_tx_d_loopback_20;
wire [9:0] tbi_tx_d_loopback_21;
wire [9:0] tbi_tx_d_loopback_22;
wire [9:0] tbi_tx_d_loopback_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
wire rev_loopback_ena_0;
wire rev_loopback_ena_1;
wire rev_loopback_ena_2;
wire rev_loopback_ena_3;
wire rev_loopback_ena_4;
wire rev_loopback_ena_5;
wire rev_loopback_ena_6;
wire rev_loopback_ena_7;
wire rev_loopback_ena_8;
wire rev_loopback_ena_9;
wire rev_loopback_ena_10;
wire rev_loopback_ena_11;
wire rev_loopback_ena_12;
wire rev_loopback_ena_13;
wire rev_loopback_ena_14;
wire rev_loopback_ena_15;
wire rev_loopback_ena_16;
wire rev_loopback_ena_17;
wire rev_loopback_ena_18;
wire rev_loopback_ena_19;
wire rev_loopback_ena_20;
wire rev_loopback_ena_21;
wire rev_loopback_ena_22;
wire rev_loopback_ena_23;
wire rev_loopback_ena_ref_clk_0;
wire rev_loopback_ena_ref_clk_1;
wire rev_loopback_ena_ref_clk_2;
wire rev_loopback_ena_ref_clk_3;
wire rev_loopback_ena_ref_clk_4;
wire rev_loopback_ena_ref_clk_5;
wire rev_loopback_ena_ref_clk_6;
wire rev_loopback_ena_ref_clk_7;
wire rev_loopback_ena_ref_clk_8;
wire rev_loopback_ena_ref_clk_9;
wire rev_loopback_ena_ref_clk_10;
wire rev_loopback_ena_ref_clk_11;
wire rev_loopback_ena_ref_clk_12;
wire rev_loopback_ena_ref_clk_13;
wire rev_loopback_ena_ref_clk_14;
wire rev_loopback_ena_ref_clk_15;
wire rev_loopback_ena_ref_clk_16;
wire rev_loopback_ena_ref_clk_17;
wire rev_loopback_ena_ref_clk_18;
wire rev_loopback_ena_ref_clk_19;
wire rev_loopback_ena_ref_clk_20;
wire rev_loopback_ena_ref_clk_21;
wire rev_loopback_ena_ref_clk_22;
wire rev_loopback_ena_ref_clk_23;
wire tbi_rx_clk_0;
wire tbi_rx_clk_1;
wire tbi_rx_clk_2;
wire tbi_rx_clk_3;
wire tbi_rx_clk_4;
wire tbi_rx_clk_5;
wire tbi_rx_clk_6;
wire tbi_rx_clk_7;
wire tbi_rx_clk_8;
wire tbi_rx_clk_9;
wire tbi_rx_clk_10;
wire tbi_rx_clk_11;
wire tbi_rx_clk_12;
wire tbi_rx_clk_13;
wire tbi_rx_clk_14;
wire tbi_rx_clk_15;
wire tbi_rx_clk_16;
wire tbi_rx_clk_17;
wire tbi_rx_clk_18;
wire tbi_rx_clk_19;
wire tbi_rx_clk_20;
wire tbi_rx_clk_21;
wire tbi_rx_clk_22;
wire tbi_rx_clk_23;
wire tbi_tx_clk_0;
wire tbi_tx_clk_1;
wire tbi_tx_clk_2;
wire tbi_tx_clk_3;
wire tbi_tx_clk_4;
wire tbi_tx_clk_5;
wire tbi_tx_clk_6;
wire tbi_tx_clk_7;
wire tbi_tx_clk_8;
wire tbi_tx_clk_9;
wire tbi_tx_clk_10;
wire tbi_tx_clk_11;
wire tbi_tx_clk_12;
wire tbi_tx_clk_13;
wire tbi_tx_clk_14;
wire tbi_tx_clk_15;
wire tbi_tx_clk_16;
wire tbi_tx_clk_17;
wire tbi_tx_clk_18;
wire tbi_tx_clk_19;
wire tbi_tx_clk_20;
wire tbi_tx_clk_21;
wire tbi_tx_clk_22;
wire tbi_tx_clk_23;
wire reset_tbi_rx_clk_0_int;
wire reset_tbi_rx_clk_1_int;
wire reset_tbi_rx_clk_2_int;
wire reset_tbi_rx_clk_3_int;
wire reset_tbi_rx_clk_4_int;
wire reset_tbi_rx_clk_5_int;
wire reset_tbi_rx_clk_6_int;
wire reset_tbi_rx_clk_7_int;
wire reset_tbi_rx_clk_8_int;
wire reset_tbi_rx_clk_9_int;
wire reset_tbi_rx_clk_10_int;
wire reset_tbi_rx_clk_11_int;
wire reset_tbi_rx_clk_12_int;
wire reset_tbi_rx_clk_13_int;
wire reset_tbi_rx_clk_14_int;
wire reset_tbi_rx_clk_15_int;
wire reset_tbi_rx_clk_16_int;
wire reset_tbi_rx_clk_17_int;
wire reset_tbi_rx_clk_18_int;
wire reset_tbi_rx_clk_19_int;
wire reset_tbi_rx_clk_20_int;
wire reset_tbi_rx_clk_21_int;
wire reset_tbi_rx_clk_22_int;
wire reset_tbi_rx_clk_23_int;
wire pll_areset_0,rx_cda_reset_0,rx_channel_data_align_0,rx_locked_0,rx_reset_0,rx_reset_sequence_done_0;
wire pll_areset_1,rx_cda_reset_1,rx_channel_data_align_1,rx_locked_1,rx_reset_1,rx_reset_sequence_done_1;
wire pll_areset_2,rx_cda_reset_2,rx_channel_data_align_2,rx_locked_2,rx_reset_2,rx_reset_sequence_done_2;
wire pll_areset_3,rx_cda_reset_3,rx_channel_data_align_3,rx_locked_3,rx_reset_3,rx_reset_sequence_done_3;
wire pll_areset_4,rx_cda_reset_4,rx_channel_data_align_4,rx_locked_4,rx_reset_4,rx_reset_sequence_done_4;
wire pll_areset_5,rx_cda_reset_5,rx_channel_data_align_5,rx_locked_5,rx_reset_5,rx_reset_sequence_done_5;
wire pll_areset_6,rx_cda_reset_6,rx_channel_data_align_6,rx_locked_6,rx_reset_6,rx_reset_sequence_done_6;
wire pll_areset_7,rx_cda_reset_7,rx_channel_data_align_7,rx_locked_7,rx_reset_7,rx_reset_sequence_done_7;
wire pll_areset_8,rx_cda_reset_8,rx_channel_data_align_8,rx_locked_8,rx_reset_8,rx_reset_sequence_done_8;
wire pll_areset_9,rx_cda_reset_9,rx_channel_data_align_9,rx_locked_9,rx_reset_9,rx_reset_sequence_done_9;
wire pll_areset_10,rx_cda_reset_10,rx_channel_data_align_10,rx_locked_10,rx_reset_10,rx_reset_sequence_done_10;
wire pll_areset_11,rx_cda_reset_11,rx_channel_data_align_11,rx_locked_11,rx_reset_11,rx_reset_sequence_done_11;
wire pll_areset_12,rx_cda_reset_12,rx_channel_data_align_12,rx_locked_12,rx_reset_12,rx_reset_sequence_done_12;
wire pll_areset_13,rx_cda_reset_13,rx_channel_data_align_13,rx_locked_13,rx_reset_13,rx_reset_sequence_done_13;
wire pll_areset_14,rx_cda_reset_14,rx_channel_data_align_14,rx_locked_14,rx_reset_14,rx_reset_sequence_done_14;
wire pll_areset_15,rx_cda_reset_15,rx_channel_data_align_15,rx_locked_15,rx_reset_15,rx_reset_sequence_done_15;
wire pll_areset_16,rx_cda_reset_16,rx_channel_data_align_16,rx_locked_16,rx_reset_16,rx_reset_sequence_done_16;
wire pll_areset_17,rx_cda_reset_17,rx_channel_data_align_17,rx_locked_17,rx_reset_17,rx_reset_sequence_done_17;
wire pll_areset_18,rx_cda_reset_18,rx_channel_data_align_18,rx_locked_18,rx_reset_18,rx_reset_sequence_done_18;
wire pll_areset_19,rx_cda_reset_19,rx_channel_data_align_19,rx_locked_19,rx_reset_19,rx_reset_sequence_done_19;
wire pll_areset_20,rx_cda_reset_20,rx_channel_data_align_20,rx_locked_20,rx_reset_20,rx_reset_sequence_done_20;
wire pll_areset_21,rx_cda_reset_21,rx_channel_data_align_21,rx_locked_21,rx_reset_21,rx_reset_sequence_done_21;
wire pll_areset_22,rx_cda_reset_22,rx_channel_data_align_22,rx_locked_22,rx_reset_22,rx_reset_sequence_done_22;
wire pll_areset_23,rx_cda_reset_23,rx_channel_data_align_23,rx_locked_23,rx_reset_23,rx_reset_sequence_done_23;
assign rx_recovclkout_0 = tbi_rx_clk_0;
assign rx_recovclkout_1 = tbi_rx_clk_1;
assign rx_recovclkout_2 = tbi_rx_clk_2;
assign rx_recovclkout_3 = tbi_rx_clk_3;
assign rx_recovclkout_4 = tbi_rx_clk_4;
assign rx_recovclkout_5 = tbi_rx_clk_5;
assign rx_recovclkout_6 = tbi_rx_clk_6;
assign rx_recovclkout_7 = tbi_rx_clk_7;
assign rx_recovclkout_8 = tbi_rx_clk_8;
assign rx_recovclkout_9 = tbi_rx_clk_9;
assign rx_recovclkout_10 = tbi_rx_clk_10;
assign rx_recovclkout_11 = tbi_rx_clk_11;
assign rx_recovclkout_12 = tbi_rx_clk_12;
assign rx_recovclkout_13 = tbi_rx_clk_13;
assign rx_recovclkout_14 = tbi_rx_clk_14;
assign rx_recovclkout_15 = tbi_rx_clk_15;
assign rx_recovclkout_16 = tbi_rx_clk_16;
assign rx_recovclkout_17 = tbi_rx_clk_17;
assign rx_recovclkout_18 = tbi_rx_clk_18;
assign rx_recovclkout_19 = tbi_rx_clk_19;
assign rx_recovclkout_20 = tbi_rx_clk_20;
assign rx_recovclkout_21 = tbi_rx_clk_21;
assign rx_recovclkout_22 = tbi_rx_clk_22;
assign rx_recovclkout_23 = tbi_rx_clk_23;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.tbi_rx_clk_0(tbi_rx_clk_0), //INPUT : Receive TBI Clock
.tbi_tx_clk_0(tbi_tx_clk_0), //INPUT : Transmit TBI Clock
.tbi_rx_d_0(tbi_rx_d_0), //INPUT : Receive TBI Interface
.tbi_tx_d_0(tbi_tx_d_0), //OUTPUT : Transmit TBI Interface
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_0(rev_loopback_ena_0), //OUTPUT : PHY reverse loopback enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_0), //OUTPUT : Character error
.led_disp_err_0(led_disp_err_0), //OUTPUT : Disparity error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(led_link_0), //OUTPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.tbi_rx_clk_1(tbi_rx_clk_1), //INPUT : Receive TBI Clock
.tbi_tx_clk_1(tbi_tx_clk_1), //INPUT : Transmit TBI Clock
.tbi_rx_d_1(tbi_rx_d_1), //INPUT : Receive TBI Interface
.tbi_tx_d_1(tbi_tx_d_1), //OUTPUT : Transmit TBI Interface
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_1(rev_loopback_ena_1), //OUTPUT : PHY reverse loopback enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_1), //OUTPUT : Character error
.led_disp_err_1(led_disp_err_1), //OUTPUT : Disparity error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(led_link_1), //OUTPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.tbi_rx_clk_2(tbi_rx_clk_2), //INPUT : Receive TBI Clock
.tbi_tx_clk_2(tbi_tx_clk_2), //INPUT : Transmit TBI Clock
.tbi_rx_d_2(tbi_rx_d_2), //INPUT : Receive TBI Interface
.tbi_tx_d_2(tbi_tx_d_2), //OUTPUT : Transmit TBI Interface
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_2(rev_loopback_ena_2), //OUTPUT : PHY reverse loopback enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_2), //OUTPUT : Character error
.led_disp_err_2(led_disp_err_2), //OUTPUT : Disparity error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(led_link_2), //OUTPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.tbi_rx_clk_3(tbi_rx_clk_3), //INPUT : Receive TBI Clock
.tbi_tx_clk_3(tbi_tx_clk_3), //INPUT : Transmit TBI Clock
.tbi_rx_d_3(tbi_rx_d_3), //INPUT : Receive TBI Interface
.tbi_tx_d_3(tbi_tx_d_3), //OUTPUT : Transmit TBI Interface
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_3(rev_loopback_ena_3), //OUTPUT : PHY reverse loopback enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_3), //OUTPUT : Character error
.led_disp_err_3(led_disp_err_3), //OUTPUT : Disparity error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(led_link_3), //OUTPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.tbi_rx_clk_4(tbi_rx_clk_4), //INPUT : Receive TBI Clock
.tbi_tx_clk_4(tbi_tx_clk_4), //INPUT : Transmit TBI Clock
.tbi_rx_d_4(tbi_rx_d_4), //INPUT : Receive TBI Interface
.tbi_tx_d_4(tbi_tx_d_4), //OUTPUT : Transmit TBI Interface
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_4(rev_loopback_ena_4), //OUTPUT : PHY reverse loopback enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_4), //OUTPUT : Character error
.led_disp_err_4(led_disp_err_4), //OUTPUT : Disparity error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(led_link_4), //OUTPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.tbi_rx_clk_5(tbi_rx_clk_5), //INPUT : Receive TBI Clock
.tbi_tx_clk_5(tbi_tx_clk_5), //INPUT : Transmit TBI Clock
.tbi_rx_d_5(tbi_rx_d_5), //INPUT : Receive TBI Interface
.tbi_tx_d_5(tbi_tx_d_5), //OUTPUT : Transmit TBI Interface
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_5(rev_loopback_ena_5), //OUTPUT : PHY reverse loopback enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_5), //OUTPUT : Character error
.led_disp_err_5(led_disp_err_5), //OUTPUT : Disparity error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(led_link_5), //OUTPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.tbi_rx_clk_6(tbi_rx_clk_6), //INPUT : Receive TBI Clock
.tbi_tx_clk_6(tbi_tx_clk_6), //INPUT : Transmit TBI Clock
.tbi_rx_d_6(tbi_rx_d_6), //INPUT : Receive TBI Interface
.tbi_tx_d_6(tbi_tx_d_6), //OUTPUT : Transmit TBI Interface
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_6(rev_loopback_ena_6), //OUTPUT : PHY reverse loopback enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_6), //OUTPUT : Character error
.led_disp_err_6(led_disp_err_6), //OUTPUT : Disparity error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(led_link_6), //OUTPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.tbi_rx_clk_7(tbi_rx_clk_7), //INPUT : Receive TBI Clock
.tbi_tx_clk_7(tbi_tx_clk_7), //INPUT : Transmit TBI Clock
.tbi_rx_d_7(tbi_rx_d_7), //INPUT : Receive TBI Interface
.tbi_tx_d_7(tbi_tx_d_7), //OUTPUT : Transmit TBI Interface
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_7(rev_loopback_ena_7), //OUTPUT : PHY reverse loopback enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_7), //OUTPUT : Character error
.led_disp_err_7(led_disp_err_7), //OUTPUT : Disparity error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(led_link_7), //OUTPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.tbi_rx_clk_8(tbi_rx_clk_8), //INPUT : Receive TBI Clock
.tbi_tx_clk_8(tbi_tx_clk_8), //INPUT : Transmit TBI Clock
.tbi_rx_d_8(tbi_rx_d_8), //INPUT : Receive TBI Interface
.tbi_tx_d_8(tbi_tx_d_8), //OUTPUT : Transmit TBI Interface
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_8(rev_loopback_ena_8), //OUTPUT : PHY reverse loopback enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_8), //OUTPUT : Character error
.led_disp_err_8(led_disp_err_8), //OUTPUT : Disparity error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(led_link_8), //OUTPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.tbi_rx_clk_9(tbi_rx_clk_9), //INPUT : Receive TBI Clock
.tbi_tx_clk_9(tbi_tx_clk_9), //INPUT : Transmit TBI Clock
.tbi_rx_d_9(tbi_rx_d_9), //INPUT : Receive TBI Interface
.tbi_tx_d_9(tbi_tx_d_9), //OUTPUT : Transmit TBI Interface
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_9(rev_loopback_ena_9), //OUTPUT : PHY reverse loopback enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_9), //OUTPUT : Character error
.led_disp_err_9(led_disp_err_9), //OUTPUT : Disparity error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(led_link_9), //OUTPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.tbi_rx_clk_10(tbi_rx_clk_10), //INPUT : Receive TBI Clock
.tbi_tx_clk_10(tbi_tx_clk_10), //INPUT : Transmit TBI Clock
.tbi_rx_d_10(tbi_rx_d_10), //INPUT : Receive TBI Interface
.tbi_tx_d_10(tbi_tx_d_10), //OUTPUT : Transmit TBI Interface
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_10(rev_loopback_ena_10), //OUTPUT : PHY reverse loopback enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_10), //OUTPUT : Character error
.led_disp_err_10(led_disp_err_10), //OUTPUT : Disparity error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(led_link_10), //OUTPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.tbi_rx_clk_11(tbi_rx_clk_11), //INPUT : Receive TBI Clock
.tbi_tx_clk_11(tbi_tx_clk_11), //INPUT : Transmit TBI Clock
.tbi_rx_d_11(tbi_rx_d_11), //INPUT : Receive TBI Interface
.tbi_tx_d_11(tbi_tx_d_11), //OUTPUT : Transmit TBI Interface
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_11(rev_loopback_ena_11), //OUTPUT : PHY reverse loopback enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_11), //OUTPUT : Character error
.led_disp_err_11(led_disp_err_11), //OUTPUT : Disparity error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(led_link_11), //OUTPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.tbi_rx_clk_12(tbi_rx_clk_12), //INPUT : Receive TBI Clock
.tbi_tx_clk_12(tbi_tx_clk_12), //INPUT : Transmit TBI Clock
.tbi_rx_d_12(tbi_rx_d_12), //INPUT : Receive TBI Interface
.tbi_tx_d_12(tbi_tx_d_12), //OUTPUT : Transmit TBI Interface
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_12(rev_loopback_ena_12), //OUTPUT : PHY reverse loopback enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_12), //OUTPUT : Character error
.led_disp_err_12(led_disp_err_12), //OUTPUT : Disparity error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(led_link_12), //OUTPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.tbi_rx_clk_13(tbi_rx_clk_13), //INPUT : Receive TBI Clock
.tbi_tx_clk_13(tbi_tx_clk_13), //INPUT : Transmit TBI Clock
.tbi_rx_d_13(tbi_rx_d_13), //INPUT : Receive TBI Interface
.tbi_tx_d_13(tbi_tx_d_13), //OUTPUT : Transmit TBI Interface
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_13(rev_loopback_ena_13), //OUTPUT : PHY reverse loopback enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_13), //OUTPUT : Character error
.led_disp_err_13(led_disp_err_13), //OUTPUT : Disparity error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(led_link_13), //OUTPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.tbi_rx_clk_14(tbi_rx_clk_14), //INPUT : Receive TBI Clock
.tbi_tx_clk_14(tbi_tx_clk_14), //INPUT : Transmit TBI Clock
.tbi_rx_d_14(tbi_rx_d_14), //INPUT : Receive TBI Interface
.tbi_tx_d_14(tbi_tx_d_14), //OUTPUT : Transmit TBI Interface
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_14(rev_loopback_ena_14), //OUTPUT : PHY reverse loopback enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_14), //OUTPUT : Character error
.led_disp_err_14(led_disp_err_14), //OUTPUT : Disparity error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(led_link_14), //OUTPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.tbi_rx_clk_15(tbi_rx_clk_15), //INPUT : Receive TBI Clock
.tbi_tx_clk_15(tbi_tx_clk_15), //INPUT : Transmit TBI Clock
.tbi_rx_d_15(tbi_rx_d_15), //INPUT : Receive TBI Interface
.tbi_tx_d_15(tbi_tx_d_15), //OUTPUT : Transmit TBI Interface
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_15(rev_loopback_ena_15), //OUTPUT : PHY reverse loopback enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_15), //OUTPUT : Character error
.led_disp_err_15(led_disp_err_15), //OUTPUT : Disparity error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(led_link_15), //OUTPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.tbi_rx_clk_16(tbi_rx_clk_16), //INPUT : Receive TBI Clock
.tbi_tx_clk_16(tbi_tx_clk_16), //INPUT : Transmit TBI Clock
.tbi_rx_d_16(tbi_rx_d_16), //INPUT : Receive TBI Interface
.tbi_tx_d_16(tbi_tx_d_16), //OUTPUT : Transmit TBI Interface
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_16(rev_loopback_ena_16), //OUTPUT : PHY reverse loopback enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_16), //OUTPUT : Character error
.led_disp_err_16(led_disp_err_16), //OUTPUT : Disparity error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(led_link_16), //OUTPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.tbi_rx_clk_17(tbi_rx_clk_17), //INPUT : Receive TBI Clock
.tbi_tx_clk_17(tbi_tx_clk_17), //INPUT : Transmit TBI Clock
.tbi_rx_d_17(tbi_rx_d_17), //INPUT : Receive TBI Interface
.tbi_tx_d_17(tbi_tx_d_17), //OUTPUT : Transmit TBI Interface
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_17(rev_loopback_ena_17), //OUTPUT : PHY reverse loopback enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_17), //OUTPUT : Character error
.led_disp_err_17(led_disp_err_17), //OUTPUT : Disparity error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(led_link_17), //OUTPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.tbi_rx_clk_18(tbi_rx_clk_18), //INPUT : Receive TBI Clock
.tbi_tx_clk_18(tbi_tx_clk_18), //INPUT : Transmit TBI Clock
.tbi_rx_d_18(tbi_rx_d_18), //INPUT : Receive TBI Interface
.tbi_tx_d_18(tbi_tx_d_18), //OUTPUT : Transmit TBI Interface
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_18(rev_loopback_ena_18), //OUTPUT : PHY reverse loopback enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_18), //OUTPUT : Character error
.led_disp_err_18(led_disp_err_18), //OUTPUT : Disparity error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(led_link_18), //OUTPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.tbi_rx_clk_19(tbi_rx_clk_19), //INPUT : Receive TBI Clock
.tbi_tx_clk_19(tbi_tx_clk_19), //INPUT : Transmit TBI Clock
.tbi_rx_d_19(tbi_rx_d_19), //INPUT : Receive TBI Interface
.tbi_tx_d_19(tbi_tx_d_19), //OUTPUT : Transmit TBI Interface
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_19(rev_loopback_ena_19), //OUTPUT : PHY reverse loopback enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_19), //OUTPUT : Character error
.led_disp_err_19(led_disp_err_19), //OUTPUT : Disparity error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(led_link_19), //OUTPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.tbi_rx_clk_20(tbi_rx_clk_20), //INPUT : Receive TBI Clock
.tbi_tx_clk_20(tbi_tx_clk_20), //INPUT : Transmit TBI Clock
.tbi_rx_d_20(tbi_rx_d_20), //INPUT : Receive TBI Interface
.tbi_tx_d_20(tbi_tx_d_20), //OUTPUT : Transmit TBI Interface
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_20(rev_loopback_ena_20), //OUTPUT : PHY reverse loopback enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_20), //OUTPUT : Character error
.led_disp_err_20(led_disp_err_20), //OUTPUT : Disparity error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(led_link_20), //OUTPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.tbi_rx_clk_21(tbi_rx_clk_21), //INPUT : Receive TBI Clock
.tbi_tx_clk_21(tbi_tx_clk_21), //INPUT : Transmit TBI Clock
.tbi_rx_d_21(tbi_rx_d_21), //INPUT : Receive TBI Interface
.tbi_tx_d_21(tbi_tx_d_21), //OUTPUT : Transmit TBI Interface
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_21(rev_loopback_ena_21), //OUTPUT : PHY reverse loopback enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_21), //OUTPUT : Character error
.led_disp_err_21(led_disp_err_21), //OUTPUT : Disparity error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(led_link_21), //OUTPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.tbi_rx_clk_22(tbi_rx_clk_22), //INPUT : Receive TBI Clock
.tbi_tx_clk_22(tbi_tx_clk_22), //INPUT : Transmit TBI Clock
.tbi_rx_d_22(tbi_rx_d_22), //INPUT : Receive TBI Interface
.tbi_tx_d_22(tbi_tx_d_22), //OUTPUT : Transmit TBI Interface
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_22(rev_loopback_ena_22), //OUTPUT : PHY reverse loopback enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_22), //OUTPUT : Character error
.led_disp_err_22(led_disp_err_22), //OUTPUT : Disparity error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(led_link_22), //OUTPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.tbi_rx_clk_23(tbi_rx_clk_23), //INPUT : Receive TBI Clock
.tbi_tx_clk_23(tbi_tx_clk_23), //INPUT : Transmit TBI Clock
.tbi_rx_d_23(tbi_rx_d_23), //INPUT : Receive TBI Interface
.tbi_tx_d_23(tbi_tx_d_23), //OUTPUT : Transmit TBI Interface
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.rev_loopback_ena_23(rev_loopback_ena_23), //OUTPUT : PHY reverse loopback enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_23), //OUTPUT : Character error
.led_disp_err_23(led_disp_err_23), //OUTPUT : Disparity error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(led_link_23), //OUTPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
altera_tse_reset_synchronizer reset_sync_0 (
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_ref_clk_int)
);
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 0)
begin
assign gxb_pwrdn_in_sig[0] = gxb_pwrdn_in_0;
assign pcs_pwrdn_out_0 = pcs_pwrdn_out_sig[0];
end
else
begin
assign gxb_pwrdn_in_sig[0] = pcs_pwrdn_out_sig[0];
assign pcs_pwrdn_out_0 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 0)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_0(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_0), //INPUT
.dout(rev_loopback_ena_ref_clk_0));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_0 (
.reset_wclk(reset_tbi_rx_clk_0_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_0),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_0),
.tbi_tx_clk (tbi_tx_d_loopback_0)
);
assign tbi_tx_d_muxed_0 = rev_loopback_ena_ref_clk_0 ? tbi_tx_d_loopback_0: tbi_tx_d_flip_0;
end
else
begin
assign tbi_tx_d_muxed_0 = tbi_tx_d_flip_0;
// Unused wires
assign tbi_tx_d_loopback_0 = 10'd0;
assign rev_loopback_ena_ref_clk_0 = 1'b0;
end
assign tbi_tx_clk_0 = ref_clk;
assign tbi_rx_d_0 = tbi_rx_d_flip_0;
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(tbi_rx_clk_0),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_0_int)
);
always @(posedge tbi_rx_clk_0 or posedge reset_tbi_rx_clk_0_int)
begin
if (reset_tbi_rx_clk_0_int == 1)
tbi_rx_d_flip_0 <= 0;
else
begin
if (rx_reset_sequence_done_0 == 1)
begin
tbi_rx_d_flip_0[0] <= tbi_rx_d_lvds_0[9];
tbi_rx_d_flip_0[1] <= tbi_rx_d_lvds_0[8];
tbi_rx_d_flip_0[2] <= tbi_rx_d_lvds_0[7];
tbi_rx_d_flip_0[3] <= tbi_rx_d_lvds_0[6];
tbi_rx_d_flip_0[4] <= tbi_rx_d_lvds_0[5];
tbi_rx_d_flip_0[5] <= tbi_rx_d_lvds_0[4];
tbi_rx_d_flip_0[6] <= tbi_rx_d_lvds_0[3];
tbi_rx_d_flip_0[7] <= tbi_rx_d_lvds_0[2];
tbi_rx_d_flip_0[8] <= tbi_rx_d_lvds_0[1];
tbi_rx_d_flip_0[9] <= tbi_rx_d_lvds_0[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_0 <= 0;
else
begin
tbi_tx_d_flip_0[0] <= tbi_tx_d_0[9];
tbi_tx_d_flip_0[1] <= tbi_tx_d_0[8];
tbi_tx_d_flip_0[2] <= tbi_tx_d_0[7];
tbi_tx_d_flip_0[3] <= tbi_tx_d_0[6];
tbi_tx_d_flip_0[4] <= tbi_tx_d_0[5];
tbi_tx_d_flip_0[5] <= tbi_tx_d_0[4];
tbi_tx_d_flip_0[6] <= tbi_tx_d_0[3];
tbi_tx_d_flip_0[7] <= tbi_tx_d_0[2];
tbi_tx_d_flip_0[8] <= tbi_tx_d_0[1];
tbi_tx_d_flip_0[9] <= tbi_tx_d_0[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_0
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_0 ),
.rx_locked ( rx_locked_0 ),
.rx_divfwdclk (tbi_rx_clk_0),
.rx_in (rxp_0),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_0),
.rx_outclock (),
.rx_reset (rx_reset_0)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_0
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_0 ),
.rx_channel_data_align ( rx_channel_data_align_0 ),
.rx_locked ( rx_locked_0 ),
.rx_divfwdclk (tbi_rx_clk_0),
.rx_in (rxp_0),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_0),
.rx_outclock (),
.rx_reset (rx_reset_0)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_0 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_0 ),
.rx_channel_data_align ( rx_channel_data_align_0 ),
.pll_areset ( pll_areset_0 ),
.rx_reset ( rx_reset_0 ),
.rx_cda_reset ( rx_cda_reset_0 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_0 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_0
(
.tx_in (tbi_tx_d_muxed_0),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_0)
);
end
else
begin
assign txp_0 = 1'b0;
assign tbi_rx_clk_0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 1)
begin
assign gxb_pwrdn_in_sig[1] = gxb_pwrdn_in_1;
assign pcs_pwrdn_out_1 = pcs_pwrdn_out_sig[1];
end
else
begin
assign gxb_pwrdn_in_sig[1] = pcs_pwrdn_out_sig[1];
assign pcs_pwrdn_out_1 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 1)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_1(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_1), //INPUT
.dout(rev_loopback_ena_ref_clk_1));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_1 (
.reset_wclk(reset_tbi_rx_clk_1_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_1),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_1),
.tbi_tx_clk (tbi_tx_d_loopback_1)
);
assign tbi_tx_d_muxed_1 = rev_loopback_ena_ref_clk_1 ? tbi_tx_d_loopback_1: tbi_tx_d_flip_1;
end
else
begin
assign tbi_tx_d_muxed_1 = tbi_tx_d_flip_1;
// Unused wires
assign tbi_tx_d_loopback_1 = 10'd0;
assign rev_loopback_ena_ref_clk_1 = 1'b0;
end
assign tbi_tx_clk_1 = ref_clk;
assign tbi_rx_d_1 = tbi_rx_d_flip_1;
altera_tse_reset_synchronizer ch_1_reset_sync_0 (
.clk(tbi_rx_clk_1),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_1_int)
);
always @(posedge tbi_rx_clk_1 or posedge reset_tbi_rx_clk_1_int)
begin
if (reset_tbi_rx_clk_1_int == 1)
tbi_rx_d_flip_1 <= 0;
else
begin
if (rx_reset_sequence_done_1 == 1)
begin
tbi_rx_d_flip_1[0] <= tbi_rx_d_lvds_1[9];
tbi_rx_d_flip_1[1] <= tbi_rx_d_lvds_1[8];
tbi_rx_d_flip_1[2] <= tbi_rx_d_lvds_1[7];
tbi_rx_d_flip_1[3] <= tbi_rx_d_lvds_1[6];
tbi_rx_d_flip_1[4] <= tbi_rx_d_lvds_1[5];
tbi_rx_d_flip_1[5] <= tbi_rx_d_lvds_1[4];
tbi_rx_d_flip_1[6] <= tbi_rx_d_lvds_1[3];
tbi_rx_d_flip_1[7] <= tbi_rx_d_lvds_1[2];
tbi_rx_d_flip_1[8] <= tbi_rx_d_lvds_1[1];
tbi_rx_d_flip_1[9] <= tbi_rx_d_lvds_1[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_1 <= 0;
else
begin
tbi_tx_d_flip_1[0] <= tbi_tx_d_1[9];
tbi_tx_d_flip_1[1] <= tbi_tx_d_1[8];
tbi_tx_d_flip_1[2] <= tbi_tx_d_1[7];
tbi_tx_d_flip_1[3] <= tbi_tx_d_1[6];
tbi_tx_d_flip_1[4] <= tbi_tx_d_1[5];
tbi_tx_d_flip_1[5] <= tbi_tx_d_1[4];
tbi_tx_d_flip_1[6] <= tbi_tx_d_1[3];
tbi_tx_d_flip_1[7] <= tbi_tx_d_1[2];
tbi_tx_d_flip_1[8] <= tbi_tx_d_1[1];
tbi_tx_d_flip_1[9] <= tbi_tx_d_1[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_1
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_1 ),
.rx_locked ( rx_locked_1 ),
.rx_divfwdclk (tbi_rx_clk_1),
.rx_in (rxp_1),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_1),
.rx_outclock (),
.rx_reset (rx_reset_1)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_1
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_1 ),
.rx_channel_data_align ( rx_channel_data_align_1 ),
.rx_locked ( rx_locked_1 ),
.rx_divfwdclk (tbi_rx_clk_1),
.rx_in (rxp_1),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_1),
.rx_outclock (),
.rx_reset (rx_reset_1)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_1 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_1 ),
.rx_channel_data_align ( rx_channel_data_align_1 ),
.pll_areset ( pll_areset_1 ),
.rx_reset ( rx_reset_1 ),
.rx_cda_reset ( rx_cda_reset_1 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_1 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_1
(
.tx_in (tbi_tx_d_muxed_1),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_1)
);
end
else
begin
assign txp_1 = 1'b0;
assign tbi_rx_clk_1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
begin
assign gxb_pwrdn_in_sig[2] = gxb_pwrdn_in_2;
assign pcs_pwrdn_out_2 = pcs_pwrdn_out_sig[2];
end
else
begin
assign gxb_pwrdn_in_sig[2] = pcs_pwrdn_out_sig[2];
assign pcs_pwrdn_out_2 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 2)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_2(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_2), //INPUT
.dout(rev_loopback_ena_ref_clk_2));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_2 (
.reset_wclk(reset_tbi_rx_clk_2_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_2),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_2),
.tbi_tx_clk (tbi_tx_d_loopback_2)
);
assign tbi_tx_d_muxed_2 = rev_loopback_ena_ref_clk_2 ? tbi_tx_d_loopback_2: tbi_tx_d_flip_2;
end
else
begin
assign tbi_tx_d_muxed_2 = tbi_tx_d_flip_2;
// Unused wires
assign tbi_tx_d_loopback_2 = 10'd0;
assign rev_loopback_ena_ref_clk_2 = 1'b0;
end
assign tbi_tx_clk_2 = ref_clk;
assign tbi_rx_d_2 = tbi_rx_d_flip_2;
altera_tse_reset_synchronizer ch_2_reset_sync_0 (
.clk(tbi_rx_clk_2),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_2_int)
);
always @(posedge tbi_rx_clk_2 or posedge reset_tbi_rx_clk_2_int)
begin
if (reset_tbi_rx_clk_2_int == 1)
tbi_rx_d_flip_2 <= 0;
else
begin
if (rx_reset_sequence_done_2 == 1)
begin
tbi_rx_d_flip_2[0] <= tbi_rx_d_lvds_2[9];
tbi_rx_d_flip_2[1] <= tbi_rx_d_lvds_2[8];
tbi_rx_d_flip_2[2] <= tbi_rx_d_lvds_2[7];
tbi_rx_d_flip_2[3] <= tbi_rx_d_lvds_2[6];
tbi_rx_d_flip_2[4] <= tbi_rx_d_lvds_2[5];
tbi_rx_d_flip_2[5] <= tbi_rx_d_lvds_2[4];
tbi_rx_d_flip_2[6] <= tbi_rx_d_lvds_2[3];
tbi_rx_d_flip_2[7] <= tbi_rx_d_lvds_2[2];
tbi_rx_d_flip_2[8] <= tbi_rx_d_lvds_2[1];
tbi_rx_d_flip_2[9] <= tbi_rx_d_lvds_2[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_2 <= 0;
else
begin
tbi_tx_d_flip_2[0] <= tbi_tx_d_2[9];
tbi_tx_d_flip_2[1] <= tbi_tx_d_2[8];
tbi_tx_d_flip_2[2] <= tbi_tx_d_2[7];
tbi_tx_d_flip_2[3] <= tbi_tx_d_2[6];
tbi_tx_d_flip_2[4] <= tbi_tx_d_2[5];
tbi_tx_d_flip_2[5] <= tbi_tx_d_2[4];
tbi_tx_d_flip_2[6] <= tbi_tx_d_2[3];
tbi_tx_d_flip_2[7] <= tbi_tx_d_2[2];
tbi_tx_d_flip_2[8] <= tbi_tx_d_2[1];
tbi_tx_d_flip_2[9] <= tbi_tx_d_2[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_2
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_2 ),
.rx_locked ( rx_locked_2 ),
.rx_divfwdclk (tbi_rx_clk_2),
.rx_in (rxp_2),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_2),
.rx_outclock (),
.rx_reset (rx_reset_2)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_2
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_2 ),
.rx_channel_data_align ( rx_channel_data_align_2 ),
.rx_locked ( rx_locked_2 ),
.rx_divfwdclk (tbi_rx_clk_2),
.rx_in (rxp_2),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_2),
.rx_outclock (),
.rx_reset (rx_reset_2)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_2 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_2 ),
.rx_channel_data_align ( rx_channel_data_align_2 ),
.pll_areset ( pll_areset_2 ),
.rx_reset ( rx_reset_2 ),
.rx_cda_reset ( rx_cda_reset_2 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_2 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_2
(
.tx_in (tbi_tx_d_muxed_2),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_2)
);
end
else
begin
assign txp_2 = 1'b0;
assign tbi_rx_clk_2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 3)
begin
assign gxb_pwrdn_in_sig[3] = gxb_pwrdn_in_3;
assign pcs_pwrdn_out_3 = pcs_pwrdn_out_sig[3];
end
else
begin
assign gxb_pwrdn_in_sig[3] = pcs_pwrdn_out_sig[3];
assign pcs_pwrdn_out_3 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 3)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_3(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_3), //INPUT
.dout(rev_loopback_ena_ref_clk_3));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_3 (
.reset_wclk(reset_tbi_rx_clk_3_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_3),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_3),
.tbi_tx_clk (tbi_tx_d_loopback_3)
);
assign tbi_tx_d_muxed_3 = rev_loopback_ena_ref_clk_3 ? tbi_tx_d_loopback_3: tbi_tx_d_flip_3;
end
else
begin
assign tbi_tx_d_muxed_3 = tbi_tx_d_flip_3;
// Unused wires
assign tbi_tx_d_loopback_3 = 10'd0;
assign rev_loopback_ena_ref_clk_3 = 1'b0;
end
assign tbi_tx_clk_3 = ref_clk;
assign tbi_rx_d_3 = tbi_rx_d_flip_3;
altera_tse_reset_synchronizer ch_3_reset_sync_0 (
.clk(tbi_rx_clk_3),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_3_int)
);
always @(posedge tbi_rx_clk_3 or posedge reset_tbi_rx_clk_3_int)
begin
if (reset_tbi_rx_clk_3_int == 1)
tbi_rx_d_flip_3 <= 0;
else
begin
if (rx_reset_sequence_done_3 == 1)
begin
tbi_rx_d_flip_3[0] <= tbi_rx_d_lvds_3[9];
tbi_rx_d_flip_3[1] <= tbi_rx_d_lvds_3[8];
tbi_rx_d_flip_3[2] <= tbi_rx_d_lvds_3[7];
tbi_rx_d_flip_3[3] <= tbi_rx_d_lvds_3[6];
tbi_rx_d_flip_3[4] <= tbi_rx_d_lvds_3[5];
tbi_rx_d_flip_3[5] <= tbi_rx_d_lvds_3[4];
tbi_rx_d_flip_3[6] <= tbi_rx_d_lvds_3[3];
tbi_rx_d_flip_3[7] <= tbi_rx_d_lvds_3[2];
tbi_rx_d_flip_3[8] <= tbi_rx_d_lvds_3[1];
tbi_rx_d_flip_3[9] <= tbi_rx_d_lvds_3[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_3 <= 0;
else
begin
tbi_tx_d_flip_3[0] <= tbi_tx_d_3[9];
tbi_tx_d_flip_3[1] <= tbi_tx_d_3[8];
tbi_tx_d_flip_3[2] <= tbi_tx_d_3[7];
tbi_tx_d_flip_3[3] <= tbi_tx_d_3[6];
tbi_tx_d_flip_3[4] <= tbi_tx_d_3[5];
tbi_tx_d_flip_3[5] <= tbi_tx_d_3[4];
tbi_tx_d_flip_3[6] <= tbi_tx_d_3[3];
tbi_tx_d_flip_3[7] <= tbi_tx_d_3[2];
tbi_tx_d_flip_3[8] <= tbi_tx_d_3[1];
tbi_tx_d_flip_3[9] <= tbi_tx_d_3[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_3
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_3 ),
.rx_locked ( rx_locked_3 ),
.rx_divfwdclk (tbi_rx_clk_3),
.rx_in (rxp_3),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_3),
.rx_outclock (),
.rx_reset (rx_reset_3)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_3
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_3 ),
.rx_channel_data_align ( rx_channel_data_align_3 ),
.rx_locked ( rx_locked_3 ),
.rx_divfwdclk (tbi_rx_clk_3),
.rx_in (rxp_3),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_3),
.rx_outclock (),
.rx_reset (rx_reset_3)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_3 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_3 ),
.rx_channel_data_align ( rx_channel_data_align_3 ),
.pll_areset ( pll_areset_3 ),
.rx_reset ( rx_reset_3 ),
.rx_cda_reset ( rx_cda_reset_3 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_3 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_3
(
.tx_in (tbi_tx_d_muxed_3),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_3)
);
end
else
begin
assign txp_3 = 1'b0;
assign tbi_rx_clk_3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 4)
begin
assign gxb_pwrdn_in_sig[4] = gxb_pwrdn_in_4;
assign pcs_pwrdn_out_4 = pcs_pwrdn_out_sig[4];
end
else
begin
assign gxb_pwrdn_in_sig[4] = pcs_pwrdn_out_sig[4];
assign pcs_pwrdn_out_4 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 4)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_4(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_4), //INPUT
.dout(rev_loopback_ena_ref_clk_4));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_4 (
.reset_wclk(reset_tbi_rx_clk_4_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_4),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_4),
.tbi_tx_clk (tbi_tx_d_loopback_4)
);
assign tbi_tx_d_muxed_4 = rev_loopback_ena_ref_clk_4 ? tbi_tx_d_loopback_4: tbi_tx_d_flip_4;
end
else
begin
assign tbi_tx_d_muxed_4 = tbi_tx_d_flip_4;
// Unused wires
assign tbi_tx_d_loopback_4 = 10'd0;
assign rev_loopback_ena_ref_clk_4 = 1'b0;
end
assign tbi_tx_clk_4 = ref_clk;
assign tbi_rx_d_4 = tbi_rx_d_flip_4;
altera_tse_reset_synchronizer ch_4_reset_sync_0 (
.clk(tbi_rx_clk_4),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_4_int)
);
always @(posedge tbi_rx_clk_4 or posedge reset_tbi_rx_clk_4_int)
begin
if (reset_tbi_rx_clk_4_int == 1)
tbi_rx_d_flip_4 <= 0;
else
begin
if (rx_reset_sequence_done_4 == 1)
begin
tbi_rx_d_flip_4[0] <= tbi_rx_d_lvds_4[9];
tbi_rx_d_flip_4[1] <= tbi_rx_d_lvds_4[8];
tbi_rx_d_flip_4[2] <= tbi_rx_d_lvds_4[7];
tbi_rx_d_flip_4[3] <= tbi_rx_d_lvds_4[6];
tbi_rx_d_flip_4[4] <= tbi_rx_d_lvds_4[5];
tbi_rx_d_flip_4[5] <= tbi_rx_d_lvds_4[4];
tbi_rx_d_flip_4[6] <= tbi_rx_d_lvds_4[3];
tbi_rx_d_flip_4[7] <= tbi_rx_d_lvds_4[2];
tbi_rx_d_flip_4[8] <= tbi_rx_d_lvds_4[1];
tbi_rx_d_flip_4[9] <= tbi_rx_d_lvds_4[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_4 <= 0;
else
begin
tbi_tx_d_flip_4[0] <= tbi_tx_d_4[9];
tbi_tx_d_flip_4[1] <= tbi_tx_d_4[8];
tbi_tx_d_flip_4[2] <= tbi_tx_d_4[7];
tbi_tx_d_flip_4[3] <= tbi_tx_d_4[6];
tbi_tx_d_flip_4[4] <= tbi_tx_d_4[5];
tbi_tx_d_flip_4[5] <= tbi_tx_d_4[4];
tbi_tx_d_flip_4[6] <= tbi_tx_d_4[3];
tbi_tx_d_flip_4[7] <= tbi_tx_d_4[2];
tbi_tx_d_flip_4[8] <= tbi_tx_d_4[1];
tbi_tx_d_flip_4[9] <= tbi_tx_d_4[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_4
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_4 ),
.rx_locked ( rx_locked_4 ),
.rx_divfwdclk (tbi_rx_clk_4),
.rx_in (rxp_4),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_4),
.rx_outclock (),
.rx_reset (rx_reset_4)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_4
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_4 ),
.rx_channel_data_align ( rx_channel_data_align_4 ),
.rx_locked ( rx_locked_4 ),
.rx_divfwdclk (tbi_rx_clk_4),
.rx_in (rxp_4),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_4),
.rx_outclock (),
.rx_reset (rx_reset_4)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_4 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_4 ),
.rx_channel_data_align ( rx_channel_data_align_4 ),
.pll_areset ( pll_areset_4 ),
.rx_reset ( rx_reset_4 ),
.rx_cda_reset ( rx_cda_reset_4 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_4 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_4
(
.tx_in (tbi_tx_d_muxed_4),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_4)
);
end
else
begin
assign txp_4 = 1'b0;
assign tbi_rx_clk_4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 5)
begin
assign gxb_pwrdn_in_sig[5] = gxb_pwrdn_in_5;
assign pcs_pwrdn_out_5 = pcs_pwrdn_out_sig[5];
end
else
begin
assign gxb_pwrdn_in_sig[5] = pcs_pwrdn_out_sig[5];
assign pcs_pwrdn_out_5 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 5)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_5(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_5), //INPUT
.dout(rev_loopback_ena_ref_clk_5));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_5 (
.reset_wclk(reset_tbi_rx_clk_5_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_5),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_5),
.tbi_tx_clk (tbi_tx_d_loopback_5)
);
assign tbi_tx_d_muxed_5 = rev_loopback_ena_ref_clk_5 ? tbi_tx_d_loopback_5: tbi_tx_d_flip_5;
end
else
begin
assign tbi_tx_d_muxed_5 = tbi_tx_d_flip_5;
// Unused wires
assign tbi_tx_d_loopback_5 = 10'd0;
assign rev_loopback_ena_ref_clk_5 = 1'b0;
end
assign tbi_tx_clk_5 = ref_clk;
assign tbi_rx_d_5 = tbi_rx_d_flip_5;
altera_tse_reset_synchronizer ch_5_reset_sync_0 (
.clk(tbi_rx_clk_5),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_5_int)
);
always @(posedge tbi_rx_clk_5 or posedge reset_tbi_rx_clk_5_int)
begin
if (reset_tbi_rx_clk_5_int == 1)
tbi_rx_d_flip_5 <= 0;
else
begin
if (rx_reset_sequence_done_5 == 1)
begin
tbi_rx_d_flip_5[0] <= tbi_rx_d_lvds_5[9];
tbi_rx_d_flip_5[1] <= tbi_rx_d_lvds_5[8];
tbi_rx_d_flip_5[2] <= tbi_rx_d_lvds_5[7];
tbi_rx_d_flip_5[3] <= tbi_rx_d_lvds_5[6];
tbi_rx_d_flip_5[4] <= tbi_rx_d_lvds_5[5];
tbi_rx_d_flip_5[5] <= tbi_rx_d_lvds_5[4];
tbi_rx_d_flip_5[6] <= tbi_rx_d_lvds_5[3];
tbi_rx_d_flip_5[7] <= tbi_rx_d_lvds_5[2];
tbi_rx_d_flip_5[8] <= tbi_rx_d_lvds_5[1];
tbi_rx_d_flip_5[9] <= tbi_rx_d_lvds_5[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_5 <= 0;
else
begin
tbi_tx_d_flip_5[0] <= tbi_tx_d_5[9];
tbi_tx_d_flip_5[1] <= tbi_tx_d_5[8];
tbi_tx_d_flip_5[2] <= tbi_tx_d_5[7];
tbi_tx_d_flip_5[3] <= tbi_tx_d_5[6];
tbi_tx_d_flip_5[4] <= tbi_tx_d_5[5];
tbi_tx_d_flip_5[5] <= tbi_tx_d_5[4];
tbi_tx_d_flip_5[6] <= tbi_tx_d_5[3];
tbi_tx_d_flip_5[7] <= tbi_tx_d_5[2];
tbi_tx_d_flip_5[8] <= tbi_tx_d_5[1];
tbi_tx_d_flip_5[9] <= tbi_tx_d_5[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_5
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_5 ),
.rx_locked ( rx_locked_5 ),
.rx_divfwdclk (tbi_rx_clk_5),
.rx_in (rxp_5),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_5),
.rx_outclock (),
.rx_reset (rx_reset_5)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_5
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_5 ),
.rx_channel_data_align ( rx_channel_data_align_5 ),
.rx_locked ( rx_locked_5 ),
.rx_divfwdclk (tbi_rx_clk_5),
.rx_in (rxp_5),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_5),
.rx_outclock (),
.rx_reset (rx_reset_5)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_5 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_5 ),
.rx_channel_data_align ( rx_channel_data_align_5 ),
.pll_areset ( pll_areset_5 ),
.rx_reset ( rx_reset_5 ),
.rx_cda_reset ( rx_cda_reset_5 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_5 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_5
(
.tx_in (tbi_tx_d_muxed_5),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_5)
);
end
else
begin
assign txp_5 = 1'b0;
assign tbi_rx_clk_5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 6)
begin
assign gxb_pwrdn_in_sig[6] = gxb_pwrdn_in_6;
assign pcs_pwrdn_out_6 = pcs_pwrdn_out_sig[6];
end
else
begin
assign gxb_pwrdn_in_sig[6] = pcs_pwrdn_out_sig[6];
assign pcs_pwrdn_out_6 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 6)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_6(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_6), //INPUT
.dout(rev_loopback_ena_ref_clk_6));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_6 (
.reset_wclk(reset_tbi_rx_clk_6_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_6),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_6),
.tbi_tx_clk (tbi_tx_d_loopback_6)
);
assign tbi_tx_d_muxed_6 = rev_loopback_ena_ref_clk_6 ? tbi_tx_d_loopback_6: tbi_tx_d_flip_6;
end
else
begin
assign tbi_tx_d_muxed_6 = tbi_tx_d_flip_6;
// Unused wires
assign tbi_tx_d_loopback_6 = 10'd0;
assign rev_loopback_ena_ref_clk_6 = 1'b0;
end
assign tbi_tx_clk_6 = ref_clk;
assign tbi_rx_d_6 = tbi_rx_d_flip_6;
altera_tse_reset_synchronizer ch_6_reset_sync_0 (
.clk(tbi_rx_clk_6),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_6_int)
);
always @(posedge tbi_rx_clk_6 or posedge reset_tbi_rx_clk_6_int)
begin
if (reset_tbi_rx_clk_6_int == 1)
tbi_rx_d_flip_6 <= 0;
else
begin
if (rx_reset_sequence_done_6 == 1)
begin
tbi_rx_d_flip_6[0] <= tbi_rx_d_lvds_6[9];
tbi_rx_d_flip_6[1] <= tbi_rx_d_lvds_6[8];
tbi_rx_d_flip_6[2] <= tbi_rx_d_lvds_6[7];
tbi_rx_d_flip_6[3] <= tbi_rx_d_lvds_6[6];
tbi_rx_d_flip_6[4] <= tbi_rx_d_lvds_6[5];
tbi_rx_d_flip_6[5] <= tbi_rx_d_lvds_6[4];
tbi_rx_d_flip_6[6] <= tbi_rx_d_lvds_6[3];
tbi_rx_d_flip_6[7] <= tbi_rx_d_lvds_6[2];
tbi_rx_d_flip_6[8] <= tbi_rx_d_lvds_6[1];
tbi_rx_d_flip_6[9] <= tbi_rx_d_lvds_6[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_6 <= 0;
else
begin
tbi_tx_d_flip_6[0] <= tbi_tx_d_6[9];
tbi_tx_d_flip_6[1] <= tbi_tx_d_6[8];
tbi_tx_d_flip_6[2] <= tbi_tx_d_6[7];
tbi_tx_d_flip_6[3] <= tbi_tx_d_6[6];
tbi_tx_d_flip_6[4] <= tbi_tx_d_6[5];
tbi_tx_d_flip_6[5] <= tbi_tx_d_6[4];
tbi_tx_d_flip_6[6] <= tbi_tx_d_6[3];
tbi_tx_d_flip_6[7] <= tbi_tx_d_6[2];
tbi_tx_d_flip_6[8] <= tbi_tx_d_6[1];
tbi_tx_d_flip_6[9] <= tbi_tx_d_6[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_6
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_6 ),
.rx_locked ( rx_locked_6 ),
.rx_divfwdclk (tbi_rx_clk_6),
.rx_in (rxp_6),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_6),
.rx_outclock (),
.rx_reset (rx_reset_6)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_6
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_6 ),
.rx_channel_data_align ( rx_channel_data_align_6 ),
.rx_locked ( rx_locked_6 ),
.rx_divfwdclk (tbi_rx_clk_6),
.rx_in (rxp_6),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_6),
.rx_outclock (),
.rx_reset (rx_reset_6)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_6 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_6 ),
.rx_channel_data_align ( rx_channel_data_align_6 ),
.pll_areset ( pll_areset_6 ),
.rx_reset ( rx_reset_6 ),
.rx_cda_reset ( rx_cda_reset_6 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_6 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_6
(
.tx_in (tbi_tx_d_muxed_6),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_6)
);
end
else
begin
assign txp_6 = 1'b0;
assign tbi_rx_clk_6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 7)
begin
assign gxb_pwrdn_in_sig[7] = gxb_pwrdn_in_7;
assign pcs_pwrdn_out_7 = pcs_pwrdn_out_sig[7];
end
else
begin
assign gxb_pwrdn_in_sig[7] = pcs_pwrdn_out_sig[7];
assign pcs_pwrdn_out_7 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 7)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_7(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_7), //INPUT
.dout(rev_loopback_ena_ref_clk_7));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_7 (
.reset_wclk(reset_tbi_rx_clk_7_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_7),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_7),
.tbi_tx_clk (tbi_tx_d_loopback_7)
);
assign tbi_tx_d_muxed_7 = rev_loopback_ena_ref_clk_7 ? tbi_tx_d_loopback_7: tbi_tx_d_flip_7;
end
else
begin
assign tbi_tx_d_muxed_7 = tbi_tx_d_flip_7;
// Unused wires
assign tbi_tx_d_loopback_7 = 10'd0;
assign rev_loopback_ena_ref_clk_7 = 1'b0;
end
assign tbi_tx_clk_7 = ref_clk;
assign tbi_rx_d_7 = tbi_rx_d_flip_7;
altera_tse_reset_synchronizer ch_7_reset_sync_0 (
.clk(tbi_rx_clk_7),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_7_int)
);
always @(posedge tbi_rx_clk_7 or posedge reset_tbi_rx_clk_7_int)
begin
if (reset_tbi_rx_clk_7_int == 1)
tbi_rx_d_flip_7 <= 0;
else
begin
if (rx_reset_sequence_done_7 == 1)
begin
tbi_rx_d_flip_7[0] <= tbi_rx_d_lvds_7[9];
tbi_rx_d_flip_7[1] <= tbi_rx_d_lvds_7[8];
tbi_rx_d_flip_7[2] <= tbi_rx_d_lvds_7[7];
tbi_rx_d_flip_7[3] <= tbi_rx_d_lvds_7[6];
tbi_rx_d_flip_7[4] <= tbi_rx_d_lvds_7[5];
tbi_rx_d_flip_7[5] <= tbi_rx_d_lvds_7[4];
tbi_rx_d_flip_7[6] <= tbi_rx_d_lvds_7[3];
tbi_rx_d_flip_7[7] <= tbi_rx_d_lvds_7[2];
tbi_rx_d_flip_7[8] <= tbi_rx_d_lvds_7[1];
tbi_rx_d_flip_7[9] <= tbi_rx_d_lvds_7[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_7 <= 0;
else
begin
tbi_tx_d_flip_7[0] <= tbi_tx_d_7[9];
tbi_tx_d_flip_7[1] <= tbi_tx_d_7[8];
tbi_tx_d_flip_7[2] <= tbi_tx_d_7[7];
tbi_tx_d_flip_7[3] <= tbi_tx_d_7[6];
tbi_tx_d_flip_7[4] <= tbi_tx_d_7[5];
tbi_tx_d_flip_7[5] <= tbi_tx_d_7[4];
tbi_tx_d_flip_7[6] <= tbi_tx_d_7[3];
tbi_tx_d_flip_7[7] <= tbi_tx_d_7[2];
tbi_tx_d_flip_7[8] <= tbi_tx_d_7[1];
tbi_tx_d_flip_7[9] <= tbi_tx_d_7[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_7
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_7 ),
.rx_locked ( rx_locked_7 ),
.rx_divfwdclk (tbi_rx_clk_7),
.rx_in (rxp_7),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_7),
.rx_outclock (),
.rx_reset (rx_reset_7)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_7
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_7 ),
.rx_channel_data_align ( rx_channel_data_align_7 ),
.rx_locked ( rx_locked_7 ),
.rx_divfwdclk (tbi_rx_clk_7),
.rx_in (rxp_7),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_7),
.rx_outclock (),
.rx_reset (rx_reset_7)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_7 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_7 ),
.rx_channel_data_align ( rx_channel_data_align_7 ),
.pll_areset ( pll_areset_7 ),
.rx_reset ( rx_reset_7 ),
.rx_cda_reset ( rx_cda_reset_7 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_7 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_7
(
.tx_in (tbi_tx_d_muxed_7),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_7)
);
end
else
begin
assign txp_7 = 1'b0;
assign tbi_rx_clk_7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 8)
begin
assign gxb_pwrdn_in_sig[8] = gxb_pwrdn_in_8;
assign pcs_pwrdn_out_8 = pcs_pwrdn_out_sig[8];
end
else
begin
assign gxb_pwrdn_in_sig[8] = pcs_pwrdn_out_sig[8];
assign pcs_pwrdn_out_8 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 8)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_8(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_8), //INPUT
.dout(rev_loopback_ena_ref_clk_8));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_8 (
.reset_wclk(reset_tbi_rx_clk_8_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_8),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_8),
.tbi_tx_clk (tbi_tx_d_loopback_8)
);
assign tbi_tx_d_muxed_8 = rev_loopback_ena_ref_clk_8 ? tbi_tx_d_loopback_8: tbi_tx_d_flip_8;
end
else
begin
assign tbi_tx_d_muxed_8 = tbi_tx_d_flip_8;
// Unused wires
assign tbi_tx_d_loopback_8 = 10'd0;
assign rev_loopback_ena_ref_clk_8 = 1'b0;
end
assign tbi_tx_clk_8 = ref_clk;
assign tbi_rx_d_8 = tbi_rx_d_flip_8;
altera_tse_reset_synchronizer ch_8_reset_sync_0 (
.clk(tbi_rx_clk_8),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_8_int)
);
always @(posedge tbi_rx_clk_8 or posedge reset_tbi_rx_clk_8_int)
begin
if (reset_tbi_rx_clk_8_int == 1)
tbi_rx_d_flip_8 <= 0;
else
begin
if (rx_reset_sequence_done_8 == 1)
begin
tbi_rx_d_flip_8[0] <= tbi_rx_d_lvds_8[9];
tbi_rx_d_flip_8[1] <= tbi_rx_d_lvds_8[8];
tbi_rx_d_flip_8[2] <= tbi_rx_d_lvds_8[7];
tbi_rx_d_flip_8[3] <= tbi_rx_d_lvds_8[6];
tbi_rx_d_flip_8[4] <= tbi_rx_d_lvds_8[5];
tbi_rx_d_flip_8[5] <= tbi_rx_d_lvds_8[4];
tbi_rx_d_flip_8[6] <= tbi_rx_d_lvds_8[3];
tbi_rx_d_flip_8[7] <= tbi_rx_d_lvds_8[2];
tbi_rx_d_flip_8[8] <= tbi_rx_d_lvds_8[1];
tbi_rx_d_flip_8[9] <= tbi_rx_d_lvds_8[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_8 <= 0;
else
begin
tbi_tx_d_flip_8[0] <= tbi_tx_d_8[9];
tbi_tx_d_flip_8[1] <= tbi_tx_d_8[8];
tbi_tx_d_flip_8[2] <= tbi_tx_d_8[7];
tbi_tx_d_flip_8[3] <= tbi_tx_d_8[6];
tbi_tx_d_flip_8[4] <= tbi_tx_d_8[5];
tbi_tx_d_flip_8[5] <= tbi_tx_d_8[4];
tbi_tx_d_flip_8[6] <= tbi_tx_d_8[3];
tbi_tx_d_flip_8[7] <= tbi_tx_d_8[2];
tbi_tx_d_flip_8[8] <= tbi_tx_d_8[1];
tbi_tx_d_flip_8[9] <= tbi_tx_d_8[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_8
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_8 ),
.rx_locked ( rx_locked_8 ),
.rx_divfwdclk (tbi_rx_clk_8),
.rx_in (rxp_8),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_8),
.rx_outclock (),
.rx_reset (rx_reset_8)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_8
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_8 ),
.rx_channel_data_align ( rx_channel_data_align_8 ),
.rx_locked ( rx_locked_8 ),
.rx_divfwdclk (tbi_rx_clk_8),
.rx_in (rxp_8),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_8),
.rx_outclock (),
.rx_reset (rx_reset_8)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_8 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_8 ),
.rx_channel_data_align ( rx_channel_data_align_8 ),
.pll_areset ( pll_areset_8 ),
.rx_reset ( rx_reset_8 ),
.rx_cda_reset ( rx_cda_reset_8 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_8 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_8
(
.tx_in (tbi_tx_d_muxed_8),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_8)
);
end
else
begin
assign txp_8 = 1'b0;
assign tbi_rx_clk_8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 9)
begin
assign gxb_pwrdn_in_sig[9] = gxb_pwrdn_in_9;
assign pcs_pwrdn_out_9 = pcs_pwrdn_out_sig[9];
end
else
begin
assign gxb_pwrdn_in_sig[9] = pcs_pwrdn_out_sig[9];
assign pcs_pwrdn_out_9 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 9)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_9(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_9), //INPUT
.dout(rev_loopback_ena_ref_clk_9));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_9 (
.reset_wclk(reset_tbi_rx_clk_9_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_9),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_9),
.tbi_tx_clk (tbi_tx_d_loopback_9)
);
assign tbi_tx_d_muxed_9 = rev_loopback_ena_ref_clk_9 ? tbi_tx_d_loopback_9: tbi_tx_d_flip_9;
end
else
begin
assign tbi_tx_d_muxed_9 = tbi_tx_d_flip_9;
// Unused wires
assign tbi_tx_d_loopback_9 = 10'd0;
assign rev_loopback_ena_ref_clk_9 = 1'b0;
end
assign tbi_tx_clk_9 = ref_clk;
assign tbi_rx_d_9 = tbi_rx_d_flip_9;
altera_tse_reset_synchronizer ch_9_reset_sync_0 (
.clk(tbi_rx_clk_9),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_9_int)
);
always @(posedge tbi_rx_clk_9 or posedge reset_tbi_rx_clk_9_int)
begin
if (reset_tbi_rx_clk_9_int == 1)
tbi_rx_d_flip_9 <= 0;
else
begin
if (rx_reset_sequence_done_9 == 1)
begin
tbi_rx_d_flip_9[0] <= tbi_rx_d_lvds_9[9];
tbi_rx_d_flip_9[1] <= tbi_rx_d_lvds_9[8];
tbi_rx_d_flip_9[2] <= tbi_rx_d_lvds_9[7];
tbi_rx_d_flip_9[3] <= tbi_rx_d_lvds_9[6];
tbi_rx_d_flip_9[4] <= tbi_rx_d_lvds_9[5];
tbi_rx_d_flip_9[5] <= tbi_rx_d_lvds_9[4];
tbi_rx_d_flip_9[6] <= tbi_rx_d_lvds_9[3];
tbi_rx_d_flip_9[7] <= tbi_rx_d_lvds_9[2];
tbi_rx_d_flip_9[8] <= tbi_rx_d_lvds_9[1];
tbi_rx_d_flip_9[9] <= tbi_rx_d_lvds_9[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_9 <= 0;
else
begin
tbi_tx_d_flip_9[0] <= tbi_tx_d_9[9];
tbi_tx_d_flip_9[1] <= tbi_tx_d_9[8];
tbi_tx_d_flip_9[2] <= tbi_tx_d_9[7];
tbi_tx_d_flip_9[3] <= tbi_tx_d_9[6];
tbi_tx_d_flip_9[4] <= tbi_tx_d_9[5];
tbi_tx_d_flip_9[5] <= tbi_tx_d_9[4];
tbi_tx_d_flip_9[6] <= tbi_tx_d_9[3];
tbi_tx_d_flip_9[7] <= tbi_tx_d_9[2];
tbi_tx_d_flip_9[8] <= tbi_tx_d_9[1];
tbi_tx_d_flip_9[9] <= tbi_tx_d_9[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_9
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_9 ),
.rx_locked ( rx_locked_9 ),
.rx_divfwdclk (tbi_rx_clk_9),
.rx_in (rxp_9),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_9),
.rx_outclock (),
.rx_reset (rx_reset_9)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_9
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_9 ),
.rx_channel_data_align ( rx_channel_data_align_9 ),
.rx_locked ( rx_locked_9 ),
.rx_divfwdclk (tbi_rx_clk_9),
.rx_in (rxp_9),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_9),
.rx_outclock (),
.rx_reset (rx_reset_9)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_9 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_9 ),
.rx_channel_data_align ( rx_channel_data_align_9 ),
.pll_areset ( pll_areset_9 ),
.rx_reset ( rx_reset_9 ),
.rx_cda_reset ( rx_cda_reset_9 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_9 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_9
(
.tx_in (tbi_tx_d_muxed_9),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_9)
);
end
else
begin
assign txp_9 = 1'b0;
assign tbi_rx_clk_9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 10)
begin
assign gxb_pwrdn_in_sig[10] = gxb_pwrdn_in_10;
assign pcs_pwrdn_out_10 = pcs_pwrdn_out_sig[10];
end
else
begin
assign gxb_pwrdn_in_sig[10] = pcs_pwrdn_out_sig[10];
assign pcs_pwrdn_out_10 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 10)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_10(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_10), //INPUT
.dout(rev_loopback_ena_ref_clk_10));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_10 (
.reset_wclk(reset_tbi_rx_clk_10_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_10),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_10),
.tbi_tx_clk (tbi_tx_d_loopback_10)
);
assign tbi_tx_d_muxed_10 = rev_loopback_ena_ref_clk_10 ? tbi_tx_d_loopback_10: tbi_tx_d_flip_10;
end
else
begin
assign tbi_tx_d_muxed_10 = tbi_tx_d_flip_10;
// Unused wires
assign tbi_tx_d_loopback_10 = 10'd0;
assign rev_loopback_ena_ref_clk_10 = 1'b0;
end
assign tbi_tx_clk_10 = ref_clk;
assign tbi_rx_d_10 = tbi_rx_d_flip_10;
altera_tse_reset_synchronizer ch_10_reset_sync_0 (
.clk(tbi_rx_clk_10),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_10_int)
);
always @(posedge tbi_rx_clk_10 or posedge reset_tbi_rx_clk_10_int)
begin
if (reset_tbi_rx_clk_10_int == 1)
tbi_rx_d_flip_10 <= 0;
else
begin
if (rx_reset_sequence_done_10 == 1)
begin
tbi_rx_d_flip_10[0] <= tbi_rx_d_lvds_10[9];
tbi_rx_d_flip_10[1] <= tbi_rx_d_lvds_10[8];
tbi_rx_d_flip_10[2] <= tbi_rx_d_lvds_10[7];
tbi_rx_d_flip_10[3] <= tbi_rx_d_lvds_10[6];
tbi_rx_d_flip_10[4] <= tbi_rx_d_lvds_10[5];
tbi_rx_d_flip_10[5] <= tbi_rx_d_lvds_10[4];
tbi_rx_d_flip_10[6] <= tbi_rx_d_lvds_10[3];
tbi_rx_d_flip_10[7] <= tbi_rx_d_lvds_10[2];
tbi_rx_d_flip_10[8] <= tbi_rx_d_lvds_10[1];
tbi_rx_d_flip_10[9] <= tbi_rx_d_lvds_10[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_10 <= 0;
else
begin
tbi_tx_d_flip_10[0] <= tbi_tx_d_10[9];
tbi_tx_d_flip_10[1] <= tbi_tx_d_10[8];
tbi_tx_d_flip_10[2] <= tbi_tx_d_10[7];
tbi_tx_d_flip_10[3] <= tbi_tx_d_10[6];
tbi_tx_d_flip_10[4] <= tbi_tx_d_10[5];
tbi_tx_d_flip_10[5] <= tbi_tx_d_10[4];
tbi_tx_d_flip_10[6] <= tbi_tx_d_10[3];
tbi_tx_d_flip_10[7] <= tbi_tx_d_10[2];
tbi_tx_d_flip_10[8] <= tbi_tx_d_10[1];
tbi_tx_d_flip_10[9] <= tbi_tx_d_10[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_10
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_10 ),
.rx_locked ( rx_locked_10 ),
.rx_divfwdclk (tbi_rx_clk_10),
.rx_in (rxp_10),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_10),
.rx_outclock (),
.rx_reset (rx_reset_10)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_10
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_10 ),
.rx_channel_data_align ( rx_channel_data_align_10 ),
.rx_locked ( rx_locked_10 ),
.rx_divfwdclk (tbi_rx_clk_10),
.rx_in (rxp_10),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_10),
.rx_outclock (),
.rx_reset (rx_reset_10)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_10 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_10 ),
.rx_channel_data_align ( rx_channel_data_align_10 ),
.pll_areset ( pll_areset_10 ),
.rx_reset ( rx_reset_10 ),
.rx_cda_reset ( rx_cda_reset_10 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_10 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_10
(
.tx_in (tbi_tx_d_muxed_10),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_10)
);
end
else
begin
assign txp_10 = 1'b0;
assign tbi_rx_clk_10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 11)
begin
assign gxb_pwrdn_in_sig[11] = gxb_pwrdn_in_11;
assign pcs_pwrdn_out_11 = pcs_pwrdn_out_sig[11];
end
else
begin
assign gxb_pwrdn_in_sig[11] = pcs_pwrdn_out_sig[11];
assign pcs_pwrdn_out_11 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 11)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_11(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_11), //INPUT
.dout(rev_loopback_ena_ref_clk_11));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_11 (
.reset_wclk(reset_tbi_rx_clk_11_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_11),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_11),
.tbi_tx_clk (tbi_tx_d_loopback_11)
);
assign tbi_tx_d_muxed_11 = rev_loopback_ena_ref_clk_11 ? tbi_tx_d_loopback_11: tbi_tx_d_flip_11;
end
else
begin
assign tbi_tx_d_muxed_11 = tbi_tx_d_flip_11;
// Unused wires
assign tbi_tx_d_loopback_11 = 10'd0;
assign rev_loopback_ena_ref_clk_11 = 1'b0;
end
assign tbi_tx_clk_11 = ref_clk;
assign tbi_rx_d_11 = tbi_rx_d_flip_11;
altera_tse_reset_synchronizer ch_11_reset_sync_0 (
.clk(tbi_rx_clk_11),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_11_int)
);
always @(posedge tbi_rx_clk_11 or posedge reset_tbi_rx_clk_11_int)
begin
if (reset_tbi_rx_clk_11_int == 1)
tbi_rx_d_flip_11 <= 0;
else
begin
if (rx_reset_sequence_done_11 == 1)
begin
tbi_rx_d_flip_11[0] <= tbi_rx_d_lvds_11[9];
tbi_rx_d_flip_11[1] <= tbi_rx_d_lvds_11[8];
tbi_rx_d_flip_11[2] <= tbi_rx_d_lvds_11[7];
tbi_rx_d_flip_11[3] <= tbi_rx_d_lvds_11[6];
tbi_rx_d_flip_11[4] <= tbi_rx_d_lvds_11[5];
tbi_rx_d_flip_11[5] <= tbi_rx_d_lvds_11[4];
tbi_rx_d_flip_11[6] <= tbi_rx_d_lvds_11[3];
tbi_rx_d_flip_11[7] <= tbi_rx_d_lvds_11[2];
tbi_rx_d_flip_11[8] <= tbi_rx_d_lvds_11[1];
tbi_rx_d_flip_11[9] <= tbi_rx_d_lvds_11[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_11 <= 0;
else
begin
tbi_tx_d_flip_11[0] <= tbi_tx_d_11[9];
tbi_tx_d_flip_11[1] <= tbi_tx_d_11[8];
tbi_tx_d_flip_11[2] <= tbi_tx_d_11[7];
tbi_tx_d_flip_11[3] <= tbi_tx_d_11[6];
tbi_tx_d_flip_11[4] <= tbi_tx_d_11[5];
tbi_tx_d_flip_11[5] <= tbi_tx_d_11[4];
tbi_tx_d_flip_11[6] <= tbi_tx_d_11[3];
tbi_tx_d_flip_11[7] <= tbi_tx_d_11[2];
tbi_tx_d_flip_11[8] <= tbi_tx_d_11[1];
tbi_tx_d_flip_11[9] <= tbi_tx_d_11[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_11
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_11 ),
.rx_locked ( rx_locked_11 ),
.rx_divfwdclk (tbi_rx_clk_11),
.rx_in (rxp_11),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_11),
.rx_outclock (),
.rx_reset (rx_reset_11)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_11
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_11 ),
.rx_channel_data_align ( rx_channel_data_align_11 ),
.rx_locked ( rx_locked_11 ),
.rx_divfwdclk (tbi_rx_clk_11),
.rx_in (rxp_11),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_11),
.rx_outclock (),
.rx_reset (rx_reset_11)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_11 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_11 ),
.rx_channel_data_align ( rx_channel_data_align_11 ),
.pll_areset ( pll_areset_11 ),
.rx_reset ( rx_reset_11 ),
.rx_cda_reset ( rx_cda_reset_11 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_11 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_11
(
.tx_in (tbi_tx_d_muxed_11),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_11)
);
end
else
begin
assign txp_11 = 1'b0;
assign tbi_rx_clk_11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 12)
begin
assign gxb_pwrdn_in_sig[12] = gxb_pwrdn_in_12;
assign pcs_pwrdn_out_12 = pcs_pwrdn_out_sig[12];
end
else
begin
assign gxb_pwrdn_in_sig[12] = pcs_pwrdn_out_sig[12];
assign pcs_pwrdn_out_12 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 12)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_12(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_12), //INPUT
.dout(rev_loopback_ena_ref_clk_12));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_12 (
.reset_wclk(reset_tbi_rx_clk_12_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_12),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_12),
.tbi_tx_clk (tbi_tx_d_loopback_12)
);
assign tbi_tx_d_muxed_12 = rev_loopback_ena_ref_clk_12 ? tbi_tx_d_loopback_12: tbi_tx_d_flip_12;
end
else
begin
assign tbi_tx_d_muxed_12 = tbi_tx_d_flip_12;
// Unused wires
assign tbi_tx_d_loopback_12 = 10'd0;
assign rev_loopback_ena_ref_clk_12 = 1'b0;
end
assign tbi_tx_clk_12 = ref_clk;
assign tbi_rx_d_12 = tbi_rx_d_flip_12;
altera_tse_reset_synchronizer ch_12_reset_sync_0 (
.clk(tbi_rx_clk_12),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_12_int)
);
always @(posedge tbi_rx_clk_12 or posedge reset_tbi_rx_clk_12_int)
begin
if (reset_tbi_rx_clk_12_int == 1)
tbi_rx_d_flip_12 <= 0;
else
begin
if (rx_reset_sequence_done_12 == 1)
begin
tbi_rx_d_flip_12[0] <= tbi_rx_d_lvds_12[9];
tbi_rx_d_flip_12[1] <= tbi_rx_d_lvds_12[8];
tbi_rx_d_flip_12[2] <= tbi_rx_d_lvds_12[7];
tbi_rx_d_flip_12[3] <= tbi_rx_d_lvds_12[6];
tbi_rx_d_flip_12[4] <= tbi_rx_d_lvds_12[5];
tbi_rx_d_flip_12[5] <= tbi_rx_d_lvds_12[4];
tbi_rx_d_flip_12[6] <= tbi_rx_d_lvds_12[3];
tbi_rx_d_flip_12[7] <= tbi_rx_d_lvds_12[2];
tbi_rx_d_flip_12[8] <= tbi_rx_d_lvds_12[1];
tbi_rx_d_flip_12[9] <= tbi_rx_d_lvds_12[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_12 <= 0;
else
begin
tbi_tx_d_flip_12[0] <= tbi_tx_d_12[9];
tbi_tx_d_flip_12[1] <= tbi_tx_d_12[8];
tbi_tx_d_flip_12[2] <= tbi_tx_d_12[7];
tbi_tx_d_flip_12[3] <= tbi_tx_d_12[6];
tbi_tx_d_flip_12[4] <= tbi_tx_d_12[5];
tbi_tx_d_flip_12[5] <= tbi_tx_d_12[4];
tbi_tx_d_flip_12[6] <= tbi_tx_d_12[3];
tbi_tx_d_flip_12[7] <= tbi_tx_d_12[2];
tbi_tx_d_flip_12[8] <= tbi_tx_d_12[1];
tbi_tx_d_flip_12[9] <= tbi_tx_d_12[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_12
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_12 ),
.rx_locked ( rx_locked_12 ),
.rx_divfwdclk (tbi_rx_clk_12),
.rx_in (rxp_12),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_12),
.rx_outclock (),
.rx_reset (rx_reset_12)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_12
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_12 ),
.rx_channel_data_align ( rx_channel_data_align_12 ),
.rx_locked ( rx_locked_12 ),
.rx_divfwdclk (tbi_rx_clk_12),
.rx_in (rxp_12),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_12),
.rx_outclock (),
.rx_reset (rx_reset_12)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_12 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_12 ),
.rx_channel_data_align ( rx_channel_data_align_12 ),
.pll_areset ( pll_areset_12 ),
.rx_reset ( rx_reset_12 ),
.rx_cda_reset ( rx_cda_reset_12 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_12 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_12
(
.tx_in (tbi_tx_d_muxed_12),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_12)
);
end
else
begin
assign txp_12 = 1'b0;
assign tbi_rx_clk_12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 13)
begin
assign gxb_pwrdn_in_sig[13] = gxb_pwrdn_in_13;
assign pcs_pwrdn_out_13 = pcs_pwrdn_out_sig[13];
end
else
begin
assign gxb_pwrdn_in_sig[13] = pcs_pwrdn_out_sig[13];
assign pcs_pwrdn_out_13 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 13)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_13(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_13), //INPUT
.dout(rev_loopback_ena_ref_clk_13));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_13 (
.reset_wclk(reset_tbi_rx_clk_13_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_13),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_13),
.tbi_tx_clk (tbi_tx_d_loopback_13)
);
assign tbi_tx_d_muxed_13 = rev_loopback_ena_ref_clk_13 ? tbi_tx_d_loopback_13: tbi_tx_d_flip_13;
end
else
begin
assign tbi_tx_d_muxed_13 = tbi_tx_d_flip_13;
// Unused wires
assign tbi_tx_d_loopback_13 = 10'd0;
assign rev_loopback_ena_ref_clk_13 = 1'b0;
end
assign tbi_tx_clk_13 = ref_clk;
assign tbi_rx_d_13 = tbi_rx_d_flip_13;
altera_tse_reset_synchronizer ch_13_reset_sync_0 (
.clk(tbi_rx_clk_13),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_13_int)
);
always @(posedge tbi_rx_clk_13 or posedge reset_tbi_rx_clk_13_int)
begin
if (reset_tbi_rx_clk_13_int == 1)
tbi_rx_d_flip_13 <= 0;
else
begin
if (rx_reset_sequence_done_13 == 1)
begin
tbi_rx_d_flip_13[0] <= tbi_rx_d_lvds_13[9];
tbi_rx_d_flip_13[1] <= tbi_rx_d_lvds_13[8];
tbi_rx_d_flip_13[2] <= tbi_rx_d_lvds_13[7];
tbi_rx_d_flip_13[3] <= tbi_rx_d_lvds_13[6];
tbi_rx_d_flip_13[4] <= tbi_rx_d_lvds_13[5];
tbi_rx_d_flip_13[5] <= tbi_rx_d_lvds_13[4];
tbi_rx_d_flip_13[6] <= tbi_rx_d_lvds_13[3];
tbi_rx_d_flip_13[7] <= tbi_rx_d_lvds_13[2];
tbi_rx_d_flip_13[8] <= tbi_rx_d_lvds_13[1];
tbi_rx_d_flip_13[9] <= tbi_rx_d_lvds_13[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_13 <= 0;
else
begin
tbi_tx_d_flip_13[0] <= tbi_tx_d_13[9];
tbi_tx_d_flip_13[1] <= tbi_tx_d_13[8];
tbi_tx_d_flip_13[2] <= tbi_tx_d_13[7];
tbi_tx_d_flip_13[3] <= tbi_tx_d_13[6];
tbi_tx_d_flip_13[4] <= tbi_tx_d_13[5];
tbi_tx_d_flip_13[5] <= tbi_tx_d_13[4];
tbi_tx_d_flip_13[6] <= tbi_tx_d_13[3];
tbi_tx_d_flip_13[7] <= tbi_tx_d_13[2];
tbi_tx_d_flip_13[8] <= tbi_tx_d_13[1];
tbi_tx_d_flip_13[9] <= tbi_tx_d_13[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_13
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_13 ),
.rx_locked ( rx_locked_13 ),
.rx_divfwdclk (tbi_rx_clk_13),
.rx_in (rxp_13),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_13),
.rx_outclock (),
.rx_reset (rx_reset_13)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_13
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_13 ),
.rx_channel_data_align ( rx_channel_data_align_13 ),
.rx_locked ( rx_locked_13 ),
.rx_divfwdclk (tbi_rx_clk_13),
.rx_in (rxp_13),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_13),
.rx_outclock (),
.rx_reset (rx_reset_13)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_13 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_13 ),
.rx_channel_data_align ( rx_channel_data_align_13 ),
.pll_areset ( pll_areset_13 ),
.rx_reset ( rx_reset_13 ),
.rx_cda_reset ( rx_cda_reset_13 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_13 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_13
(
.tx_in (tbi_tx_d_muxed_13),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_13)
);
end
else
begin
assign txp_13 = 1'b0;
assign tbi_rx_clk_13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 14)
begin
assign gxb_pwrdn_in_sig[14] = gxb_pwrdn_in_14;
assign pcs_pwrdn_out_14 = pcs_pwrdn_out_sig[14];
end
else
begin
assign gxb_pwrdn_in_sig[14] = pcs_pwrdn_out_sig[14];
assign pcs_pwrdn_out_14 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 14)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_14(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_14), //INPUT
.dout(rev_loopback_ena_ref_clk_14));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_14 (
.reset_wclk(reset_tbi_rx_clk_14_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_14),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_14),
.tbi_tx_clk (tbi_tx_d_loopback_14)
);
assign tbi_tx_d_muxed_14 = rev_loopback_ena_ref_clk_14 ? tbi_tx_d_loopback_14: tbi_tx_d_flip_14;
end
else
begin
assign tbi_tx_d_muxed_14 = tbi_tx_d_flip_14;
// Unused wires
assign tbi_tx_d_loopback_14 = 10'd0;
assign rev_loopback_ena_ref_clk_14 = 1'b0;
end
assign tbi_tx_clk_14 = ref_clk;
assign tbi_rx_d_14 = tbi_rx_d_flip_14;
altera_tse_reset_synchronizer ch_14_reset_sync_0 (
.clk(tbi_rx_clk_14),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_14_int)
);
always @(posedge tbi_rx_clk_14 or posedge reset_tbi_rx_clk_14_int)
begin
if (reset_tbi_rx_clk_14_int == 1)
tbi_rx_d_flip_14 <= 0;
else
begin
if (rx_reset_sequence_done_14 == 1)
begin
tbi_rx_d_flip_14[0] <= tbi_rx_d_lvds_14[9];
tbi_rx_d_flip_14[1] <= tbi_rx_d_lvds_14[8];
tbi_rx_d_flip_14[2] <= tbi_rx_d_lvds_14[7];
tbi_rx_d_flip_14[3] <= tbi_rx_d_lvds_14[6];
tbi_rx_d_flip_14[4] <= tbi_rx_d_lvds_14[5];
tbi_rx_d_flip_14[5] <= tbi_rx_d_lvds_14[4];
tbi_rx_d_flip_14[6] <= tbi_rx_d_lvds_14[3];
tbi_rx_d_flip_14[7] <= tbi_rx_d_lvds_14[2];
tbi_rx_d_flip_14[8] <= tbi_rx_d_lvds_14[1];
tbi_rx_d_flip_14[9] <= tbi_rx_d_lvds_14[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_14 <= 0;
else
begin
tbi_tx_d_flip_14[0] <= tbi_tx_d_14[9];
tbi_tx_d_flip_14[1] <= tbi_tx_d_14[8];
tbi_tx_d_flip_14[2] <= tbi_tx_d_14[7];
tbi_tx_d_flip_14[3] <= tbi_tx_d_14[6];
tbi_tx_d_flip_14[4] <= tbi_tx_d_14[5];
tbi_tx_d_flip_14[5] <= tbi_tx_d_14[4];
tbi_tx_d_flip_14[6] <= tbi_tx_d_14[3];
tbi_tx_d_flip_14[7] <= tbi_tx_d_14[2];
tbi_tx_d_flip_14[8] <= tbi_tx_d_14[1];
tbi_tx_d_flip_14[9] <= tbi_tx_d_14[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_14
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_14 ),
.rx_locked ( rx_locked_14 ),
.rx_divfwdclk (tbi_rx_clk_14),
.rx_in (rxp_14),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_14),
.rx_outclock (),
.rx_reset (rx_reset_14)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_14
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_14 ),
.rx_channel_data_align ( rx_channel_data_align_14 ),
.rx_locked ( rx_locked_14 ),
.rx_divfwdclk (tbi_rx_clk_14),
.rx_in (rxp_14),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_14),
.rx_outclock (),
.rx_reset (rx_reset_14)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_14 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_14 ),
.rx_channel_data_align ( rx_channel_data_align_14 ),
.pll_areset ( pll_areset_14 ),
.rx_reset ( rx_reset_14 ),
.rx_cda_reset ( rx_cda_reset_14 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_14 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_14
(
.tx_in (tbi_tx_d_muxed_14),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_14)
);
end
else
begin
assign txp_14 = 1'b0;
assign tbi_rx_clk_14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 15)
begin
assign gxb_pwrdn_in_sig[15] = gxb_pwrdn_in_15;
assign pcs_pwrdn_out_15 = pcs_pwrdn_out_sig[15];
end
else
begin
assign gxb_pwrdn_in_sig[15] = pcs_pwrdn_out_sig[15];
assign pcs_pwrdn_out_15 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 15)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_15(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_15), //INPUT
.dout(rev_loopback_ena_ref_clk_15));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_15 (
.reset_wclk(reset_tbi_rx_clk_15_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_15),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_15),
.tbi_tx_clk (tbi_tx_d_loopback_15)
);
assign tbi_tx_d_muxed_15 = rev_loopback_ena_ref_clk_15 ? tbi_tx_d_loopback_15: tbi_tx_d_flip_15;
end
else
begin
assign tbi_tx_d_muxed_15 = tbi_tx_d_flip_15;
// Unused wires
assign tbi_tx_d_loopback_15 = 10'd0;
assign rev_loopback_ena_ref_clk_15 = 1'b0;
end
assign tbi_tx_clk_15 = ref_clk;
assign tbi_rx_d_15 = tbi_rx_d_flip_15;
altera_tse_reset_synchronizer ch_15_reset_sync_0 (
.clk(tbi_rx_clk_15),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_15_int)
);
always @(posedge tbi_rx_clk_15 or posedge reset_tbi_rx_clk_15_int)
begin
if (reset_tbi_rx_clk_15_int == 1)
tbi_rx_d_flip_15 <= 0;
else
begin
if (rx_reset_sequence_done_15 == 1)
begin
tbi_rx_d_flip_15[0] <= tbi_rx_d_lvds_15[9];
tbi_rx_d_flip_15[1] <= tbi_rx_d_lvds_15[8];
tbi_rx_d_flip_15[2] <= tbi_rx_d_lvds_15[7];
tbi_rx_d_flip_15[3] <= tbi_rx_d_lvds_15[6];
tbi_rx_d_flip_15[4] <= tbi_rx_d_lvds_15[5];
tbi_rx_d_flip_15[5] <= tbi_rx_d_lvds_15[4];
tbi_rx_d_flip_15[6] <= tbi_rx_d_lvds_15[3];
tbi_rx_d_flip_15[7] <= tbi_rx_d_lvds_15[2];
tbi_rx_d_flip_15[8] <= tbi_rx_d_lvds_15[1];
tbi_rx_d_flip_15[9] <= tbi_rx_d_lvds_15[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_15 <= 0;
else
begin
tbi_tx_d_flip_15[0] <= tbi_tx_d_15[9];
tbi_tx_d_flip_15[1] <= tbi_tx_d_15[8];
tbi_tx_d_flip_15[2] <= tbi_tx_d_15[7];
tbi_tx_d_flip_15[3] <= tbi_tx_d_15[6];
tbi_tx_d_flip_15[4] <= tbi_tx_d_15[5];
tbi_tx_d_flip_15[5] <= tbi_tx_d_15[4];
tbi_tx_d_flip_15[6] <= tbi_tx_d_15[3];
tbi_tx_d_flip_15[7] <= tbi_tx_d_15[2];
tbi_tx_d_flip_15[8] <= tbi_tx_d_15[1];
tbi_tx_d_flip_15[9] <= tbi_tx_d_15[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_15
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_15 ),
.rx_locked ( rx_locked_15 ),
.rx_divfwdclk (tbi_rx_clk_15),
.rx_in (rxp_15),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_15),
.rx_outclock (),
.rx_reset (rx_reset_15)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_15
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_15 ),
.rx_channel_data_align ( rx_channel_data_align_15 ),
.rx_locked ( rx_locked_15 ),
.rx_divfwdclk (tbi_rx_clk_15),
.rx_in (rxp_15),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_15),
.rx_outclock (),
.rx_reset (rx_reset_15)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_15 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_15 ),
.rx_channel_data_align ( rx_channel_data_align_15 ),
.pll_areset ( pll_areset_15 ),
.rx_reset ( rx_reset_15 ),
.rx_cda_reset ( rx_cda_reset_15 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_15 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_15
(
.tx_in (tbi_tx_d_muxed_15),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_15)
);
end
else
begin
assign txp_15 = 1'b0;
assign tbi_rx_clk_15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 16)
begin
assign gxb_pwrdn_in_sig[16] = gxb_pwrdn_in_16;
assign pcs_pwrdn_out_16 = pcs_pwrdn_out_sig[16];
end
else
begin
assign gxb_pwrdn_in_sig[16] = pcs_pwrdn_out_sig[16];
assign pcs_pwrdn_out_16 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 16)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_16(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_16), //INPUT
.dout(rev_loopback_ena_ref_clk_16));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_16 (
.reset_wclk(reset_tbi_rx_clk_16_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_16),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_16),
.tbi_tx_clk (tbi_tx_d_loopback_16)
);
assign tbi_tx_d_muxed_16 = rev_loopback_ena_ref_clk_16 ? tbi_tx_d_loopback_16: tbi_tx_d_flip_16;
end
else
begin
assign tbi_tx_d_muxed_16 = tbi_tx_d_flip_16;
// Unused wires
assign tbi_tx_d_loopback_16 = 10'd0;
assign rev_loopback_ena_ref_clk_16 = 1'b0;
end
assign tbi_tx_clk_16 = ref_clk;
assign tbi_rx_d_16 = tbi_rx_d_flip_16;
altera_tse_reset_synchronizer ch_16_reset_sync_0 (
.clk(tbi_rx_clk_16),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_16_int)
);
always @(posedge tbi_rx_clk_16 or posedge reset_tbi_rx_clk_16_int)
begin
if (reset_tbi_rx_clk_16_int == 1)
tbi_rx_d_flip_16 <= 0;
else
begin
if (rx_reset_sequence_done_16 == 1)
begin
tbi_rx_d_flip_16[0] <= tbi_rx_d_lvds_16[9];
tbi_rx_d_flip_16[1] <= tbi_rx_d_lvds_16[8];
tbi_rx_d_flip_16[2] <= tbi_rx_d_lvds_16[7];
tbi_rx_d_flip_16[3] <= tbi_rx_d_lvds_16[6];
tbi_rx_d_flip_16[4] <= tbi_rx_d_lvds_16[5];
tbi_rx_d_flip_16[5] <= tbi_rx_d_lvds_16[4];
tbi_rx_d_flip_16[6] <= tbi_rx_d_lvds_16[3];
tbi_rx_d_flip_16[7] <= tbi_rx_d_lvds_16[2];
tbi_rx_d_flip_16[8] <= tbi_rx_d_lvds_16[1];
tbi_rx_d_flip_16[9] <= tbi_rx_d_lvds_16[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_16 <= 0;
else
begin
tbi_tx_d_flip_16[0] <= tbi_tx_d_16[9];
tbi_tx_d_flip_16[1] <= tbi_tx_d_16[8];
tbi_tx_d_flip_16[2] <= tbi_tx_d_16[7];
tbi_tx_d_flip_16[3] <= tbi_tx_d_16[6];
tbi_tx_d_flip_16[4] <= tbi_tx_d_16[5];
tbi_tx_d_flip_16[5] <= tbi_tx_d_16[4];
tbi_tx_d_flip_16[6] <= tbi_tx_d_16[3];
tbi_tx_d_flip_16[7] <= tbi_tx_d_16[2];
tbi_tx_d_flip_16[8] <= tbi_tx_d_16[1];
tbi_tx_d_flip_16[9] <= tbi_tx_d_16[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_16
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_16 ),
.rx_locked ( rx_locked_16 ),
.rx_divfwdclk (tbi_rx_clk_16),
.rx_in (rxp_16),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_16),
.rx_outclock (),
.rx_reset (rx_reset_16)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_16
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_16 ),
.rx_channel_data_align ( rx_channel_data_align_16 ),
.rx_locked ( rx_locked_16 ),
.rx_divfwdclk (tbi_rx_clk_16),
.rx_in (rxp_16),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_16),
.rx_outclock (),
.rx_reset (rx_reset_16)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_16 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_16 ),
.rx_channel_data_align ( rx_channel_data_align_16 ),
.pll_areset ( pll_areset_16 ),
.rx_reset ( rx_reset_16 ),
.rx_cda_reset ( rx_cda_reset_16 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_16 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_16
(
.tx_in (tbi_tx_d_muxed_16),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_16)
);
end
else
begin
assign txp_16 = 1'b0;
assign tbi_rx_clk_16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 17)
begin
assign gxb_pwrdn_in_sig[17] = gxb_pwrdn_in_17;
assign pcs_pwrdn_out_17 = pcs_pwrdn_out_sig[17];
end
else
begin
assign gxb_pwrdn_in_sig[17] = pcs_pwrdn_out_sig[17];
assign pcs_pwrdn_out_17 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 17)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_17(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_17), //INPUT
.dout(rev_loopback_ena_ref_clk_17));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_17 (
.reset_wclk(reset_tbi_rx_clk_17_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_17),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_17),
.tbi_tx_clk (tbi_tx_d_loopback_17)
);
assign tbi_tx_d_muxed_17 = rev_loopback_ena_ref_clk_17 ? tbi_tx_d_loopback_17: tbi_tx_d_flip_17;
end
else
begin
assign tbi_tx_d_muxed_17 = tbi_tx_d_flip_17;
// Unused wires
assign tbi_tx_d_loopback_17 = 10'd0;
assign rev_loopback_ena_ref_clk_17 = 1'b0;
end
assign tbi_tx_clk_17 = ref_clk;
assign tbi_rx_d_17 = tbi_rx_d_flip_17;
altera_tse_reset_synchronizer ch_17_reset_sync_0 (
.clk(tbi_rx_clk_17),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_17_int)
);
always @(posedge tbi_rx_clk_17 or posedge reset_tbi_rx_clk_17_int)
begin
if (reset_tbi_rx_clk_17_int == 1)
tbi_rx_d_flip_17 <= 0;
else
begin
if (rx_reset_sequence_done_17 == 1)
begin
tbi_rx_d_flip_17[0] <= tbi_rx_d_lvds_17[9];
tbi_rx_d_flip_17[1] <= tbi_rx_d_lvds_17[8];
tbi_rx_d_flip_17[2] <= tbi_rx_d_lvds_17[7];
tbi_rx_d_flip_17[3] <= tbi_rx_d_lvds_17[6];
tbi_rx_d_flip_17[4] <= tbi_rx_d_lvds_17[5];
tbi_rx_d_flip_17[5] <= tbi_rx_d_lvds_17[4];
tbi_rx_d_flip_17[6] <= tbi_rx_d_lvds_17[3];
tbi_rx_d_flip_17[7] <= tbi_rx_d_lvds_17[2];
tbi_rx_d_flip_17[8] <= tbi_rx_d_lvds_17[1];
tbi_rx_d_flip_17[9] <= tbi_rx_d_lvds_17[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_17 <= 0;
else
begin
tbi_tx_d_flip_17[0] <= tbi_tx_d_17[9];
tbi_tx_d_flip_17[1] <= tbi_tx_d_17[8];
tbi_tx_d_flip_17[2] <= tbi_tx_d_17[7];
tbi_tx_d_flip_17[3] <= tbi_tx_d_17[6];
tbi_tx_d_flip_17[4] <= tbi_tx_d_17[5];
tbi_tx_d_flip_17[5] <= tbi_tx_d_17[4];
tbi_tx_d_flip_17[6] <= tbi_tx_d_17[3];
tbi_tx_d_flip_17[7] <= tbi_tx_d_17[2];
tbi_tx_d_flip_17[8] <= tbi_tx_d_17[1];
tbi_tx_d_flip_17[9] <= tbi_tx_d_17[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_17
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_17 ),
.rx_locked ( rx_locked_17 ),
.rx_divfwdclk (tbi_rx_clk_17),
.rx_in (rxp_17),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_17),
.rx_outclock (),
.rx_reset (rx_reset_17)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_17
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_17 ),
.rx_channel_data_align ( rx_channel_data_align_17 ),
.rx_locked ( rx_locked_17 ),
.rx_divfwdclk (tbi_rx_clk_17),
.rx_in (rxp_17),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_17),
.rx_outclock (),
.rx_reset (rx_reset_17)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_17 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_17 ),
.rx_channel_data_align ( rx_channel_data_align_17 ),
.pll_areset ( pll_areset_17 ),
.rx_reset ( rx_reset_17 ),
.rx_cda_reset ( rx_cda_reset_17 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_17 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_17
(
.tx_in (tbi_tx_d_muxed_17),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_17)
);
end
else
begin
assign txp_17 = 1'b0;
assign tbi_rx_clk_17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 18)
begin
assign gxb_pwrdn_in_sig[18] = gxb_pwrdn_in_18;
assign pcs_pwrdn_out_18 = pcs_pwrdn_out_sig[18];
end
else
begin
assign gxb_pwrdn_in_sig[18] = pcs_pwrdn_out_sig[18];
assign pcs_pwrdn_out_18 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 18)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_18(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_18), //INPUT
.dout(rev_loopback_ena_ref_clk_18));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_18 (
.reset_wclk(reset_tbi_rx_clk_18_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_18),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_18),
.tbi_tx_clk (tbi_tx_d_loopback_18)
);
assign tbi_tx_d_muxed_18 = rev_loopback_ena_ref_clk_18 ? tbi_tx_d_loopback_18: tbi_tx_d_flip_18;
end
else
begin
assign tbi_tx_d_muxed_18 = tbi_tx_d_flip_18;
// Unused wires
assign tbi_tx_d_loopback_18 = 10'd0;
assign rev_loopback_ena_ref_clk_18 = 1'b0;
end
assign tbi_tx_clk_18 = ref_clk;
assign tbi_rx_d_18 = tbi_rx_d_flip_18;
altera_tse_reset_synchronizer ch_18_reset_sync_0 (
.clk(tbi_rx_clk_18),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_18_int)
);
always @(posedge tbi_rx_clk_18 or posedge reset_tbi_rx_clk_18_int)
begin
if (reset_tbi_rx_clk_18_int == 1)
tbi_rx_d_flip_18 <= 0;
else
begin
if (rx_reset_sequence_done_18 == 1)
begin
tbi_rx_d_flip_18[0] <= tbi_rx_d_lvds_18[9];
tbi_rx_d_flip_18[1] <= tbi_rx_d_lvds_18[8];
tbi_rx_d_flip_18[2] <= tbi_rx_d_lvds_18[7];
tbi_rx_d_flip_18[3] <= tbi_rx_d_lvds_18[6];
tbi_rx_d_flip_18[4] <= tbi_rx_d_lvds_18[5];
tbi_rx_d_flip_18[5] <= tbi_rx_d_lvds_18[4];
tbi_rx_d_flip_18[6] <= tbi_rx_d_lvds_18[3];
tbi_rx_d_flip_18[7] <= tbi_rx_d_lvds_18[2];
tbi_rx_d_flip_18[8] <= tbi_rx_d_lvds_18[1];
tbi_rx_d_flip_18[9] <= tbi_rx_d_lvds_18[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_18 <= 0;
else
begin
tbi_tx_d_flip_18[0] <= tbi_tx_d_18[9];
tbi_tx_d_flip_18[1] <= tbi_tx_d_18[8];
tbi_tx_d_flip_18[2] <= tbi_tx_d_18[7];
tbi_tx_d_flip_18[3] <= tbi_tx_d_18[6];
tbi_tx_d_flip_18[4] <= tbi_tx_d_18[5];
tbi_tx_d_flip_18[5] <= tbi_tx_d_18[4];
tbi_tx_d_flip_18[6] <= tbi_tx_d_18[3];
tbi_tx_d_flip_18[7] <= tbi_tx_d_18[2];
tbi_tx_d_flip_18[8] <= tbi_tx_d_18[1];
tbi_tx_d_flip_18[9] <= tbi_tx_d_18[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_18
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_18 ),
.rx_locked ( rx_locked_18 ),
.rx_divfwdclk (tbi_rx_clk_18),
.rx_in (rxp_18),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_18),
.rx_outclock (),
.rx_reset (rx_reset_18)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_18
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_18 ),
.rx_channel_data_align ( rx_channel_data_align_18 ),
.rx_locked ( rx_locked_18 ),
.rx_divfwdclk (tbi_rx_clk_18),
.rx_in (rxp_18),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_18),
.rx_outclock (),
.rx_reset (rx_reset_18)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_18 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_18 ),
.rx_channel_data_align ( rx_channel_data_align_18 ),
.pll_areset ( pll_areset_18 ),
.rx_reset ( rx_reset_18 ),
.rx_cda_reset ( rx_cda_reset_18 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_18 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_18
(
.tx_in (tbi_tx_d_muxed_18),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_18)
);
end
else
begin
assign txp_18 = 1'b0;
assign tbi_rx_clk_18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 19)
begin
assign gxb_pwrdn_in_sig[19] = gxb_pwrdn_in_19;
assign pcs_pwrdn_out_19 = pcs_pwrdn_out_sig[19];
end
else
begin
assign gxb_pwrdn_in_sig[19] = pcs_pwrdn_out_sig[19];
assign pcs_pwrdn_out_19 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 19)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_19(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_19), //INPUT
.dout(rev_loopback_ena_ref_clk_19));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_19 (
.reset_wclk(reset_tbi_rx_clk_19_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_19),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_19),
.tbi_tx_clk (tbi_tx_d_loopback_19)
);
assign tbi_tx_d_muxed_19 = rev_loopback_ena_ref_clk_19 ? tbi_tx_d_loopback_19: tbi_tx_d_flip_19;
end
else
begin
assign tbi_tx_d_muxed_19 = tbi_tx_d_flip_19;
// Unused wires
assign tbi_tx_d_loopback_19 = 10'd0;
assign rev_loopback_ena_ref_clk_19 = 1'b0;
end
assign tbi_tx_clk_19 = ref_clk;
assign tbi_rx_d_19 = tbi_rx_d_flip_19;
altera_tse_reset_synchronizer ch_19_reset_sync_0 (
.clk(tbi_rx_clk_19),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_19_int)
);
always @(posedge tbi_rx_clk_19 or posedge reset_tbi_rx_clk_19_int)
begin
if (reset_tbi_rx_clk_19_int == 1)
tbi_rx_d_flip_19 <= 0;
else
begin
if (rx_reset_sequence_done_19 == 1)
begin
tbi_rx_d_flip_19[0] <= tbi_rx_d_lvds_19[9];
tbi_rx_d_flip_19[1] <= tbi_rx_d_lvds_19[8];
tbi_rx_d_flip_19[2] <= tbi_rx_d_lvds_19[7];
tbi_rx_d_flip_19[3] <= tbi_rx_d_lvds_19[6];
tbi_rx_d_flip_19[4] <= tbi_rx_d_lvds_19[5];
tbi_rx_d_flip_19[5] <= tbi_rx_d_lvds_19[4];
tbi_rx_d_flip_19[6] <= tbi_rx_d_lvds_19[3];
tbi_rx_d_flip_19[7] <= tbi_rx_d_lvds_19[2];
tbi_rx_d_flip_19[8] <= tbi_rx_d_lvds_19[1];
tbi_rx_d_flip_19[9] <= tbi_rx_d_lvds_19[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_19 <= 0;
else
begin
tbi_tx_d_flip_19[0] <= tbi_tx_d_19[9];
tbi_tx_d_flip_19[1] <= tbi_tx_d_19[8];
tbi_tx_d_flip_19[2] <= tbi_tx_d_19[7];
tbi_tx_d_flip_19[3] <= tbi_tx_d_19[6];
tbi_tx_d_flip_19[4] <= tbi_tx_d_19[5];
tbi_tx_d_flip_19[5] <= tbi_tx_d_19[4];
tbi_tx_d_flip_19[6] <= tbi_tx_d_19[3];
tbi_tx_d_flip_19[7] <= tbi_tx_d_19[2];
tbi_tx_d_flip_19[8] <= tbi_tx_d_19[1];
tbi_tx_d_flip_19[9] <= tbi_tx_d_19[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_19
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_19 ),
.rx_locked ( rx_locked_19 ),
.rx_divfwdclk (tbi_rx_clk_19),
.rx_in (rxp_19),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_19),
.rx_outclock (),
.rx_reset (rx_reset_19)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_19
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_19 ),
.rx_channel_data_align ( rx_channel_data_align_19 ),
.rx_locked ( rx_locked_19 ),
.rx_divfwdclk (tbi_rx_clk_19),
.rx_in (rxp_19),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_19),
.rx_outclock (),
.rx_reset (rx_reset_19)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_19 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_19 ),
.rx_channel_data_align ( rx_channel_data_align_19 ),
.pll_areset ( pll_areset_19 ),
.rx_reset ( rx_reset_19 ),
.rx_cda_reset ( rx_cda_reset_19 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_19 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_19
(
.tx_in (tbi_tx_d_muxed_19),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_19)
);
end
else
begin
assign txp_19 = 1'b0;
assign tbi_rx_clk_19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 20)
begin
assign gxb_pwrdn_in_sig[20] = gxb_pwrdn_in_20;
assign pcs_pwrdn_out_20 = pcs_pwrdn_out_sig[20];
end
else
begin
assign gxb_pwrdn_in_sig[20] = pcs_pwrdn_out_sig[20];
assign pcs_pwrdn_out_20 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 20)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_20(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_20), //INPUT
.dout(rev_loopback_ena_ref_clk_20));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_20 (
.reset_wclk(reset_tbi_rx_clk_20_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_20),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_20),
.tbi_tx_clk (tbi_tx_d_loopback_20)
);
assign tbi_tx_d_muxed_20 = rev_loopback_ena_ref_clk_20 ? tbi_tx_d_loopback_20: tbi_tx_d_flip_20;
end
else
begin
assign tbi_tx_d_muxed_20 = tbi_tx_d_flip_20;
// Unused wires
assign tbi_tx_d_loopback_20 = 10'd0;
assign rev_loopback_ena_ref_clk_20 = 1'b0;
end
assign tbi_tx_clk_20 = ref_clk;
assign tbi_rx_d_20 = tbi_rx_d_flip_20;
altera_tse_reset_synchronizer ch_20_reset_sync_0 (
.clk(tbi_rx_clk_20),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_20_int)
);
always @(posedge tbi_rx_clk_20 or posedge reset_tbi_rx_clk_20_int)
begin
if (reset_tbi_rx_clk_20_int == 1)
tbi_rx_d_flip_20 <= 0;
else
begin
if (rx_reset_sequence_done_20 == 1)
begin
tbi_rx_d_flip_20[0] <= tbi_rx_d_lvds_20[9];
tbi_rx_d_flip_20[1] <= tbi_rx_d_lvds_20[8];
tbi_rx_d_flip_20[2] <= tbi_rx_d_lvds_20[7];
tbi_rx_d_flip_20[3] <= tbi_rx_d_lvds_20[6];
tbi_rx_d_flip_20[4] <= tbi_rx_d_lvds_20[5];
tbi_rx_d_flip_20[5] <= tbi_rx_d_lvds_20[4];
tbi_rx_d_flip_20[6] <= tbi_rx_d_lvds_20[3];
tbi_rx_d_flip_20[7] <= tbi_rx_d_lvds_20[2];
tbi_rx_d_flip_20[8] <= tbi_rx_d_lvds_20[1];
tbi_rx_d_flip_20[9] <= tbi_rx_d_lvds_20[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_20 <= 0;
else
begin
tbi_tx_d_flip_20[0] <= tbi_tx_d_20[9];
tbi_tx_d_flip_20[1] <= tbi_tx_d_20[8];
tbi_tx_d_flip_20[2] <= tbi_tx_d_20[7];
tbi_tx_d_flip_20[3] <= tbi_tx_d_20[6];
tbi_tx_d_flip_20[4] <= tbi_tx_d_20[5];
tbi_tx_d_flip_20[5] <= tbi_tx_d_20[4];
tbi_tx_d_flip_20[6] <= tbi_tx_d_20[3];
tbi_tx_d_flip_20[7] <= tbi_tx_d_20[2];
tbi_tx_d_flip_20[8] <= tbi_tx_d_20[1];
tbi_tx_d_flip_20[9] <= tbi_tx_d_20[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_20
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_20 ),
.rx_locked ( rx_locked_20 ),
.rx_divfwdclk (tbi_rx_clk_20),
.rx_in (rxp_20),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_20),
.rx_outclock (),
.rx_reset (rx_reset_20)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_20
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_20 ),
.rx_channel_data_align ( rx_channel_data_align_20 ),
.rx_locked ( rx_locked_20 ),
.rx_divfwdclk (tbi_rx_clk_20),
.rx_in (rxp_20),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_20),
.rx_outclock (),
.rx_reset (rx_reset_20)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_20 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_20 ),
.rx_channel_data_align ( rx_channel_data_align_20 ),
.pll_areset ( pll_areset_20 ),
.rx_reset ( rx_reset_20 ),
.rx_cda_reset ( rx_cda_reset_20 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_20 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_20
(
.tx_in (tbi_tx_d_muxed_20),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_20)
);
end
else
begin
assign txp_20 = 1'b0;
assign tbi_rx_clk_20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 21)
begin
assign gxb_pwrdn_in_sig[21] = gxb_pwrdn_in_21;
assign pcs_pwrdn_out_21 = pcs_pwrdn_out_sig[21];
end
else
begin
assign gxb_pwrdn_in_sig[21] = pcs_pwrdn_out_sig[21];
assign pcs_pwrdn_out_21 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 21)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_21(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_21), //INPUT
.dout(rev_loopback_ena_ref_clk_21));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_21 (
.reset_wclk(reset_tbi_rx_clk_21_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_21),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_21),
.tbi_tx_clk (tbi_tx_d_loopback_21)
);
assign tbi_tx_d_muxed_21 = rev_loopback_ena_ref_clk_21 ? tbi_tx_d_loopback_21: tbi_tx_d_flip_21;
end
else
begin
assign tbi_tx_d_muxed_21 = tbi_tx_d_flip_21;
// Unused wires
assign tbi_tx_d_loopback_21 = 10'd0;
assign rev_loopback_ena_ref_clk_21 = 1'b0;
end
assign tbi_tx_clk_21 = ref_clk;
assign tbi_rx_d_21 = tbi_rx_d_flip_21;
altera_tse_reset_synchronizer ch_21_reset_sync_0 (
.clk(tbi_rx_clk_21),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_21_int)
);
always @(posedge tbi_rx_clk_21 or posedge reset_tbi_rx_clk_21_int)
begin
if (reset_tbi_rx_clk_21_int == 1)
tbi_rx_d_flip_21 <= 0;
else
begin
if (rx_reset_sequence_done_21 == 1)
begin
tbi_rx_d_flip_21[0] <= tbi_rx_d_lvds_21[9];
tbi_rx_d_flip_21[1] <= tbi_rx_d_lvds_21[8];
tbi_rx_d_flip_21[2] <= tbi_rx_d_lvds_21[7];
tbi_rx_d_flip_21[3] <= tbi_rx_d_lvds_21[6];
tbi_rx_d_flip_21[4] <= tbi_rx_d_lvds_21[5];
tbi_rx_d_flip_21[5] <= tbi_rx_d_lvds_21[4];
tbi_rx_d_flip_21[6] <= tbi_rx_d_lvds_21[3];
tbi_rx_d_flip_21[7] <= tbi_rx_d_lvds_21[2];
tbi_rx_d_flip_21[8] <= tbi_rx_d_lvds_21[1];
tbi_rx_d_flip_21[9] <= tbi_rx_d_lvds_21[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_21 <= 0;
else
begin
tbi_tx_d_flip_21[0] <= tbi_tx_d_21[9];
tbi_tx_d_flip_21[1] <= tbi_tx_d_21[8];
tbi_tx_d_flip_21[2] <= tbi_tx_d_21[7];
tbi_tx_d_flip_21[3] <= tbi_tx_d_21[6];
tbi_tx_d_flip_21[4] <= tbi_tx_d_21[5];
tbi_tx_d_flip_21[5] <= tbi_tx_d_21[4];
tbi_tx_d_flip_21[6] <= tbi_tx_d_21[3];
tbi_tx_d_flip_21[7] <= tbi_tx_d_21[2];
tbi_tx_d_flip_21[8] <= tbi_tx_d_21[1];
tbi_tx_d_flip_21[9] <= tbi_tx_d_21[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_21
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_21 ),
.rx_locked ( rx_locked_21 ),
.rx_divfwdclk (tbi_rx_clk_21),
.rx_in (rxp_21),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_21),
.rx_outclock (),
.rx_reset (rx_reset_21)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_21
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_21 ),
.rx_channel_data_align ( rx_channel_data_align_21 ),
.rx_locked ( rx_locked_21 ),
.rx_divfwdclk (tbi_rx_clk_21),
.rx_in (rxp_21),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_21),
.rx_outclock (),
.rx_reset (rx_reset_21)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_21 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_21 ),
.rx_channel_data_align ( rx_channel_data_align_21 ),
.pll_areset ( pll_areset_21 ),
.rx_reset ( rx_reset_21 ),
.rx_cda_reset ( rx_cda_reset_21 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_21 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_21
(
.tx_in (tbi_tx_d_muxed_21),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_21)
);
end
else
begin
assign txp_21 = 1'b0;
assign tbi_rx_clk_21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 22)
begin
assign gxb_pwrdn_in_sig[22] = gxb_pwrdn_in_22;
assign pcs_pwrdn_out_22 = pcs_pwrdn_out_sig[22];
end
else
begin
assign gxb_pwrdn_in_sig[22] = pcs_pwrdn_out_sig[22];
assign pcs_pwrdn_out_22 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 22)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_22(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_22), //INPUT
.dout(rev_loopback_ena_ref_clk_22));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_22 (
.reset_wclk(reset_tbi_rx_clk_22_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_22),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_22),
.tbi_tx_clk (tbi_tx_d_loopback_22)
);
assign tbi_tx_d_muxed_22 = rev_loopback_ena_ref_clk_22 ? tbi_tx_d_loopback_22: tbi_tx_d_flip_22;
end
else
begin
assign tbi_tx_d_muxed_22 = tbi_tx_d_flip_22;
// Unused wires
assign tbi_tx_d_loopback_22 = 10'd0;
assign rev_loopback_ena_ref_clk_22 = 1'b0;
end
assign tbi_tx_clk_22 = ref_clk;
assign tbi_rx_d_22 = tbi_rx_d_flip_22;
altera_tse_reset_synchronizer ch_22_reset_sync_0 (
.clk(tbi_rx_clk_22),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_22_int)
);
always @(posedge tbi_rx_clk_22 or posedge reset_tbi_rx_clk_22_int)
begin
if (reset_tbi_rx_clk_22_int == 1)
tbi_rx_d_flip_22 <= 0;
else
begin
if (rx_reset_sequence_done_22 == 1)
begin
tbi_rx_d_flip_22[0] <= tbi_rx_d_lvds_22[9];
tbi_rx_d_flip_22[1] <= tbi_rx_d_lvds_22[8];
tbi_rx_d_flip_22[2] <= tbi_rx_d_lvds_22[7];
tbi_rx_d_flip_22[3] <= tbi_rx_d_lvds_22[6];
tbi_rx_d_flip_22[4] <= tbi_rx_d_lvds_22[5];
tbi_rx_d_flip_22[5] <= tbi_rx_d_lvds_22[4];
tbi_rx_d_flip_22[6] <= tbi_rx_d_lvds_22[3];
tbi_rx_d_flip_22[7] <= tbi_rx_d_lvds_22[2];
tbi_rx_d_flip_22[8] <= tbi_rx_d_lvds_22[1];
tbi_rx_d_flip_22[9] <= tbi_rx_d_lvds_22[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_22 <= 0;
else
begin
tbi_tx_d_flip_22[0] <= tbi_tx_d_22[9];
tbi_tx_d_flip_22[1] <= tbi_tx_d_22[8];
tbi_tx_d_flip_22[2] <= tbi_tx_d_22[7];
tbi_tx_d_flip_22[3] <= tbi_tx_d_22[6];
tbi_tx_d_flip_22[4] <= tbi_tx_d_22[5];
tbi_tx_d_flip_22[5] <= tbi_tx_d_22[4];
tbi_tx_d_flip_22[6] <= tbi_tx_d_22[3];
tbi_tx_d_flip_22[7] <= tbi_tx_d_22[2];
tbi_tx_d_flip_22[8] <= tbi_tx_d_22[1];
tbi_tx_d_flip_22[9] <= tbi_tx_d_22[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_22
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_22 ),
.rx_locked ( rx_locked_22 ),
.rx_divfwdclk (tbi_rx_clk_22),
.rx_in (rxp_22),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_22),
.rx_outclock (),
.rx_reset (rx_reset_22)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_22
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_22 ),
.rx_channel_data_align ( rx_channel_data_align_22 ),
.rx_locked ( rx_locked_22 ),
.rx_divfwdclk (tbi_rx_clk_22),
.rx_in (rxp_22),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_22),
.rx_outclock (),
.rx_reset (rx_reset_22)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_22 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_22 ),
.rx_channel_data_align ( rx_channel_data_align_22 ),
.pll_areset ( pll_areset_22 ),
.rx_reset ( rx_reset_22 ),
.rx_cda_reset ( rx_cda_reset_22 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_22 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_22
(
.tx_in (tbi_tx_d_muxed_22),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_22)
);
end
else
begin
assign txp_22 = 1'b0;
assign tbi_rx_clk_22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 23)
begin
assign gxb_pwrdn_in_sig[23] = gxb_pwrdn_in_23;
assign pcs_pwrdn_out_23 = pcs_pwrdn_out_sig[23];
end
else
begin
assign gxb_pwrdn_in_sig[23] = pcs_pwrdn_out_sig[23];
assign pcs_pwrdn_out_23 = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 23)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX_23(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena_23), //INPUT
.dout(rev_loopback_ena_ref_clk_23));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK_23 (
.reset_wclk(reset_tbi_rx_clk_23_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk_23),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds_23),
.tbi_tx_clk (tbi_tx_d_loopback_23)
);
assign tbi_tx_d_muxed_23 = rev_loopback_ena_ref_clk_23 ? tbi_tx_d_loopback_23: tbi_tx_d_flip_23;
end
else
begin
assign tbi_tx_d_muxed_23 = tbi_tx_d_flip_23;
// Unused wires
assign tbi_tx_d_loopback_23 = 10'd0;
assign rev_loopback_ena_ref_clk_23 = 1'b0;
end
assign tbi_tx_clk_23 = ref_clk;
assign tbi_rx_d_23 = tbi_rx_d_flip_23;
altera_tse_reset_synchronizer ch_23_reset_sync_0 (
.clk(tbi_rx_clk_23),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_23_int)
);
always @(posedge tbi_rx_clk_23 or posedge reset_tbi_rx_clk_23_int)
begin
if (reset_tbi_rx_clk_23_int == 1)
tbi_rx_d_flip_23 <= 0;
else
begin
if (rx_reset_sequence_done_23 == 1)
begin
tbi_rx_d_flip_23[0] <= tbi_rx_d_lvds_23[9];
tbi_rx_d_flip_23[1] <= tbi_rx_d_lvds_23[8];
tbi_rx_d_flip_23[2] <= tbi_rx_d_lvds_23[7];
tbi_rx_d_flip_23[3] <= tbi_rx_d_lvds_23[6];
tbi_rx_d_flip_23[4] <= tbi_rx_d_lvds_23[5];
tbi_rx_d_flip_23[5] <= tbi_rx_d_lvds_23[4];
tbi_rx_d_flip_23[6] <= tbi_rx_d_lvds_23[3];
tbi_rx_d_flip_23[7] <= tbi_rx_d_lvds_23[2];
tbi_rx_d_flip_23[8] <= tbi_rx_d_lvds_23[1];
tbi_rx_d_flip_23[9] <= tbi_rx_d_lvds_23[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip_23 <= 0;
else
begin
tbi_tx_d_flip_23[0] <= tbi_tx_d_23[9];
tbi_tx_d_flip_23[1] <= tbi_tx_d_23[8];
tbi_tx_d_flip_23[2] <= tbi_tx_d_23[7];
tbi_tx_d_flip_23[3] <= tbi_tx_d_23[6];
tbi_tx_d_flip_23[4] <= tbi_tx_d_23[5];
tbi_tx_d_flip_23[5] <= tbi_tx_d_23[4];
tbi_tx_d_flip_23[6] <= tbi_tx_d_23[3];
tbi_tx_d_flip_23[7] <= tbi_tx_d_23[2];
tbi_tx_d_flip_23[8] <= tbi_tx_d_23[1];
tbi_tx_d_flip_23[9] <= tbi_tx_d_23[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx_23
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align_23 ),
.rx_locked ( rx_locked_23 ),
.rx_divfwdclk (tbi_rx_clk_23),
.rx_in (rxp_23),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_23),
.rx_outclock (),
.rx_reset (rx_reset_23)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_23
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset_23 ),
.rx_channel_data_align ( rx_channel_data_align_23 ),
.rx_locked ( rx_locked_23 ),
.rx_divfwdclk (tbi_rx_clk_23),
.rx_in (rxp_23),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds_23),
.rx_outclock (),
.rx_reset (rx_reset_23)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer_23 (
.clk ( ref_clk ),
.reset ( reset_ref_clk_int ),
.rx_locked ( rx_locked_23 ),
.rx_channel_data_align ( rx_channel_data_align_23 ),
.pll_areset ( pll_areset_23 ),
.rx_reset ( rx_reset_23 ),
.rx_cda_reset ( rx_cda_reset_23 ),
.rx_reset_sequence_done ( rx_reset_sequence_done_23 )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_23
(
.tx_in (tbi_tx_d_muxed_23),
.tx_inclock (ref_clk),
.pll_areset ( reset ),
.tx_out (txp_23)
);
end
else
begin
assign txp_23 = 1'b0;
assign tbi_rx_clk_23 = 1'b0;
end
endgenerate
endmodule // module altera_tse_multi_mac_pcs_pma
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF;SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" } *)
module altera_tse_multi_mac_pcs_pma_gige
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8,
//IEEE1588 code
parameter ENABLE_TIMESTAMPING = 0, // To enable time stamping logic
parameter ENABLE_PTP_1STEP = 0, // To enable time 1 step clock PTP
parameter TSTAMP_FP_WIDTH = 4 // Finger print width associated to the timestamp request
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
input wire pcs_phase_measure_clk, // Measurement clock for PHY FIFO phase
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
input wire gxb_pwrdn_in_0, // Powerdown signal to GXB
output wire pcs_pwrdn_out_0, // Powerdown Enable from PCS
output wire rx_recovclkout_0, // Receiver Recovered Clock
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_0, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_0, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_0, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_0, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_0, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_0, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_0, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_0, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_0, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_0, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_0, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_0, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_0, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_0, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_0, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_0, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_0, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_0, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_0, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_0, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_0, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_0, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_0, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_0, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_0, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_0, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_0, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_0, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_0, // Clock for reconfiguration block
input wire reconfig_busy_0, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
input wire gxb_pwrdn_in_1, // Powerdown signal to GXB
output wire pcs_pwrdn_out_1, // Powerdown Enable from PCS
output wire rx_recovclkout_1, // Receiver Recovered Clock
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_1, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_1, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_1, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_1, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_1, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_1, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_1, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_1, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_1, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_1, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_1, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_1, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_1, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_1, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_1, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_1, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_1, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_1, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_1, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_1, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_1, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_1, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_1, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_1, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_1, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_1, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_1, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_1, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_1, // Clock for reconfiguration block
input wire reconfig_busy_1, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
input wire gxb_pwrdn_in_2, // Powerdown signal to GXB
output wire pcs_pwrdn_out_2, // Powerdown Enable from PCS
output wire rx_recovclkout_2, // Receiver Recovered Clock
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_2, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_2, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_2, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_2, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_2, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_2, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_2, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_2, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_2, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_2, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_2, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_2, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_2, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_2, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_2, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_2, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_2, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_2, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_2, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_2, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_2, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_2, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_2, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_2, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_2, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_2, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_2, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_2, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_2, // Clock for reconfiguration block
input wire reconfig_busy_2, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
input wire gxb_pwrdn_in_3, // Powerdown signal to GXB
output wire pcs_pwrdn_out_3, // Powerdown Enable from PCS
output wire rx_recovclkout_3, // Receiver Recovered Clock
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_3, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_3, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_3, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_3, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_3, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_3, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_3, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_3, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_3, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_3, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_3, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_3, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_3, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_3, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_3, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_3, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_3, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_3, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_3, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_3, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_3, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_3, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_3, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_3, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_3, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_3, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_3, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_3, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_3, // Clock for reconfiguration block
input wire reconfig_busy_3, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
input wire gxb_pwrdn_in_4, // Powerdown signal to GXB
output wire pcs_pwrdn_out_4, // Powerdown Enable from PCS
output wire rx_recovclkout_4, // Receiver Recovered Clock
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_4, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_4, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_4, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_4, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_4, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_4, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_4, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_4, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_4, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_4, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_4, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_4, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_4, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_4, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_4, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_4, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_4, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_4, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_4, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_4, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_4, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_4, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_4, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_4, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_4, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_4, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_4, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_4, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_4, // Clock for reconfiguration block
input wire reconfig_busy_4, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
input wire gxb_pwrdn_in_5, // Powerdown signal to GXB
output wire pcs_pwrdn_out_5, // Powerdown Enable from PCS
output wire rx_recovclkout_5, // Receiver Recovered Clock
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_5, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_5, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_5, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_5, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_5, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_5, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_5, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_5, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_5, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_5, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_5, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_5, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_5, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_5, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_5, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_5, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_5, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_5, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_5, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_5, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_5, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_5, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_5, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_5, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_5, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_5, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_5, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_5, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_5, // Clock for reconfiguration block
input wire reconfig_busy_5, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
input wire gxb_pwrdn_in_6, // Powerdown signal to GXB
output wire pcs_pwrdn_out_6, // Powerdown Enable from PCS
output wire rx_recovclkout_6, // Receiver Recovered Clock
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_6, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_6, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_6, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_6, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_6, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_6, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_6, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_6, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_6, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_6, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_6, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_6, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_6, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_6, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_6, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_6, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_6, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_6, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_6, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_6, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_6, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_6, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_6, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_6, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_6, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_6, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_6, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_6, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_6, // Clock for reconfiguration block
input wire reconfig_busy_6, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
input wire gxb_pwrdn_in_7, // Powerdown signal to GXB
output wire pcs_pwrdn_out_7, // Powerdown Enable from PCS
output wire rx_recovclkout_7, // Receiver Recovered Clock
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_7, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_7, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_7, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_7, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_7, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_7, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_7, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_7, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_7, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_7, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_7, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_7, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_7, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_7, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_7, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_7, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_7, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_7, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_7, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_7, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_7, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_7, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_7, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_7, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_7, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_7, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_7, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_7, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_7, // Clock for reconfiguration block
input wire reconfig_busy_7, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
input wire gxb_pwrdn_in_8, // Powerdown signal to GXB
output wire pcs_pwrdn_out_8, // Powerdown Enable from PCS
output wire rx_recovclkout_8, // Receiver Recovered Clock
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_8, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_8, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_8, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_8, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_8, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_8, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_8, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_8, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_8, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_8, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_8, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_8, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_8, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_8, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_8, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_8, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_8, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_8, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_8, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_8, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_8, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_8, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_8, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_8, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_8, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_8, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_8, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_8, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_8, // Clock for reconfiguration block
input wire reconfig_busy_8, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
input wire gxb_pwrdn_in_9, // Powerdown signal to GXB
output wire pcs_pwrdn_out_9, // Powerdown Enable from PCS
output wire rx_recovclkout_9, // Receiver Recovered Clock
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_9, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_9, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_9, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_9, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_9, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_9, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_9, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_9, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_9, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_9, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_9, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_9, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_9, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_9, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_9, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_9, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_9, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_9, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_9, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_9, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_9, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_9, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_9, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_9, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_9, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_9, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_9, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_9, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_9, // Clock for reconfiguration block
input wire reconfig_busy_9, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
input wire gxb_pwrdn_in_10, // Powerdown signal to GXB
output wire pcs_pwrdn_out_10, // Powerdown Enable from PCS
output wire rx_recovclkout_10, // Receiver Recovered Clock
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_10, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_10, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_10, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_10, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_10, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_10, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_10, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_10, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_10, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_10, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_10, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_10, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_10, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_10, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_10, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_10, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_10, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_10, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_10, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_10, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_10, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_10, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_10, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_10, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_10, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_10, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_10, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_10, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_10, // Clock for reconfiguration block
input wire reconfig_busy_10, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
input wire gxb_pwrdn_in_11, // Powerdown signal to GXB
output wire pcs_pwrdn_out_11, // Powerdown Enable from PCS
output wire rx_recovclkout_11, // Receiver Recovered Clock
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_11, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_11, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_11, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_11, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_11, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_11, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_11, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_11, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_11, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_11, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_11, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_11, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_11, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_11, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_11, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_11, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_11, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_11, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_11, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_11, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_11, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_11, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_11, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_11, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_11, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_11, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_11, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_11, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_11, // Clock for reconfiguration block
input wire reconfig_busy_11, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
input wire gxb_pwrdn_in_12, // Powerdown signal to GXB
output wire pcs_pwrdn_out_12, // Powerdown Enable from PCS
output wire rx_recovclkout_12, // Receiver Recovered Clock
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_12, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_12, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_12, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_12, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_12, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_12, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_12, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_12, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_12, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_12, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_12, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_12, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_12, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_12, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_12, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_12, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_12, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_12, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_12, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_12, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_12, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_12, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_12, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_12, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_12, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_12, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_12, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_12, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_12, // Clock for reconfiguration block
input wire reconfig_busy_12, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
input wire gxb_pwrdn_in_13, // Powerdown signal to GXB
output wire pcs_pwrdn_out_13, // Powerdown Enable from PCS
output wire rx_recovclkout_13, // Receiver Recovered Clock
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_13, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_13, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_13, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_13, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_13, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_13, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_13, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_13, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_13, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_13, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_13, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_13, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_13, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_13, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_13, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_13, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_13, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_13, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_13, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_13, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_13, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_13, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_13, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_13, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_13, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_13, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_13, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_13, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_13, // Clock for reconfiguration block
input wire reconfig_busy_13, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
input wire gxb_pwrdn_in_14, // Powerdown signal to GXB
output wire pcs_pwrdn_out_14, // Powerdown Enable from PCS
output wire rx_recovclkout_14, // Receiver Recovered Clock
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_14, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_14, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_14, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_14, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_14, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_14, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_14, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_14, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_14, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_14, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_14, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_14, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_14, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_14, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_14, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_14, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_14, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_14, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_14, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_14, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_14, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_14, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_14, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_14, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_14, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_14, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_14, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_14, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_14, // Clock for reconfiguration block
input wire reconfig_busy_14, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
input wire gxb_pwrdn_in_15, // Powerdown signal to GXB
output wire pcs_pwrdn_out_15, // Powerdown Enable from PCS
output wire rx_recovclkout_15, // Receiver Recovered Clock
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_15, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_15, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_15, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_15, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_15, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_15, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_15, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_15, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_15, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_15, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_15, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_15, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_15, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_15, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_15, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_15, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_15, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_15, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_15, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_15, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_15, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_15, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_15, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_15, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_15, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_15, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_15, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_15, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_15, // Clock for reconfiguration block
input wire reconfig_busy_15, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
input wire gxb_pwrdn_in_16, // Powerdown signal to GXB
output wire pcs_pwrdn_out_16, // Powerdown Enable from PCS
output wire rx_recovclkout_16, // Receiver Recovered Clock
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_16, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_16, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_16, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_16, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_16, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_16, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_16, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_16, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_16, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_16, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_16, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_16, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_16, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_16, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_16, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_16, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_16, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_16, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_16, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_16, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_16, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_16, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_16, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_16, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_16, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_16, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_16, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_16, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_16, // Clock for reconfiguration block
input wire reconfig_busy_16, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
input wire gxb_pwrdn_in_17, // Powerdown signal to GXB
output wire pcs_pwrdn_out_17, // Powerdown Enable from PCS
output wire rx_recovclkout_17, // Receiver Recovered Clock
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_17, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_17, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_17, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_17, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_17, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_17, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_17, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_17, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_17, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_17, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_17, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_17, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_17, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_17, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_17, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_17, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_17, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_17, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_17, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_17, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_17, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_17, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_17, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_17, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_17, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_17, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_17, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_17, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_17, // Clock for reconfiguration block
input wire reconfig_busy_17, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
input wire gxb_pwrdn_in_18, // Powerdown signal to GXB
output wire pcs_pwrdn_out_18, // Powerdown Enable from PCS
output wire rx_recovclkout_18, // Receiver Recovered Clock
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_18, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_18, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_18, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_18, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_18, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_18, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_18, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_18, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_18, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_18, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_18, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_18, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_18, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_18, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_18, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_18, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_18, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_18, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_18, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_18, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_18, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_18, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_18, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_18, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_18, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_18, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_18, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_18, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_18, // Clock for reconfiguration block
input wire reconfig_busy_18, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
input wire gxb_pwrdn_in_19, // Powerdown signal to GXB
output wire pcs_pwrdn_out_19, // Powerdown Enable from PCS
output wire rx_recovclkout_19, // Receiver Recovered Clock
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_19, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_19, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_19, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_19, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_19, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_19, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_19, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_19, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_19, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_19, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_19, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_19, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_19, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_19, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_19, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_19, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_19, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_19, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_19, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_19, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_19, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_19, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_19, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_19, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_19, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_19, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_19, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_19, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_19, // Clock for reconfiguration block
input wire reconfig_busy_19, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
input wire gxb_pwrdn_in_20, // Powerdown signal to GXB
output wire pcs_pwrdn_out_20, // Powerdown Enable from PCS
output wire rx_recovclkout_20, // Receiver Recovered Clock
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_20, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_20, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_20, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_20, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_20, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_20, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_20, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_20, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_20, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_20, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_20, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_20, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_20, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_20, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_20, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_20, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_20, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_20, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_20, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_20, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_20, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_20, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_20, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_20, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_20, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_20, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_20, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_20, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_20, // Clock for reconfiguration block
input wire reconfig_busy_20, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
input wire gxb_pwrdn_in_21, // Powerdown signal to GXB
output wire pcs_pwrdn_out_21, // Powerdown Enable from PCS
output wire rx_recovclkout_21, // Receiver Recovered Clock
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_21, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_21, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_21, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_21, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_21, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_21, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_21, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_21, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_21, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_21, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_21, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_21, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_21, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_21, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_21, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_21, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_21, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_21, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_21, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_21, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_21, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_21, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_21, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_21, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_21, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_21, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_21, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_21, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_21, // Clock for reconfiguration block
input wire reconfig_busy_21, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
input wire gxb_pwrdn_in_22, // Powerdown signal to GXB
output wire pcs_pwrdn_out_22, // Powerdown Enable from PCS
output wire rx_recovclkout_22, // Receiver Recovered Clock
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_22, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_22, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_22, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_22, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_22, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_22, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_22, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_22, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_22, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_22, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_22, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_22, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_22, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_22, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_22, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_22, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_22, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_22, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_22, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_22, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_22, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_22, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_22, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_22, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_22, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_22, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_22, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_22, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_22, // Clock for reconfiguration block
input wire reconfig_busy_22, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
input wire gxb_pwrdn_in_23, // Powerdown signal to GXB
output wire pcs_pwrdn_out_23, // Powerdown Enable from PCS
output wire rx_recovclkout_23, // Receiver Recovered Clock
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23, // Wake Up Request
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_23, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_23, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_23, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_23, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_23, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_23, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_23, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_23, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_23, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_23, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_23, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_23, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_23, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_23, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_23, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_23, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_23, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_23, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_23, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_23, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_23, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_23, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_23, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_23, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_23, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_23, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_23, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_23, // 64 bit Time of Day
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_23, // Clock for reconfiguration block
input wire reconfig_busy_23, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_23); // Signals from the gxb block to the reconfig block
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire gige_pma_reset;
wire [23:0] led_char_err_gx;
wire [23:0] link_status;
//wire [23:0] pcs_clk;
wire tx_pcs_clk_c0;
wire tx_pcs_clk_c1;
wire tx_pcs_clk_c2;
wire tx_pcs_clk_c3;
wire tx_pcs_clk_c4;
wire tx_pcs_clk_c5;
wire tx_pcs_clk_c6;
wire tx_pcs_clk_c7;
wire tx_pcs_clk_c8;
wire tx_pcs_clk_c9;
wire tx_pcs_clk_c10;
wire tx_pcs_clk_c11;
wire tx_pcs_clk_c12;
wire tx_pcs_clk_c13;
wire tx_pcs_clk_c14;
wire tx_pcs_clk_c15;
wire tx_pcs_clk_c16;
wire tx_pcs_clk_c17;
wire tx_pcs_clk_c18;
wire tx_pcs_clk_c19;
wire tx_pcs_clk_c20;
wire tx_pcs_clk_c21;
wire tx_pcs_clk_c22;
wire tx_pcs_clk_c23;
wire rx_pcs_clk_c0;
wire rx_pcs_clk_c1;
wire rx_pcs_clk_c2;
wire rx_pcs_clk_c3;
wire rx_pcs_clk_c4;
wire rx_pcs_clk_c5;
wire rx_pcs_clk_c6;
wire rx_pcs_clk_c7;
wire rx_pcs_clk_c8;
wire rx_pcs_clk_c9;
wire rx_pcs_clk_c10;
wire rx_pcs_clk_c11;
wire rx_pcs_clk_c12;
wire rx_pcs_clk_c13;
wire rx_pcs_clk_c14;
wire rx_pcs_clk_c15;
wire rx_pcs_clk_c16;
wire rx_pcs_clk_c17;
wire rx_pcs_clk_c18;
wire rx_pcs_clk_c19;
wire rx_pcs_clk_c20;
wire rx_pcs_clk_c21;
wire rx_pcs_clk_c22;
wire rx_pcs_clk_c23;
wire [23:0] rx_char_err_gx;
wire [23:0] rx_disp_err;
wire [23:0] rx_syncstatus;
wire [23:0] rx_runlengthviolation;
wire [23:0] rx_patterndetect;
wire [23:0] rx_runningdisp;
wire [23:0] rx_rmfifodatadeleted;
wire [23:0] rx_rmfifodatainserted;
wire [23:0] pcs_rx_rmfifodatadeleted;
wire [23:0] pcs_rx_rmfifodatainserted;
wire [23:0] pcs_rx_carrierdetected;
wire rx_kchar_0;
wire [7:0] rx_frame_0;
wire pcs_rx_kchar_0;
wire [7:0] pcs_rx_frame_0;
wire tx_kchar_0;
wire [7:0] tx_frame_0;
wire rx_kchar_1;
wire [7:0] rx_frame_1;
wire pcs_rx_kchar_1;
wire [7:0] pcs_rx_frame_1;
wire tx_kchar_1;
wire [7:0] tx_frame_1;
wire rx_kchar_2;
wire [7:0] rx_frame_2;
wire pcs_rx_kchar_2;
wire [7:0] pcs_rx_frame_2;
wire tx_kchar_2;
wire [7:0] tx_frame_2;
wire rx_kchar_3;
wire [7:0] rx_frame_3;
wire pcs_rx_kchar_3;
wire [7:0] pcs_rx_frame_3;
wire tx_kchar_3;
wire [7:0] tx_frame_3;
wire rx_kchar_4;
wire [7:0] rx_frame_4;
wire pcs_rx_kchar_4;
wire [7:0] pcs_rx_frame_4;
wire tx_kchar_4;
wire [7:0] tx_frame_4;
wire rx_kchar_5;
wire [7:0] rx_frame_5;
wire pcs_rx_kchar_5;
wire [7:0] pcs_rx_frame_5;
wire tx_kchar_5;
wire [7:0] tx_frame_5;
wire rx_kchar_6;
wire [7:0] rx_frame_6;
wire pcs_rx_kchar_6;
wire [7:0] pcs_rx_frame_6;
wire tx_kchar_6;
wire [7:0] tx_frame_6;
wire rx_kchar_7;
wire [7:0] rx_frame_7;
wire pcs_rx_kchar_7;
wire [7:0] pcs_rx_frame_7;
wire tx_kchar_7;
wire [7:0] tx_frame_7;
wire rx_kchar_8;
wire [7:0] rx_frame_8;
wire pcs_rx_kchar_8;
wire [7:0] pcs_rx_frame_8;
wire tx_kchar_8;
wire [7:0] tx_frame_8;
wire rx_kchar_9;
wire [7:0] rx_frame_9;
wire pcs_rx_kchar_9;
wire [7:0] pcs_rx_frame_9;
wire tx_kchar_9;
wire [7:0] tx_frame_9;
wire rx_kchar_10;
wire [7:0] rx_frame_10;
wire pcs_rx_kchar_10;
wire [7:0] pcs_rx_frame_10;
wire tx_kchar_10;
wire [7:0] tx_frame_10;
wire rx_kchar_11;
wire [7:0] rx_frame_11;
wire pcs_rx_kchar_11;
wire [7:0] pcs_rx_frame_11;
wire tx_kchar_11;
wire [7:0] tx_frame_11;
wire rx_kchar_12;
wire [7:0] rx_frame_12;
wire pcs_rx_kchar_12;
wire [7:0] pcs_rx_frame_12;
wire tx_kchar_12;
wire [7:0] tx_frame_12;
wire rx_kchar_13;
wire [7:0] rx_frame_13;
wire pcs_rx_kchar_13;
wire [7:0] pcs_rx_frame_13;
wire tx_kchar_13;
wire [7:0] tx_frame_13;
wire rx_kchar_14;
wire [7:0] rx_frame_14;
wire pcs_rx_kchar_14;
wire [7:0] pcs_rx_frame_14;
wire tx_kchar_14;
wire [7:0] tx_frame_14;
wire rx_kchar_15;
wire [7:0] rx_frame_15;
wire pcs_rx_kchar_15;
wire [7:0] pcs_rx_frame_15;
wire tx_kchar_15;
wire [7:0] tx_frame_15;
wire rx_kchar_16;
wire [7:0] rx_frame_16;
wire pcs_rx_kchar_16;
wire [7:0] pcs_rx_frame_16;
wire tx_kchar_16;
wire [7:0] tx_frame_16;
wire rx_kchar_17;
wire [7:0] rx_frame_17;
wire pcs_rx_kchar_17;
wire [7:0] pcs_rx_frame_17;
wire tx_kchar_17;
wire [7:0] tx_frame_17;
wire rx_kchar_18;
wire [7:0] rx_frame_18;
wire pcs_rx_kchar_18;
wire [7:0] pcs_rx_frame_18;
wire tx_kchar_18;
wire [7:0] tx_frame_18;
wire rx_kchar_19;
wire [7:0] rx_frame_19;
wire pcs_rx_kchar_19;
wire [7:0] pcs_rx_frame_19;
wire tx_kchar_19;
wire [7:0] tx_frame_19;
wire rx_kchar_20;
wire [7:0] rx_frame_20;
wire pcs_rx_kchar_20;
wire [7:0] pcs_rx_frame_20;
wire tx_kchar_20;
wire [7:0] tx_frame_20;
wire rx_kchar_21;
wire [7:0] rx_frame_21;
wire pcs_rx_kchar_21;
wire [7:0] pcs_rx_frame_21;
wire tx_kchar_21;
wire [7:0] tx_frame_21;
wire rx_kchar_22;
wire [7:0] rx_frame_22;
wire pcs_rx_kchar_22;
wire [7:0] pcs_rx_frame_22;
wire tx_kchar_22;
wire [7:0] tx_frame_22;
wire rx_kchar_23;
wire [7:0] rx_frame_23;
wire pcs_rx_kchar_23;
wire [7:0] pcs_rx_frame_23;
wire tx_kchar_23;
wire [7:0] tx_frame_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
wire reset_rx_pcs_clk_c0_int;
wire reset_rx_pcs_clk_c1_int;
wire reset_rx_pcs_clk_c2_int;
wire reset_rx_pcs_clk_c3_int;
wire reset_rx_pcs_clk_c4_int;
wire reset_rx_pcs_clk_c5_int;
wire reset_rx_pcs_clk_c6_int;
wire reset_rx_pcs_clk_c7_int;
wire reset_rx_pcs_clk_c8_int;
wire reset_rx_pcs_clk_c9_int;
wire reset_rx_pcs_clk_c10_int;
wire reset_rx_pcs_clk_c11_int;
wire reset_rx_pcs_clk_c12_int;
wire reset_rx_pcs_clk_c13_int;
wire reset_rx_pcs_clk_c14_int;
wire reset_rx_pcs_clk_c15_int;
wire reset_rx_pcs_clk_c16_int;
wire reset_rx_pcs_clk_c17_int;
wire reset_rx_pcs_clk_c18_int;
wire reset_rx_pcs_clk_c19_int;
wire reset_rx_pcs_clk_c20_int;
wire reset_rx_pcs_clk_c21_int;
wire reset_rx_pcs_clk_c22_int;
wire reset_rx_pcs_clk_c23_int;
wire pll_powerdown_sqcnr_0,tx_digitalreset_sqcnr_0,rx_analogreset_sqcnr_0,rx_digitalreset_sqcnr_0,gxb_powerdown_sqcnr_0,pll_locked_0,rx_freqlocked_0;
wire pll_powerdown_sqcnr_1,tx_digitalreset_sqcnr_1,rx_analogreset_sqcnr_1,rx_digitalreset_sqcnr_1,gxb_powerdown_sqcnr_1,pll_locked_1,rx_freqlocked_1;
wire pll_powerdown_sqcnr_2,tx_digitalreset_sqcnr_2,rx_analogreset_sqcnr_2,rx_digitalreset_sqcnr_2,gxb_powerdown_sqcnr_2,pll_locked_2,rx_freqlocked_2;
wire pll_powerdown_sqcnr_3,tx_digitalreset_sqcnr_3,rx_analogreset_sqcnr_3,rx_digitalreset_sqcnr_3,gxb_powerdown_sqcnr_3,pll_locked_3,rx_freqlocked_3;
wire pll_powerdown_sqcnr_4,tx_digitalreset_sqcnr_4,rx_analogreset_sqcnr_4,rx_digitalreset_sqcnr_4,gxb_powerdown_sqcnr_4,pll_locked_4,rx_freqlocked_4;
wire pll_powerdown_sqcnr_5,tx_digitalreset_sqcnr_5,rx_analogreset_sqcnr_5,rx_digitalreset_sqcnr_5,gxb_powerdown_sqcnr_5,pll_locked_5,rx_freqlocked_5;
wire pll_powerdown_sqcnr_6,tx_digitalreset_sqcnr_6,rx_analogreset_sqcnr_6,rx_digitalreset_sqcnr_6,gxb_powerdown_sqcnr_6,pll_locked_6,rx_freqlocked_6;
wire pll_powerdown_sqcnr_7,tx_digitalreset_sqcnr_7,rx_analogreset_sqcnr_7,rx_digitalreset_sqcnr_7,gxb_powerdown_sqcnr_7,pll_locked_7,rx_freqlocked_7;
wire pll_powerdown_sqcnr_8,tx_digitalreset_sqcnr_8,rx_analogreset_sqcnr_8,rx_digitalreset_sqcnr_8,gxb_powerdown_sqcnr_8,pll_locked_8,rx_freqlocked_8;
wire pll_powerdown_sqcnr_9,tx_digitalreset_sqcnr_9,rx_analogreset_sqcnr_9,rx_digitalreset_sqcnr_9,gxb_powerdown_sqcnr_9,pll_locked_9,rx_freqlocked_9;
wire pll_powerdown_sqcnr_10,tx_digitalreset_sqcnr_10,rx_analogreset_sqcnr_10,rx_digitalreset_sqcnr_10,gxb_powerdown_sqcnr_10,pll_locked_10,rx_freqlocked_10;
wire pll_powerdown_sqcnr_11,tx_digitalreset_sqcnr_11,rx_analogreset_sqcnr_11,rx_digitalreset_sqcnr_11,gxb_powerdown_sqcnr_11,pll_locked_11,rx_freqlocked_11;
wire pll_powerdown_sqcnr_12,tx_digitalreset_sqcnr_12,rx_analogreset_sqcnr_12,rx_digitalreset_sqcnr_12,gxb_powerdown_sqcnr_12,pll_locked_12,rx_freqlocked_12;
wire pll_powerdown_sqcnr_13,tx_digitalreset_sqcnr_13,rx_analogreset_sqcnr_13,rx_digitalreset_sqcnr_13,gxb_powerdown_sqcnr_13,pll_locked_13,rx_freqlocked_13;
wire pll_powerdown_sqcnr_14,tx_digitalreset_sqcnr_14,rx_analogreset_sqcnr_14,rx_digitalreset_sqcnr_14,gxb_powerdown_sqcnr_14,pll_locked_14,rx_freqlocked_14;
wire pll_powerdown_sqcnr_15,tx_digitalreset_sqcnr_15,rx_analogreset_sqcnr_15,rx_digitalreset_sqcnr_15,gxb_powerdown_sqcnr_15,pll_locked_15,rx_freqlocked_15;
wire pll_powerdown_sqcnr_16,tx_digitalreset_sqcnr_16,rx_analogreset_sqcnr_16,rx_digitalreset_sqcnr_16,gxb_powerdown_sqcnr_16,pll_locked_16,rx_freqlocked_16;
wire pll_powerdown_sqcnr_17,tx_digitalreset_sqcnr_17,rx_analogreset_sqcnr_17,rx_digitalreset_sqcnr_17,gxb_powerdown_sqcnr_17,pll_locked_17,rx_freqlocked_17;
wire pll_powerdown_sqcnr_18,tx_digitalreset_sqcnr_18,rx_analogreset_sqcnr_18,rx_digitalreset_sqcnr_18,gxb_powerdown_sqcnr_18,pll_locked_18,rx_freqlocked_18;
wire pll_powerdown_sqcnr_19,tx_digitalreset_sqcnr_19,rx_analogreset_sqcnr_19,rx_digitalreset_sqcnr_19,gxb_powerdown_sqcnr_19,pll_locked_19,rx_freqlocked_19;
wire pll_powerdown_sqcnr_20,tx_digitalreset_sqcnr_20,rx_analogreset_sqcnr_20,rx_digitalreset_sqcnr_20,gxb_powerdown_sqcnr_20,pll_locked_20,rx_freqlocked_20;
wire pll_powerdown_sqcnr_21,tx_digitalreset_sqcnr_21,rx_analogreset_sqcnr_21,rx_digitalreset_sqcnr_21,gxb_powerdown_sqcnr_21,pll_locked_21,rx_freqlocked_21;
wire pll_powerdown_sqcnr_22,tx_digitalreset_sqcnr_22,rx_analogreset_sqcnr_22,rx_digitalreset_sqcnr_22,gxb_powerdown_sqcnr_22,pll_locked_22,rx_freqlocked_22;
wire pll_powerdown_sqcnr_23,tx_digitalreset_sqcnr_23,rx_analogreset_sqcnr_23,rx_digitalreset_sqcnr_23,gxb_powerdown_sqcnr_23,pll_locked_23,rx_freqlocked_23;
// Assign pcs clock for all channels
//assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err_0 = led_char_err_gx[0];
assign led_link_0 = link_status[0];
assign led_char_err_1 = led_char_err_gx[1];
assign led_link_1 = link_status[1];
assign led_char_err_2 = led_char_err_gx[2];
assign led_link_2 = link_status[2];
assign led_char_err_3 = led_char_err_gx[3];
assign led_link_3 = link_status[3];
assign led_char_err_4 = led_char_err_gx[4];
assign led_link_4 = link_status[4];
assign led_char_err_5 = led_char_err_gx[5];
assign led_link_5 = link_status[5];
assign led_char_err_6 = led_char_err_gx[6];
assign led_link_6 = link_status[6];
assign led_char_err_7 = led_char_err_gx[7];
assign led_link_7 = link_status[7];
assign led_char_err_8 = led_char_err_gx[8];
assign led_link_8 = link_status[8];
assign led_char_err_9 = led_char_err_gx[9];
assign led_link_9 = link_status[9];
assign led_char_err_10 = led_char_err_gx[10];
assign led_link_10 = link_status[10];
assign led_char_err_11 = led_char_err_gx[11];
assign led_link_11 = link_status[11];
assign led_char_err_12 = led_char_err_gx[12];
assign led_link_12 = link_status[12];
assign led_char_err_13 = led_char_err_gx[13];
assign led_link_13 = link_status[13];
assign led_char_err_14 = led_char_err_gx[14];
assign led_link_14 = link_status[14];
assign led_char_err_15 = led_char_err_gx[15];
assign led_link_15 = link_status[15];
assign led_char_err_16 = led_char_err_gx[16];
assign led_link_16 = link_status[16];
assign led_char_err_17 = led_char_err_gx[17];
assign led_link_17 = link_status[17];
assign led_char_err_18 = led_char_err_gx[18];
assign led_link_18 = link_status[18];
assign led_char_err_19 = led_char_err_gx[19];
assign led_link_19 = link_status[19];
assign led_char_err_20 = led_char_err_gx[20];
assign led_link_20 = link_status[20];
assign led_char_err_21 = led_char_err_gx[21];
assign led_link_21 = link_status[21];
assign led_char_err_22 = led_char_err_gx[22];
assign led_link_22 = link_status[22];
assign led_char_err_23 = led_char_err_gx[23];
assign led_link_23 = link_status[23];
// Based on PHYIP , when user assert reset - it hold the reset sequencer block in reset.
// , reset sequencing only start then reset_sequnece end.
wire reset_sync;
reg reset_start;
altera_tse_reset_synchronizer reset_sync_u0 (
.clk(clk),
.reset_in(reset),
.reset_out(reset_sync)
);
always@(posedge clk or posedge reset_sync) begin
if (reset_sync) begin
reset_start <= 1'b1;
end
else begin
reset_start <= 1'b0;
end
end
wire pcs_phase_measure_clk_w;
generate
if (ENABLE_TIMESTAMPING == 0)
begin
assign pcs_phase_measure_clk_w = 1'b0;
end
else
begin
assign pcs_phase_measure_clk_w = pcs_phase_measure_clk;
end
endgenerate
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
.pcs_phase_measure_clk(pcs_phase_measure_clk_w), //INPUT : Phase Measurement Clock
// Channel 0
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
.rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
.rx_clkout_0(rx_pcs_clk_c0), //INPUT : Receive Clock
.tx_clkout_0(tx_pcs_clk_c0), //INPUT : Transmit Clock
.rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
.tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
.rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
.tx_frame_0(tx_frame_0), //OUTPUT : Frame
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(link_status[0]), //INPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_0(tx_egress_timestamp_request_valid_0), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_0(tx_egress_timestamp_request_fingerprint_0), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_0(tx_etstamp_ins_ctrl_ingress_timestamp_96b_0), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_0(tx_etstamp_ins_ctrl_ingress_timestamp_64b_0), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_0(tx_etstamp_ins_ctrl_timestamp_insert_0), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_0(tx_etstamp_ins_ctrl_residence_time_update_0), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_0(tx_etstamp_ins_ctrl_checksum_zero_0), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_0(tx_etstamp_ins_ctrl_checksum_correct_0), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_0(tx_etstamp_ins_ctrl_residence_time_calc_format_0), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_0(tx_etstamp_ins_ctrl_timestamp_format_0), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_0(tx_etstamp_ins_ctrl_offset_timestamp_0), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_0(tx_etstamp_ins_ctrl_offset_correction_field_0), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_0(tx_etstamp_ins_ctrl_offset_checksum_field_0), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_0(tx_etstamp_ins_ctrl_offset_checksum_correction_0), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_0(tx_time_of_day_96b_data_0), // Time of Day
.tx_time_of_day_64b_data_0(tx_time_of_day_64b_data_0), // Time of Day
.tx_egress_timestamp_96b_valid_0(tx_egress_timestamp_96b_valid_0), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_0(tx_egress_timestamp_96b_data_0), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_0(tx_egress_timestamp_96b_fingerprint_0), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_0(tx_egress_timestamp_64b_valid_0), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_0(tx_egress_timestamp_64b_data_0), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_0(tx_egress_timestamp_64b_fingerprint_0), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_0(rx_ingress_timestamp_96b_valid_0), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_0(rx_ingress_timestamp_96b_data_0), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_0(rx_ingress_timestamp_64b_valid_0), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_0(rx_ingress_timestamp_64b_data_0), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_0(rx_time_of_day_96b_data_0), // Time of Day
.rx_time_of_day_64b_data_0(rx_time_of_day_64b_data_0), //INPUT: Time of Day
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
.rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
.rx_clkout_1(rx_pcs_clk_c1), //INPUT : Receive Clock
.tx_clkout_1(tx_pcs_clk_c1), //INPUT : Transmit Clock
.rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
.tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
.rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
.tx_frame_1(tx_frame_1), //OUTPUT : Frame
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(link_status[1]), //INPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_1(tx_egress_timestamp_request_valid_1), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_1(tx_egress_timestamp_request_fingerprint_1), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_1(tx_etstamp_ins_ctrl_ingress_timestamp_96b_1), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_1(tx_etstamp_ins_ctrl_ingress_timestamp_64b_1), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_1(tx_etstamp_ins_ctrl_timestamp_insert_1), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_1(tx_etstamp_ins_ctrl_residence_time_update_1), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_1(tx_etstamp_ins_ctrl_checksum_zero_1), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_1(tx_etstamp_ins_ctrl_checksum_correct_1), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_1(tx_etstamp_ins_ctrl_residence_time_calc_format_1), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_1(tx_etstamp_ins_ctrl_timestamp_format_1), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_1(tx_etstamp_ins_ctrl_offset_timestamp_1), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_1(tx_etstamp_ins_ctrl_offset_correction_field_1), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_1(tx_etstamp_ins_ctrl_offset_checksum_field_1), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_1(tx_etstamp_ins_ctrl_offset_checksum_correction_1), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_1(tx_time_of_day_96b_data_1), // Time of Day
.tx_time_of_day_64b_data_1(tx_time_of_day_64b_data_1), // Time of Day
.tx_egress_timestamp_96b_valid_1(tx_egress_timestamp_96b_valid_1), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_1(tx_egress_timestamp_96b_data_1), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_1(tx_egress_timestamp_96b_fingerprint_1), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_1(tx_egress_timestamp_64b_valid_1), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_1(tx_egress_timestamp_64b_data_1), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_1(tx_egress_timestamp_64b_fingerprint_1), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_1(rx_ingress_timestamp_96b_valid_1), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_1(rx_ingress_timestamp_96b_data_1), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_1(rx_ingress_timestamp_64b_valid_1), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_1(rx_ingress_timestamp_64b_data_1), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_1(rx_time_of_day_96b_data_1), // Time of Day
.rx_time_of_day_64b_data_1(rx_time_of_day_64b_data_1), //INPUT: Time of Day
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
.rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
.rx_clkout_2(rx_pcs_clk_c2), //INPUT : Receive Clock
.tx_clkout_2(tx_pcs_clk_c2), //INPUT : Transmit Clock
.rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
.tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
.rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
.tx_frame_2(tx_frame_2), //OUTPUT : Frame
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(link_status[2]), //INPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_2(tx_egress_timestamp_request_valid_2), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_2(tx_egress_timestamp_request_fingerprint_2), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_2(tx_etstamp_ins_ctrl_ingress_timestamp_96b_2), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_2(tx_etstamp_ins_ctrl_ingress_timestamp_64b_2), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_2(tx_etstamp_ins_ctrl_timestamp_insert_2), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_2(tx_etstamp_ins_ctrl_residence_time_update_2), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_2(tx_etstamp_ins_ctrl_checksum_zero_2), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_2(tx_etstamp_ins_ctrl_checksum_correct_2), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_2(tx_etstamp_ins_ctrl_residence_time_calc_format_2), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_2(tx_etstamp_ins_ctrl_timestamp_format_2), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_2(tx_etstamp_ins_ctrl_offset_timestamp_2), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_2(tx_etstamp_ins_ctrl_offset_correction_field_2), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_2(tx_etstamp_ins_ctrl_offset_checksum_field_2), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_2(tx_etstamp_ins_ctrl_offset_checksum_correction_2), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_2(tx_time_of_day_96b_data_2), // Time of Day
.tx_time_of_day_64b_data_2(tx_time_of_day_64b_data_2), // Time of Day
.tx_egress_timestamp_96b_valid_2(tx_egress_timestamp_96b_valid_2), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_2(tx_egress_timestamp_96b_data_2), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_2(tx_egress_timestamp_96b_fingerprint_2), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_2(tx_egress_timestamp_64b_valid_2), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_2(tx_egress_timestamp_64b_data_2), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_2(tx_egress_timestamp_64b_fingerprint_2), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_2(rx_ingress_timestamp_96b_valid_2), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_2(rx_ingress_timestamp_96b_data_2), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_2(rx_ingress_timestamp_64b_valid_2), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_2(rx_ingress_timestamp_64b_data_2), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_2(rx_time_of_day_96b_data_2), // Time of Day
.rx_time_of_day_64b_data_2(rx_time_of_day_64b_data_2), //INPUT: Time of Day
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
.rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
.rx_clkout_3(rx_pcs_clk_c3), //INPUT : Receive Clock
.tx_clkout_3(tx_pcs_clk_c3), //INPUT : Transmit Clock
.rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
.tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
.rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
.tx_frame_3(tx_frame_3), //OUTPUT : Frame
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(link_status[3]), //INPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_3(tx_egress_timestamp_request_valid_3), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_3(tx_egress_timestamp_request_fingerprint_3), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_3(tx_etstamp_ins_ctrl_ingress_timestamp_96b_3), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_3(tx_etstamp_ins_ctrl_ingress_timestamp_64b_3), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_3(tx_etstamp_ins_ctrl_timestamp_insert_3), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_3(tx_etstamp_ins_ctrl_residence_time_update_3), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_3(tx_etstamp_ins_ctrl_checksum_zero_3), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_3(tx_etstamp_ins_ctrl_checksum_correct_3), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_3(tx_etstamp_ins_ctrl_residence_time_calc_format_3), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_3(tx_etstamp_ins_ctrl_timestamp_format_3), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_3(tx_etstamp_ins_ctrl_offset_timestamp_3), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_3(tx_etstamp_ins_ctrl_offset_correction_field_3), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_3(tx_etstamp_ins_ctrl_offset_checksum_field_3), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_3(tx_etstamp_ins_ctrl_offset_checksum_correction_3), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_3(tx_time_of_day_96b_data_3), // Time of Day
.tx_time_of_day_64b_data_3(tx_time_of_day_64b_data_3), // Time of Day
.tx_egress_timestamp_96b_valid_3(tx_egress_timestamp_96b_valid_3), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_3(tx_egress_timestamp_96b_data_3), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_3(tx_egress_timestamp_96b_fingerprint_3), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_3(tx_egress_timestamp_64b_valid_3), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_3(tx_egress_timestamp_64b_data_3), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_3(tx_egress_timestamp_64b_fingerprint_3), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_3(rx_ingress_timestamp_96b_valid_3), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_3(rx_ingress_timestamp_96b_data_3), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_3(rx_ingress_timestamp_64b_valid_3), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_3(rx_ingress_timestamp_64b_data_3), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_3(rx_time_of_day_96b_data_3), // Time of Day
.rx_time_of_day_64b_data_3(rx_time_of_day_64b_data_3), //INPUT: Time of Day
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
.rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
.rx_clkout_4(rx_pcs_clk_c4), //INPUT : Receive Clock
.tx_clkout_4(tx_pcs_clk_c4), //INPUT : Transmit Clock
.rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
.tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
.rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
.tx_frame_4(tx_frame_4), //OUTPUT : Frame
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(link_status[4]), //INPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_4(tx_egress_timestamp_request_valid_4), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_4(tx_egress_timestamp_request_fingerprint_4), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_4(tx_etstamp_ins_ctrl_ingress_timestamp_96b_4), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_4(tx_etstamp_ins_ctrl_ingress_timestamp_64b_4), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_4(tx_etstamp_ins_ctrl_timestamp_insert_4), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_4(tx_etstamp_ins_ctrl_residence_time_update_4), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_4(tx_etstamp_ins_ctrl_checksum_zero_4), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_4(tx_etstamp_ins_ctrl_checksum_correct_4), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_4(tx_etstamp_ins_ctrl_residence_time_calc_format_4), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_4(tx_etstamp_ins_ctrl_timestamp_format_4), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_4(tx_etstamp_ins_ctrl_offset_timestamp_4), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_4(tx_etstamp_ins_ctrl_offset_correction_field_4), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_4(tx_etstamp_ins_ctrl_offset_checksum_field_4), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_4(tx_etstamp_ins_ctrl_offset_checksum_correction_4), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_4(tx_time_of_day_96b_data_4), // Time of Day
.tx_time_of_day_64b_data_4(tx_time_of_day_64b_data_4), // Time of Day
.tx_egress_timestamp_96b_valid_4(tx_egress_timestamp_96b_valid_4), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_4(tx_egress_timestamp_96b_data_4), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_4(tx_egress_timestamp_96b_fingerprint_4), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_4(tx_egress_timestamp_64b_valid_4), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_4(tx_egress_timestamp_64b_data_4), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_4(tx_egress_timestamp_64b_fingerprint_4), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_4(rx_ingress_timestamp_96b_valid_4), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_4(rx_ingress_timestamp_96b_data_4), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_4(rx_ingress_timestamp_64b_valid_4), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_4(rx_ingress_timestamp_64b_data_4), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_4(rx_time_of_day_96b_data_4), // Time of Day
.rx_time_of_day_64b_data_4(rx_time_of_day_64b_data_4), //INPUT: Time of Day
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
.rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
.rx_clkout_5(rx_pcs_clk_c5), //INPUT : Receive Clock
.tx_clkout_5(tx_pcs_clk_c5), //INPUT : Transmit Clock
.rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
.tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
.rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
.tx_frame_5(tx_frame_5), //OUTPUT : Frame
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(link_status[5]), //INPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_5(tx_egress_timestamp_request_valid_5), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_5(tx_egress_timestamp_request_fingerprint_5), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_5(tx_etstamp_ins_ctrl_ingress_timestamp_96b_5), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_5(tx_etstamp_ins_ctrl_ingress_timestamp_64b_5), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_5(tx_etstamp_ins_ctrl_timestamp_insert_5), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_5(tx_etstamp_ins_ctrl_residence_time_update_5), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_5(tx_etstamp_ins_ctrl_checksum_zero_5), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_5(tx_etstamp_ins_ctrl_checksum_correct_5), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_5(tx_etstamp_ins_ctrl_residence_time_calc_format_5), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_5(tx_etstamp_ins_ctrl_timestamp_format_5), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_5(tx_etstamp_ins_ctrl_offset_timestamp_5), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_5(tx_etstamp_ins_ctrl_offset_correction_field_5), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_5(tx_etstamp_ins_ctrl_offset_checksum_field_5), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_5(tx_etstamp_ins_ctrl_offset_checksum_correction_5), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_5(tx_time_of_day_96b_data_5), // Time of Day
.tx_time_of_day_64b_data_5(tx_time_of_day_64b_data_5), // Time of Day
.tx_egress_timestamp_96b_valid_5(tx_egress_timestamp_96b_valid_5), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_5(tx_egress_timestamp_96b_data_5), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_5(tx_egress_timestamp_96b_fingerprint_5), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_5(tx_egress_timestamp_64b_valid_5), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_5(tx_egress_timestamp_64b_data_5), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_5(tx_egress_timestamp_64b_fingerprint_5), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_5(rx_ingress_timestamp_96b_valid_5), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_5(rx_ingress_timestamp_96b_data_5), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_5(rx_ingress_timestamp_64b_valid_5), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_5(rx_ingress_timestamp_64b_data_5), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_5(rx_time_of_day_96b_data_5), // Time of Day
.rx_time_of_day_64b_data_5(rx_time_of_day_64b_data_5), //INPUT: Time of Day
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
.rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
.rx_clkout_6(rx_pcs_clk_c6), //INPUT : Receive Clock
.tx_clkout_6(tx_pcs_clk_c6), //INPUT : Transmit Clock
.rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
.tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
.rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
.tx_frame_6(tx_frame_6), //OUTPUT : Frame
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(link_status[6]), //INPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_6(tx_egress_timestamp_request_valid_6), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_6(tx_egress_timestamp_request_fingerprint_6), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_6(tx_etstamp_ins_ctrl_ingress_timestamp_96b_6), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_6(tx_etstamp_ins_ctrl_ingress_timestamp_64b_6), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_6(tx_etstamp_ins_ctrl_timestamp_insert_6), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_6(tx_etstamp_ins_ctrl_residence_time_update_6), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_6(tx_etstamp_ins_ctrl_checksum_zero_6), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_6(tx_etstamp_ins_ctrl_checksum_correct_6), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_6(tx_etstamp_ins_ctrl_residence_time_calc_format_6), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_6(tx_etstamp_ins_ctrl_timestamp_format_6), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_6(tx_etstamp_ins_ctrl_offset_timestamp_6), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_6(tx_etstamp_ins_ctrl_offset_correction_field_6), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_6(tx_etstamp_ins_ctrl_offset_checksum_field_6), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_6(tx_etstamp_ins_ctrl_offset_checksum_correction_6), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_6(tx_time_of_day_96b_data_6), // Time of Day
.tx_time_of_day_64b_data_6(tx_time_of_day_64b_data_6), // Time of Day
.tx_egress_timestamp_96b_valid_6(tx_egress_timestamp_96b_valid_6), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_6(tx_egress_timestamp_96b_data_6), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_6(tx_egress_timestamp_96b_fingerprint_6), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_6(tx_egress_timestamp_64b_valid_6), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_6(tx_egress_timestamp_64b_data_6), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_6(tx_egress_timestamp_64b_fingerprint_6), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_6(rx_ingress_timestamp_96b_valid_6), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_6(rx_ingress_timestamp_96b_data_6), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_6(rx_ingress_timestamp_64b_valid_6), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_6(rx_ingress_timestamp_64b_data_6), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_6(rx_time_of_day_96b_data_6), // Time of Day
.rx_time_of_day_64b_data_6(rx_time_of_day_64b_data_6), //INPUT: Time of Day
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
.rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
.rx_clkout_7(rx_pcs_clk_c7), //INPUT : Receive Clock
.tx_clkout_7(tx_pcs_clk_c7), //INPUT : Transmit Clock
.rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
.tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
.rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
.tx_frame_7(tx_frame_7), //OUTPUT : Frame
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(link_status[7]), //INPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_7(tx_egress_timestamp_request_valid_7), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_7(tx_egress_timestamp_request_fingerprint_7), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_7(tx_etstamp_ins_ctrl_ingress_timestamp_96b_7), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_7(tx_etstamp_ins_ctrl_ingress_timestamp_64b_7), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_7(tx_etstamp_ins_ctrl_timestamp_insert_7), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_7(tx_etstamp_ins_ctrl_residence_time_update_7), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_7(tx_etstamp_ins_ctrl_checksum_zero_7), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_7(tx_etstamp_ins_ctrl_checksum_correct_7), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_7(tx_etstamp_ins_ctrl_residence_time_calc_format_7), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_7(tx_etstamp_ins_ctrl_timestamp_format_7), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_7(tx_etstamp_ins_ctrl_offset_timestamp_7), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_7(tx_etstamp_ins_ctrl_offset_correction_field_7), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_7(tx_etstamp_ins_ctrl_offset_checksum_field_7), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_7(tx_etstamp_ins_ctrl_offset_checksum_correction_7), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_7(tx_time_of_day_96b_data_7), // Time of Day
.tx_time_of_day_64b_data_7(tx_time_of_day_64b_data_7), // Time of Day
.tx_egress_timestamp_96b_valid_7(tx_egress_timestamp_96b_valid_7), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_7(tx_egress_timestamp_96b_data_7), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_7(tx_egress_timestamp_96b_fingerprint_7), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_7(tx_egress_timestamp_64b_valid_7), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_7(tx_egress_timestamp_64b_data_7), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_7(tx_egress_timestamp_64b_fingerprint_7), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_7(rx_ingress_timestamp_96b_valid_7), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_7(rx_ingress_timestamp_96b_data_7), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_7(rx_ingress_timestamp_64b_valid_7), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_7(rx_ingress_timestamp_64b_data_7), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_7(rx_time_of_day_96b_data_7), // Time of Day
.rx_time_of_day_64b_data_7(rx_time_of_day_64b_data_7), //INPUT: Time of Day
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
.rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
.rx_clkout_8(rx_pcs_clk_c8), //INPUT : Receive Clock
.tx_clkout_8(tx_pcs_clk_c8), //INPUT : Transmit Clock
.rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
.tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
.rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
.tx_frame_8(tx_frame_8), //OUTPUT : Frame
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(link_status[8]), //INPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_8(tx_egress_timestamp_request_valid_8), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_8(tx_egress_timestamp_request_fingerprint_8), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_8(tx_etstamp_ins_ctrl_ingress_timestamp_96b_8), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_8(tx_etstamp_ins_ctrl_ingress_timestamp_64b_8), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_8(tx_etstamp_ins_ctrl_timestamp_insert_8), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_8(tx_etstamp_ins_ctrl_residence_time_update_8), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_8(tx_etstamp_ins_ctrl_checksum_zero_8), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_8(tx_etstamp_ins_ctrl_checksum_correct_8), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_8(tx_etstamp_ins_ctrl_residence_time_calc_format_8), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_8(tx_etstamp_ins_ctrl_timestamp_format_8), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_8(tx_etstamp_ins_ctrl_offset_timestamp_8), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_8(tx_etstamp_ins_ctrl_offset_correction_field_8), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_8(tx_etstamp_ins_ctrl_offset_checksum_field_8), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_8(tx_etstamp_ins_ctrl_offset_checksum_correction_8), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_8(tx_time_of_day_96b_data_8), // Time of Day
.tx_time_of_day_64b_data_8(tx_time_of_day_64b_data_8), // Time of Day
.tx_egress_timestamp_96b_valid_8(tx_egress_timestamp_96b_valid_8), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_8(tx_egress_timestamp_96b_data_8), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_8(tx_egress_timestamp_96b_fingerprint_8), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_8(tx_egress_timestamp_64b_valid_8), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_8(tx_egress_timestamp_64b_data_8), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_8(tx_egress_timestamp_64b_fingerprint_8), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_8(rx_ingress_timestamp_96b_valid_8), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_8(rx_ingress_timestamp_96b_data_8), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_8(rx_ingress_timestamp_64b_valid_8), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_8(rx_ingress_timestamp_64b_data_8), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_8(rx_time_of_day_96b_data_8), // Time of Day
.rx_time_of_day_64b_data_8(rx_time_of_day_64b_data_8), //INPUT: Time of Day
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
.rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
.rx_clkout_9(rx_pcs_clk_c9), //INPUT : Receive Clock
.tx_clkout_9(tx_pcs_clk_c9), //INPUT : Transmit Clock
.rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
.tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
.rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
.tx_frame_9(tx_frame_9), //OUTPUT : Frame
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(link_status[9]), //INPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_9(tx_egress_timestamp_request_valid_9), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_9(tx_egress_timestamp_request_fingerprint_9), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_9(tx_etstamp_ins_ctrl_ingress_timestamp_96b_9), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_9(tx_etstamp_ins_ctrl_ingress_timestamp_64b_9), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_9(tx_etstamp_ins_ctrl_timestamp_insert_9), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_9(tx_etstamp_ins_ctrl_residence_time_update_9), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_9(tx_etstamp_ins_ctrl_checksum_zero_9), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_9(tx_etstamp_ins_ctrl_checksum_correct_9), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_9(tx_etstamp_ins_ctrl_residence_time_calc_format_9), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_9(tx_etstamp_ins_ctrl_timestamp_format_9), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_9(tx_etstamp_ins_ctrl_offset_timestamp_9), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_9(tx_etstamp_ins_ctrl_offset_correction_field_9), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_9(tx_etstamp_ins_ctrl_offset_checksum_field_9), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_9(tx_etstamp_ins_ctrl_offset_checksum_correction_9), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_9(tx_time_of_day_96b_data_9), // Time of Day
.tx_time_of_day_64b_data_9(tx_time_of_day_64b_data_9), // Time of Day
.tx_egress_timestamp_96b_valid_9(tx_egress_timestamp_96b_valid_9), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_9(tx_egress_timestamp_96b_data_9), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_9(tx_egress_timestamp_96b_fingerprint_9), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_9(tx_egress_timestamp_64b_valid_9), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_9(tx_egress_timestamp_64b_data_9), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_9(tx_egress_timestamp_64b_fingerprint_9), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_9(rx_ingress_timestamp_96b_valid_9), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_9(rx_ingress_timestamp_96b_data_9), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_9(rx_ingress_timestamp_64b_valid_9), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_9(rx_ingress_timestamp_64b_data_9), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_9(rx_time_of_day_96b_data_9), // Time of Day
.rx_time_of_day_64b_data_9(rx_time_of_day_64b_data_9), //INPUT: Time of Day
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
.rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
.rx_clkout_10(rx_pcs_clk_c10), //INPUT : Receive Clock
.tx_clkout_10(tx_pcs_clk_c10), //INPUT : Transmit Clock
.rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
.tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
.rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
.tx_frame_10(tx_frame_10), //OUTPUT : Frame
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(link_status[10]), //INPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_10(tx_egress_timestamp_request_valid_10), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_10(tx_egress_timestamp_request_fingerprint_10), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_10(tx_etstamp_ins_ctrl_ingress_timestamp_96b_10), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_10(tx_etstamp_ins_ctrl_ingress_timestamp_64b_10), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_10(tx_etstamp_ins_ctrl_timestamp_insert_10), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_10(tx_etstamp_ins_ctrl_residence_time_update_10), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_10(tx_etstamp_ins_ctrl_checksum_zero_10), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_10(tx_etstamp_ins_ctrl_checksum_correct_10), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_10(tx_etstamp_ins_ctrl_residence_time_calc_format_10), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_10(tx_etstamp_ins_ctrl_timestamp_format_10), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_10(tx_etstamp_ins_ctrl_offset_timestamp_10), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_10(tx_etstamp_ins_ctrl_offset_correction_field_10), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_10(tx_etstamp_ins_ctrl_offset_checksum_field_10), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_10(tx_etstamp_ins_ctrl_offset_checksum_correction_10), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_10(tx_time_of_day_96b_data_10), // Time of Day
.tx_time_of_day_64b_data_10(tx_time_of_day_64b_data_10), // Time of Day
.tx_egress_timestamp_96b_valid_10(tx_egress_timestamp_96b_valid_10), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_10(tx_egress_timestamp_96b_data_10), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_10(tx_egress_timestamp_96b_fingerprint_10), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_10(tx_egress_timestamp_64b_valid_10), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_10(tx_egress_timestamp_64b_data_10), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_10(tx_egress_timestamp_64b_fingerprint_10), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_10(rx_ingress_timestamp_96b_valid_10), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_10(rx_ingress_timestamp_96b_data_10), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_10(rx_ingress_timestamp_64b_valid_10), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_10(rx_ingress_timestamp_64b_data_10), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_10(rx_time_of_day_96b_data_10), // Time of Day
.rx_time_of_day_64b_data_10(rx_time_of_day_64b_data_10), //INPUT: Time of Day
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
.rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
.rx_clkout_11(rx_pcs_clk_c11), //INPUT : Receive Clock
.tx_clkout_11(tx_pcs_clk_c11), //INPUT : Transmit Clock
.rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
.tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
.rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
.tx_frame_11(tx_frame_11), //OUTPUT : Frame
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(link_status[11]), //INPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_11(tx_egress_timestamp_request_valid_11), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_11(tx_egress_timestamp_request_fingerprint_11), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_11(tx_etstamp_ins_ctrl_ingress_timestamp_96b_11), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_11(tx_etstamp_ins_ctrl_ingress_timestamp_64b_11), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_11(tx_etstamp_ins_ctrl_timestamp_insert_11), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_11(tx_etstamp_ins_ctrl_residence_time_update_11), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_11(tx_etstamp_ins_ctrl_checksum_zero_11), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_11(tx_etstamp_ins_ctrl_checksum_correct_11), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_11(tx_etstamp_ins_ctrl_residence_time_calc_format_11), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_11(tx_etstamp_ins_ctrl_timestamp_format_11), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_11(tx_etstamp_ins_ctrl_offset_timestamp_11), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_11(tx_etstamp_ins_ctrl_offset_correction_field_11), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_11(tx_etstamp_ins_ctrl_offset_checksum_field_11), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_11(tx_etstamp_ins_ctrl_offset_checksum_correction_11), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_11(tx_time_of_day_96b_data_11), // Time of Day
.tx_time_of_day_64b_data_11(tx_time_of_day_64b_data_11), // Time of Day
.tx_egress_timestamp_96b_valid_11(tx_egress_timestamp_96b_valid_11), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_11(tx_egress_timestamp_96b_data_11), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_11(tx_egress_timestamp_96b_fingerprint_11), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_11(tx_egress_timestamp_64b_valid_11), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_11(tx_egress_timestamp_64b_data_11), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_11(tx_egress_timestamp_64b_fingerprint_11), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_11(rx_ingress_timestamp_96b_valid_11), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_11(rx_ingress_timestamp_96b_data_11), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_11(rx_ingress_timestamp_64b_valid_11), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_11(rx_ingress_timestamp_64b_data_11), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_11(rx_time_of_day_96b_data_11), // Time of Day
.rx_time_of_day_64b_data_11(rx_time_of_day_64b_data_11), //INPUT: Time of Day
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
.rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
.rx_clkout_12(rx_pcs_clk_c12), //INPUT : Receive Clock
.tx_clkout_12(tx_pcs_clk_c12), //INPUT : Transmit Clock
.rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
.tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
.rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
.tx_frame_12(tx_frame_12), //OUTPUT : Frame
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(link_status[12]), //INPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_12(tx_egress_timestamp_request_valid_12), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_12(tx_egress_timestamp_request_fingerprint_12), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_12(tx_etstamp_ins_ctrl_ingress_timestamp_96b_12), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_12(tx_etstamp_ins_ctrl_ingress_timestamp_64b_12), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_12(tx_etstamp_ins_ctrl_timestamp_insert_12), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_12(tx_etstamp_ins_ctrl_residence_time_update_12), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_12(tx_etstamp_ins_ctrl_checksum_zero_12), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_12(tx_etstamp_ins_ctrl_checksum_correct_12), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_12(tx_etstamp_ins_ctrl_residence_time_calc_format_12), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_12(tx_etstamp_ins_ctrl_timestamp_format_12), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_12(tx_etstamp_ins_ctrl_offset_timestamp_12), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_12(tx_etstamp_ins_ctrl_offset_correction_field_12), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_12(tx_etstamp_ins_ctrl_offset_checksum_field_12), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_12(tx_etstamp_ins_ctrl_offset_checksum_correction_12), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_12(tx_time_of_day_96b_data_12), // Time of Day
.tx_time_of_day_64b_data_12(tx_time_of_day_64b_data_12), // Time of Day
.tx_egress_timestamp_96b_valid_12(tx_egress_timestamp_96b_valid_12), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_12(tx_egress_timestamp_96b_data_12), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_12(tx_egress_timestamp_96b_fingerprint_12), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_12(tx_egress_timestamp_64b_valid_12), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_12(tx_egress_timestamp_64b_data_12), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_12(tx_egress_timestamp_64b_fingerprint_12), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_12(rx_ingress_timestamp_96b_valid_12), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_12(rx_ingress_timestamp_96b_data_12), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_12(rx_ingress_timestamp_64b_valid_12), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_12(rx_ingress_timestamp_64b_data_12), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_12(rx_time_of_day_96b_data_12), // Time of Day
.rx_time_of_day_64b_data_12(rx_time_of_day_64b_data_12), //INPUT: Time of Day
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
.rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
.rx_clkout_13(rx_pcs_clk_c13), //INPUT : Receive Clock
.tx_clkout_13(tx_pcs_clk_c13), //INPUT : Transmit Clock
.rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
.tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
.rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
.tx_frame_13(tx_frame_13), //OUTPUT : Frame
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(link_status[13]), //INPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_13(tx_egress_timestamp_request_valid_13), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_13(tx_egress_timestamp_request_fingerprint_13), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_13(tx_etstamp_ins_ctrl_ingress_timestamp_96b_13), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_13(tx_etstamp_ins_ctrl_ingress_timestamp_64b_13), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_13(tx_etstamp_ins_ctrl_timestamp_insert_13), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_13(tx_etstamp_ins_ctrl_residence_time_update_13), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_13(tx_etstamp_ins_ctrl_checksum_zero_13), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_13(tx_etstamp_ins_ctrl_checksum_correct_13), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_13(tx_etstamp_ins_ctrl_residence_time_calc_format_13), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_13(tx_etstamp_ins_ctrl_timestamp_format_13), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_13(tx_etstamp_ins_ctrl_offset_timestamp_13), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_13(tx_etstamp_ins_ctrl_offset_correction_field_13), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_13(tx_etstamp_ins_ctrl_offset_checksum_field_13), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_13(tx_etstamp_ins_ctrl_offset_checksum_correction_13), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_13(tx_time_of_day_96b_data_13), // Time of Day
.tx_time_of_day_64b_data_13(tx_time_of_day_64b_data_13), // Time of Day
.tx_egress_timestamp_96b_valid_13(tx_egress_timestamp_96b_valid_13), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_13(tx_egress_timestamp_96b_data_13), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_13(tx_egress_timestamp_96b_fingerprint_13), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_13(tx_egress_timestamp_64b_valid_13), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_13(tx_egress_timestamp_64b_data_13), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_13(tx_egress_timestamp_64b_fingerprint_13), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_13(rx_ingress_timestamp_96b_valid_13), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_13(rx_ingress_timestamp_96b_data_13), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_13(rx_ingress_timestamp_64b_valid_13), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_13(rx_ingress_timestamp_64b_data_13), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_13(rx_time_of_day_96b_data_13), // Time of Day
.rx_time_of_day_64b_data_13(rx_time_of_day_64b_data_13), //INPUT: Time of Day
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
.rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
.rx_clkout_14(rx_pcs_clk_c14), //INPUT : Receive Clock
.tx_clkout_14(tx_pcs_clk_c14), //INPUT : Transmit Clock
.rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
.tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
.rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
.tx_frame_14(tx_frame_14), //OUTPUT : Frame
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(link_status[14]), //INPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_14(tx_egress_timestamp_request_valid_14), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_14(tx_egress_timestamp_request_fingerprint_14), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_14(tx_etstamp_ins_ctrl_ingress_timestamp_96b_14), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_14(tx_etstamp_ins_ctrl_ingress_timestamp_64b_14), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_14(tx_etstamp_ins_ctrl_timestamp_insert_14), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_14(tx_etstamp_ins_ctrl_residence_time_update_14), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_14(tx_etstamp_ins_ctrl_checksum_zero_14), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_14(tx_etstamp_ins_ctrl_checksum_correct_14), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_14(tx_etstamp_ins_ctrl_residence_time_calc_format_14), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_14(tx_etstamp_ins_ctrl_timestamp_format_14), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_14(tx_etstamp_ins_ctrl_offset_timestamp_14), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_14(tx_etstamp_ins_ctrl_offset_correction_field_14), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_14(tx_etstamp_ins_ctrl_offset_checksum_field_14), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_14(tx_etstamp_ins_ctrl_offset_checksum_correction_14), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_14(tx_time_of_day_96b_data_14), // Time of Day
.tx_time_of_day_64b_data_14(tx_time_of_day_64b_data_14), // Time of Day
.tx_egress_timestamp_96b_valid_14(tx_egress_timestamp_96b_valid_14), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_14(tx_egress_timestamp_96b_data_14), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_14(tx_egress_timestamp_96b_fingerprint_14), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_14(tx_egress_timestamp_64b_valid_14), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_14(tx_egress_timestamp_64b_data_14), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_14(tx_egress_timestamp_64b_fingerprint_14), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_14(rx_ingress_timestamp_96b_valid_14), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_14(rx_ingress_timestamp_96b_data_14), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_14(rx_ingress_timestamp_64b_valid_14), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_14(rx_ingress_timestamp_64b_data_14), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_14(rx_time_of_day_96b_data_14), // Time of Day
.rx_time_of_day_64b_data_14(rx_time_of_day_64b_data_14), //INPUT: Time of Day
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
.rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
.rx_clkout_15(rx_pcs_clk_c15), //INPUT : Receive Clock
.tx_clkout_15(tx_pcs_clk_c15), //INPUT : Transmit Clock
.rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
.tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
.rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
.tx_frame_15(tx_frame_15), //OUTPUT : Frame
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(link_status[15]), //INPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_15(tx_egress_timestamp_request_valid_15), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_15(tx_egress_timestamp_request_fingerprint_15), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_15(tx_etstamp_ins_ctrl_ingress_timestamp_96b_15), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_15(tx_etstamp_ins_ctrl_ingress_timestamp_64b_15), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_15(tx_etstamp_ins_ctrl_timestamp_insert_15), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_15(tx_etstamp_ins_ctrl_residence_time_update_15), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_15(tx_etstamp_ins_ctrl_checksum_zero_15), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_15(tx_etstamp_ins_ctrl_checksum_correct_15), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_15(tx_etstamp_ins_ctrl_residence_time_calc_format_15), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_15(tx_etstamp_ins_ctrl_timestamp_format_15), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_15(tx_etstamp_ins_ctrl_offset_timestamp_15), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_15(tx_etstamp_ins_ctrl_offset_correction_field_15), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_15(tx_etstamp_ins_ctrl_offset_checksum_field_15), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_15(tx_etstamp_ins_ctrl_offset_checksum_correction_15), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_15(tx_time_of_day_96b_data_15), // Time of Day
.tx_time_of_day_64b_data_15(tx_time_of_day_64b_data_15), // Time of Day
.tx_egress_timestamp_96b_valid_15(tx_egress_timestamp_96b_valid_15), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_15(tx_egress_timestamp_96b_data_15), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_15(tx_egress_timestamp_96b_fingerprint_15), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_15(tx_egress_timestamp_64b_valid_15), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_15(tx_egress_timestamp_64b_data_15), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_15(tx_egress_timestamp_64b_fingerprint_15), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_15(rx_ingress_timestamp_96b_valid_15), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_15(rx_ingress_timestamp_96b_data_15), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_15(rx_ingress_timestamp_64b_valid_15), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_15(rx_ingress_timestamp_64b_data_15), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_15(rx_time_of_day_96b_data_15), // Time of Day
.rx_time_of_day_64b_data_15(rx_time_of_day_64b_data_15), //INPUT: Time of Day
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
.rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
.rx_clkout_16(rx_pcs_clk_c16), //INPUT : Receive Clock
.tx_clkout_16(tx_pcs_clk_c16), //INPUT : Transmit Clock
.rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
.tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
.rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
.tx_frame_16(tx_frame_16), //OUTPUT : Frame
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(link_status[16]), //INPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_16(tx_egress_timestamp_request_valid_16), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_16(tx_egress_timestamp_request_fingerprint_16), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_16(tx_etstamp_ins_ctrl_ingress_timestamp_96b_16), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_16(tx_etstamp_ins_ctrl_ingress_timestamp_64b_16), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_16(tx_etstamp_ins_ctrl_timestamp_insert_16), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_16(tx_etstamp_ins_ctrl_residence_time_update_16), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_16(tx_etstamp_ins_ctrl_checksum_zero_16), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_16(tx_etstamp_ins_ctrl_checksum_correct_16), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_16(tx_etstamp_ins_ctrl_residence_time_calc_format_16), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_16(tx_etstamp_ins_ctrl_timestamp_format_16), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_16(tx_etstamp_ins_ctrl_offset_timestamp_16), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_16(tx_etstamp_ins_ctrl_offset_correction_field_16), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_16(tx_etstamp_ins_ctrl_offset_checksum_field_16), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_16(tx_etstamp_ins_ctrl_offset_checksum_correction_16), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_16(tx_time_of_day_96b_data_16), // Time of Day
.tx_time_of_day_64b_data_16(tx_time_of_day_64b_data_16), // Time of Day
.tx_egress_timestamp_96b_valid_16(tx_egress_timestamp_96b_valid_16), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_16(tx_egress_timestamp_96b_data_16), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_16(tx_egress_timestamp_96b_fingerprint_16), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_16(tx_egress_timestamp_64b_valid_16), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_16(tx_egress_timestamp_64b_data_16), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_16(tx_egress_timestamp_64b_fingerprint_16), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_16(rx_ingress_timestamp_96b_valid_16), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_16(rx_ingress_timestamp_96b_data_16), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_16(rx_ingress_timestamp_64b_valid_16), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_16(rx_ingress_timestamp_64b_data_16), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_16(rx_time_of_day_96b_data_16), // Time of Day
.rx_time_of_day_64b_data_16(rx_time_of_day_64b_data_16), //INPUT: Time of Day
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
.rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
.rx_clkout_17(rx_pcs_clk_c17), //INPUT : Receive Clock
.tx_clkout_17(tx_pcs_clk_c17), //INPUT : Transmit Clock
.rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
.tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
.rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
.tx_frame_17(tx_frame_17), //OUTPUT : Frame
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(link_status[17]), //INPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_17(tx_egress_timestamp_request_valid_17), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_17(tx_egress_timestamp_request_fingerprint_17), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_17(tx_etstamp_ins_ctrl_ingress_timestamp_96b_17), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_17(tx_etstamp_ins_ctrl_ingress_timestamp_64b_17), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_17(tx_etstamp_ins_ctrl_timestamp_insert_17), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_17(tx_etstamp_ins_ctrl_residence_time_update_17), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_17(tx_etstamp_ins_ctrl_checksum_zero_17), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_17(tx_etstamp_ins_ctrl_checksum_correct_17), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_17(tx_etstamp_ins_ctrl_residence_time_calc_format_17), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_17(tx_etstamp_ins_ctrl_timestamp_format_17), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_17(tx_etstamp_ins_ctrl_offset_timestamp_17), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_17(tx_etstamp_ins_ctrl_offset_correction_field_17), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_17(tx_etstamp_ins_ctrl_offset_checksum_field_17), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_17(tx_etstamp_ins_ctrl_offset_checksum_correction_17), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_17(tx_time_of_day_96b_data_17), // Time of Day
.tx_time_of_day_64b_data_17(tx_time_of_day_64b_data_17), // Time of Day
.tx_egress_timestamp_96b_valid_17(tx_egress_timestamp_96b_valid_17), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_17(tx_egress_timestamp_96b_data_17), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_17(tx_egress_timestamp_96b_fingerprint_17), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_17(tx_egress_timestamp_64b_valid_17), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_17(tx_egress_timestamp_64b_data_17), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_17(tx_egress_timestamp_64b_fingerprint_17), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_17(rx_ingress_timestamp_96b_valid_17), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_17(rx_ingress_timestamp_96b_data_17), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_17(rx_ingress_timestamp_64b_valid_17), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_17(rx_ingress_timestamp_64b_data_17), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_17(rx_time_of_day_96b_data_17), // Time of Day
.rx_time_of_day_64b_data_17(rx_time_of_day_64b_data_17), //INPUT: Time of Day
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
.rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
.rx_clkout_18(rx_pcs_clk_c18), //INPUT : Receive Clock
.tx_clkout_18(tx_pcs_clk_c18), //INPUT : Transmit Clock
.rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
.tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
.rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
.tx_frame_18(tx_frame_18), //OUTPUT : Frame
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(link_status[18]), //INPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_18(tx_egress_timestamp_request_valid_18), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_18(tx_egress_timestamp_request_fingerprint_18), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_18(tx_etstamp_ins_ctrl_ingress_timestamp_96b_18), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_18(tx_etstamp_ins_ctrl_ingress_timestamp_64b_18), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_18(tx_etstamp_ins_ctrl_timestamp_insert_18), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_18(tx_etstamp_ins_ctrl_residence_time_update_18), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_18(tx_etstamp_ins_ctrl_checksum_zero_18), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_18(tx_etstamp_ins_ctrl_checksum_correct_18), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_18(tx_etstamp_ins_ctrl_residence_time_calc_format_18), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_18(tx_etstamp_ins_ctrl_timestamp_format_18), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_18(tx_etstamp_ins_ctrl_offset_timestamp_18), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_18(tx_etstamp_ins_ctrl_offset_correction_field_18), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_18(tx_etstamp_ins_ctrl_offset_checksum_field_18), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_18(tx_etstamp_ins_ctrl_offset_checksum_correction_18), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_18(tx_time_of_day_96b_data_18), // Time of Day
.tx_time_of_day_64b_data_18(tx_time_of_day_64b_data_18), // Time of Day
.tx_egress_timestamp_96b_valid_18(tx_egress_timestamp_96b_valid_18), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_18(tx_egress_timestamp_96b_data_18), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_18(tx_egress_timestamp_96b_fingerprint_18), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_18(tx_egress_timestamp_64b_valid_18), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_18(tx_egress_timestamp_64b_data_18), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_18(tx_egress_timestamp_64b_fingerprint_18), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_18(rx_ingress_timestamp_96b_valid_18), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_18(rx_ingress_timestamp_96b_data_18), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_18(rx_ingress_timestamp_64b_valid_18), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_18(rx_ingress_timestamp_64b_data_18), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_18(rx_time_of_day_96b_data_18), // Time of Day
.rx_time_of_day_64b_data_18(rx_time_of_day_64b_data_18), //INPUT: Time of Day
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
.rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
.rx_clkout_19(rx_pcs_clk_c19), //INPUT : Receive Clock
.tx_clkout_19(tx_pcs_clk_c19), //INPUT : Transmit Clock
.rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
.tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
.rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
.tx_frame_19(tx_frame_19), //OUTPUT : Frame
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(link_status[19]), //INPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_19(tx_egress_timestamp_request_valid_19), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_19(tx_egress_timestamp_request_fingerprint_19), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_19(tx_etstamp_ins_ctrl_ingress_timestamp_96b_19), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_19(tx_etstamp_ins_ctrl_ingress_timestamp_64b_19), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_19(tx_etstamp_ins_ctrl_timestamp_insert_19), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_19(tx_etstamp_ins_ctrl_residence_time_update_19), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_19(tx_etstamp_ins_ctrl_checksum_zero_19), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_19(tx_etstamp_ins_ctrl_checksum_correct_19), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_19(tx_etstamp_ins_ctrl_residence_time_calc_format_19), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_19(tx_etstamp_ins_ctrl_timestamp_format_19), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_19(tx_etstamp_ins_ctrl_offset_timestamp_19), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_19(tx_etstamp_ins_ctrl_offset_correction_field_19), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_19(tx_etstamp_ins_ctrl_offset_checksum_field_19), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_19(tx_etstamp_ins_ctrl_offset_checksum_correction_19), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_19(tx_time_of_day_96b_data_19), // Time of Day
.tx_time_of_day_64b_data_19(tx_time_of_day_64b_data_19), // Time of Day
.tx_egress_timestamp_96b_valid_19(tx_egress_timestamp_96b_valid_19), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_19(tx_egress_timestamp_96b_data_19), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_19(tx_egress_timestamp_96b_fingerprint_19), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_19(tx_egress_timestamp_64b_valid_19), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_19(tx_egress_timestamp_64b_data_19), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_19(tx_egress_timestamp_64b_fingerprint_19), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_19(rx_ingress_timestamp_96b_valid_19), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_19(rx_ingress_timestamp_96b_data_19), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_19(rx_ingress_timestamp_64b_valid_19), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_19(rx_ingress_timestamp_64b_data_19), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_19(rx_time_of_day_96b_data_19), // Time of Day
.rx_time_of_day_64b_data_19(rx_time_of_day_64b_data_19), //INPUT: Time of Day
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
.rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
.rx_clkout_20(rx_pcs_clk_c20), //INPUT : Receive Clock
.tx_clkout_20(tx_pcs_clk_c20), //INPUT : Transmit Clock
.rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
.tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
.rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
.tx_frame_20(tx_frame_20), //OUTPUT : Frame
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(link_status[20]), //INPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_20(tx_egress_timestamp_request_valid_20), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_20(tx_egress_timestamp_request_fingerprint_20), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_20(tx_etstamp_ins_ctrl_ingress_timestamp_96b_20), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_20(tx_etstamp_ins_ctrl_ingress_timestamp_64b_20), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_20(tx_etstamp_ins_ctrl_timestamp_insert_20), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_20(tx_etstamp_ins_ctrl_residence_time_update_20), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_20(tx_etstamp_ins_ctrl_checksum_zero_20), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_20(tx_etstamp_ins_ctrl_checksum_correct_20), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_20(tx_etstamp_ins_ctrl_residence_time_calc_format_20), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_20(tx_etstamp_ins_ctrl_timestamp_format_20), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_20(tx_etstamp_ins_ctrl_offset_timestamp_20), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_20(tx_etstamp_ins_ctrl_offset_correction_field_20), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_20(tx_etstamp_ins_ctrl_offset_checksum_field_20), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_20(tx_etstamp_ins_ctrl_offset_checksum_correction_20), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_20(tx_time_of_day_96b_data_20), // Time of Day
.tx_time_of_day_64b_data_20(tx_time_of_day_64b_data_20), // Time of Day
.tx_egress_timestamp_96b_valid_20(tx_egress_timestamp_96b_valid_20), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_20(tx_egress_timestamp_96b_data_20), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_20(tx_egress_timestamp_96b_fingerprint_20), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_20(tx_egress_timestamp_64b_valid_20), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_20(tx_egress_timestamp_64b_data_20), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_20(tx_egress_timestamp_64b_fingerprint_20), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_20(rx_ingress_timestamp_96b_valid_20), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_20(rx_ingress_timestamp_96b_data_20), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_20(rx_ingress_timestamp_64b_valid_20), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_20(rx_ingress_timestamp_64b_data_20), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_20(rx_time_of_day_96b_data_20), // Time of Day
.rx_time_of_day_64b_data_20(rx_time_of_day_64b_data_20), //INPUT: Time of Day
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
.rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
.rx_clkout_21(rx_pcs_clk_c21), //INPUT : Receive Clock
.tx_clkout_21(tx_pcs_clk_c21), //INPUT : Transmit Clock
.rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
.tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
.rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
.tx_frame_21(tx_frame_21), //OUTPUT : Frame
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(link_status[21]), //INPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_21(tx_egress_timestamp_request_valid_21), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_21(tx_egress_timestamp_request_fingerprint_21), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_21(tx_etstamp_ins_ctrl_ingress_timestamp_96b_21), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_21(tx_etstamp_ins_ctrl_ingress_timestamp_64b_21), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_21(tx_etstamp_ins_ctrl_timestamp_insert_21), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_21(tx_etstamp_ins_ctrl_residence_time_update_21), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_21(tx_etstamp_ins_ctrl_checksum_zero_21), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_21(tx_etstamp_ins_ctrl_checksum_correct_21), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_21(tx_etstamp_ins_ctrl_residence_time_calc_format_21), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_21(tx_etstamp_ins_ctrl_timestamp_format_21), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_21(tx_etstamp_ins_ctrl_offset_timestamp_21), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_21(tx_etstamp_ins_ctrl_offset_correction_field_21), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_21(tx_etstamp_ins_ctrl_offset_checksum_field_21), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_21(tx_etstamp_ins_ctrl_offset_checksum_correction_21), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_21(tx_time_of_day_96b_data_21), // Time of Day
.tx_time_of_day_64b_data_21(tx_time_of_day_64b_data_21), // Time of Day
.tx_egress_timestamp_96b_valid_21(tx_egress_timestamp_96b_valid_21), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_21(tx_egress_timestamp_96b_data_21), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_21(tx_egress_timestamp_96b_fingerprint_21), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_21(tx_egress_timestamp_64b_valid_21), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_21(tx_egress_timestamp_64b_data_21), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_21(tx_egress_timestamp_64b_fingerprint_21), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_21(rx_ingress_timestamp_96b_valid_21), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_21(rx_ingress_timestamp_96b_data_21), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_21(rx_ingress_timestamp_64b_valid_21), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_21(rx_ingress_timestamp_64b_data_21), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_21(rx_time_of_day_96b_data_21), // Time of Day
.rx_time_of_day_64b_data_21(rx_time_of_day_64b_data_21), //INPUT: Time of Day
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
.rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
.rx_clkout_22(rx_pcs_clk_c22), //INPUT : Receive Clock
.tx_clkout_22(tx_pcs_clk_c22), //INPUT : Transmit Clock
.rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
.tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
.rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
.tx_frame_22(tx_frame_22), //OUTPUT : Frame
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(link_status[22]), //INPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_22(tx_egress_timestamp_request_valid_22), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_22(tx_egress_timestamp_request_fingerprint_22), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_22(tx_etstamp_ins_ctrl_ingress_timestamp_96b_22), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_22(tx_etstamp_ins_ctrl_ingress_timestamp_64b_22), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_22(tx_etstamp_ins_ctrl_timestamp_insert_22), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_22(tx_etstamp_ins_ctrl_residence_time_update_22), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_22(tx_etstamp_ins_ctrl_checksum_zero_22), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_22(tx_etstamp_ins_ctrl_checksum_correct_22), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_22(tx_etstamp_ins_ctrl_residence_time_calc_format_22), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_22(tx_etstamp_ins_ctrl_timestamp_format_22), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_22(tx_etstamp_ins_ctrl_offset_timestamp_22), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_22(tx_etstamp_ins_ctrl_offset_correction_field_22), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_22(tx_etstamp_ins_ctrl_offset_checksum_field_22), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_22(tx_etstamp_ins_ctrl_offset_checksum_correction_22), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_22(tx_time_of_day_96b_data_22), // Time of Day
.tx_time_of_day_64b_data_22(tx_time_of_day_64b_data_22), // Time of Day
.tx_egress_timestamp_96b_valid_22(tx_egress_timestamp_96b_valid_22), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_22(tx_egress_timestamp_96b_data_22), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_22(tx_egress_timestamp_96b_fingerprint_22), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_22(tx_egress_timestamp_64b_valid_22), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_22(tx_egress_timestamp_64b_data_22), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_22(tx_egress_timestamp_64b_fingerprint_22), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_22(rx_ingress_timestamp_96b_valid_22), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_22(rx_ingress_timestamp_96b_data_22), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_22(rx_ingress_timestamp_64b_valid_22), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_22(rx_ingress_timestamp_64b_data_22), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_22(rx_time_of_day_96b_data_22), // Time of Day
.rx_time_of_day_64b_data_22(rx_time_of_day_64b_data_22), //INPUT: Time of Day
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
.rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
.rx_clkout_23(rx_pcs_clk_c23), //INPUT : Receive Clock
.tx_clkout_23(tx_pcs_clk_c23), //INPUT : Transmit Clock
.rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
.tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
.rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
.tx_frame_23(tx_frame_23), //OUTPUT : Frame
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(link_status[23]), //INPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
//IEEE1588's code
.tx_egress_timestamp_request_valid_23(tx_egress_timestamp_request_valid_23), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_23(tx_egress_timestamp_request_fingerprint_23), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_23(tx_etstamp_ins_ctrl_ingress_timestamp_96b_23), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_23(tx_etstamp_ins_ctrl_ingress_timestamp_64b_23), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_23(tx_etstamp_ins_ctrl_timestamp_insert_23), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_23(tx_etstamp_ins_ctrl_residence_time_update_23), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_23(tx_etstamp_ins_ctrl_checksum_zero_23), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_23(tx_etstamp_ins_ctrl_checksum_correct_23), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_23(tx_etstamp_ins_ctrl_residence_time_calc_format_23), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_23(tx_etstamp_ins_ctrl_timestamp_format_23), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_23(tx_etstamp_ins_ctrl_offset_timestamp_23), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_23(tx_etstamp_ins_ctrl_offset_correction_field_23), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_23(tx_etstamp_ins_ctrl_offset_checksum_field_23), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_23(tx_etstamp_ins_ctrl_offset_checksum_correction_23), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_23(tx_time_of_day_96b_data_23), // Time of Day
.tx_time_of_day_64b_data_23(tx_time_of_day_64b_data_23), // Time of Day
.tx_egress_timestamp_96b_valid_23(tx_egress_timestamp_96b_valid_23), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_23(tx_egress_timestamp_96b_data_23), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_23(tx_egress_timestamp_96b_fingerprint_23), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_23(tx_egress_timestamp_64b_valid_23), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_23(tx_egress_timestamp_64b_data_23), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_23(tx_egress_timestamp_64b_fingerprint_23), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_23(rx_ingress_timestamp_96b_valid_23), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_23(rx_ingress_timestamp_96b_data_23), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_23(rx_ingress_timestamp_64b_valid_23), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_23(rx_ingress_timestamp_64b_data_23), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_23(rx_time_of_day_96b_data_23), // Time of Day
.rx_time_of_day_64b_data_23(rx_time_of_day_64b_data_23), //INPUT: Time of Day
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING,
U_MULTI_MAC_PCS.TSTAMP_FP_WIDTH = TSTAMP_FP_WIDTH,
U_MULTI_MAC_PCS.ENABLE_TIMESTAMPING = ENABLE_TIMESTAMPING,
U_MULTI_MAC_PCS.ENABLE_PTP_1STEP = ENABLE_PTP_1STEP;
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_0,gxb_pwrdn_in_sig_clk_0;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 0)
begin
always @(posedge clk or posedge gxb_pwrdn_in_0)
begin
if (gxb_pwrdn_in_0 == 1) begin
data_in_0 <= 1;
gxb_pwrdn_in_sig_clk_0 <= 1;
end else begin
data_in_0 <= 1'b0;
gxb_pwrdn_in_sig_clk_0 <= data_in_0;
end
end
assign gxb_pwrdn_in_sig[0] = gxb_pwrdn_in_0;
assign pcs_pwrdn_out_0 = pcs_pwrdn_out_sig[0];
end
else
begin
assign gxb_pwrdn_in_sig[0] = pcs_pwrdn_out_sig[0];
assign pcs_pwrdn_out_0 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_0 = gxb_pwrdn_in_sig[0];
end
end
endgenerate
generate if (MAX_CHANNELS > 0)
begin
wire locked_signal_0;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_0(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_0),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_0),// output
.tx_digitalreset(tx_digitalreset_sqcnr_0),// output
.rx_analogreset(rx_analogreset_sqcnr_0),// output
.rx_digitalreset(rx_digitalreset_sqcnr_0),// output
.gxb_powerdown(gxb_powerdown_sqcnr_0),// output
.pll_is_locked(locked_signal_0),
.rx_is_lockedtodata(rx_freqlocked_0),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_0)
);
assign locked_signal_0 = (reset? 1'b0: pll_locked_0);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk_c0),
.reset_in(rx_digitalreset_sqcnr_0),
.reset_out(reset_rx_pcs_clk_c0_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
(
.clk(rx_pcs_clk_c0),
.reset(reset_rx_pcs_clk_c0_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_0),
.alt_sync(rx_syncstatus[0]),
.alt_disperr(rx_disp_err[0]),
.alt_ctrldetect(rx_kchar_0),
.alt_errdetect(rx_char_err_gx[0]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
.alt_runlengthviolation(rx_runlengthviolation[0]),
.alt_patterndetect(rx_patterndetect[0]),
.alt_runningdisp(rx_runningdisp[0]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_0),
.altpcs_sync(link_status[0]),
.altpcs_disperr(led_disp_err_0),
.altpcs_ctrldetect(pcs_rx_kchar_0),
.altpcs_errdetect(led_char_err_gx[0]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[0])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_0
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[0]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_0),
.reconfig_clk(reconfig_clk_0),
.reconfig_togxb(reconfig_togxb_0),
.reconfig_fromgxb(reconfig_fromgxb_0),
.rx_analogreset (rx_analogreset_sqcnr_0),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_0),
.rx_clkout (rx_pcs_clk_c0),
.rx_datain (rxp_0),
.rx_dataout (rx_frame_0),
.rx_digitalreset (rx_digitalreset_sqcnr_0),
.rx_disperr (rx_disp_err[0]),
.rx_errdetect (rx_char_err_gx[0]),
.rx_patterndetect (rx_patterndetect[0]),
.rx_rlv (rx_runlengthviolation[0]),
.rx_seriallpbken (sd_loopback_0),
.rx_syncstatus (rx_syncstatus[0]),
.tx_clkout (tx_pcs_clk_c0),
.tx_ctrlenable (tx_kchar_0),
.tx_datain (tx_frame_0),
.rx_freqlocked (rx_freqlocked_0),
.tx_dataout (txp_0),
.tx_digitalreset (tx_digitalreset_sqcnr_0),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
.rx_runningdisp(rx_runningdisp[0]),
.pll_powerdown(gxb_pwrdn_in_sig[0]),
.pll_locked(pll_locked_0)
);
defparam
the_altera_tse_gxb_gige_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_0.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_0.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_0 = {17{1'b0}};
assign led_char_err_gx[0] = 1'b0;
assign link_status[0] = 1'b0;
assign led_disp_err_0 = 1'b0;
assign txp_0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_1,gxb_pwrdn_in_sig_clk_1;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 1)
begin
always @(posedge clk or posedge gxb_pwrdn_in_1)
begin
if (gxb_pwrdn_in_1 == 1) begin
data_in_1 <= 1;
gxb_pwrdn_in_sig_clk_1 <= 1;
end else begin
data_in_1 <= 1'b0;
gxb_pwrdn_in_sig_clk_1 <= data_in_1;
end
end
assign gxb_pwrdn_in_sig[1] = gxb_pwrdn_in_1;
assign pcs_pwrdn_out_1 = pcs_pwrdn_out_sig[1];
end
else
begin
assign gxb_pwrdn_in_sig[1] = pcs_pwrdn_out_sig[1];
assign pcs_pwrdn_out_1 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_1 = gxb_pwrdn_in_sig[1];
end
end
endgenerate
generate if (MAX_CHANNELS > 1)
begin
wire locked_signal_1;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_1(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_1),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_1),// output
.tx_digitalreset(tx_digitalreset_sqcnr_1),// output
.rx_analogreset(rx_analogreset_sqcnr_1),// output
.rx_digitalreset(rx_digitalreset_sqcnr_1),// output
.gxb_powerdown(gxb_powerdown_sqcnr_1),// output
.pll_is_locked(locked_signal_1),
.rx_is_lockedtodata(rx_freqlocked_1),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_1)
);
assign locked_signal_1 = (reset? 1'b0: pll_locked_1);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_1_reset_sync_0 (
.clk(rx_pcs_clk_c1),
.reset_in(rx_digitalreset_sqcnr_1),
.reset_out(reset_rx_pcs_clk_c1_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
(
.clk(rx_pcs_clk_c1),
.reset(reset_rx_pcs_clk_c1_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_1),
.alt_sync(rx_syncstatus[1]),
.alt_disperr(rx_disp_err[1]),
.alt_ctrldetect(rx_kchar_1),
.alt_errdetect(rx_char_err_gx[1]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
.alt_runlengthviolation(rx_runlengthviolation[1]),
.alt_patterndetect(rx_patterndetect[1]),
.alt_runningdisp(rx_runningdisp[1]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_1),
.altpcs_sync(link_status[1]),
.altpcs_disperr(led_disp_err_1),
.altpcs_ctrldetect(pcs_rx_kchar_1),
.altpcs_errdetect(led_char_err_gx[1]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[1])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_1
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[1]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_1),
.reconfig_clk(reconfig_clk_1),
.reconfig_togxb(reconfig_togxb_1),
.reconfig_fromgxb(reconfig_fromgxb_1),
.rx_analogreset (rx_analogreset_sqcnr_1),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_1),
.rx_clkout (rx_pcs_clk_c1),
.rx_datain (rxp_1),
.rx_dataout (rx_frame_1),
.rx_digitalreset (rx_digitalreset_sqcnr_1),
.rx_disperr (rx_disp_err[1]),
.rx_errdetect (rx_char_err_gx[1]),
.rx_patterndetect (rx_patterndetect[1]),
.rx_rlv (rx_runlengthviolation[1]),
.rx_seriallpbken (sd_loopback_1),
.rx_syncstatus (rx_syncstatus[1]),
.tx_clkout (tx_pcs_clk_c1),
.tx_ctrlenable (tx_kchar_1),
.tx_datain (tx_frame_1),
.rx_freqlocked (rx_freqlocked_1),
.tx_dataout (txp_1),
.tx_digitalreset (tx_digitalreset_sqcnr_1),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
.rx_runningdisp(rx_runningdisp[1]),
.pll_powerdown(gxb_pwrdn_in_sig[1]),
.pll_locked(pll_locked_1)
);
defparam
the_altera_tse_gxb_gige_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_1.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_1.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 4,
the_altera_tse_gxb_gige_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_1 = {17{1'b0}};
assign led_char_err_gx[1] = 1'b0;
assign link_status[1] = 1'b0;
assign led_disp_err_1 = 1'b0;
assign txp_1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_2,gxb_pwrdn_in_sig_clk_2;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
begin
always @(posedge clk or posedge gxb_pwrdn_in_2)
begin
if (gxb_pwrdn_in_2 == 1) begin
data_in_2 <= 1;
gxb_pwrdn_in_sig_clk_2 <= 1;
end else begin
data_in_2 <= 1'b0;
gxb_pwrdn_in_sig_clk_2 <= data_in_2;
end
end
assign gxb_pwrdn_in_sig[2] = gxb_pwrdn_in_2;
assign pcs_pwrdn_out_2 = pcs_pwrdn_out_sig[2];
end
else
begin
assign gxb_pwrdn_in_sig[2] = pcs_pwrdn_out_sig[2];
assign pcs_pwrdn_out_2 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_2 = gxb_pwrdn_in_sig[2];
end
end
endgenerate
generate if (MAX_CHANNELS > 2)
begin
wire locked_signal_2;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_2(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_2),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_2),// output
.tx_digitalreset(tx_digitalreset_sqcnr_2),// output
.rx_analogreset(rx_analogreset_sqcnr_2),// output
.rx_digitalreset(rx_digitalreset_sqcnr_2),// output
.gxb_powerdown(gxb_powerdown_sqcnr_2),// output
.pll_is_locked(locked_signal_2),
.rx_is_lockedtodata(rx_freqlocked_2),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_2)
);
assign locked_signal_2 = (reset? 1'b0: pll_locked_2);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_2_reset_sync_0 (
.clk(rx_pcs_clk_c2),
.reset_in(rx_digitalreset_sqcnr_2),
.reset_out(reset_rx_pcs_clk_c2_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
(
.clk(rx_pcs_clk_c2),
.reset(reset_rx_pcs_clk_c2_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_2),
.alt_sync(rx_syncstatus[2]),
.alt_disperr(rx_disp_err[2]),
.alt_ctrldetect(rx_kchar_2),
.alt_errdetect(rx_char_err_gx[2]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
.alt_runlengthviolation(rx_runlengthviolation[2]),
.alt_patterndetect(rx_patterndetect[2]),
.alt_runningdisp(rx_runningdisp[2]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_2),
.altpcs_sync(link_status[2]),
.altpcs_disperr(led_disp_err_2),
.altpcs_ctrldetect(pcs_rx_kchar_2),
.altpcs_errdetect(led_char_err_gx[2]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[2])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_2
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[2]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_2),
.reconfig_clk(reconfig_clk_2),
.reconfig_togxb(reconfig_togxb_2),
.reconfig_fromgxb(reconfig_fromgxb_2),
.rx_analogreset (rx_analogreset_sqcnr_2),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_2),
.rx_clkout (rx_pcs_clk_c2),
.rx_datain (rxp_2),
.rx_dataout (rx_frame_2),
.rx_digitalreset (rx_digitalreset_sqcnr_2),
.rx_disperr (rx_disp_err[2]),
.rx_errdetect (rx_char_err_gx[2]),
.rx_patterndetect (rx_patterndetect[2]),
.rx_rlv (rx_runlengthviolation[2]),
.rx_seriallpbken (sd_loopback_2),
.rx_syncstatus (rx_syncstatus[2]),
.tx_clkout (tx_pcs_clk_c2),
.tx_ctrlenable (tx_kchar_2),
.tx_datain (tx_frame_2),
.rx_freqlocked (rx_freqlocked_2),
.tx_dataout (txp_2),
.tx_digitalreset (tx_digitalreset_sqcnr_2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
.rx_runningdisp(rx_runningdisp[2]),
.pll_powerdown(gxb_pwrdn_in_sig[2]),
.pll_locked(pll_locked_2)
);
defparam
the_altera_tse_gxb_gige_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_2.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_2.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 8,
the_altera_tse_gxb_gige_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_2 = {17{1'b0}};
assign led_char_err_gx[2] = 1'b0;
assign link_status[2] = 1'b0;
assign led_disp_err_2 = 1'b0;
assign txp_2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_3,gxb_pwrdn_in_sig_clk_3;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 3)
begin
always @(posedge clk or posedge gxb_pwrdn_in_3)
begin
if (gxb_pwrdn_in_3 == 1) begin
data_in_3 <= 1;
gxb_pwrdn_in_sig_clk_3 <= 1;
end else begin
data_in_3 <= 1'b0;
gxb_pwrdn_in_sig_clk_3 <= data_in_3;
end
end
assign gxb_pwrdn_in_sig[3] = gxb_pwrdn_in_3;
assign pcs_pwrdn_out_3 = pcs_pwrdn_out_sig[3];
end
else
begin
assign gxb_pwrdn_in_sig[3] = pcs_pwrdn_out_sig[3];
assign pcs_pwrdn_out_3 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_3 = gxb_pwrdn_in_sig[3];
end
end
endgenerate
generate if (MAX_CHANNELS > 3)
begin
wire locked_signal_3;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_3(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_3),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_3),// output
.tx_digitalreset(tx_digitalreset_sqcnr_3),// output
.rx_analogreset(rx_analogreset_sqcnr_3),// output
.rx_digitalreset(rx_digitalreset_sqcnr_3),// output
.gxb_powerdown(gxb_powerdown_sqcnr_3),// output
.pll_is_locked(locked_signal_3),
.rx_is_lockedtodata(rx_freqlocked_3),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_3)
);
assign locked_signal_3 = (reset? 1'b0: pll_locked_3);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_3_reset_sync_0 (
.clk(rx_pcs_clk_c3),
.reset_in(rx_digitalreset_sqcnr_3),
.reset_out(reset_rx_pcs_clk_c3_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
(
.clk(rx_pcs_clk_c3),
.reset(reset_rx_pcs_clk_c3_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_3),
.alt_sync(rx_syncstatus[3]),
.alt_disperr(rx_disp_err[3]),
.alt_ctrldetect(rx_kchar_3),
.alt_errdetect(rx_char_err_gx[3]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
.alt_runlengthviolation(rx_runlengthviolation[3]),
.alt_patterndetect(rx_patterndetect[3]),
.alt_runningdisp(rx_runningdisp[3]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_3),
.altpcs_sync(link_status[3]),
.altpcs_disperr(led_disp_err_3),
.altpcs_ctrldetect(pcs_rx_kchar_3),
.altpcs_errdetect(led_char_err_gx[3]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[3])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_3
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[3]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_3),
.reconfig_clk(reconfig_clk_3),
.reconfig_togxb(reconfig_togxb_3),
.reconfig_fromgxb(reconfig_fromgxb_3),
.rx_analogreset (rx_analogreset_sqcnr_3),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_3),
.rx_clkout (rx_pcs_clk_c3),
.rx_datain (rxp_3),
.rx_dataout (rx_frame_3),
.rx_digitalreset (rx_digitalreset_sqcnr_3),
.rx_disperr (rx_disp_err[3]),
.rx_errdetect (rx_char_err_gx[3]),
.rx_patterndetect (rx_patterndetect[3]),
.rx_rlv (rx_runlengthviolation[3]),
.rx_seriallpbken (sd_loopback_3),
.rx_syncstatus (rx_syncstatus[3]),
.tx_clkout (tx_pcs_clk_c3),
.tx_ctrlenable (tx_kchar_3),
.tx_datain (tx_frame_3),
.rx_freqlocked (rx_freqlocked_3),
.tx_dataout (txp_3),
.tx_digitalreset (tx_digitalreset_sqcnr_3),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
.rx_runningdisp(rx_runningdisp[3]),
.pll_powerdown(gxb_pwrdn_in_sig[3]),
.pll_locked(pll_locked_3)
);
defparam
the_altera_tse_gxb_gige_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_3.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_3.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 12,
the_altera_tse_gxb_gige_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_3 = {17{1'b0}};
assign led_char_err_gx[3] = 1'b0;
assign link_status[3] = 1'b0;
assign led_disp_err_3 = 1'b0;
assign txp_3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_4,gxb_pwrdn_in_sig_clk_4;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 4)
begin
always @(posedge clk or posedge gxb_pwrdn_in_4)
begin
if (gxb_pwrdn_in_4 == 1) begin
data_in_4 <= 1;
gxb_pwrdn_in_sig_clk_4 <= 1;
end else begin
data_in_4 <= 1'b0;
gxb_pwrdn_in_sig_clk_4 <= data_in_4;
end
end
assign gxb_pwrdn_in_sig[4] = gxb_pwrdn_in_4;
assign pcs_pwrdn_out_4 = pcs_pwrdn_out_sig[4];
end
else
begin
assign gxb_pwrdn_in_sig[4] = pcs_pwrdn_out_sig[4];
assign pcs_pwrdn_out_4 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_4 = gxb_pwrdn_in_sig[4];
end
end
endgenerate
generate if (MAX_CHANNELS > 4)
begin
wire locked_signal_4;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_4(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_4),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_4),// output
.tx_digitalreset(tx_digitalreset_sqcnr_4),// output
.rx_analogreset(rx_analogreset_sqcnr_4),// output
.rx_digitalreset(rx_digitalreset_sqcnr_4),// output
.gxb_powerdown(gxb_powerdown_sqcnr_4),// output
.pll_is_locked(locked_signal_4),
.rx_is_lockedtodata(rx_freqlocked_4),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_4)
);
assign locked_signal_4 = (reset? 1'b0: pll_locked_4);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_4_reset_sync_0 (
.clk(rx_pcs_clk_c4),
.reset_in(rx_digitalreset_sqcnr_4),
.reset_out(reset_rx_pcs_clk_c4_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
(
.clk(rx_pcs_clk_c4),
.reset(reset_rx_pcs_clk_c4_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_4),
.alt_sync(rx_syncstatus[4]),
.alt_disperr(rx_disp_err[4]),
.alt_ctrldetect(rx_kchar_4),
.alt_errdetect(rx_char_err_gx[4]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
.alt_runlengthviolation(rx_runlengthviolation[4]),
.alt_patterndetect(rx_patterndetect[4]),
.alt_runningdisp(rx_runningdisp[4]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_4),
.altpcs_sync(link_status[4]),
.altpcs_disperr(led_disp_err_4),
.altpcs_ctrldetect(pcs_rx_kchar_4),
.altpcs_errdetect(led_char_err_gx[4]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[4])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_4
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[4]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_4),
.reconfig_clk(reconfig_clk_4),
.reconfig_togxb(reconfig_togxb_4),
.reconfig_fromgxb(reconfig_fromgxb_4),
.rx_analogreset (rx_analogreset_sqcnr_4),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_4),
.rx_clkout (rx_pcs_clk_c4),
.rx_datain (rxp_4),
.rx_dataout (rx_frame_4),
.rx_digitalreset (rx_digitalreset_sqcnr_4),
.rx_disperr (rx_disp_err[4]),
.rx_errdetect (rx_char_err_gx[4]),
.rx_patterndetect (rx_patterndetect[4]),
.rx_rlv (rx_runlengthviolation[4]),
.rx_seriallpbken (sd_loopback_4),
.rx_syncstatus (rx_syncstatus[4]),
.tx_clkout (tx_pcs_clk_c4),
.tx_ctrlenable (tx_kchar_4),
.tx_datain (tx_frame_4),
.rx_freqlocked (rx_freqlocked_4),
.tx_dataout (txp_4),
.tx_digitalreset (tx_digitalreset_sqcnr_4),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
.rx_runningdisp(rx_runningdisp[4]),
.pll_powerdown(gxb_pwrdn_in_sig[4]),
.pll_locked(pll_locked_4)
);
defparam
the_altera_tse_gxb_gige_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_4.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_4.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 16,
the_altera_tse_gxb_gige_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_4 = {17{1'b0}};
assign led_char_err_gx[4] = 1'b0;
assign link_status[4] = 1'b0;
assign led_disp_err_4 = 1'b0;
assign txp_4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_5,gxb_pwrdn_in_sig_clk_5;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 5)
begin
always @(posedge clk or posedge gxb_pwrdn_in_5)
begin
if (gxb_pwrdn_in_5 == 1) begin
data_in_5 <= 1;
gxb_pwrdn_in_sig_clk_5 <= 1;
end else begin
data_in_5 <= 1'b0;
gxb_pwrdn_in_sig_clk_5 <= data_in_5;
end
end
assign gxb_pwrdn_in_sig[5] = gxb_pwrdn_in_5;
assign pcs_pwrdn_out_5 = pcs_pwrdn_out_sig[5];
end
else
begin
assign gxb_pwrdn_in_sig[5] = pcs_pwrdn_out_sig[5];
assign pcs_pwrdn_out_5 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_5 = gxb_pwrdn_in_sig[5];
end
end
endgenerate
generate if (MAX_CHANNELS > 5)
begin
wire locked_signal_5;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_5(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_5),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_5),// output
.tx_digitalreset(tx_digitalreset_sqcnr_5),// output
.rx_analogreset(rx_analogreset_sqcnr_5),// output
.rx_digitalreset(rx_digitalreset_sqcnr_5),// output
.gxb_powerdown(gxb_powerdown_sqcnr_5),// output
.pll_is_locked(locked_signal_5),
.rx_is_lockedtodata(rx_freqlocked_5),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_5)
);
assign locked_signal_5 = (reset? 1'b0: pll_locked_5);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_5_reset_sync_0 (
.clk(rx_pcs_clk_c5),
.reset_in(rx_digitalreset_sqcnr_5),
.reset_out(reset_rx_pcs_clk_c5_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
(
.clk(rx_pcs_clk_c5),
.reset(reset_rx_pcs_clk_c5_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_5),
.alt_sync(rx_syncstatus[5]),
.alt_disperr(rx_disp_err[5]),
.alt_ctrldetect(rx_kchar_5),
.alt_errdetect(rx_char_err_gx[5]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
.alt_runlengthviolation(rx_runlengthviolation[5]),
.alt_patterndetect(rx_patterndetect[5]),
.alt_runningdisp(rx_runningdisp[5]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_5),
.altpcs_sync(link_status[5]),
.altpcs_disperr(led_disp_err_5),
.altpcs_ctrldetect(pcs_rx_kchar_5),
.altpcs_errdetect(led_char_err_gx[5]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[5])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_5
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[5]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_5),
.reconfig_clk(reconfig_clk_5),
.reconfig_togxb(reconfig_togxb_5),
.reconfig_fromgxb(reconfig_fromgxb_5),
.rx_analogreset (rx_analogreset_sqcnr_5),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_5),
.rx_clkout (rx_pcs_clk_c5),
.rx_datain (rxp_5),
.rx_dataout (rx_frame_5),
.rx_digitalreset (rx_digitalreset_sqcnr_5),
.rx_disperr (rx_disp_err[5]),
.rx_errdetect (rx_char_err_gx[5]),
.rx_patterndetect (rx_patterndetect[5]),
.rx_rlv (rx_runlengthviolation[5]),
.rx_seriallpbken (sd_loopback_5),
.rx_syncstatus (rx_syncstatus[5]),
.tx_clkout (tx_pcs_clk_c5),
.tx_ctrlenable (tx_kchar_5),
.tx_datain (tx_frame_5),
.rx_freqlocked (rx_freqlocked_5),
.tx_dataout (txp_5),
.tx_digitalreset (tx_digitalreset_sqcnr_5),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
.rx_runningdisp(rx_runningdisp[5]),
.pll_powerdown(gxb_pwrdn_in_sig[5]),
.pll_locked(pll_locked_5)
);
defparam
the_altera_tse_gxb_gige_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_5.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_5.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 20,
the_altera_tse_gxb_gige_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_5 = {17{1'b0}};
assign led_char_err_gx[5] = 1'b0;
assign link_status[5] = 1'b0;
assign led_disp_err_5 = 1'b0;
assign txp_5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_6,gxb_pwrdn_in_sig_clk_6;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 6)
begin
always @(posedge clk or posedge gxb_pwrdn_in_6)
begin
if (gxb_pwrdn_in_6 == 1) begin
data_in_6 <= 1;
gxb_pwrdn_in_sig_clk_6 <= 1;
end else begin
data_in_6 <= 1'b0;
gxb_pwrdn_in_sig_clk_6 <= data_in_6;
end
end
assign gxb_pwrdn_in_sig[6] = gxb_pwrdn_in_6;
assign pcs_pwrdn_out_6 = pcs_pwrdn_out_sig[6];
end
else
begin
assign gxb_pwrdn_in_sig[6] = pcs_pwrdn_out_sig[6];
assign pcs_pwrdn_out_6 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_6 = gxb_pwrdn_in_sig[6];
end
end
endgenerate
generate if (MAX_CHANNELS > 6)
begin
wire locked_signal_6;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_6(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_6),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_6),// output
.tx_digitalreset(tx_digitalreset_sqcnr_6),// output
.rx_analogreset(rx_analogreset_sqcnr_6),// output
.rx_digitalreset(rx_digitalreset_sqcnr_6),// output
.gxb_powerdown(gxb_powerdown_sqcnr_6),// output
.pll_is_locked(locked_signal_6),
.rx_is_lockedtodata(rx_freqlocked_6),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_6)
);
assign locked_signal_6 = (reset? 1'b0: pll_locked_6);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_6_reset_sync_0 (
.clk(rx_pcs_clk_c6),
.reset_in(rx_digitalreset_sqcnr_6),
.reset_out(reset_rx_pcs_clk_c6_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
(
.clk(rx_pcs_clk_c6),
.reset(reset_rx_pcs_clk_c6_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_6),
.alt_sync(rx_syncstatus[6]),
.alt_disperr(rx_disp_err[6]),
.alt_ctrldetect(rx_kchar_6),
.alt_errdetect(rx_char_err_gx[6]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
.alt_runlengthviolation(rx_runlengthviolation[6]),
.alt_patterndetect(rx_patterndetect[6]),
.alt_runningdisp(rx_runningdisp[6]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_6),
.altpcs_sync(link_status[6]),
.altpcs_disperr(led_disp_err_6),
.altpcs_ctrldetect(pcs_rx_kchar_6),
.altpcs_errdetect(led_char_err_gx[6]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[6])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_6
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[6]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_6),
.reconfig_clk(reconfig_clk_6),
.reconfig_togxb(reconfig_togxb_6),
.reconfig_fromgxb(reconfig_fromgxb_6),
.rx_analogreset (rx_analogreset_sqcnr_6),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_6),
.rx_clkout (rx_pcs_clk_c6),
.rx_datain (rxp_6),
.rx_dataout (rx_frame_6),
.rx_digitalreset (rx_digitalreset_sqcnr_6),
.rx_disperr (rx_disp_err[6]),
.rx_errdetect (rx_char_err_gx[6]),
.rx_patterndetect (rx_patterndetect[6]),
.rx_rlv (rx_runlengthviolation[6]),
.rx_seriallpbken (sd_loopback_6),
.rx_syncstatus (rx_syncstatus[6]),
.tx_clkout (tx_pcs_clk_c6),
.tx_ctrlenable (tx_kchar_6),
.tx_datain (tx_frame_6),
.rx_freqlocked (rx_freqlocked_6),
.tx_dataout (txp_6),
.tx_digitalreset (tx_digitalreset_sqcnr_6),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
.rx_runningdisp(rx_runningdisp[6]),
.pll_powerdown(gxb_pwrdn_in_sig[6]),
.pll_locked(pll_locked_6)
);
defparam
the_altera_tse_gxb_gige_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_6.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_6.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 24,
the_altera_tse_gxb_gige_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_6 = {17{1'b0}};
assign led_char_err_gx[6] = 1'b0;
assign link_status[6] = 1'b0;
assign led_disp_err_6 = 1'b0;
assign txp_6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_7,gxb_pwrdn_in_sig_clk_7;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 7)
begin
always @(posedge clk or posedge gxb_pwrdn_in_7)
begin
if (gxb_pwrdn_in_7 == 1) begin
data_in_7 <= 1;
gxb_pwrdn_in_sig_clk_7 <= 1;
end else begin
data_in_7 <= 1'b0;
gxb_pwrdn_in_sig_clk_7 <= data_in_7;
end
end
assign gxb_pwrdn_in_sig[7] = gxb_pwrdn_in_7;
assign pcs_pwrdn_out_7 = pcs_pwrdn_out_sig[7];
end
else
begin
assign gxb_pwrdn_in_sig[7] = pcs_pwrdn_out_sig[7];
assign pcs_pwrdn_out_7 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_7 = gxb_pwrdn_in_sig[7];
end
end
endgenerate
generate if (MAX_CHANNELS > 7)
begin
wire locked_signal_7;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_7(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_7),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_7),// output
.tx_digitalreset(tx_digitalreset_sqcnr_7),// output
.rx_analogreset(rx_analogreset_sqcnr_7),// output
.rx_digitalreset(rx_digitalreset_sqcnr_7),// output
.gxb_powerdown(gxb_powerdown_sqcnr_7),// output
.pll_is_locked(locked_signal_7),
.rx_is_lockedtodata(rx_freqlocked_7),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_7)
);
assign locked_signal_7 = (reset? 1'b0: pll_locked_7);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_7_reset_sync_0 (
.clk(rx_pcs_clk_c7),
.reset_in(rx_digitalreset_sqcnr_7),
.reset_out(reset_rx_pcs_clk_c7_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
(
.clk(rx_pcs_clk_c7),
.reset(reset_rx_pcs_clk_c7_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_7),
.alt_sync(rx_syncstatus[7]),
.alt_disperr(rx_disp_err[7]),
.alt_ctrldetect(rx_kchar_7),
.alt_errdetect(rx_char_err_gx[7]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
.alt_runlengthviolation(rx_runlengthviolation[7]),
.alt_patterndetect(rx_patterndetect[7]),
.alt_runningdisp(rx_runningdisp[7]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_7),
.altpcs_sync(link_status[7]),
.altpcs_disperr(led_disp_err_7),
.altpcs_ctrldetect(pcs_rx_kchar_7),
.altpcs_errdetect(led_char_err_gx[7]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[7])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_7
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[7]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_7),
.reconfig_clk(reconfig_clk_7),
.reconfig_togxb(reconfig_togxb_7),
.reconfig_fromgxb(reconfig_fromgxb_7),
.rx_analogreset (rx_analogreset_sqcnr_7),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_7),
.rx_clkout (rx_pcs_clk_c7),
.rx_datain (rxp_7),
.rx_dataout (rx_frame_7),
.rx_digitalreset (rx_digitalreset_sqcnr_7),
.rx_disperr (rx_disp_err[7]),
.rx_errdetect (rx_char_err_gx[7]),
.rx_patterndetect (rx_patterndetect[7]),
.rx_rlv (rx_runlengthviolation[7]),
.rx_seriallpbken (sd_loopback_7),
.rx_syncstatus (rx_syncstatus[7]),
.tx_clkout (tx_pcs_clk_c7),
.tx_ctrlenable (tx_kchar_7),
.tx_datain (tx_frame_7),
.rx_freqlocked (rx_freqlocked_7),
.tx_dataout (txp_7),
.tx_digitalreset (tx_digitalreset_sqcnr_7),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
.rx_runningdisp(rx_runningdisp[7]),
.pll_powerdown(gxb_pwrdn_in_sig[7]),
.pll_locked(pll_locked_7)
);
defparam
the_altera_tse_gxb_gige_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_7.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_7.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 28,
the_altera_tse_gxb_gige_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_7 = {17{1'b0}};
assign led_char_err_gx[7] = 1'b0;
assign link_status[7] = 1'b0;
assign led_disp_err_7 = 1'b0;
assign txp_7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_8,gxb_pwrdn_in_sig_clk_8;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 8)
begin
always @(posedge clk or posedge gxb_pwrdn_in_8)
begin
if (gxb_pwrdn_in_8 == 1) begin
data_in_8 <= 1;
gxb_pwrdn_in_sig_clk_8 <= 1;
end else begin
data_in_8 <= 1'b0;
gxb_pwrdn_in_sig_clk_8 <= data_in_8;
end
end
assign gxb_pwrdn_in_sig[8] = gxb_pwrdn_in_8;
assign pcs_pwrdn_out_8 = pcs_pwrdn_out_sig[8];
end
else
begin
assign gxb_pwrdn_in_sig[8] = pcs_pwrdn_out_sig[8];
assign pcs_pwrdn_out_8 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_8 = gxb_pwrdn_in_sig[8];
end
end
endgenerate
generate if (MAX_CHANNELS > 8)
begin
wire locked_signal_8;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_8(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_8),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_8),// output
.tx_digitalreset(tx_digitalreset_sqcnr_8),// output
.rx_analogreset(rx_analogreset_sqcnr_8),// output
.rx_digitalreset(rx_digitalreset_sqcnr_8),// output
.gxb_powerdown(gxb_powerdown_sqcnr_8),// output
.pll_is_locked(locked_signal_8),
.rx_is_lockedtodata(rx_freqlocked_8),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_8)
);
assign locked_signal_8 = (reset? 1'b0: pll_locked_8);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_8_reset_sync_0 (
.clk(rx_pcs_clk_c8),
.reset_in(rx_digitalreset_sqcnr_8),
.reset_out(reset_rx_pcs_clk_c8_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
(
.clk(rx_pcs_clk_c8),
.reset(reset_rx_pcs_clk_c8_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_8),
.alt_sync(rx_syncstatus[8]),
.alt_disperr(rx_disp_err[8]),
.alt_ctrldetect(rx_kchar_8),
.alt_errdetect(rx_char_err_gx[8]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
.alt_runlengthviolation(rx_runlengthviolation[8]),
.alt_patterndetect(rx_patterndetect[8]),
.alt_runningdisp(rx_runningdisp[8]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_8),
.altpcs_sync(link_status[8]),
.altpcs_disperr(led_disp_err_8),
.altpcs_ctrldetect(pcs_rx_kchar_8),
.altpcs_errdetect(led_char_err_gx[8]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[8])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_8
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[8]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_8),
.reconfig_clk(reconfig_clk_8),
.reconfig_togxb(reconfig_togxb_8),
.reconfig_fromgxb(reconfig_fromgxb_8),
.rx_analogreset (rx_analogreset_sqcnr_8),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_8),
.rx_clkout (rx_pcs_clk_c8),
.rx_datain (rxp_8),
.rx_dataout (rx_frame_8),
.rx_digitalreset (rx_digitalreset_sqcnr_8),
.rx_disperr (rx_disp_err[8]),
.rx_errdetect (rx_char_err_gx[8]),
.rx_patterndetect (rx_patterndetect[8]),
.rx_rlv (rx_runlengthviolation[8]),
.rx_seriallpbken (sd_loopback_8),
.rx_syncstatus (rx_syncstatus[8]),
.tx_clkout (tx_pcs_clk_c8),
.tx_ctrlenable (tx_kchar_8),
.tx_datain (tx_frame_8),
.rx_freqlocked (rx_freqlocked_8),
.tx_dataout (txp_8),
.tx_digitalreset (tx_digitalreset_sqcnr_8),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
.rx_runningdisp(rx_runningdisp[8]),
.pll_powerdown(gxb_pwrdn_in_sig[8]),
.pll_locked(pll_locked_8)
);
defparam
the_altera_tse_gxb_gige_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_8.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_8.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 32,
the_altera_tse_gxb_gige_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_8 = {17{1'b0}};
assign led_char_err_gx[8] = 1'b0;
assign link_status[8] = 1'b0;
assign led_disp_err_8 = 1'b0;
assign txp_8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_9,gxb_pwrdn_in_sig_clk_9;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 9)
begin
always @(posedge clk or posedge gxb_pwrdn_in_9)
begin
if (gxb_pwrdn_in_9 == 1) begin
data_in_9 <= 1;
gxb_pwrdn_in_sig_clk_9 <= 1;
end else begin
data_in_9 <= 1'b0;
gxb_pwrdn_in_sig_clk_9 <= data_in_9;
end
end
assign gxb_pwrdn_in_sig[9] = gxb_pwrdn_in_9;
assign pcs_pwrdn_out_9 = pcs_pwrdn_out_sig[9];
end
else
begin
assign gxb_pwrdn_in_sig[9] = pcs_pwrdn_out_sig[9];
assign pcs_pwrdn_out_9 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_9 = gxb_pwrdn_in_sig[9];
end
end
endgenerate
generate if (MAX_CHANNELS > 9)
begin
wire locked_signal_9;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_9(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_9),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_9),// output
.tx_digitalreset(tx_digitalreset_sqcnr_9),// output
.rx_analogreset(rx_analogreset_sqcnr_9),// output
.rx_digitalreset(rx_digitalreset_sqcnr_9),// output
.gxb_powerdown(gxb_powerdown_sqcnr_9),// output
.pll_is_locked(locked_signal_9),
.rx_is_lockedtodata(rx_freqlocked_9),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_9)
);
assign locked_signal_9 = (reset? 1'b0: pll_locked_9);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_9_reset_sync_0 (
.clk(rx_pcs_clk_c9),
.reset_in(rx_digitalreset_sqcnr_9),
.reset_out(reset_rx_pcs_clk_c9_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
(
.clk(rx_pcs_clk_c9),
.reset(reset_rx_pcs_clk_c9_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_9),
.alt_sync(rx_syncstatus[9]),
.alt_disperr(rx_disp_err[9]),
.alt_ctrldetect(rx_kchar_9),
.alt_errdetect(rx_char_err_gx[9]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
.alt_runlengthviolation(rx_runlengthviolation[9]),
.alt_patterndetect(rx_patterndetect[9]),
.alt_runningdisp(rx_runningdisp[9]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_9),
.altpcs_sync(link_status[9]),
.altpcs_disperr(led_disp_err_9),
.altpcs_ctrldetect(pcs_rx_kchar_9),
.altpcs_errdetect(led_char_err_gx[9]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[9])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_9
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[9]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_9),
.reconfig_clk(reconfig_clk_9),
.reconfig_togxb(reconfig_togxb_9),
.reconfig_fromgxb(reconfig_fromgxb_9),
.rx_analogreset (rx_analogreset_sqcnr_9),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_9),
.rx_clkout (rx_pcs_clk_c9),
.rx_datain (rxp_9),
.rx_dataout (rx_frame_9),
.rx_digitalreset (rx_digitalreset_sqcnr_9),
.rx_disperr (rx_disp_err[9]),
.rx_errdetect (rx_char_err_gx[9]),
.rx_patterndetect (rx_patterndetect[9]),
.rx_rlv (rx_runlengthviolation[9]),
.rx_seriallpbken (sd_loopback_9),
.rx_syncstatus (rx_syncstatus[9]),
.tx_clkout (tx_pcs_clk_c9),
.tx_ctrlenable (tx_kchar_9),
.tx_datain (tx_frame_9),
.rx_freqlocked (rx_freqlocked_9),
.tx_dataout (txp_9),
.tx_digitalreset (tx_digitalreset_sqcnr_9),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
.rx_runningdisp(rx_runningdisp[9]),
.pll_powerdown(gxb_pwrdn_in_sig[9]),
.pll_locked(pll_locked_9)
);
defparam
the_altera_tse_gxb_gige_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_9.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_9.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 36,
the_altera_tse_gxb_gige_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_9 = {17{1'b0}};
assign led_char_err_gx[9] = 1'b0;
assign link_status[9] = 1'b0;
assign led_disp_err_9 = 1'b0;
assign txp_9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_10,gxb_pwrdn_in_sig_clk_10;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 10)
begin
always @(posedge clk or posedge gxb_pwrdn_in_10)
begin
if (gxb_pwrdn_in_10 == 1) begin
data_in_10 <= 1;
gxb_pwrdn_in_sig_clk_10 <= 1;
end else begin
data_in_10 <= 1'b0;
gxb_pwrdn_in_sig_clk_10 <= data_in_10;
end
end
assign gxb_pwrdn_in_sig[10] = gxb_pwrdn_in_10;
assign pcs_pwrdn_out_10 = pcs_pwrdn_out_sig[10];
end
else
begin
assign gxb_pwrdn_in_sig[10] = pcs_pwrdn_out_sig[10];
assign pcs_pwrdn_out_10 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_10 = gxb_pwrdn_in_sig[10];
end
end
endgenerate
generate if (MAX_CHANNELS > 10)
begin
wire locked_signal_10;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_10(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_10),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_10),// output
.tx_digitalreset(tx_digitalreset_sqcnr_10),// output
.rx_analogreset(rx_analogreset_sqcnr_10),// output
.rx_digitalreset(rx_digitalreset_sqcnr_10),// output
.gxb_powerdown(gxb_powerdown_sqcnr_10),// output
.pll_is_locked(locked_signal_10),
.rx_is_lockedtodata(rx_freqlocked_10),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_10)
);
assign locked_signal_10 = (reset? 1'b0: pll_locked_10);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_10_reset_sync_0 (
.clk(rx_pcs_clk_c10),
.reset_in(rx_digitalreset_sqcnr_10),
.reset_out(reset_rx_pcs_clk_c10_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
(
.clk(rx_pcs_clk_c10),
.reset(reset_rx_pcs_clk_c10_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_10),
.alt_sync(rx_syncstatus[10]),
.alt_disperr(rx_disp_err[10]),
.alt_ctrldetect(rx_kchar_10),
.alt_errdetect(rx_char_err_gx[10]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
.alt_runlengthviolation(rx_runlengthviolation[10]),
.alt_patterndetect(rx_patterndetect[10]),
.alt_runningdisp(rx_runningdisp[10]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_10),
.altpcs_sync(link_status[10]),
.altpcs_disperr(led_disp_err_10),
.altpcs_ctrldetect(pcs_rx_kchar_10),
.altpcs_errdetect(led_char_err_gx[10]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[10])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_10
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[10]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_10),
.reconfig_clk(reconfig_clk_10),
.reconfig_togxb(reconfig_togxb_10),
.reconfig_fromgxb(reconfig_fromgxb_10),
.rx_analogreset (rx_analogreset_sqcnr_10),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_10),
.rx_clkout (rx_pcs_clk_c10),
.rx_datain (rxp_10),
.rx_dataout (rx_frame_10),
.rx_digitalreset (rx_digitalreset_sqcnr_10),
.rx_disperr (rx_disp_err[10]),
.rx_errdetect (rx_char_err_gx[10]),
.rx_patterndetect (rx_patterndetect[10]),
.rx_rlv (rx_runlengthviolation[10]),
.rx_seriallpbken (sd_loopback_10),
.rx_syncstatus (rx_syncstatus[10]),
.tx_clkout (tx_pcs_clk_c10),
.tx_ctrlenable (tx_kchar_10),
.tx_datain (tx_frame_10),
.rx_freqlocked (rx_freqlocked_10),
.tx_dataout (txp_10),
.tx_digitalreset (tx_digitalreset_sqcnr_10),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
.rx_runningdisp(rx_runningdisp[10]),
.pll_powerdown(gxb_pwrdn_in_sig[10]),
.pll_locked(pll_locked_10)
);
defparam
the_altera_tse_gxb_gige_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_10.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_10.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 40,
the_altera_tse_gxb_gige_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_10 = {17{1'b0}};
assign led_char_err_gx[10] = 1'b0;
assign link_status[10] = 1'b0;
assign led_disp_err_10 = 1'b0;
assign txp_10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_11,gxb_pwrdn_in_sig_clk_11;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 11)
begin
always @(posedge clk or posedge gxb_pwrdn_in_11)
begin
if (gxb_pwrdn_in_11 == 1) begin
data_in_11 <= 1;
gxb_pwrdn_in_sig_clk_11 <= 1;
end else begin
data_in_11 <= 1'b0;
gxb_pwrdn_in_sig_clk_11 <= data_in_11;
end
end
assign gxb_pwrdn_in_sig[11] = gxb_pwrdn_in_11;
assign pcs_pwrdn_out_11 = pcs_pwrdn_out_sig[11];
end
else
begin
assign gxb_pwrdn_in_sig[11] = pcs_pwrdn_out_sig[11];
assign pcs_pwrdn_out_11 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_11 = gxb_pwrdn_in_sig[11];
end
end
endgenerate
generate if (MAX_CHANNELS > 11)
begin
wire locked_signal_11;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_11(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_11),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_11),// output
.tx_digitalreset(tx_digitalreset_sqcnr_11),// output
.rx_analogreset(rx_analogreset_sqcnr_11),// output
.rx_digitalreset(rx_digitalreset_sqcnr_11),// output
.gxb_powerdown(gxb_powerdown_sqcnr_11),// output
.pll_is_locked(locked_signal_11),
.rx_is_lockedtodata(rx_freqlocked_11),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_11)
);
assign locked_signal_11 = (reset? 1'b0: pll_locked_11);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_11_reset_sync_0 (
.clk(rx_pcs_clk_c11),
.reset_in(rx_digitalreset_sqcnr_11),
.reset_out(reset_rx_pcs_clk_c11_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
(
.clk(rx_pcs_clk_c11),
.reset(reset_rx_pcs_clk_c11_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_11),
.alt_sync(rx_syncstatus[11]),
.alt_disperr(rx_disp_err[11]),
.alt_ctrldetect(rx_kchar_11),
.alt_errdetect(rx_char_err_gx[11]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
.alt_runlengthviolation(rx_runlengthviolation[11]),
.alt_patterndetect(rx_patterndetect[11]),
.alt_runningdisp(rx_runningdisp[11]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_11),
.altpcs_sync(link_status[11]),
.altpcs_disperr(led_disp_err_11),
.altpcs_ctrldetect(pcs_rx_kchar_11),
.altpcs_errdetect(led_char_err_gx[11]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[11])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_11
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[11]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_11),
.reconfig_clk(reconfig_clk_11),
.reconfig_togxb(reconfig_togxb_11),
.reconfig_fromgxb(reconfig_fromgxb_11),
.rx_analogreset (rx_analogreset_sqcnr_11),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_11),
.rx_clkout (rx_pcs_clk_c11),
.rx_datain (rxp_11),
.rx_dataout (rx_frame_11),
.rx_digitalreset (rx_digitalreset_sqcnr_11),
.rx_disperr (rx_disp_err[11]),
.rx_errdetect (rx_char_err_gx[11]),
.rx_patterndetect (rx_patterndetect[11]),
.rx_rlv (rx_runlengthviolation[11]),
.rx_seriallpbken (sd_loopback_11),
.rx_syncstatus (rx_syncstatus[11]),
.tx_clkout (tx_pcs_clk_c11),
.tx_ctrlenable (tx_kchar_11),
.tx_datain (tx_frame_11),
.rx_freqlocked (rx_freqlocked_11),
.tx_dataout (txp_11),
.tx_digitalreset (tx_digitalreset_sqcnr_11),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
.rx_runningdisp(rx_runningdisp[11]),
.pll_powerdown(gxb_pwrdn_in_sig[11]),
.pll_locked(pll_locked_11)
);
defparam
the_altera_tse_gxb_gige_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_11.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_11.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 44,
the_altera_tse_gxb_gige_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_11 = {17{1'b0}};
assign led_char_err_gx[11] = 1'b0;
assign link_status[11] = 1'b0;
assign led_disp_err_11 = 1'b0;
assign txp_11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_12,gxb_pwrdn_in_sig_clk_12;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 12)
begin
always @(posedge clk or posedge gxb_pwrdn_in_12)
begin
if (gxb_pwrdn_in_12 == 1) begin
data_in_12 <= 1;
gxb_pwrdn_in_sig_clk_12 <= 1;
end else begin
data_in_12 <= 1'b0;
gxb_pwrdn_in_sig_clk_12 <= data_in_12;
end
end
assign gxb_pwrdn_in_sig[12] = gxb_pwrdn_in_12;
assign pcs_pwrdn_out_12 = pcs_pwrdn_out_sig[12];
end
else
begin
assign gxb_pwrdn_in_sig[12] = pcs_pwrdn_out_sig[12];
assign pcs_pwrdn_out_12 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_12 = gxb_pwrdn_in_sig[12];
end
end
endgenerate
generate if (MAX_CHANNELS > 12)
begin
wire locked_signal_12;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_12(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_12),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_12),// output
.tx_digitalreset(tx_digitalreset_sqcnr_12),// output
.rx_analogreset(rx_analogreset_sqcnr_12),// output
.rx_digitalreset(rx_digitalreset_sqcnr_12),// output
.gxb_powerdown(gxb_powerdown_sqcnr_12),// output
.pll_is_locked(locked_signal_12),
.rx_is_lockedtodata(rx_freqlocked_12),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_12)
);
assign locked_signal_12 = (reset? 1'b0: pll_locked_12);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_12_reset_sync_0 (
.clk(rx_pcs_clk_c12),
.reset_in(rx_digitalreset_sqcnr_12),
.reset_out(reset_rx_pcs_clk_c12_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
(
.clk(rx_pcs_clk_c12),
.reset(reset_rx_pcs_clk_c12_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_12),
.alt_sync(rx_syncstatus[12]),
.alt_disperr(rx_disp_err[12]),
.alt_ctrldetect(rx_kchar_12),
.alt_errdetect(rx_char_err_gx[12]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
.alt_runlengthviolation(rx_runlengthviolation[12]),
.alt_patterndetect(rx_patterndetect[12]),
.alt_runningdisp(rx_runningdisp[12]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_12),
.altpcs_sync(link_status[12]),
.altpcs_disperr(led_disp_err_12),
.altpcs_ctrldetect(pcs_rx_kchar_12),
.altpcs_errdetect(led_char_err_gx[12]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[12])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_12
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[12]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_12),
.reconfig_clk(reconfig_clk_12),
.reconfig_togxb(reconfig_togxb_12),
.reconfig_fromgxb(reconfig_fromgxb_12),
.rx_analogreset (rx_analogreset_sqcnr_12),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_12),
.rx_clkout (rx_pcs_clk_c12),
.rx_datain (rxp_12),
.rx_dataout (rx_frame_12),
.rx_digitalreset (rx_digitalreset_sqcnr_12),
.rx_disperr (rx_disp_err[12]),
.rx_errdetect (rx_char_err_gx[12]),
.rx_patterndetect (rx_patterndetect[12]),
.rx_rlv (rx_runlengthviolation[12]),
.rx_seriallpbken (sd_loopback_12),
.rx_syncstatus (rx_syncstatus[12]),
.tx_clkout (tx_pcs_clk_c12),
.tx_ctrlenable (tx_kchar_12),
.tx_datain (tx_frame_12),
.rx_freqlocked (rx_freqlocked_12),
.tx_dataout (txp_12),
.tx_digitalreset (tx_digitalreset_sqcnr_12),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
.rx_runningdisp(rx_runningdisp[12]),
.pll_powerdown(gxb_pwrdn_in_sig[12]),
.pll_locked(pll_locked_12)
);
defparam
the_altera_tse_gxb_gige_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_12.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_12.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 48,
the_altera_tse_gxb_gige_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_12 = {17{1'b0}};
assign led_char_err_gx[12] = 1'b0;
assign link_status[12] = 1'b0;
assign led_disp_err_12 = 1'b0;
assign txp_12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_13,gxb_pwrdn_in_sig_clk_13;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 13)
begin
always @(posedge clk or posedge gxb_pwrdn_in_13)
begin
if (gxb_pwrdn_in_13 == 1) begin
data_in_13 <= 1;
gxb_pwrdn_in_sig_clk_13 <= 1;
end else begin
data_in_13 <= 1'b0;
gxb_pwrdn_in_sig_clk_13 <= data_in_13;
end
end
assign gxb_pwrdn_in_sig[13] = gxb_pwrdn_in_13;
assign pcs_pwrdn_out_13 = pcs_pwrdn_out_sig[13];
end
else
begin
assign gxb_pwrdn_in_sig[13] = pcs_pwrdn_out_sig[13];
assign pcs_pwrdn_out_13 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_13 = gxb_pwrdn_in_sig[13];
end
end
endgenerate
generate if (MAX_CHANNELS > 13)
begin
wire locked_signal_13;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_13(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_13),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_13),// output
.tx_digitalreset(tx_digitalreset_sqcnr_13),// output
.rx_analogreset(rx_analogreset_sqcnr_13),// output
.rx_digitalreset(rx_digitalreset_sqcnr_13),// output
.gxb_powerdown(gxb_powerdown_sqcnr_13),// output
.pll_is_locked(locked_signal_13),
.rx_is_lockedtodata(rx_freqlocked_13),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_13)
);
assign locked_signal_13 = (reset? 1'b0: pll_locked_13);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_13_reset_sync_0 (
.clk(rx_pcs_clk_c13),
.reset_in(rx_digitalreset_sqcnr_13),
.reset_out(reset_rx_pcs_clk_c13_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
(
.clk(rx_pcs_clk_c13),
.reset(reset_rx_pcs_clk_c13_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_13),
.alt_sync(rx_syncstatus[13]),
.alt_disperr(rx_disp_err[13]),
.alt_ctrldetect(rx_kchar_13),
.alt_errdetect(rx_char_err_gx[13]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
.alt_runlengthviolation(rx_runlengthviolation[13]),
.alt_patterndetect(rx_patterndetect[13]),
.alt_runningdisp(rx_runningdisp[13]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_13),
.altpcs_sync(link_status[13]),
.altpcs_disperr(led_disp_err_13),
.altpcs_ctrldetect(pcs_rx_kchar_13),
.altpcs_errdetect(led_char_err_gx[13]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[13])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_13
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[13]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_13),
.reconfig_clk(reconfig_clk_13),
.reconfig_togxb(reconfig_togxb_13),
.reconfig_fromgxb(reconfig_fromgxb_13),
.rx_analogreset (rx_analogreset_sqcnr_13),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_13),
.rx_clkout (rx_pcs_clk_c13),
.rx_datain (rxp_13),
.rx_dataout (rx_frame_13),
.rx_digitalreset (rx_digitalreset_sqcnr_13),
.rx_disperr (rx_disp_err[13]),
.rx_errdetect (rx_char_err_gx[13]),
.rx_patterndetect (rx_patterndetect[13]),
.rx_rlv (rx_runlengthviolation[13]),
.rx_seriallpbken (sd_loopback_13),
.rx_syncstatus (rx_syncstatus[13]),
.tx_clkout (tx_pcs_clk_c13),
.tx_ctrlenable (tx_kchar_13),
.tx_datain (tx_frame_13),
.rx_freqlocked (rx_freqlocked_13),
.tx_dataout (txp_13),
.tx_digitalreset (tx_digitalreset_sqcnr_13),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
.rx_runningdisp(rx_runningdisp[13]),
.pll_powerdown(gxb_pwrdn_in_sig[13]),
.pll_locked(pll_locked_13)
);
defparam
the_altera_tse_gxb_gige_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_13.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_13.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 52,
the_altera_tse_gxb_gige_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_13 = {17{1'b0}};
assign led_char_err_gx[13] = 1'b0;
assign link_status[13] = 1'b0;
assign led_disp_err_13 = 1'b0;
assign txp_13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_14,gxb_pwrdn_in_sig_clk_14;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 14)
begin
always @(posedge clk or posedge gxb_pwrdn_in_14)
begin
if (gxb_pwrdn_in_14 == 1) begin
data_in_14 <= 1;
gxb_pwrdn_in_sig_clk_14 <= 1;
end else begin
data_in_14 <= 1'b0;
gxb_pwrdn_in_sig_clk_14 <= data_in_14;
end
end
assign gxb_pwrdn_in_sig[14] = gxb_pwrdn_in_14;
assign pcs_pwrdn_out_14 = pcs_pwrdn_out_sig[14];
end
else
begin
assign gxb_pwrdn_in_sig[14] = pcs_pwrdn_out_sig[14];
assign pcs_pwrdn_out_14 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_14 = gxb_pwrdn_in_sig[14];
end
end
endgenerate
generate if (MAX_CHANNELS > 14)
begin
wire locked_signal_14;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_14(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_14),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_14),// output
.tx_digitalreset(tx_digitalreset_sqcnr_14),// output
.rx_analogreset(rx_analogreset_sqcnr_14),// output
.rx_digitalreset(rx_digitalreset_sqcnr_14),// output
.gxb_powerdown(gxb_powerdown_sqcnr_14),// output
.pll_is_locked(locked_signal_14),
.rx_is_lockedtodata(rx_freqlocked_14),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_14)
);
assign locked_signal_14 = (reset? 1'b0: pll_locked_14);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_14_reset_sync_0 (
.clk(rx_pcs_clk_c14),
.reset_in(rx_digitalreset_sqcnr_14),
.reset_out(reset_rx_pcs_clk_c14_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
(
.clk(rx_pcs_clk_c14),
.reset(reset_rx_pcs_clk_c14_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_14),
.alt_sync(rx_syncstatus[14]),
.alt_disperr(rx_disp_err[14]),
.alt_ctrldetect(rx_kchar_14),
.alt_errdetect(rx_char_err_gx[14]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
.alt_runlengthviolation(rx_runlengthviolation[14]),
.alt_patterndetect(rx_patterndetect[14]),
.alt_runningdisp(rx_runningdisp[14]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_14),
.altpcs_sync(link_status[14]),
.altpcs_disperr(led_disp_err_14),
.altpcs_ctrldetect(pcs_rx_kchar_14),
.altpcs_errdetect(led_char_err_gx[14]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[14])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_14
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[14]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_14),
.reconfig_clk(reconfig_clk_14),
.reconfig_togxb(reconfig_togxb_14),
.reconfig_fromgxb(reconfig_fromgxb_14),
.rx_analogreset (rx_analogreset_sqcnr_14),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_14),
.rx_clkout (rx_pcs_clk_c14),
.rx_datain (rxp_14),
.rx_dataout (rx_frame_14),
.rx_digitalreset (rx_digitalreset_sqcnr_14),
.rx_disperr (rx_disp_err[14]),
.rx_errdetect (rx_char_err_gx[14]),
.rx_patterndetect (rx_patterndetect[14]),
.rx_rlv (rx_runlengthviolation[14]),
.rx_seriallpbken (sd_loopback_14),
.rx_syncstatus (rx_syncstatus[14]),
.tx_clkout (tx_pcs_clk_c14),
.tx_ctrlenable (tx_kchar_14),
.tx_datain (tx_frame_14),
.rx_freqlocked (rx_freqlocked_14),
.tx_dataout (txp_14),
.tx_digitalreset (tx_digitalreset_sqcnr_14),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
.rx_runningdisp(rx_runningdisp[14]),
.pll_powerdown(gxb_pwrdn_in_sig[14]),
.pll_locked(pll_locked_14)
);
defparam
the_altera_tse_gxb_gige_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_14.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_14.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 56,
the_altera_tse_gxb_gige_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_14 = {17{1'b0}};
assign led_char_err_gx[14] = 1'b0;
assign link_status[14] = 1'b0;
assign led_disp_err_14 = 1'b0;
assign txp_14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_15,gxb_pwrdn_in_sig_clk_15;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 15)
begin
always @(posedge clk or posedge gxb_pwrdn_in_15)
begin
if (gxb_pwrdn_in_15 == 1) begin
data_in_15 <= 1;
gxb_pwrdn_in_sig_clk_15 <= 1;
end else begin
data_in_15 <= 1'b0;
gxb_pwrdn_in_sig_clk_15 <= data_in_15;
end
end
assign gxb_pwrdn_in_sig[15] = gxb_pwrdn_in_15;
assign pcs_pwrdn_out_15 = pcs_pwrdn_out_sig[15];
end
else
begin
assign gxb_pwrdn_in_sig[15] = pcs_pwrdn_out_sig[15];
assign pcs_pwrdn_out_15 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_15 = gxb_pwrdn_in_sig[15];
end
end
endgenerate
generate if (MAX_CHANNELS > 15)
begin
wire locked_signal_15;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_15(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_15),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_15),// output
.tx_digitalreset(tx_digitalreset_sqcnr_15),// output
.rx_analogreset(rx_analogreset_sqcnr_15),// output
.rx_digitalreset(rx_digitalreset_sqcnr_15),// output
.gxb_powerdown(gxb_powerdown_sqcnr_15),// output
.pll_is_locked(locked_signal_15),
.rx_is_lockedtodata(rx_freqlocked_15),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_15)
);
assign locked_signal_15 = (reset? 1'b0: pll_locked_15);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_15_reset_sync_0 (
.clk(rx_pcs_clk_c15),
.reset_in(rx_digitalreset_sqcnr_15),
.reset_out(reset_rx_pcs_clk_c15_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
(
.clk(rx_pcs_clk_c15),
.reset(reset_rx_pcs_clk_c15_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_15),
.alt_sync(rx_syncstatus[15]),
.alt_disperr(rx_disp_err[15]),
.alt_ctrldetect(rx_kchar_15),
.alt_errdetect(rx_char_err_gx[15]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
.alt_runlengthviolation(rx_runlengthviolation[15]),
.alt_patterndetect(rx_patterndetect[15]),
.alt_runningdisp(rx_runningdisp[15]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_15),
.altpcs_sync(link_status[15]),
.altpcs_disperr(led_disp_err_15),
.altpcs_ctrldetect(pcs_rx_kchar_15),
.altpcs_errdetect(led_char_err_gx[15]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[15])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_15
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[15]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_15),
.reconfig_clk(reconfig_clk_15),
.reconfig_togxb(reconfig_togxb_15),
.reconfig_fromgxb(reconfig_fromgxb_15),
.rx_analogreset (rx_analogreset_sqcnr_15),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_15),
.rx_clkout (rx_pcs_clk_c15),
.rx_datain (rxp_15),
.rx_dataout (rx_frame_15),
.rx_digitalreset (rx_digitalreset_sqcnr_15),
.rx_disperr (rx_disp_err[15]),
.rx_errdetect (rx_char_err_gx[15]),
.rx_patterndetect (rx_patterndetect[15]),
.rx_rlv (rx_runlengthviolation[15]),
.rx_seriallpbken (sd_loopback_15),
.rx_syncstatus (rx_syncstatus[15]),
.tx_clkout (tx_pcs_clk_c15),
.tx_ctrlenable (tx_kchar_15),
.tx_datain (tx_frame_15),
.rx_freqlocked (rx_freqlocked_15),
.tx_dataout (txp_15),
.tx_digitalreset (tx_digitalreset_sqcnr_15),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
.rx_runningdisp(rx_runningdisp[15]),
.pll_powerdown(gxb_pwrdn_in_sig[15]),
.pll_locked(pll_locked_15)
);
defparam
the_altera_tse_gxb_gige_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_15.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_15.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 60,
the_altera_tse_gxb_gige_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_15 = {17{1'b0}};
assign led_char_err_gx[15] = 1'b0;
assign link_status[15] = 1'b0;
assign led_disp_err_15 = 1'b0;
assign txp_15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_16,gxb_pwrdn_in_sig_clk_16;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 16)
begin
always @(posedge clk or posedge gxb_pwrdn_in_16)
begin
if (gxb_pwrdn_in_16 == 1) begin
data_in_16 <= 1;
gxb_pwrdn_in_sig_clk_16 <= 1;
end else begin
data_in_16 <= 1'b0;
gxb_pwrdn_in_sig_clk_16 <= data_in_16;
end
end
assign gxb_pwrdn_in_sig[16] = gxb_pwrdn_in_16;
assign pcs_pwrdn_out_16 = pcs_pwrdn_out_sig[16];
end
else
begin
assign gxb_pwrdn_in_sig[16] = pcs_pwrdn_out_sig[16];
assign pcs_pwrdn_out_16 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_16 = gxb_pwrdn_in_sig[16];
end
end
endgenerate
generate if (MAX_CHANNELS > 16)
begin
wire locked_signal_16;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_16(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_16),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_16),// output
.tx_digitalreset(tx_digitalreset_sqcnr_16),// output
.rx_analogreset(rx_analogreset_sqcnr_16),// output
.rx_digitalreset(rx_digitalreset_sqcnr_16),// output
.gxb_powerdown(gxb_powerdown_sqcnr_16),// output
.pll_is_locked(locked_signal_16),
.rx_is_lockedtodata(rx_freqlocked_16),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_16)
);
assign locked_signal_16 = (reset? 1'b0: pll_locked_16);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_16_reset_sync_0 (
.clk(rx_pcs_clk_c16),
.reset_in(rx_digitalreset_sqcnr_16),
.reset_out(reset_rx_pcs_clk_c16_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
(
.clk(rx_pcs_clk_c16),
.reset(reset_rx_pcs_clk_c16_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_16),
.alt_sync(rx_syncstatus[16]),
.alt_disperr(rx_disp_err[16]),
.alt_ctrldetect(rx_kchar_16),
.alt_errdetect(rx_char_err_gx[16]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
.alt_runlengthviolation(rx_runlengthviolation[16]),
.alt_patterndetect(rx_patterndetect[16]),
.alt_runningdisp(rx_runningdisp[16]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_16),
.altpcs_sync(link_status[16]),
.altpcs_disperr(led_disp_err_16),
.altpcs_ctrldetect(pcs_rx_kchar_16),
.altpcs_errdetect(led_char_err_gx[16]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[16])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_16
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[16]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_16),
.reconfig_clk(reconfig_clk_16),
.reconfig_togxb(reconfig_togxb_16),
.reconfig_fromgxb(reconfig_fromgxb_16),
.rx_analogreset (rx_analogreset_sqcnr_16),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_16),
.rx_clkout (rx_pcs_clk_c16),
.rx_datain (rxp_16),
.rx_dataout (rx_frame_16),
.rx_digitalreset (rx_digitalreset_sqcnr_16),
.rx_disperr (rx_disp_err[16]),
.rx_errdetect (rx_char_err_gx[16]),
.rx_patterndetect (rx_patterndetect[16]),
.rx_rlv (rx_runlengthviolation[16]),
.rx_seriallpbken (sd_loopback_16),
.rx_syncstatus (rx_syncstatus[16]),
.tx_clkout (tx_pcs_clk_c16),
.tx_ctrlenable (tx_kchar_16),
.tx_datain (tx_frame_16),
.rx_freqlocked (rx_freqlocked_16),
.tx_dataout (txp_16),
.tx_digitalreset (tx_digitalreset_sqcnr_16),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
.rx_runningdisp(rx_runningdisp[16]),
.pll_powerdown(gxb_pwrdn_in_sig[16]),
.pll_locked(pll_locked_16)
);
defparam
the_altera_tse_gxb_gige_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_16.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_16.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 64,
the_altera_tse_gxb_gige_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_16 = {17{1'b0}};
assign led_char_err_gx[16] = 1'b0;
assign link_status[16] = 1'b0;
assign led_disp_err_16 = 1'b0;
assign txp_16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_17,gxb_pwrdn_in_sig_clk_17;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 17)
begin
always @(posedge clk or posedge gxb_pwrdn_in_17)
begin
if (gxb_pwrdn_in_17 == 1) begin
data_in_17 <= 1;
gxb_pwrdn_in_sig_clk_17 <= 1;
end else begin
data_in_17 <= 1'b0;
gxb_pwrdn_in_sig_clk_17 <= data_in_17;
end
end
assign gxb_pwrdn_in_sig[17] = gxb_pwrdn_in_17;
assign pcs_pwrdn_out_17 = pcs_pwrdn_out_sig[17];
end
else
begin
assign gxb_pwrdn_in_sig[17] = pcs_pwrdn_out_sig[17];
assign pcs_pwrdn_out_17 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_17 = gxb_pwrdn_in_sig[17];
end
end
endgenerate
generate if (MAX_CHANNELS > 17)
begin
wire locked_signal_17;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_17(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_17),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_17),// output
.tx_digitalreset(tx_digitalreset_sqcnr_17),// output
.rx_analogreset(rx_analogreset_sqcnr_17),// output
.rx_digitalreset(rx_digitalreset_sqcnr_17),// output
.gxb_powerdown(gxb_powerdown_sqcnr_17),// output
.pll_is_locked(locked_signal_17),
.rx_is_lockedtodata(rx_freqlocked_17),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_17)
);
assign locked_signal_17 = (reset? 1'b0: pll_locked_17);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_17_reset_sync_0 (
.clk(rx_pcs_clk_c17),
.reset_in(rx_digitalreset_sqcnr_17),
.reset_out(reset_rx_pcs_clk_c17_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
(
.clk(rx_pcs_clk_c17),
.reset(reset_rx_pcs_clk_c17_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_17),
.alt_sync(rx_syncstatus[17]),
.alt_disperr(rx_disp_err[17]),
.alt_ctrldetect(rx_kchar_17),
.alt_errdetect(rx_char_err_gx[17]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
.alt_runlengthviolation(rx_runlengthviolation[17]),
.alt_patterndetect(rx_patterndetect[17]),
.alt_runningdisp(rx_runningdisp[17]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_17),
.altpcs_sync(link_status[17]),
.altpcs_disperr(led_disp_err_17),
.altpcs_ctrldetect(pcs_rx_kchar_17),
.altpcs_errdetect(led_char_err_gx[17]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[17])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_17
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[17]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_17),
.reconfig_clk(reconfig_clk_17),
.reconfig_togxb(reconfig_togxb_17),
.reconfig_fromgxb(reconfig_fromgxb_17),
.rx_analogreset (rx_analogreset_sqcnr_17),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_17),
.rx_clkout (rx_pcs_clk_c17),
.rx_datain (rxp_17),
.rx_dataout (rx_frame_17),
.rx_digitalreset (rx_digitalreset_sqcnr_17),
.rx_disperr (rx_disp_err[17]),
.rx_errdetect (rx_char_err_gx[17]),
.rx_patterndetect (rx_patterndetect[17]),
.rx_rlv (rx_runlengthviolation[17]),
.rx_seriallpbken (sd_loopback_17),
.rx_syncstatus (rx_syncstatus[17]),
.tx_clkout (tx_pcs_clk_c17),
.tx_ctrlenable (tx_kchar_17),
.tx_datain (tx_frame_17),
.rx_freqlocked (rx_freqlocked_17),
.tx_dataout (txp_17),
.tx_digitalreset (tx_digitalreset_sqcnr_17),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
.rx_runningdisp(rx_runningdisp[17]),
.pll_powerdown(gxb_pwrdn_in_sig[17]),
.pll_locked(pll_locked_17)
);
defparam
the_altera_tse_gxb_gige_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_17.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_17.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 68,
the_altera_tse_gxb_gige_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_17 = {17{1'b0}};
assign led_char_err_gx[17] = 1'b0;
assign link_status[17] = 1'b0;
assign led_disp_err_17 = 1'b0;
assign txp_17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_18,gxb_pwrdn_in_sig_clk_18;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 18)
begin
always @(posedge clk or posedge gxb_pwrdn_in_18)
begin
if (gxb_pwrdn_in_18 == 1) begin
data_in_18 <= 1;
gxb_pwrdn_in_sig_clk_18 <= 1;
end else begin
data_in_18 <= 1'b0;
gxb_pwrdn_in_sig_clk_18 <= data_in_18;
end
end
assign gxb_pwrdn_in_sig[18] = gxb_pwrdn_in_18;
assign pcs_pwrdn_out_18 = pcs_pwrdn_out_sig[18];
end
else
begin
assign gxb_pwrdn_in_sig[18] = pcs_pwrdn_out_sig[18];
assign pcs_pwrdn_out_18 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_18 = gxb_pwrdn_in_sig[18];
end
end
endgenerate
generate if (MAX_CHANNELS > 18)
begin
wire locked_signal_18;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_18(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_18),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_18),// output
.tx_digitalreset(tx_digitalreset_sqcnr_18),// output
.rx_analogreset(rx_analogreset_sqcnr_18),// output
.rx_digitalreset(rx_digitalreset_sqcnr_18),// output
.gxb_powerdown(gxb_powerdown_sqcnr_18),// output
.pll_is_locked(locked_signal_18),
.rx_is_lockedtodata(rx_freqlocked_18),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_18)
);
assign locked_signal_18 = (reset? 1'b0: pll_locked_18);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_18_reset_sync_0 (
.clk(rx_pcs_clk_c18),
.reset_in(rx_digitalreset_sqcnr_18),
.reset_out(reset_rx_pcs_clk_c18_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
(
.clk(rx_pcs_clk_c18),
.reset(reset_rx_pcs_clk_c18_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_18),
.alt_sync(rx_syncstatus[18]),
.alt_disperr(rx_disp_err[18]),
.alt_ctrldetect(rx_kchar_18),
.alt_errdetect(rx_char_err_gx[18]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
.alt_runlengthviolation(rx_runlengthviolation[18]),
.alt_patterndetect(rx_patterndetect[18]),
.alt_runningdisp(rx_runningdisp[18]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_18),
.altpcs_sync(link_status[18]),
.altpcs_disperr(led_disp_err_18),
.altpcs_ctrldetect(pcs_rx_kchar_18),
.altpcs_errdetect(led_char_err_gx[18]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[18])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_18
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[18]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_18),
.reconfig_clk(reconfig_clk_18),
.reconfig_togxb(reconfig_togxb_18),
.reconfig_fromgxb(reconfig_fromgxb_18),
.rx_analogreset (rx_analogreset_sqcnr_18),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_18),
.rx_clkout (rx_pcs_clk_c18),
.rx_datain (rxp_18),
.rx_dataout (rx_frame_18),
.rx_digitalreset (rx_digitalreset_sqcnr_18),
.rx_disperr (rx_disp_err[18]),
.rx_errdetect (rx_char_err_gx[18]),
.rx_patterndetect (rx_patterndetect[18]),
.rx_rlv (rx_runlengthviolation[18]),
.rx_seriallpbken (sd_loopback_18),
.rx_syncstatus (rx_syncstatus[18]),
.tx_clkout (tx_pcs_clk_c18),
.tx_ctrlenable (tx_kchar_18),
.tx_datain (tx_frame_18),
.rx_freqlocked (rx_freqlocked_18),
.tx_dataout (txp_18),
.tx_digitalreset (tx_digitalreset_sqcnr_18),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
.rx_runningdisp(rx_runningdisp[18]),
.pll_powerdown(gxb_pwrdn_in_sig[18]),
.pll_locked(pll_locked_18)
);
defparam
the_altera_tse_gxb_gige_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_18.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_18.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 72,
the_altera_tse_gxb_gige_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_18 = {17{1'b0}};
assign led_char_err_gx[18] = 1'b0;
assign link_status[18] = 1'b0;
assign led_disp_err_18 = 1'b0;
assign txp_18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_19,gxb_pwrdn_in_sig_clk_19;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 19)
begin
always @(posedge clk or posedge gxb_pwrdn_in_19)
begin
if (gxb_pwrdn_in_19 == 1) begin
data_in_19 <= 1;
gxb_pwrdn_in_sig_clk_19 <= 1;
end else begin
data_in_19 <= 1'b0;
gxb_pwrdn_in_sig_clk_19 <= data_in_19;
end
end
assign gxb_pwrdn_in_sig[19] = gxb_pwrdn_in_19;
assign pcs_pwrdn_out_19 = pcs_pwrdn_out_sig[19];
end
else
begin
assign gxb_pwrdn_in_sig[19] = pcs_pwrdn_out_sig[19];
assign pcs_pwrdn_out_19 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_19 = gxb_pwrdn_in_sig[19];
end
end
endgenerate
generate if (MAX_CHANNELS > 19)
begin
wire locked_signal_19;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_19(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_19),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_19),// output
.tx_digitalreset(tx_digitalreset_sqcnr_19),// output
.rx_analogreset(rx_analogreset_sqcnr_19),// output
.rx_digitalreset(rx_digitalreset_sqcnr_19),// output
.gxb_powerdown(gxb_powerdown_sqcnr_19),// output
.pll_is_locked(locked_signal_19),
.rx_is_lockedtodata(rx_freqlocked_19),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_19)
);
assign locked_signal_19 = (reset? 1'b0: pll_locked_19);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_19_reset_sync_0 (
.clk(rx_pcs_clk_c19),
.reset_in(rx_digitalreset_sqcnr_19),
.reset_out(reset_rx_pcs_clk_c19_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
(
.clk(rx_pcs_clk_c19),
.reset(reset_rx_pcs_clk_c19_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_19),
.alt_sync(rx_syncstatus[19]),
.alt_disperr(rx_disp_err[19]),
.alt_ctrldetect(rx_kchar_19),
.alt_errdetect(rx_char_err_gx[19]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
.alt_runlengthviolation(rx_runlengthviolation[19]),
.alt_patterndetect(rx_patterndetect[19]),
.alt_runningdisp(rx_runningdisp[19]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_19),
.altpcs_sync(link_status[19]),
.altpcs_disperr(led_disp_err_19),
.altpcs_ctrldetect(pcs_rx_kchar_19),
.altpcs_errdetect(led_char_err_gx[19]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[19])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_19
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[19]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_19),
.reconfig_clk(reconfig_clk_19),
.reconfig_togxb(reconfig_togxb_19),
.reconfig_fromgxb(reconfig_fromgxb_19),
.rx_analogreset (rx_analogreset_sqcnr_19),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_19),
.rx_clkout (rx_pcs_clk_c19),
.rx_datain (rxp_19),
.rx_dataout (rx_frame_19),
.rx_digitalreset (rx_digitalreset_sqcnr_19),
.rx_disperr (rx_disp_err[19]),
.rx_errdetect (rx_char_err_gx[19]),
.rx_patterndetect (rx_patterndetect[19]),
.rx_rlv (rx_runlengthviolation[19]),
.rx_seriallpbken (sd_loopback_19),
.rx_syncstatus (rx_syncstatus[19]),
.tx_clkout (tx_pcs_clk_c19),
.tx_ctrlenable (tx_kchar_19),
.tx_datain (tx_frame_19),
.rx_freqlocked (rx_freqlocked_19),
.tx_dataout (txp_19),
.tx_digitalreset (tx_digitalreset_sqcnr_19),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
.rx_runningdisp(rx_runningdisp[19]),
.pll_powerdown(gxb_pwrdn_in_sig[19]),
.pll_locked(pll_locked_19)
);
defparam
the_altera_tse_gxb_gige_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_19.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_19.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 76,
the_altera_tse_gxb_gige_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_19 = {17{1'b0}};
assign led_char_err_gx[19] = 1'b0;
assign link_status[19] = 1'b0;
assign led_disp_err_19 = 1'b0;
assign txp_19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_20,gxb_pwrdn_in_sig_clk_20;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 20)
begin
always @(posedge clk or posedge gxb_pwrdn_in_20)
begin
if (gxb_pwrdn_in_20 == 1) begin
data_in_20 <= 1;
gxb_pwrdn_in_sig_clk_20 <= 1;
end else begin
data_in_20 <= 1'b0;
gxb_pwrdn_in_sig_clk_20 <= data_in_20;
end
end
assign gxb_pwrdn_in_sig[20] = gxb_pwrdn_in_20;
assign pcs_pwrdn_out_20 = pcs_pwrdn_out_sig[20];
end
else
begin
assign gxb_pwrdn_in_sig[20] = pcs_pwrdn_out_sig[20];
assign pcs_pwrdn_out_20 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_20 = gxb_pwrdn_in_sig[20];
end
end
endgenerate
generate if (MAX_CHANNELS > 20)
begin
wire locked_signal_20;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_20(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_20),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_20),// output
.tx_digitalreset(tx_digitalreset_sqcnr_20),// output
.rx_analogreset(rx_analogreset_sqcnr_20),// output
.rx_digitalreset(rx_digitalreset_sqcnr_20),// output
.gxb_powerdown(gxb_powerdown_sqcnr_20),// output
.pll_is_locked(locked_signal_20),
.rx_is_lockedtodata(rx_freqlocked_20),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_20)
);
assign locked_signal_20 = (reset? 1'b0: pll_locked_20);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_20_reset_sync_0 (
.clk(rx_pcs_clk_c20),
.reset_in(rx_digitalreset_sqcnr_20),
.reset_out(reset_rx_pcs_clk_c20_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
(
.clk(rx_pcs_clk_c20),
.reset(reset_rx_pcs_clk_c20_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_20),
.alt_sync(rx_syncstatus[20]),
.alt_disperr(rx_disp_err[20]),
.alt_ctrldetect(rx_kchar_20),
.alt_errdetect(rx_char_err_gx[20]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
.alt_runlengthviolation(rx_runlengthviolation[20]),
.alt_patterndetect(rx_patterndetect[20]),
.alt_runningdisp(rx_runningdisp[20]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_20),
.altpcs_sync(link_status[20]),
.altpcs_disperr(led_disp_err_20),
.altpcs_ctrldetect(pcs_rx_kchar_20),
.altpcs_errdetect(led_char_err_gx[20]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[20])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_20
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[20]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_20),
.reconfig_clk(reconfig_clk_20),
.reconfig_togxb(reconfig_togxb_20),
.reconfig_fromgxb(reconfig_fromgxb_20),
.rx_analogreset (rx_analogreset_sqcnr_20),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_20),
.rx_clkout (rx_pcs_clk_c20),
.rx_datain (rxp_20),
.rx_dataout (rx_frame_20),
.rx_digitalreset (rx_digitalreset_sqcnr_20),
.rx_disperr (rx_disp_err[20]),
.rx_errdetect (rx_char_err_gx[20]),
.rx_patterndetect (rx_patterndetect[20]),
.rx_rlv (rx_runlengthviolation[20]),
.rx_seriallpbken (sd_loopback_20),
.rx_syncstatus (rx_syncstatus[20]),
.tx_clkout (tx_pcs_clk_c20),
.tx_ctrlenable (tx_kchar_20),
.tx_datain (tx_frame_20),
.rx_freqlocked (rx_freqlocked_20),
.tx_dataout (txp_20),
.tx_digitalreset (tx_digitalreset_sqcnr_20),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
.rx_runningdisp(rx_runningdisp[20]),
.pll_powerdown(gxb_pwrdn_in_sig[20]),
.pll_locked(pll_locked_20)
);
defparam
the_altera_tse_gxb_gige_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_20.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_20.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 80,
the_altera_tse_gxb_gige_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_20 = {17{1'b0}};
assign led_char_err_gx[20] = 1'b0;
assign link_status[20] = 1'b0;
assign led_disp_err_20 = 1'b0;
assign txp_20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_21,gxb_pwrdn_in_sig_clk_21;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 21)
begin
always @(posedge clk or posedge gxb_pwrdn_in_21)
begin
if (gxb_pwrdn_in_21 == 1) begin
data_in_21 <= 1;
gxb_pwrdn_in_sig_clk_21 <= 1;
end else begin
data_in_21 <= 1'b0;
gxb_pwrdn_in_sig_clk_21 <= data_in_21;
end
end
assign gxb_pwrdn_in_sig[21] = gxb_pwrdn_in_21;
assign pcs_pwrdn_out_21 = pcs_pwrdn_out_sig[21];
end
else
begin
assign gxb_pwrdn_in_sig[21] = pcs_pwrdn_out_sig[21];
assign pcs_pwrdn_out_21 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_21 = gxb_pwrdn_in_sig[21];
end
end
endgenerate
generate if (MAX_CHANNELS > 21)
begin
wire locked_signal_21;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_21(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_21),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_21),// output
.tx_digitalreset(tx_digitalreset_sqcnr_21),// output
.rx_analogreset(rx_analogreset_sqcnr_21),// output
.rx_digitalreset(rx_digitalreset_sqcnr_21),// output
.gxb_powerdown(gxb_powerdown_sqcnr_21),// output
.pll_is_locked(locked_signal_21),
.rx_is_lockedtodata(rx_freqlocked_21),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_21)
);
assign locked_signal_21 = (reset? 1'b0: pll_locked_21);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_21_reset_sync_0 (
.clk(rx_pcs_clk_c21),
.reset_in(rx_digitalreset_sqcnr_21),
.reset_out(reset_rx_pcs_clk_c21_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
(
.clk(rx_pcs_clk_c21),
.reset(reset_rx_pcs_clk_c21_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_21),
.alt_sync(rx_syncstatus[21]),
.alt_disperr(rx_disp_err[21]),
.alt_ctrldetect(rx_kchar_21),
.alt_errdetect(rx_char_err_gx[21]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
.alt_runlengthviolation(rx_runlengthviolation[21]),
.alt_patterndetect(rx_patterndetect[21]),
.alt_runningdisp(rx_runningdisp[21]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_21),
.altpcs_sync(link_status[21]),
.altpcs_disperr(led_disp_err_21),
.altpcs_ctrldetect(pcs_rx_kchar_21),
.altpcs_errdetect(led_char_err_gx[21]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[21])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_21
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[21]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_21),
.reconfig_clk(reconfig_clk_21),
.reconfig_togxb(reconfig_togxb_21),
.reconfig_fromgxb(reconfig_fromgxb_21),
.rx_analogreset (rx_analogreset_sqcnr_21),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_21),
.rx_clkout (rx_pcs_clk_c21),
.rx_datain (rxp_21),
.rx_dataout (rx_frame_21),
.rx_digitalreset (rx_digitalreset_sqcnr_21),
.rx_disperr (rx_disp_err[21]),
.rx_errdetect (rx_char_err_gx[21]),
.rx_patterndetect (rx_patterndetect[21]),
.rx_rlv (rx_runlengthviolation[21]),
.rx_seriallpbken (sd_loopback_21),
.rx_syncstatus (rx_syncstatus[21]),
.tx_clkout (tx_pcs_clk_c21),
.tx_ctrlenable (tx_kchar_21),
.tx_datain (tx_frame_21),
.rx_freqlocked (rx_freqlocked_21),
.tx_dataout (txp_21),
.tx_digitalreset (tx_digitalreset_sqcnr_21),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
.rx_runningdisp(rx_runningdisp[21]),
.pll_powerdown(gxb_pwrdn_in_sig[21]),
.pll_locked(pll_locked_21)
);
defparam
the_altera_tse_gxb_gige_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_21.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_21.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 84,
the_altera_tse_gxb_gige_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_21 = {17{1'b0}};
assign led_char_err_gx[21] = 1'b0;
assign link_status[21] = 1'b0;
assign led_disp_err_21 = 1'b0;
assign txp_21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_22,gxb_pwrdn_in_sig_clk_22;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 22)
begin
always @(posedge clk or posedge gxb_pwrdn_in_22)
begin
if (gxb_pwrdn_in_22 == 1) begin
data_in_22 <= 1;
gxb_pwrdn_in_sig_clk_22 <= 1;
end else begin
data_in_22 <= 1'b0;
gxb_pwrdn_in_sig_clk_22 <= data_in_22;
end
end
assign gxb_pwrdn_in_sig[22] = gxb_pwrdn_in_22;
assign pcs_pwrdn_out_22 = pcs_pwrdn_out_sig[22];
end
else
begin
assign gxb_pwrdn_in_sig[22] = pcs_pwrdn_out_sig[22];
assign pcs_pwrdn_out_22 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_22 = gxb_pwrdn_in_sig[22];
end
end
endgenerate
generate if (MAX_CHANNELS > 22)
begin
wire locked_signal_22;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_22(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_22),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_22),// output
.tx_digitalreset(tx_digitalreset_sqcnr_22),// output
.rx_analogreset(rx_analogreset_sqcnr_22),// output
.rx_digitalreset(rx_digitalreset_sqcnr_22),// output
.gxb_powerdown(gxb_powerdown_sqcnr_22),// output
.pll_is_locked(locked_signal_22),
.rx_is_lockedtodata(rx_freqlocked_22),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_22)
);
assign locked_signal_22 = (reset? 1'b0: pll_locked_22);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_22_reset_sync_0 (
.clk(rx_pcs_clk_c22),
.reset_in(rx_digitalreset_sqcnr_22),
.reset_out(reset_rx_pcs_clk_c22_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
(
.clk(rx_pcs_clk_c22),
.reset(reset_rx_pcs_clk_c22_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_22),
.alt_sync(rx_syncstatus[22]),
.alt_disperr(rx_disp_err[22]),
.alt_ctrldetect(rx_kchar_22),
.alt_errdetect(rx_char_err_gx[22]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
.alt_runlengthviolation(rx_runlengthviolation[22]),
.alt_patterndetect(rx_patterndetect[22]),
.alt_runningdisp(rx_runningdisp[22]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_22),
.altpcs_sync(link_status[22]),
.altpcs_disperr(led_disp_err_22),
.altpcs_ctrldetect(pcs_rx_kchar_22),
.altpcs_errdetect(led_char_err_gx[22]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[22])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_22
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[22]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_22),
.reconfig_clk(reconfig_clk_22),
.reconfig_togxb(reconfig_togxb_22),
.reconfig_fromgxb(reconfig_fromgxb_22),
.rx_analogreset (rx_analogreset_sqcnr_22),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_22),
.rx_clkout (rx_pcs_clk_c22),
.rx_datain (rxp_22),
.rx_dataout (rx_frame_22),
.rx_digitalreset (rx_digitalreset_sqcnr_22),
.rx_disperr (rx_disp_err[22]),
.rx_errdetect (rx_char_err_gx[22]),
.rx_patterndetect (rx_patterndetect[22]),
.rx_rlv (rx_runlengthviolation[22]),
.rx_seriallpbken (sd_loopback_22),
.rx_syncstatus (rx_syncstatus[22]),
.tx_clkout (tx_pcs_clk_c22),
.tx_ctrlenable (tx_kchar_22),
.tx_datain (tx_frame_22),
.rx_freqlocked (rx_freqlocked_22),
.tx_dataout (txp_22),
.tx_digitalreset (tx_digitalreset_sqcnr_22),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
.rx_runningdisp(rx_runningdisp[22]),
.pll_powerdown(gxb_pwrdn_in_sig[22]),
.pll_locked(pll_locked_22)
);
defparam
the_altera_tse_gxb_gige_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_22.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_22.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 88,
the_altera_tse_gxb_gige_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_22 = {17{1'b0}};
assign led_char_err_gx[22] = 1'b0;
assign link_status[22] = 1'b0;
assign led_disp_err_22 = 1'b0;
assign txp_22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_23,gxb_pwrdn_in_sig_clk_23;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 23)
begin
always @(posedge clk or posedge gxb_pwrdn_in_23)
begin
if (gxb_pwrdn_in_23 == 1) begin
data_in_23 <= 1;
gxb_pwrdn_in_sig_clk_23 <= 1;
end else begin
data_in_23 <= 1'b0;
gxb_pwrdn_in_sig_clk_23 <= data_in_23;
end
end
assign gxb_pwrdn_in_sig[23] = gxb_pwrdn_in_23;
assign pcs_pwrdn_out_23 = pcs_pwrdn_out_sig[23];
end
else
begin
assign gxb_pwrdn_in_sig[23] = pcs_pwrdn_out_sig[23];
assign pcs_pwrdn_out_23 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_23 = gxb_pwrdn_in_sig[23];
end
end
endgenerate
generate if (MAX_CHANNELS > 23)
begin
wire locked_signal_23;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_23(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_23),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_23),// output
.tx_digitalreset(tx_digitalreset_sqcnr_23),// output
.rx_analogreset(rx_analogreset_sqcnr_23),// output
.rx_digitalreset(rx_digitalreset_sqcnr_23),// output
.gxb_powerdown(gxb_powerdown_sqcnr_23),// output
.pll_is_locked(locked_signal_23),
.rx_is_lockedtodata(rx_freqlocked_23),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_23)
);
assign locked_signal_23 = (reset? 1'b0: pll_locked_23);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_23_reset_sync_0 (
.clk(rx_pcs_clk_c23),
.reset_in(rx_digitalreset_sqcnr_23),
.reset_out(reset_rx_pcs_clk_c23_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
(
.clk(rx_pcs_clk_c23),
.reset(reset_rx_pcs_clk_c23_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_23),
.alt_sync(rx_syncstatus[23]),
.alt_disperr(rx_disp_err[23]),
.alt_ctrldetect(rx_kchar_23),
.alt_errdetect(rx_char_err_gx[23]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
.alt_runlengthviolation(rx_runlengthviolation[23]),
.alt_patterndetect(rx_patterndetect[23]),
.alt_runningdisp(rx_runningdisp[23]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_23),
.altpcs_sync(link_status[23]),
.altpcs_disperr(led_disp_err_23),
.altpcs_ctrldetect(pcs_rx_kchar_23),
.altpcs_errdetect(led_char_err_gx[23]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[23])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_23
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[23]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_23),
.reconfig_clk(reconfig_clk_23),
.reconfig_togxb(reconfig_togxb_23),
.reconfig_fromgxb(reconfig_fromgxb_23),
.rx_analogreset (rx_analogreset_sqcnr_23),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_23),
.rx_clkout (rx_pcs_clk_c23),
.rx_datain (rxp_23),
.rx_dataout (rx_frame_23),
.rx_digitalreset (rx_digitalreset_sqcnr_23),
.rx_disperr (rx_disp_err[23]),
.rx_errdetect (rx_char_err_gx[23]),
.rx_patterndetect (rx_patterndetect[23]),
.rx_rlv (rx_runlengthviolation[23]),
.rx_seriallpbken (sd_loopback_23),
.rx_syncstatus (rx_syncstatus[23]),
.tx_clkout (tx_pcs_clk_c23),
.tx_ctrlenable (tx_kchar_23),
.tx_datain (tx_frame_23),
.rx_freqlocked (rx_freqlocked_23),
.tx_dataout (txp_23),
.tx_digitalreset (tx_digitalreset_sqcnr_23),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
.rx_runningdisp(rx_runningdisp[23]),
.pll_powerdown(gxb_pwrdn_in_sig[23]),
.pll_locked(pll_locked_23)
);
defparam
the_altera_tse_gxb_gige_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_23.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_23.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 92,
the_altera_tse_gxb_gige_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_23 = {17{1'b0}};
assign led_char_err_gx[23] = 1'b0;
assign link_status[23] = 1'b0;
assign led_disp_err_23 = 1'b0;
assign txp_23 = 1'b0;
end
endgenerate
endmodule // module altera_tse_multi_mac_pcs_pma_gige
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige_phyip.v,v $
//
// $Revision: #7 $
// $Date: 2012/07/03 $
// Check in by : $Author: skyeow $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF;SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" } *)
module altera_tse_multi_mac_pcs_pma_gige_phyip
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
//IEEE1588 code
parameter TSTAMP_FP_WIDTH = 4, // Finger print width associated to the timestamp request
parameter ENABLE_TIMESTAMPING = 0, // To enable time stamping logic
parameter ENABLE_PTP_1STEP = 0, // To enable time 1 step clock PTP
// Internal parameters
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
input wire pcs_phase_measure_clk, // Phase Measurement Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
output wire rx_recovclkout_0, // Receiver Recovered Clock
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_0, // address to PHYIP management interface
input wire phy_mgmt_read_0, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_0, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_0, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_0, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_0,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_0, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_0, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_0, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_0, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_0, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_0, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_0, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_0, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_0, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_0, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_0, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_0, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_0, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_0, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_0, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_0, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_0, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_0, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_0, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_0, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_0, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_0, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_0, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_0, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_0, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_0, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_0, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_0, // 64 bit Time of Day
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
output wire rx_recovclkout_1, // Receiver Recovered Clock
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_1, // address to PHYIP management interface
input wire phy_mgmt_read_1, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_1, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_1, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_1, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_1,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_1, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_1, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_1, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_1, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_1, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_1, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_1, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_1, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_1, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_1, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_1, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_1, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_1, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_1, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_1, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_1, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_1, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_1, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_1, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_1, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_1, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_1, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_1, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_1, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_1, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_1, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_1, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_1, // 64 bit Time of Day
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
output wire rx_recovclkout_2, // Receiver Recovered Clock
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_2, // address to PHYIP management interface
input wire phy_mgmt_read_2, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_2, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_2, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_2, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_2,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_2, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_2, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_2, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_2, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_2, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_2, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_2, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_2, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_2, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_2, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_2, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_2, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_2, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_2, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_2, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_2, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_2, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_2, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_2, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_2, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_2, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_2, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_2, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_2, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_2, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_2, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_2, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_2, // 64 bit Time of Day
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
output wire rx_recovclkout_3, // Receiver Recovered Clock
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_3, // address to PHYIP management interface
input wire phy_mgmt_read_3, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_3, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_3, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_3, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_3,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_3, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_3, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_3, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_3, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_3, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_3, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_3, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_3, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_3, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_3, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_3, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_3, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_3, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_3, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_3, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_3, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_3, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_3, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_3, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_3, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_3, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_3, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_3, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_3, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_3, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_3, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_3, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_3, // 64 bit Time of Day
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
output wire rx_recovclkout_4, // Receiver Recovered Clock
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_4, // address to PHYIP management interface
input wire phy_mgmt_read_4, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_4, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_4, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_4, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_4,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_4, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_4, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_4, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_4, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_4, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_4, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_4, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_4, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_4, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_4, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_4, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_4, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_4, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_4, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_4, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_4, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_4, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_4, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_4, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_4, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_4, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_4, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_4, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_4, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_4, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_4, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_4, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_4, // 64 bit Time of Day
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
output wire rx_recovclkout_5, // Receiver Recovered Clock
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_5, // address to PHYIP management interface
input wire phy_mgmt_read_5, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_5, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_5, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_5, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_5,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_5, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_5, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_5, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_5, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_5, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_5, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_5, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_5, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_5, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_5, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_5, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_5, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_5, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_5, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_5, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_5, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_5, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_5, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_5, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_5, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_5, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_5, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_5, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_5, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_5, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_5, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_5, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_5, // 64 bit Time of Day
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
output wire rx_recovclkout_6, // Receiver Recovered Clock
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_6, // address to PHYIP management interface
input wire phy_mgmt_read_6, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_6, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_6, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_6, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_6,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_6, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_6, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_6, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_6, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_6, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_6, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_6, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_6, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_6, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_6, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_6, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_6, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_6, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_6, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_6, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_6, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_6, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_6, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_6, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_6, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_6, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_6, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_6, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_6, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_6, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_6, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_6, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_6, // 64 bit Time of Day
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
output wire rx_recovclkout_7, // Receiver Recovered Clock
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_7, // address to PHYIP management interface
input wire phy_mgmt_read_7, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_7, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_7, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_7, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_7,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_7, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_7, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_7, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_7, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_7, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_7, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_7, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_7, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_7, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_7, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_7, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_7, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_7, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_7, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_7, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_7, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_7, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_7, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_7, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_7, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_7, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_7, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_7, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_7, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_7, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_7, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_7, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_7, // 64 bit Time of Day
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
output wire rx_recovclkout_8, // Receiver Recovered Clock
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_8, // address to PHYIP management interface
input wire phy_mgmt_read_8, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_8, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_8, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_8, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_8,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_8, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_8, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_8, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_8, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_8, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_8, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_8, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_8, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_8, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_8, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_8, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_8, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_8, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_8, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_8, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_8, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_8, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_8, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_8, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_8, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_8, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_8, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_8, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_8, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_8, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_8, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_8, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_8, // 64 bit Time of Day
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
output wire rx_recovclkout_9, // Receiver Recovered Clock
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_9, // address to PHYIP management interface
input wire phy_mgmt_read_9, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_9, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_9, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_9, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_9,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_9, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_9, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_9, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_9, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_9, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_9, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_9, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_9, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_9, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_9, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_9, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_9, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_9, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_9, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_9, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_9, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_9, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_9, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_9, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_9, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_9, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_9, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_9, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_9, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_9, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_9, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_9, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_9, // 64 bit Time of Day
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
output wire rx_recovclkout_10, // Receiver Recovered Clock
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_10, // address to PHYIP management interface
input wire phy_mgmt_read_10, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_10, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_10, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_10, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_10,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_10, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_10, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_10, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_10, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_10, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_10, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_10, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_10, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_10, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_10, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_10, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_10, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_10, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_10, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_10, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_10, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_10, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_10, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_10, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_10, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_10, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_10, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_10, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_10, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_10, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_10, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_10, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_10, // 64 bit Time of Day
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
output wire rx_recovclkout_11, // Receiver Recovered Clock
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_11, // address to PHYIP management interface
input wire phy_mgmt_read_11, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_11, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_11, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_11, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_11,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_11, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_11, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_11, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_11, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_11, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_11, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_11, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_11, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_11, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_11, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_11, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_11, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_11, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_11, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_11, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_11, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_11, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_11, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_11, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_11, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_11, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_11, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_11, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_11, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_11, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_11, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_11, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_11, // 64 bit Time of Day
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
output wire rx_recovclkout_12, // Receiver Recovered Clock
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_12, // address to PHYIP management interface
input wire phy_mgmt_read_12, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_12, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_12, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_12, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_12,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_12, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_12, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_12, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_12, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_12, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_12, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_12, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_12, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_12, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_12, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_12, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_12, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_12, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_12, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_12, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_12, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_12, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_12, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_12, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_12, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_12, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_12, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_12, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_12, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_12, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_12, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_12, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_12, // 64 bit Time of Day
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
output wire rx_recovclkout_13, // Receiver Recovered Clock
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_13, // address to PHYIP management interface
input wire phy_mgmt_read_13, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_13, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_13, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_13, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_13,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_13, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_13, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_13, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_13, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_13, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_13, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_13, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_13, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_13, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_13, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_13, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_13, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_13, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_13, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_13, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_13, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_13, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_13, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_13, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_13, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_13, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_13, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_13, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_13, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_13, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_13, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_13, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_13, // 64 bit Time of Day
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
output wire rx_recovclkout_14, // Receiver Recovered Clock
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_14, // address to PHYIP management interface
input wire phy_mgmt_read_14, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_14, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_14, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_14, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_14,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_14, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_14, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_14, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_14, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_14, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_14, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_14, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_14, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_14, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_14, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_14, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_14, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_14, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_14, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_14, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_14, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_14, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_14, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_14, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_14, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_14, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_14, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_14, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_14, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_14, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_14, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_14, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_14, // 64 bit Time of Day
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
output wire rx_recovclkout_15, // Receiver Recovered Clock
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_15, // address to PHYIP management interface
input wire phy_mgmt_read_15, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_15, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_15, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_15, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_15,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_15, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_15, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_15, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_15, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_15, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_15, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_15, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_15, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_15, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_15, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_15, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_15, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_15, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_15, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_15, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_15, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_15, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_15, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_15, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_15, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_15, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_15, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_15, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_15, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_15, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_15, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_15, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_15, // 64 bit Time of Day
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
output wire rx_recovclkout_16, // Receiver Recovered Clock
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_16, // address to PHYIP management interface
input wire phy_mgmt_read_16, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_16, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_16, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_16, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_16,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_16, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_16, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_16, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_16, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_16, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_16, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_16, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_16, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_16, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_16, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_16, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_16, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_16, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_16, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_16, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_16, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_16, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_16, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_16, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_16, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_16, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_16, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_16, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_16, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_16, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_16, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_16, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_16, // 64 bit Time of Day
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
output wire rx_recovclkout_17, // Receiver Recovered Clock
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_17, // address to PHYIP management interface
input wire phy_mgmt_read_17, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_17, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_17, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_17, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_17,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_17, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_17, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_17, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_17, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_17, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_17, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_17, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_17, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_17, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_17, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_17, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_17, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_17, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_17, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_17, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_17, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_17, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_17, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_17, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_17, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_17, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_17, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_17, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_17, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_17, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_17, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_17, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_17, // 64 bit Time of Day
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
output wire rx_recovclkout_18, // Receiver Recovered Clock
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_18, // address to PHYIP management interface
input wire phy_mgmt_read_18, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_18, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_18, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_18, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_18,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_18, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_18, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_18, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_18, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_18, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_18, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_18, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_18, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_18, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_18, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_18, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_18, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_18, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_18, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_18, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_18, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_18, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_18, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_18, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_18, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_18, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_18, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_18, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_18, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_18, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_18, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_18, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_18, // 64 bit Time of Day
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
output wire rx_recovclkout_19, // Receiver Recovered Clock
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_19, // address to PHYIP management interface
input wire phy_mgmt_read_19, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_19, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_19, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_19, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_19,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_19, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_19, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_19, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_19, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_19, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_19, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_19, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_19, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_19, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_19, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_19, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_19, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_19, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_19, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_19, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_19, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_19, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_19, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_19, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_19, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_19, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_19, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_19, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_19, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_19, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_19, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_19, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_19, // 64 bit Time of Day
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
output wire rx_recovclkout_20, // Receiver Recovered Clock
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_20, // address to PHYIP management interface
input wire phy_mgmt_read_20, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_20, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_20, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_20, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_20,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_20, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_20, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_20, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_20, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_20, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_20, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_20, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_20, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_20, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_20, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_20, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_20, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_20, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_20, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_20, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_20, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_20, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_20, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_20, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_20, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_20, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_20, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_20, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_20, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_20, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_20, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_20, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_20, // 64 bit Time of Day
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
output wire rx_recovclkout_21, // Receiver Recovered Clock
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_21, // address to PHYIP management interface
input wire phy_mgmt_read_21, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_21, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_21, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_21, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_21,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_21, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_21, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_21, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_21, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_21, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_21, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_21, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_21, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_21, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_21, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_21, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_21, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_21, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_21, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_21, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_21, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_21, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_21, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_21, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_21, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_21, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_21, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_21, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_21, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_21, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_21, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_21, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_21, // 64 bit Time of Day
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
output wire rx_recovclkout_22, // Receiver Recovered Clock
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_22, // address to PHYIP management interface
input wire phy_mgmt_read_22, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_22, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_22, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_22, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_22,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_22, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_22, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_22, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_22, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_22, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_22, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_22, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_22, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_22, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_22, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_22, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_22, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_22, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_22, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_22, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_22, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_22, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_22, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_22, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_22, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_22, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_22, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_22, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_22, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_22, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_22, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_22, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_22, // 64 bit Time of Day
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
output wire rx_recovclkout_23, // Receiver Recovered Clock
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_23, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_23, // address to PHYIP management interface
input wire phy_mgmt_read_23, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_23, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_23, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_23, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_23,// writedata to PHYIP management interface
//IEEE1588's code
input wire tx_egress_timestamp_request_valid_23, // Timestamp request valid from user
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_fingerprint_23, // Fingerprint associated to the timestamp request
input wire [(96)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_96b_23, // Ingress timestamp
input wire [(64)-1:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b_23, // Ingress timestamp
input wire tx_etstamp_ins_ctrl_timestamp_insert_23, // Timestamp insert
input wire tx_etstamp_ins_ctrl_residence_time_update_23, // Residence time update
input wire tx_etstamp_ins_ctrl_checksum_zero_23, // Set checksum field to zero
input wire tx_etstamp_ins_ctrl_checksum_correct_23, // Correct extended 2bytes
input wire tx_etstamp_ins_ctrl_residence_time_calc_format_23, // Residence time calculation timestamp format -96/64
input wire tx_etstamp_ins_ctrl_timestamp_format_23, // Timestamp format - v1 or v2
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_timestamp_23, // Timestamp field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_correction_field_23, // Correction field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_field_23, // Udp checksum field offset
input wire [16-1:0] tx_etstamp_ins_ctrl_offset_checksum_correction_23, // Extended 2 bytes field offset
input wire [96-1:0] tx_time_of_day_96b_data_23, // 96 bit Time of Day
input wire [64-1:0] tx_time_of_day_64b_data_23, // 64 bit Time of Day
output wire tx_egress_timestamp_96b_valid_23, // tx 96bit egress timestamp valid
output wire [96-1:0] tx_egress_timestamp_96b_data_23, // tx 96bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_96b_fingerprint_23, // tx 96bit fingerprint
output wire tx_egress_timestamp_64b_valid_23, // tx 64bit egress timestamp valid
output wire [64-1:0] tx_egress_timestamp_64b_data_23, // tx 64bit egress timestamp data
output wire [TSTAMP_FP_WIDTH-1:0] tx_egress_timestamp_64b_fingerprint_23, // tx 64bit fingerprint
output wire rx_ingress_timestamp_96b_valid_23, // rx 96bit egress timestamp valid
output wire [96-1:0] rx_ingress_timestamp_96b_data_23, // rx 96bit egress timestamp data
output wire rx_ingress_timestamp_64b_valid_23, // rx 64bit egress timestamp valid
output wire [64-1:0] rx_ingress_timestamp_64b_data_23, // rx 64bit egress timestamp data
input wire [96-1:0] rx_time_of_day_96b_data_23, // 96 bit Time of Day
input wire [64-1:0] rx_time_of_day_64b_data_23); // 64 bit Time of Day
wire MAC_PCS_reset;
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire gige_pma_reset;
wire [23:0] led_char_err_gx;
wire [23:0] link_status;
//wire [23:0] pcs_clk;
wire tx_pcs_clk_c0;
wire tx_pcs_clk_c1;
wire tx_pcs_clk_c2;
wire tx_pcs_clk_c3;
wire tx_pcs_clk_c4;
wire tx_pcs_clk_c5;
wire tx_pcs_clk_c6;
wire tx_pcs_clk_c7;
wire tx_pcs_clk_c8;
wire tx_pcs_clk_c9;
wire tx_pcs_clk_c10;
wire tx_pcs_clk_c11;
wire tx_pcs_clk_c12;
wire tx_pcs_clk_c13;
wire tx_pcs_clk_c14;
wire tx_pcs_clk_c15;
wire tx_pcs_clk_c16;
wire tx_pcs_clk_c17;
wire tx_pcs_clk_c18;
wire tx_pcs_clk_c19;
wire tx_pcs_clk_c20;
wire tx_pcs_clk_c21;
wire tx_pcs_clk_c22;
wire tx_pcs_clk_c23;
wire rx_pcs_clk_c0;
wire rx_pcs_clk_c1;
wire rx_pcs_clk_c2;
wire rx_pcs_clk_c3;
wire rx_pcs_clk_c4;
wire rx_pcs_clk_c5;
wire rx_pcs_clk_c6;
wire rx_pcs_clk_c7;
wire rx_pcs_clk_c8;
wire rx_pcs_clk_c9;
wire rx_pcs_clk_c10;
wire rx_pcs_clk_c11;
wire rx_pcs_clk_c12;
wire rx_pcs_clk_c13;
wire rx_pcs_clk_c14;
wire rx_pcs_clk_c15;
wire rx_pcs_clk_c16;
wire rx_pcs_clk_c17;
wire rx_pcs_clk_c18;
wire rx_pcs_clk_c19;
wire rx_pcs_clk_c20;
wire rx_pcs_clk_c21;
wire rx_pcs_clk_c22;
wire rx_pcs_clk_c23;
wire [23:0] rx_char_err_gx;
wire [23:0] rx_disp_err;
wire [23:0] rx_syncstatus;
wire [23:0] rx_runlengthviolation;
wire [23:0] rx_patterndetect;
wire [23:0] rx_runningdisp;
wire [23:0] rx_rmfifodatadeleted;
wire [23:0] rx_rmfifodatainserted;
wire [23:0] pcs_rx_rmfifodatadeleted;
wire [23:0] pcs_rx_rmfifodatainserted;
wire [23:0] pcs_rx_carrierdetected;
wire rx_kchar_0;
wire [7:0] rx_frame_0;
wire pcs_rx_kchar_0;
wire [7:0] pcs_rx_frame_0;
wire tx_kchar_0;
wire [7:0] tx_frame_0;
wire [4:0] wa_boundary_0;
wire rx_kchar_1;
wire [7:0] rx_frame_1;
wire pcs_rx_kchar_1;
wire [7:0] pcs_rx_frame_1;
wire tx_kchar_1;
wire [7:0] tx_frame_1;
wire [4:0] wa_boundary_1;
wire rx_kchar_2;
wire [7:0] rx_frame_2;
wire pcs_rx_kchar_2;
wire [7:0] pcs_rx_frame_2;
wire tx_kchar_2;
wire [7:0] tx_frame_2;
wire [4:0] wa_boundary_2;
wire rx_kchar_3;
wire [7:0] rx_frame_3;
wire pcs_rx_kchar_3;
wire [7:0] pcs_rx_frame_3;
wire tx_kchar_3;
wire [7:0] tx_frame_3;
wire [4:0] wa_boundary_3;
wire rx_kchar_4;
wire [7:0] rx_frame_4;
wire pcs_rx_kchar_4;
wire [7:0] pcs_rx_frame_4;
wire tx_kchar_4;
wire [7:0] tx_frame_4;
wire [4:0] wa_boundary_4;
wire rx_kchar_5;
wire [7:0] rx_frame_5;
wire pcs_rx_kchar_5;
wire [7:0] pcs_rx_frame_5;
wire tx_kchar_5;
wire [7:0] tx_frame_5;
wire [4:0] wa_boundary_5;
wire rx_kchar_6;
wire [7:0] rx_frame_6;
wire pcs_rx_kchar_6;
wire [7:0] pcs_rx_frame_6;
wire tx_kchar_6;
wire [7:0] tx_frame_6;
wire [4:0] wa_boundary_6;
wire rx_kchar_7;
wire [7:0] rx_frame_7;
wire pcs_rx_kchar_7;
wire [7:0] pcs_rx_frame_7;
wire tx_kchar_7;
wire [7:0] tx_frame_7;
wire [4:0] wa_boundary_7;
wire rx_kchar_8;
wire [7:0] rx_frame_8;
wire pcs_rx_kchar_8;
wire [7:0] pcs_rx_frame_8;
wire tx_kchar_8;
wire [7:0] tx_frame_8;
wire [4:0] wa_boundary_8;
wire rx_kchar_9;
wire [7:0] rx_frame_9;
wire pcs_rx_kchar_9;
wire [7:0] pcs_rx_frame_9;
wire tx_kchar_9;
wire [7:0] tx_frame_9;
wire [4:0] wa_boundary_9;
wire rx_kchar_10;
wire [7:0] rx_frame_10;
wire pcs_rx_kchar_10;
wire [7:0] pcs_rx_frame_10;
wire tx_kchar_10;
wire [7:0] tx_frame_10;
wire [4:0] wa_boundary_10;
wire rx_kchar_11;
wire [7:0] rx_frame_11;
wire pcs_rx_kchar_11;
wire [7:0] pcs_rx_frame_11;
wire tx_kchar_11;
wire [7:0] tx_frame_11;
wire [4:0] wa_boundary_11;
wire rx_kchar_12;
wire [7:0] rx_frame_12;
wire pcs_rx_kchar_12;
wire [7:0] pcs_rx_frame_12;
wire tx_kchar_12;
wire [7:0] tx_frame_12;
wire [4:0] wa_boundary_12;
wire rx_kchar_13;
wire [7:0] rx_frame_13;
wire pcs_rx_kchar_13;
wire [7:0] pcs_rx_frame_13;
wire tx_kchar_13;
wire [7:0] tx_frame_13;
wire [4:0] wa_boundary_13;
wire rx_kchar_14;
wire [7:0] rx_frame_14;
wire pcs_rx_kchar_14;
wire [7:0] pcs_rx_frame_14;
wire tx_kchar_14;
wire [7:0] tx_frame_14;
wire [4:0] wa_boundary_14;
wire rx_kchar_15;
wire [7:0] rx_frame_15;
wire pcs_rx_kchar_15;
wire [7:0] pcs_rx_frame_15;
wire tx_kchar_15;
wire [7:0] tx_frame_15;
wire [4:0] wa_boundary_15;
wire rx_kchar_16;
wire [7:0] rx_frame_16;
wire pcs_rx_kchar_16;
wire [7:0] pcs_rx_frame_16;
wire tx_kchar_16;
wire [7:0] tx_frame_16;
wire [4:0] wa_boundary_16;
wire rx_kchar_17;
wire [7:0] rx_frame_17;
wire pcs_rx_kchar_17;
wire [7:0] pcs_rx_frame_17;
wire tx_kchar_17;
wire [7:0] tx_frame_17;
wire [4:0] wa_boundary_17;
wire rx_kchar_18;
wire [7:0] rx_frame_18;
wire pcs_rx_kchar_18;
wire [7:0] pcs_rx_frame_18;
wire tx_kchar_18;
wire [7:0] tx_frame_18;
wire [4:0] wa_boundary_18;
wire rx_kchar_19;
wire [7:0] rx_frame_19;
wire pcs_rx_kchar_19;
wire [7:0] pcs_rx_frame_19;
wire tx_kchar_19;
wire [7:0] tx_frame_19;
wire [4:0] wa_boundary_19;
wire rx_kchar_20;
wire [7:0] rx_frame_20;
wire pcs_rx_kchar_20;
wire [7:0] pcs_rx_frame_20;
wire tx_kchar_20;
wire [7:0] tx_frame_20;
wire [4:0] wa_boundary_20;
wire rx_kchar_21;
wire [7:0] rx_frame_21;
wire pcs_rx_kchar_21;
wire [7:0] pcs_rx_frame_21;
wire tx_kchar_21;
wire [7:0] tx_frame_21;
wire [4:0] wa_boundary_21;
wire rx_kchar_22;
wire [7:0] rx_frame_22;
wire pcs_rx_kchar_22;
wire [7:0] pcs_rx_frame_22;
wire tx_kchar_22;
wire [7:0] tx_frame_22;
wire [4:0] wa_boundary_22;
wire rx_kchar_23;
wire [7:0] rx_frame_23;
wire pcs_rx_kchar_23;
wire [7:0] pcs_rx_frame_23;
wire tx_kchar_23;
wire [7:0] tx_frame_23;
wire [4:0] wa_boundary_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
wire reset_rx_pcs_clk_c0_int;
wire reset_rx_pcs_clk_c1_int;
wire reset_rx_pcs_clk_c2_int;
wire reset_rx_pcs_clk_c3_int;
wire reset_rx_pcs_clk_c4_int;
wire reset_rx_pcs_clk_c5_int;
wire reset_rx_pcs_clk_c6_int;
wire reset_rx_pcs_clk_c7_int;
wire reset_rx_pcs_clk_c8_int;
wire reset_rx_pcs_clk_c9_int;
wire reset_rx_pcs_clk_c10_int;
wire reset_rx_pcs_clk_c11_int;
wire reset_rx_pcs_clk_c12_int;
wire reset_rx_pcs_clk_c13_int;
wire reset_rx_pcs_clk_c14_int;
wire reset_rx_pcs_clk_c15_int;
wire reset_rx_pcs_clk_c16_int;
wire reset_rx_pcs_clk_c17_int;
wire reset_rx_pcs_clk_c18_int;
wire reset_rx_pcs_clk_c19_int;
wire reset_rx_pcs_clk_c20_int;
wire reset_rx_pcs_clk_c21_int;
wire reset_rx_pcs_clk_c22_int;
wire reset_rx_pcs_clk_c23_int;
//assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err_0 = led_char_err_gx[0];
assign led_link_0 = link_status[0];
assign led_char_err_1 = led_char_err_gx[1];
assign led_link_1 = link_status[1];
assign led_char_err_2 = led_char_err_gx[2];
assign led_link_2 = link_status[2];
assign led_char_err_3 = led_char_err_gx[3];
assign led_link_3 = link_status[3];
assign led_char_err_4 = led_char_err_gx[4];
assign led_link_4 = link_status[4];
assign led_char_err_5 = led_char_err_gx[5];
assign led_link_5 = link_status[5];
assign led_char_err_6 = led_char_err_gx[6];
assign led_link_6 = link_status[6];
assign led_char_err_7 = led_char_err_gx[7];
assign led_link_7 = link_status[7];
assign led_char_err_8 = led_char_err_gx[8];
assign led_link_8 = link_status[8];
assign led_char_err_9 = led_char_err_gx[9];
assign led_link_9 = link_status[9];
assign led_char_err_10 = led_char_err_gx[10];
assign led_link_10 = link_status[10];
assign led_char_err_11 = led_char_err_gx[11];
assign led_link_11 = link_status[11];
assign led_char_err_12 = led_char_err_gx[12];
assign led_link_12 = link_status[12];
assign led_char_err_13 = led_char_err_gx[13];
assign led_link_13 = link_status[13];
assign led_char_err_14 = led_char_err_gx[14];
assign led_link_14 = link_status[14];
assign led_char_err_15 = led_char_err_gx[15];
assign led_link_15 = link_status[15];
assign led_char_err_16 = led_char_err_gx[16];
assign led_link_16 = link_status[16];
assign led_char_err_17 = led_char_err_gx[17];
assign led_link_17 = link_status[17];
assign led_char_err_18 = led_char_err_gx[18];
assign led_link_18 = link_status[18];
assign led_char_err_19 = led_char_err_gx[19];
assign led_link_19 = link_status[19];
assign led_char_err_20 = led_char_err_gx[20];
assign led_link_20 = link_status[20];
assign led_char_err_21 = led_char_err_gx[21];
assign led_link_21 = link_status[21];
assign led_char_err_22 = led_char_err_gx[22];
assign led_link_22 = link_status[22];
assign led_char_err_23 = led_char_err_gx[23];
assign led_link_23 = link_status[23];
wire pcs_phase_measure_clk_w;
generate
if (ENABLE_TIMESTAMPING == 0)
begin
assign pcs_phase_measure_clk_w = 1'b0;
end
else
begin
assign pcs_phase_measure_clk_w = pcs_phase_measure_clk;
end
endgenerate
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
.pcs_phase_measure_clk(pcs_phase_measure_clk_w),
// Channel 0
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
.rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
.rx_clkout_0(rx_pcs_clk_c0), //INPUT : Receive Clock
.tx_clkout_0(tx_pcs_clk_c0), //INPUT : Transmit Clock
.rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
.tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
.rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
.tx_frame_0(tx_frame_0), //OUTPUT : Frame
.wa_boundary_0(wa_boundary_0), //OUTPUT : Word Aligner Boundary
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(link_status[0]), //INPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_0(tx_egress_timestamp_request_valid_0), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_0(tx_egress_timestamp_request_fingerprint_0), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_0(tx_etstamp_ins_ctrl_ingress_timestamp_96b_0), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_0(tx_etstamp_ins_ctrl_ingress_timestamp_64b_0), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_0(tx_etstamp_ins_ctrl_timestamp_insert_0), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_0(tx_etstamp_ins_ctrl_residence_time_update_0), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_0(tx_etstamp_ins_ctrl_checksum_zero_0), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_0(tx_etstamp_ins_ctrl_checksum_correct_0), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_0(tx_etstamp_ins_ctrl_residence_time_calc_format_0), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_0(tx_etstamp_ins_ctrl_timestamp_format_0), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_0(tx_etstamp_ins_ctrl_offset_timestamp_0), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_0(tx_etstamp_ins_ctrl_offset_correction_field_0), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_0(tx_etstamp_ins_ctrl_offset_checksum_field_0), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_0(tx_etstamp_ins_ctrl_offset_checksum_correction_0), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_0(tx_time_of_day_96b_data_0), // Time of Day
.tx_time_of_day_64b_data_0(tx_time_of_day_64b_data_0), // Time of Day
.tx_egress_timestamp_96b_valid_0(tx_egress_timestamp_96b_valid_0), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_0(tx_egress_timestamp_96b_data_0), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_0(tx_egress_timestamp_96b_fingerprint_0), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_0(tx_egress_timestamp_64b_valid_0), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_0(tx_egress_timestamp_64b_data_0), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_0(tx_egress_timestamp_64b_fingerprint_0), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_0(rx_ingress_timestamp_96b_valid_0), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_0(rx_ingress_timestamp_96b_data_0), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_0(rx_ingress_timestamp_64b_valid_0), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_0(rx_ingress_timestamp_64b_data_0), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_0(rx_time_of_day_96b_data_0), // Time of Day
.rx_time_of_day_64b_data_0(rx_time_of_day_64b_data_0), //INPUT: Time of Day
// Channel 1
.rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
.rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
.rx_clkout_1(rx_pcs_clk_c1), //INPUT : Receive Clock
.tx_clkout_1(tx_pcs_clk_c1), //INPUT : Transmit Clock
.rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
.tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
.rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
.tx_frame_1(tx_frame_1), //OUTPUT : Frame
.wa_boundary_1(wa_boundary_1), //OUTPUT : Word Aligner Boundary
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(link_status[1]), //INPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_1(tx_egress_timestamp_request_valid_1), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_1(tx_egress_timestamp_request_fingerprint_1), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_1(tx_etstamp_ins_ctrl_ingress_timestamp_96b_1), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_1(tx_etstamp_ins_ctrl_ingress_timestamp_64b_1), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_1(tx_etstamp_ins_ctrl_timestamp_insert_1), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_1(tx_etstamp_ins_ctrl_residence_time_update_1), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_1(tx_etstamp_ins_ctrl_checksum_zero_1), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_1(tx_etstamp_ins_ctrl_checksum_correct_1), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_1(tx_etstamp_ins_ctrl_residence_time_calc_format_1), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_1(tx_etstamp_ins_ctrl_timestamp_format_1), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_1(tx_etstamp_ins_ctrl_offset_timestamp_1), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_1(tx_etstamp_ins_ctrl_offset_correction_field_1), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_1(tx_etstamp_ins_ctrl_offset_checksum_field_1), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_1(tx_etstamp_ins_ctrl_offset_checksum_correction_1), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_1(tx_time_of_day_96b_data_1), // Time of Day
.tx_time_of_day_64b_data_1(tx_time_of_day_64b_data_1), // Time of Day
.tx_egress_timestamp_96b_valid_1(tx_egress_timestamp_96b_valid_1), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_1(tx_egress_timestamp_96b_data_1), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_1(tx_egress_timestamp_96b_fingerprint_1), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_1(tx_egress_timestamp_64b_valid_1), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_1(tx_egress_timestamp_64b_data_1), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_1(tx_egress_timestamp_64b_fingerprint_1), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_1(rx_ingress_timestamp_96b_valid_1), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_1(rx_ingress_timestamp_96b_data_1), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_1(rx_ingress_timestamp_64b_valid_1), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_1(rx_ingress_timestamp_64b_data_1), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_1(rx_time_of_day_96b_data_1), // Time of Day
.rx_time_of_day_64b_data_1(rx_time_of_day_64b_data_1), //INPUT: Time of Day
// Channel 2
.rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
.rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
.rx_clkout_2(rx_pcs_clk_c2), //INPUT : Receive Clock
.tx_clkout_2(tx_pcs_clk_c2), //INPUT : Transmit Clock
.rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
.tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
.rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
.tx_frame_2(tx_frame_2), //OUTPUT : Frame
.wa_boundary_2(wa_boundary_2), //OUTPUT : Word Aligner Boundary
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(link_status[2]), //INPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_2(tx_egress_timestamp_request_valid_2), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_2(tx_egress_timestamp_request_fingerprint_2), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_2(tx_etstamp_ins_ctrl_ingress_timestamp_96b_2), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_2(tx_etstamp_ins_ctrl_ingress_timestamp_64b_2), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_2(tx_etstamp_ins_ctrl_timestamp_insert_2), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_2(tx_etstamp_ins_ctrl_residence_time_update_2), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_2(tx_etstamp_ins_ctrl_checksum_zero_2), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_2(tx_etstamp_ins_ctrl_checksum_correct_2), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_2(tx_etstamp_ins_ctrl_residence_time_calc_format_2), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_2(tx_etstamp_ins_ctrl_timestamp_format_2), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_2(tx_etstamp_ins_ctrl_offset_timestamp_2), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_2(tx_etstamp_ins_ctrl_offset_correction_field_2), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_2(tx_etstamp_ins_ctrl_offset_checksum_field_2), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_2(tx_etstamp_ins_ctrl_offset_checksum_correction_2), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_2(tx_time_of_day_96b_data_2), // Time of Day
.tx_time_of_day_64b_data_2(tx_time_of_day_64b_data_2), // Time of Day
.tx_egress_timestamp_96b_valid_2(tx_egress_timestamp_96b_valid_2), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_2(tx_egress_timestamp_96b_data_2), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_2(tx_egress_timestamp_96b_fingerprint_2), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_2(tx_egress_timestamp_64b_valid_2), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_2(tx_egress_timestamp_64b_data_2), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_2(tx_egress_timestamp_64b_fingerprint_2), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_2(rx_ingress_timestamp_96b_valid_2), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_2(rx_ingress_timestamp_96b_data_2), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_2(rx_ingress_timestamp_64b_valid_2), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_2(rx_ingress_timestamp_64b_data_2), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_2(rx_time_of_day_96b_data_2), // Time of Day
.rx_time_of_day_64b_data_2(rx_time_of_day_64b_data_2), //INPUT: Time of Day
// Channel 3
.rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
.rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
.rx_clkout_3(rx_pcs_clk_c3), //INPUT : Receive Clock
.tx_clkout_3(tx_pcs_clk_c3), //INPUT : Transmit Clock
.rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
.tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
.rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
.tx_frame_3(tx_frame_3), //OUTPUT : Frame
.wa_boundary_3(wa_boundary_3), //OUTPUT : Word Aligner Boundary
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(link_status[3]), //INPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_3(tx_egress_timestamp_request_valid_3), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_3(tx_egress_timestamp_request_fingerprint_3), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_3(tx_etstamp_ins_ctrl_ingress_timestamp_96b_3), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_3(tx_etstamp_ins_ctrl_ingress_timestamp_64b_3), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_3(tx_etstamp_ins_ctrl_timestamp_insert_3), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_3(tx_etstamp_ins_ctrl_residence_time_update_3), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_3(tx_etstamp_ins_ctrl_checksum_zero_3), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_3(tx_etstamp_ins_ctrl_checksum_correct_3), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_3(tx_etstamp_ins_ctrl_residence_time_calc_format_3), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_3(tx_etstamp_ins_ctrl_timestamp_format_3), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_3(tx_etstamp_ins_ctrl_offset_timestamp_3), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_3(tx_etstamp_ins_ctrl_offset_correction_field_3), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_3(tx_etstamp_ins_ctrl_offset_checksum_field_3), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_3(tx_etstamp_ins_ctrl_offset_checksum_correction_3), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_3(tx_time_of_day_96b_data_3), // Time of Day
.tx_time_of_day_64b_data_3(tx_time_of_day_64b_data_3), // Time of Day
.tx_egress_timestamp_96b_valid_3(tx_egress_timestamp_96b_valid_3), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_3(tx_egress_timestamp_96b_data_3), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_3(tx_egress_timestamp_96b_fingerprint_3), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_3(tx_egress_timestamp_64b_valid_3), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_3(tx_egress_timestamp_64b_data_3), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_3(tx_egress_timestamp_64b_fingerprint_3), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_3(rx_ingress_timestamp_96b_valid_3), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_3(rx_ingress_timestamp_96b_data_3), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_3(rx_ingress_timestamp_64b_valid_3), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_3(rx_ingress_timestamp_64b_data_3), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_3(rx_time_of_day_96b_data_3), // Time of Day
.rx_time_of_day_64b_data_3(rx_time_of_day_64b_data_3), //INPUT: Time of Day
// Channel 4
.rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
.rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
.rx_clkout_4(rx_pcs_clk_c4), //INPUT : Receive Clock
.tx_clkout_4(tx_pcs_clk_c4), //INPUT : Transmit Clock
.rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
.tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
.rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
.tx_frame_4(tx_frame_4), //OUTPUT : Frame
.wa_boundary_4(wa_boundary_4), //OUTPUT : Word Aligner Boundary
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(link_status[4]), //INPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_4(tx_egress_timestamp_request_valid_4), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_4(tx_egress_timestamp_request_fingerprint_4), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_4(tx_etstamp_ins_ctrl_ingress_timestamp_96b_4), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_4(tx_etstamp_ins_ctrl_ingress_timestamp_64b_4), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_4(tx_etstamp_ins_ctrl_timestamp_insert_4), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_4(tx_etstamp_ins_ctrl_residence_time_update_4), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_4(tx_etstamp_ins_ctrl_checksum_zero_4), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_4(tx_etstamp_ins_ctrl_checksum_correct_4), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_4(tx_etstamp_ins_ctrl_residence_time_calc_format_4), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_4(tx_etstamp_ins_ctrl_timestamp_format_4), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_4(tx_etstamp_ins_ctrl_offset_timestamp_4), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_4(tx_etstamp_ins_ctrl_offset_correction_field_4), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_4(tx_etstamp_ins_ctrl_offset_checksum_field_4), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_4(tx_etstamp_ins_ctrl_offset_checksum_correction_4), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_4(tx_time_of_day_96b_data_4), // Time of Day
.tx_time_of_day_64b_data_4(tx_time_of_day_64b_data_4), // Time of Day
.tx_egress_timestamp_96b_valid_4(tx_egress_timestamp_96b_valid_4), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_4(tx_egress_timestamp_96b_data_4), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_4(tx_egress_timestamp_96b_fingerprint_4), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_4(tx_egress_timestamp_64b_valid_4), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_4(tx_egress_timestamp_64b_data_4), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_4(tx_egress_timestamp_64b_fingerprint_4), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_4(rx_ingress_timestamp_96b_valid_4), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_4(rx_ingress_timestamp_96b_data_4), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_4(rx_ingress_timestamp_64b_valid_4), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_4(rx_ingress_timestamp_64b_data_4), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_4(rx_time_of_day_96b_data_4), // Time of Day
.rx_time_of_day_64b_data_4(rx_time_of_day_64b_data_4), //INPUT: Time of Day
// Channel 5
.rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
.rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
.rx_clkout_5(rx_pcs_clk_c5), //INPUT : Receive Clock
.tx_clkout_5(tx_pcs_clk_c5), //INPUT : Transmit Clock
.rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
.tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
.rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
.tx_frame_5(tx_frame_5), //OUTPUT : Frame
.wa_boundary_5(wa_boundary_5), //OUTPUT : Word Aligner Boundary
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(link_status[5]), //INPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_5(tx_egress_timestamp_request_valid_5), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_5(tx_egress_timestamp_request_fingerprint_5), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_5(tx_etstamp_ins_ctrl_ingress_timestamp_96b_5), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_5(tx_etstamp_ins_ctrl_ingress_timestamp_64b_5), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_5(tx_etstamp_ins_ctrl_timestamp_insert_5), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_5(tx_etstamp_ins_ctrl_residence_time_update_5), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_5(tx_etstamp_ins_ctrl_checksum_zero_5), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_5(tx_etstamp_ins_ctrl_checksum_correct_5), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_5(tx_etstamp_ins_ctrl_residence_time_calc_format_5), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_5(tx_etstamp_ins_ctrl_timestamp_format_5), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_5(tx_etstamp_ins_ctrl_offset_timestamp_5), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_5(tx_etstamp_ins_ctrl_offset_correction_field_5), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_5(tx_etstamp_ins_ctrl_offset_checksum_field_5), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_5(tx_etstamp_ins_ctrl_offset_checksum_correction_5), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_5(tx_time_of_day_96b_data_5), // Time of Day
.tx_time_of_day_64b_data_5(tx_time_of_day_64b_data_5), // Time of Day
.tx_egress_timestamp_96b_valid_5(tx_egress_timestamp_96b_valid_5), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_5(tx_egress_timestamp_96b_data_5), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_5(tx_egress_timestamp_96b_fingerprint_5), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_5(tx_egress_timestamp_64b_valid_5), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_5(tx_egress_timestamp_64b_data_5), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_5(tx_egress_timestamp_64b_fingerprint_5), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_5(rx_ingress_timestamp_96b_valid_5), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_5(rx_ingress_timestamp_96b_data_5), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_5(rx_ingress_timestamp_64b_valid_5), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_5(rx_ingress_timestamp_64b_data_5), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_5(rx_time_of_day_96b_data_5), // Time of Day
.rx_time_of_day_64b_data_5(rx_time_of_day_64b_data_5), //INPUT: Time of Day
// Channel 6
.rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
.rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
.rx_clkout_6(rx_pcs_clk_c6), //INPUT : Receive Clock
.tx_clkout_6(tx_pcs_clk_c6), //INPUT : Transmit Clock
.rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
.tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
.rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
.tx_frame_6(tx_frame_6), //OUTPUT : Frame
.wa_boundary_6(wa_boundary_6), //OUTPUT : Word Aligner Boundary
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(link_status[6]), //INPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_6(tx_egress_timestamp_request_valid_6), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_6(tx_egress_timestamp_request_fingerprint_6), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_6(tx_etstamp_ins_ctrl_ingress_timestamp_96b_6), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_6(tx_etstamp_ins_ctrl_ingress_timestamp_64b_6), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_6(tx_etstamp_ins_ctrl_timestamp_insert_6), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_6(tx_etstamp_ins_ctrl_residence_time_update_6), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_6(tx_etstamp_ins_ctrl_checksum_zero_6), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_6(tx_etstamp_ins_ctrl_checksum_correct_6), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_6(tx_etstamp_ins_ctrl_residence_time_calc_format_6), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_6(tx_etstamp_ins_ctrl_timestamp_format_6), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_6(tx_etstamp_ins_ctrl_offset_timestamp_6), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_6(tx_etstamp_ins_ctrl_offset_correction_field_6), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_6(tx_etstamp_ins_ctrl_offset_checksum_field_6), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_6(tx_etstamp_ins_ctrl_offset_checksum_correction_6), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_6(tx_time_of_day_96b_data_6), // Time of Day
.tx_time_of_day_64b_data_6(tx_time_of_day_64b_data_6), // Time of Day
.tx_egress_timestamp_96b_valid_6(tx_egress_timestamp_96b_valid_6), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_6(tx_egress_timestamp_96b_data_6), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_6(tx_egress_timestamp_96b_fingerprint_6), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_6(tx_egress_timestamp_64b_valid_6), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_6(tx_egress_timestamp_64b_data_6), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_6(tx_egress_timestamp_64b_fingerprint_6), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_6(rx_ingress_timestamp_96b_valid_6), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_6(rx_ingress_timestamp_96b_data_6), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_6(rx_ingress_timestamp_64b_valid_6), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_6(rx_ingress_timestamp_64b_data_6), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_6(rx_time_of_day_96b_data_6), // Time of Day
.rx_time_of_day_64b_data_6(rx_time_of_day_64b_data_6), //INPUT: Time of Day
// Channel 7
.rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
.rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
.rx_clkout_7(rx_pcs_clk_c7), //INPUT : Receive Clock
.tx_clkout_7(tx_pcs_clk_c7), //INPUT : Transmit Clock
.rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
.tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
.rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
.tx_frame_7(tx_frame_7), //OUTPUT : Frame
.wa_boundary_7(wa_boundary_7), //OUTPUT : Word Aligner Boundary
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(link_status[7]), //INPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_7(tx_egress_timestamp_request_valid_7), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_7(tx_egress_timestamp_request_fingerprint_7), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_7(tx_etstamp_ins_ctrl_ingress_timestamp_96b_7), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_7(tx_etstamp_ins_ctrl_ingress_timestamp_64b_7), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_7(tx_etstamp_ins_ctrl_timestamp_insert_7), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_7(tx_etstamp_ins_ctrl_residence_time_update_7), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_7(tx_etstamp_ins_ctrl_checksum_zero_7), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_7(tx_etstamp_ins_ctrl_checksum_correct_7), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_7(tx_etstamp_ins_ctrl_residence_time_calc_format_7), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_7(tx_etstamp_ins_ctrl_timestamp_format_7), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_7(tx_etstamp_ins_ctrl_offset_timestamp_7), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_7(tx_etstamp_ins_ctrl_offset_correction_field_7), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_7(tx_etstamp_ins_ctrl_offset_checksum_field_7), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_7(tx_etstamp_ins_ctrl_offset_checksum_correction_7), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_7(tx_time_of_day_96b_data_7), // Time of Day
.tx_time_of_day_64b_data_7(tx_time_of_day_64b_data_7), // Time of Day
.tx_egress_timestamp_96b_valid_7(tx_egress_timestamp_96b_valid_7), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_7(tx_egress_timestamp_96b_data_7), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_7(tx_egress_timestamp_96b_fingerprint_7), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_7(tx_egress_timestamp_64b_valid_7), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_7(tx_egress_timestamp_64b_data_7), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_7(tx_egress_timestamp_64b_fingerprint_7), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_7(rx_ingress_timestamp_96b_valid_7), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_7(rx_ingress_timestamp_96b_data_7), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_7(rx_ingress_timestamp_64b_valid_7), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_7(rx_ingress_timestamp_64b_data_7), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_7(rx_time_of_day_96b_data_7), // Time of Day
.rx_time_of_day_64b_data_7(rx_time_of_day_64b_data_7), //INPUT: Time of Day
// Channel 8
.rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
.rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
.rx_clkout_8(rx_pcs_clk_c8), //INPUT : Receive Clock
.tx_clkout_8(tx_pcs_clk_c8), //INPUT : Transmit Clock
.rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
.tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
.rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
.tx_frame_8(tx_frame_8), //OUTPUT : Frame
.wa_boundary_8(wa_boundary_8), //OUTPUT : Word Aligner Boundary
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(link_status[8]), //INPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_8(tx_egress_timestamp_request_valid_8), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_8(tx_egress_timestamp_request_fingerprint_8), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_8(tx_etstamp_ins_ctrl_ingress_timestamp_96b_8), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_8(tx_etstamp_ins_ctrl_ingress_timestamp_64b_8), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_8(tx_etstamp_ins_ctrl_timestamp_insert_8), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_8(tx_etstamp_ins_ctrl_residence_time_update_8), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_8(tx_etstamp_ins_ctrl_checksum_zero_8), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_8(tx_etstamp_ins_ctrl_checksum_correct_8), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_8(tx_etstamp_ins_ctrl_residence_time_calc_format_8), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_8(tx_etstamp_ins_ctrl_timestamp_format_8), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_8(tx_etstamp_ins_ctrl_offset_timestamp_8), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_8(tx_etstamp_ins_ctrl_offset_correction_field_8), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_8(tx_etstamp_ins_ctrl_offset_checksum_field_8), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_8(tx_etstamp_ins_ctrl_offset_checksum_correction_8), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_8(tx_time_of_day_96b_data_8), // Time of Day
.tx_time_of_day_64b_data_8(tx_time_of_day_64b_data_8), // Time of Day
.tx_egress_timestamp_96b_valid_8(tx_egress_timestamp_96b_valid_8), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_8(tx_egress_timestamp_96b_data_8), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_8(tx_egress_timestamp_96b_fingerprint_8), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_8(tx_egress_timestamp_64b_valid_8), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_8(tx_egress_timestamp_64b_data_8), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_8(tx_egress_timestamp_64b_fingerprint_8), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_8(rx_ingress_timestamp_96b_valid_8), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_8(rx_ingress_timestamp_96b_data_8), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_8(rx_ingress_timestamp_64b_valid_8), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_8(rx_ingress_timestamp_64b_data_8), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_8(rx_time_of_day_96b_data_8), // Time of Day
.rx_time_of_day_64b_data_8(rx_time_of_day_64b_data_8), //INPUT: Time of Day
// Channel 9
.rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
.rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
.rx_clkout_9(rx_pcs_clk_c9), //INPUT : Receive Clock
.tx_clkout_9(tx_pcs_clk_c9), //INPUT : Transmit Clock
.rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
.tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
.rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
.tx_frame_9(tx_frame_9), //OUTPUT : Frame
.wa_boundary_9(wa_boundary_9), //OUTPUT : Word Aligner Boundary
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(link_status[9]), //INPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_9(tx_egress_timestamp_request_valid_9), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_9(tx_egress_timestamp_request_fingerprint_9), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_9(tx_etstamp_ins_ctrl_ingress_timestamp_96b_9), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_9(tx_etstamp_ins_ctrl_ingress_timestamp_64b_9), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_9(tx_etstamp_ins_ctrl_timestamp_insert_9), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_9(tx_etstamp_ins_ctrl_residence_time_update_9), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_9(tx_etstamp_ins_ctrl_checksum_zero_9), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_9(tx_etstamp_ins_ctrl_checksum_correct_9), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_9(tx_etstamp_ins_ctrl_residence_time_calc_format_9), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_9(tx_etstamp_ins_ctrl_timestamp_format_9), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_9(tx_etstamp_ins_ctrl_offset_timestamp_9), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_9(tx_etstamp_ins_ctrl_offset_correction_field_9), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_9(tx_etstamp_ins_ctrl_offset_checksum_field_9), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_9(tx_etstamp_ins_ctrl_offset_checksum_correction_9), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_9(tx_time_of_day_96b_data_9), // Time of Day
.tx_time_of_day_64b_data_9(tx_time_of_day_64b_data_9), // Time of Day
.tx_egress_timestamp_96b_valid_9(tx_egress_timestamp_96b_valid_9), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_9(tx_egress_timestamp_96b_data_9), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_9(tx_egress_timestamp_96b_fingerprint_9), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_9(tx_egress_timestamp_64b_valid_9), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_9(tx_egress_timestamp_64b_data_9), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_9(tx_egress_timestamp_64b_fingerprint_9), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_9(rx_ingress_timestamp_96b_valid_9), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_9(rx_ingress_timestamp_96b_data_9), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_9(rx_ingress_timestamp_64b_valid_9), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_9(rx_ingress_timestamp_64b_data_9), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_9(rx_time_of_day_96b_data_9), // Time of Day
.rx_time_of_day_64b_data_9(rx_time_of_day_64b_data_9), //INPUT: Time of Day
// Channel 10
.rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
.rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
.rx_clkout_10(rx_pcs_clk_c10), //INPUT : Receive Clock
.tx_clkout_10(tx_pcs_clk_c10), //INPUT : Transmit Clock
.rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
.tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
.rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
.tx_frame_10(tx_frame_10), //OUTPUT : Frame
.wa_boundary_10(wa_boundary_10), //OUTPUT : Word Aligner Boundary
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(link_status[10]), //INPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_10(tx_egress_timestamp_request_valid_10), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_10(tx_egress_timestamp_request_fingerprint_10), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_10(tx_etstamp_ins_ctrl_ingress_timestamp_96b_10), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_10(tx_etstamp_ins_ctrl_ingress_timestamp_64b_10), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_10(tx_etstamp_ins_ctrl_timestamp_insert_10), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_10(tx_etstamp_ins_ctrl_residence_time_update_10), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_10(tx_etstamp_ins_ctrl_checksum_zero_10), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_10(tx_etstamp_ins_ctrl_checksum_correct_10), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_10(tx_etstamp_ins_ctrl_residence_time_calc_format_10), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_10(tx_etstamp_ins_ctrl_timestamp_format_10), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_10(tx_etstamp_ins_ctrl_offset_timestamp_10), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_10(tx_etstamp_ins_ctrl_offset_correction_field_10), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_10(tx_etstamp_ins_ctrl_offset_checksum_field_10), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_10(tx_etstamp_ins_ctrl_offset_checksum_correction_10), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_10(tx_time_of_day_96b_data_10), // Time of Day
.tx_time_of_day_64b_data_10(tx_time_of_day_64b_data_10), // Time of Day
.tx_egress_timestamp_96b_valid_10(tx_egress_timestamp_96b_valid_10), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_10(tx_egress_timestamp_96b_data_10), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_10(tx_egress_timestamp_96b_fingerprint_10), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_10(tx_egress_timestamp_64b_valid_10), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_10(tx_egress_timestamp_64b_data_10), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_10(tx_egress_timestamp_64b_fingerprint_10), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_10(rx_ingress_timestamp_96b_valid_10), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_10(rx_ingress_timestamp_96b_data_10), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_10(rx_ingress_timestamp_64b_valid_10), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_10(rx_ingress_timestamp_64b_data_10), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_10(rx_time_of_day_96b_data_10), // Time of Day
.rx_time_of_day_64b_data_10(rx_time_of_day_64b_data_10), //INPUT: Time of Day
// Channel 11
.rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
.rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
.rx_clkout_11(rx_pcs_clk_c11), //INPUT : Receive Clock
.tx_clkout_11(tx_pcs_clk_c11), //INPUT : Transmit Clock
.rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
.tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
.rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
.tx_frame_11(tx_frame_11), //OUTPUT : Frame
.wa_boundary_11(wa_boundary_11), //OUTPUT : Word Aligner Boundary
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(link_status[11]), //INPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_11(tx_egress_timestamp_request_valid_11), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_11(tx_egress_timestamp_request_fingerprint_11), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_11(tx_etstamp_ins_ctrl_ingress_timestamp_96b_11), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_11(tx_etstamp_ins_ctrl_ingress_timestamp_64b_11), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_11(tx_etstamp_ins_ctrl_timestamp_insert_11), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_11(tx_etstamp_ins_ctrl_residence_time_update_11), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_11(tx_etstamp_ins_ctrl_checksum_zero_11), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_11(tx_etstamp_ins_ctrl_checksum_correct_11), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_11(tx_etstamp_ins_ctrl_residence_time_calc_format_11), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_11(tx_etstamp_ins_ctrl_timestamp_format_11), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_11(tx_etstamp_ins_ctrl_offset_timestamp_11), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_11(tx_etstamp_ins_ctrl_offset_correction_field_11), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_11(tx_etstamp_ins_ctrl_offset_checksum_field_11), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_11(tx_etstamp_ins_ctrl_offset_checksum_correction_11), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_11(tx_time_of_day_96b_data_11), // Time of Day
.tx_time_of_day_64b_data_11(tx_time_of_day_64b_data_11), // Time of Day
.tx_egress_timestamp_96b_valid_11(tx_egress_timestamp_96b_valid_11), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_11(tx_egress_timestamp_96b_data_11), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_11(tx_egress_timestamp_96b_fingerprint_11), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_11(tx_egress_timestamp_64b_valid_11), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_11(tx_egress_timestamp_64b_data_11), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_11(tx_egress_timestamp_64b_fingerprint_11), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_11(rx_ingress_timestamp_96b_valid_11), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_11(rx_ingress_timestamp_96b_data_11), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_11(rx_ingress_timestamp_64b_valid_11), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_11(rx_ingress_timestamp_64b_data_11), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_11(rx_time_of_day_96b_data_11), // Time of Day
.rx_time_of_day_64b_data_11(rx_time_of_day_64b_data_11), //INPUT: Time of Day
// Channel 12
.rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
.rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
.rx_clkout_12(rx_pcs_clk_c12), //INPUT : Receive Clock
.tx_clkout_12(tx_pcs_clk_c12), //INPUT : Transmit Clock
.rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
.tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
.rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
.tx_frame_12(tx_frame_12), //OUTPUT : Frame
.wa_boundary_12(wa_boundary_12), //OUTPUT : Word Aligner Boundary
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(link_status[12]), //INPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_12(tx_egress_timestamp_request_valid_12), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_12(tx_egress_timestamp_request_fingerprint_12), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_12(tx_etstamp_ins_ctrl_ingress_timestamp_96b_12), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_12(tx_etstamp_ins_ctrl_ingress_timestamp_64b_12), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_12(tx_etstamp_ins_ctrl_timestamp_insert_12), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_12(tx_etstamp_ins_ctrl_residence_time_update_12), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_12(tx_etstamp_ins_ctrl_checksum_zero_12), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_12(tx_etstamp_ins_ctrl_checksum_correct_12), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_12(tx_etstamp_ins_ctrl_residence_time_calc_format_12), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_12(tx_etstamp_ins_ctrl_timestamp_format_12), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_12(tx_etstamp_ins_ctrl_offset_timestamp_12), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_12(tx_etstamp_ins_ctrl_offset_correction_field_12), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_12(tx_etstamp_ins_ctrl_offset_checksum_field_12), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_12(tx_etstamp_ins_ctrl_offset_checksum_correction_12), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_12(tx_time_of_day_96b_data_12), // Time of Day
.tx_time_of_day_64b_data_12(tx_time_of_day_64b_data_12), // Time of Day
.tx_egress_timestamp_96b_valid_12(tx_egress_timestamp_96b_valid_12), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_12(tx_egress_timestamp_96b_data_12), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_12(tx_egress_timestamp_96b_fingerprint_12), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_12(tx_egress_timestamp_64b_valid_12), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_12(tx_egress_timestamp_64b_data_12), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_12(tx_egress_timestamp_64b_fingerprint_12), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_12(rx_ingress_timestamp_96b_valid_12), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_12(rx_ingress_timestamp_96b_data_12), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_12(rx_ingress_timestamp_64b_valid_12), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_12(rx_ingress_timestamp_64b_data_12), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_12(rx_time_of_day_96b_data_12), // Time of Day
.rx_time_of_day_64b_data_12(rx_time_of_day_64b_data_12), //INPUT: Time of Day
// Channel 13
.rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
.rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
.rx_clkout_13(rx_pcs_clk_c13), //INPUT : Receive Clock
.tx_clkout_13(tx_pcs_clk_c13), //INPUT : Transmit Clock
.rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
.tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
.rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
.tx_frame_13(tx_frame_13), //OUTPUT : Frame
.wa_boundary_13(wa_boundary_13), //OUTPUT : Word Aligner Boundary
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(link_status[13]), //INPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_13(tx_egress_timestamp_request_valid_13), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_13(tx_egress_timestamp_request_fingerprint_13), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_13(tx_etstamp_ins_ctrl_ingress_timestamp_96b_13), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_13(tx_etstamp_ins_ctrl_ingress_timestamp_64b_13), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_13(tx_etstamp_ins_ctrl_timestamp_insert_13), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_13(tx_etstamp_ins_ctrl_residence_time_update_13), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_13(tx_etstamp_ins_ctrl_checksum_zero_13), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_13(tx_etstamp_ins_ctrl_checksum_correct_13), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_13(tx_etstamp_ins_ctrl_residence_time_calc_format_13), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_13(tx_etstamp_ins_ctrl_timestamp_format_13), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_13(tx_etstamp_ins_ctrl_offset_timestamp_13), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_13(tx_etstamp_ins_ctrl_offset_correction_field_13), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_13(tx_etstamp_ins_ctrl_offset_checksum_field_13), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_13(tx_etstamp_ins_ctrl_offset_checksum_correction_13), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_13(tx_time_of_day_96b_data_13), // Time of Day
.tx_time_of_day_64b_data_13(tx_time_of_day_64b_data_13), // Time of Day
.tx_egress_timestamp_96b_valid_13(tx_egress_timestamp_96b_valid_13), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_13(tx_egress_timestamp_96b_data_13), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_13(tx_egress_timestamp_96b_fingerprint_13), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_13(tx_egress_timestamp_64b_valid_13), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_13(tx_egress_timestamp_64b_data_13), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_13(tx_egress_timestamp_64b_fingerprint_13), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_13(rx_ingress_timestamp_96b_valid_13), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_13(rx_ingress_timestamp_96b_data_13), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_13(rx_ingress_timestamp_64b_valid_13), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_13(rx_ingress_timestamp_64b_data_13), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_13(rx_time_of_day_96b_data_13), // Time of Day
.rx_time_of_day_64b_data_13(rx_time_of_day_64b_data_13), //INPUT: Time of Day
// Channel 14
.rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
.rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
.rx_clkout_14(rx_pcs_clk_c14), //INPUT : Receive Clock
.tx_clkout_14(tx_pcs_clk_c14), //INPUT : Transmit Clock
.rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
.tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
.rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
.tx_frame_14(tx_frame_14), //OUTPUT : Frame
.wa_boundary_14(wa_boundary_14), //OUTPUT : Word Aligner Boundary
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(link_status[14]), //INPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_14(tx_egress_timestamp_request_valid_14), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_14(tx_egress_timestamp_request_fingerprint_14), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_14(tx_etstamp_ins_ctrl_ingress_timestamp_96b_14), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_14(tx_etstamp_ins_ctrl_ingress_timestamp_64b_14), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_14(tx_etstamp_ins_ctrl_timestamp_insert_14), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_14(tx_etstamp_ins_ctrl_residence_time_update_14), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_14(tx_etstamp_ins_ctrl_checksum_zero_14), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_14(tx_etstamp_ins_ctrl_checksum_correct_14), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_14(tx_etstamp_ins_ctrl_residence_time_calc_format_14), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_14(tx_etstamp_ins_ctrl_timestamp_format_14), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_14(tx_etstamp_ins_ctrl_offset_timestamp_14), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_14(tx_etstamp_ins_ctrl_offset_correction_field_14), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_14(tx_etstamp_ins_ctrl_offset_checksum_field_14), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_14(tx_etstamp_ins_ctrl_offset_checksum_correction_14), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_14(tx_time_of_day_96b_data_14), // Time of Day
.tx_time_of_day_64b_data_14(tx_time_of_day_64b_data_14), // Time of Day
.tx_egress_timestamp_96b_valid_14(tx_egress_timestamp_96b_valid_14), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_14(tx_egress_timestamp_96b_data_14), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_14(tx_egress_timestamp_96b_fingerprint_14), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_14(tx_egress_timestamp_64b_valid_14), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_14(tx_egress_timestamp_64b_data_14), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_14(tx_egress_timestamp_64b_fingerprint_14), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_14(rx_ingress_timestamp_96b_valid_14), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_14(rx_ingress_timestamp_96b_data_14), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_14(rx_ingress_timestamp_64b_valid_14), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_14(rx_ingress_timestamp_64b_data_14), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_14(rx_time_of_day_96b_data_14), // Time of Day
.rx_time_of_day_64b_data_14(rx_time_of_day_64b_data_14), //INPUT: Time of Day
// Channel 15
.rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
.rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
.rx_clkout_15(rx_pcs_clk_c15), //INPUT : Receive Clock
.tx_clkout_15(tx_pcs_clk_c15), //INPUT : Transmit Clock
.rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
.tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
.rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
.tx_frame_15(tx_frame_15), //OUTPUT : Frame
.wa_boundary_15(wa_boundary_15), //OUTPUT : Word Aligner Boundary
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(link_status[15]), //INPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_15(tx_egress_timestamp_request_valid_15), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_15(tx_egress_timestamp_request_fingerprint_15), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_15(tx_etstamp_ins_ctrl_ingress_timestamp_96b_15), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_15(tx_etstamp_ins_ctrl_ingress_timestamp_64b_15), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_15(tx_etstamp_ins_ctrl_timestamp_insert_15), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_15(tx_etstamp_ins_ctrl_residence_time_update_15), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_15(tx_etstamp_ins_ctrl_checksum_zero_15), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_15(tx_etstamp_ins_ctrl_checksum_correct_15), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_15(tx_etstamp_ins_ctrl_residence_time_calc_format_15), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_15(tx_etstamp_ins_ctrl_timestamp_format_15), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_15(tx_etstamp_ins_ctrl_offset_timestamp_15), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_15(tx_etstamp_ins_ctrl_offset_correction_field_15), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_15(tx_etstamp_ins_ctrl_offset_checksum_field_15), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_15(tx_etstamp_ins_ctrl_offset_checksum_correction_15), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_15(tx_time_of_day_96b_data_15), // Time of Day
.tx_time_of_day_64b_data_15(tx_time_of_day_64b_data_15), // Time of Day
.tx_egress_timestamp_96b_valid_15(tx_egress_timestamp_96b_valid_15), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_15(tx_egress_timestamp_96b_data_15), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_15(tx_egress_timestamp_96b_fingerprint_15), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_15(tx_egress_timestamp_64b_valid_15), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_15(tx_egress_timestamp_64b_data_15), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_15(tx_egress_timestamp_64b_fingerprint_15), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_15(rx_ingress_timestamp_96b_valid_15), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_15(rx_ingress_timestamp_96b_data_15), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_15(rx_ingress_timestamp_64b_valid_15), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_15(rx_ingress_timestamp_64b_data_15), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_15(rx_time_of_day_96b_data_15), // Time of Day
.rx_time_of_day_64b_data_15(rx_time_of_day_64b_data_15), //INPUT: Time of Day
// Channel 16
.rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
.rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
.rx_clkout_16(rx_pcs_clk_c16), //INPUT : Receive Clock
.tx_clkout_16(tx_pcs_clk_c16), //INPUT : Transmit Clock
.rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
.tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
.rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
.tx_frame_16(tx_frame_16), //OUTPUT : Frame
.wa_boundary_16(wa_boundary_16), //OUTPUT : Word Aligner Boundary
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(link_status[16]), //INPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_16(tx_egress_timestamp_request_valid_16), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_16(tx_egress_timestamp_request_fingerprint_16), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_16(tx_etstamp_ins_ctrl_ingress_timestamp_96b_16), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_16(tx_etstamp_ins_ctrl_ingress_timestamp_64b_16), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_16(tx_etstamp_ins_ctrl_timestamp_insert_16), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_16(tx_etstamp_ins_ctrl_residence_time_update_16), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_16(tx_etstamp_ins_ctrl_checksum_zero_16), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_16(tx_etstamp_ins_ctrl_checksum_correct_16), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_16(tx_etstamp_ins_ctrl_residence_time_calc_format_16), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_16(tx_etstamp_ins_ctrl_timestamp_format_16), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_16(tx_etstamp_ins_ctrl_offset_timestamp_16), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_16(tx_etstamp_ins_ctrl_offset_correction_field_16), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_16(tx_etstamp_ins_ctrl_offset_checksum_field_16), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_16(tx_etstamp_ins_ctrl_offset_checksum_correction_16), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_16(tx_time_of_day_96b_data_16), // Time of Day
.tx_time_of_day_64b_data_16(tx_time_of_day_64b_data_16), // Time of Day
.tx_egress_timestamp_96b_valid_16(tx_egress_timestamp_96b_valid_16), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_16(tx_egress_timestamp_96b_data_16), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_16(tx_egress_timestamp_96b_fingerprint_16), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_16(tx_egress_timestamp_64b_valid_16), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_16(tx_egress_timestamp_64b_data_16), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_16(tx_egress_timestamp_64b_fingerprint_16), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_16(rx_ingress_timestamp_96b_valid_16), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_16(rx_ingress_timestamp_96b_data_16), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_16(rx_ingress_timestamp_64b_valid_16), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_16(rx_ingress_timestamp_64b_data_16), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_16(rx_time_of_day_96b_data_16), // Time of Day
.rx_time_of_day_64b_data_16(rx_time_of_day_64b_data_16), //INPUT: Time of Day
// Channel 17
.rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
.rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
.rx_clkout_17(rx_pcs_clk_c17), //INPUT : Receive Clock
.tx_clkout_17(tx_pcs_clk_c17), //INPUT : Transmit Clock
.rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
.tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
.rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
.tx_frame_17(tx_frame_17), //OUTPUT : Frame
.wa_boundary_17(wa_boundary_17), //OUTPUT : Word Aligner Boundary
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(link_status[17]), //INPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_17(tx_egress_timestamp_request_valid_17), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_17(tx_egress_timestamp_request_fingerprint_17), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_17(tx_etstamp_ins_ctrl_ingress_timestamp_96b_17), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_17(tx_etstamp_ins_ctrl_ingress_timestamp_64b_17), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_17(tx_etstamp_ins_ctrl_timestamp_insert_17), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_17(tx_etstamp_ins_ctrl_residence_time_update_17), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_17(tx_etstamp_ins_ctrl_checksum_zero_17), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_17(tx_etstamp_ins_ctrl_checksum_correct_17), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_17(tx_etstamp_ins_ctrl_residence_time_calc_format_17), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_17(tx_etstamp_ins_ctrl_timestamp_format_17), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_17(tx_etstamp_ins_ctrl_offset_timestamp_17), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_17(tx_etstamp_ins_ctrl_offset_correction_field_17), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_17(tx_etstamp_ins_ctrl_offset_checksum_field_17), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_17(tx_etstamp_ins_ctrl_offset_checksum_correction_17), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_17(tx_time_of_day_96b_data_17), // Time of Day
.tx_time_of_day_64b_data_17(tx_time_of_day_64b_data_17), // Time of Day
.tx_egress_timestamp_96b_valid_17(tx_egress_timestamp_96b_valid_17), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_17(tx_egress_timestamp_96b_data_17), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_17(tx_egress_timestamp_96b_fingerprint_17), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_17(tx_egress_timestamp_64b_valid_17), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_17(tx_egress_timestamp_64b_data_17), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_17(tx_egress_timestamp_64b_fingerprint_17), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_17(rx_ingress_timestamp_96b_valid_17), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_17(rx_ingress_timestamp_96b_data_17), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_17(rx_ingress_timestamp_64b_valid_17), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_17(rx_ingress_timestamp_64b_data_17), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_17(rx_time_of_day_96b_data_17), // Time of Day
.rx_time_of_day_64b_data_17(rx_time_of_day_64b_data_17), //INPUT: Time of Day
// Channel 18
.rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
.rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
.rx_clkout_18(rx_pcs_clk_c18), //INPUT : Receive Clock
.tx_clkout_18(tx_pcs_clk_c18), //INPUT : Transmit Clock
.rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
.tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
.rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
.tx_frame_18(tx_frame_18), //OUTPUT : Frame
.wa_boundary_18(wa_boundary_18), //OUTPUT : Word Aligner Boundary
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(link_status[18]), //INPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_18(tx_egress_timestamp_request_valid_18), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_18(tx_egress_timestamp_request_fingerprint_18), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_18(tx_etstamp_ins_ctrl_ingress_timestamp_96b_18), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_18(tx_etstamp_ins_ctrl_ingress_timestamp_64b_18), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_18(tx_etstamp_ins_ctrl_timestamp_insert_18), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_18(tx_etstamp_ins_ctrl_residence_time_update_18), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_18(tx_etstamp_ins_ctrl_checksum_zero_18), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_18(tx_etstamp_ins_ctrl_checksum_correct_18), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_18(tx_etstamp_ins_ctrl_residence_time_calc_format_18), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_18(tx_etstamp_ins_ctrl_timestamp_format_18), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_18(tx_etstamp_ins_ctrl_offset_timestamp_18), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_18(tx_etstamp_ins_ctrl_offset_correction_field_18), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_18(tx_etstamp_ins_ctrl_offset_checksum_field_18), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_18(tx_etstamp_ins_ctrl_offset_checksum_correction_18), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_18(tx_time_of_day_96b_data_18), // Time of Day
.tx_time_of_day_64b_data_18(tx_time_of_day_64b_data_18), // Time of Day
.tx_egress_timestamp_96b_valid_18(tx_egress_timestamp_96b_valid_18), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_18(tx_egress_timestamp_96b_data_18), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_18(tx_egress_timestamp_96b_fingerprint_18), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_18(tx_egress_timestamp_64b_valid_18), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_18(tx_egress_timestamp_64b_data_18), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_18(tx_egress_timestamp_64b_fingerprint_18), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_18(rx_ingress_timestamp_96b_valid_18), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_18(rx_ingress_timestamp_96b_data_18), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_18(rx_ingress_timestamp_64b_valid_18), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_18(rx_ingress_timestamp_64b_data_18), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_18(rx_time_of_day_96b_data_18), // Time of Day
.rx_time_of_day_64b_data_18(rx_time_of_day_64b_data_18), //INPUT: Time of Day
// Channel 19
.rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
.rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
.rx_clkout_19(rx_pcs_clk_c19), //INPUT : Receive Clock
.tx_clkout_19(tx_pcs_clk_c19), //INPUT : Transmit Clock
.rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
.tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
.rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
.tx_frame_19(tx_frame_19), //OUTPUT : Frame
.wa_boundary_19(wa_boundary_19), //OUTPUT : Word Aligner Boundary
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(link_status[19]), //INPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_19(tx_egress_timestamp_request_valid_19), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_19(tx_egress_timestamp_request_fingerprint_19), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_19(tx_etstamp_ins_ctrl_ingress_timestamp_96b_19), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_19(tx_etstamp_ins_ctrl_ingress_timestamp_64b_19), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_19(tx_etstamp_ins_ctrl_timestamp_insert_19), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_19(tx_etstamp_ins_ctrl_residence_time_update_19), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_19(tx_etstamp_ins_ctrl_checksum_zero_19), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_19(tx_etstamp_ins_ctrl_checksum_correct_19), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_19(tx_etstamp_ins_ctrl_residence_time_calc_format_19), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_19(tx_etstamp_ins_ctrl_timestamp_format_19), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_19(tx_etstamp_ins_ctrl_offset_timestamp_19), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_19(tx_etstamp_ins_ctrl_offset_correction_field_19), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_19(tx_etstamp_ins_ctrl_offset_checksum_field_19), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_19(tx_etstamp_ins_ctrl_offset_checksum_correction_19), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_19(tx_time_of_day_96b_data_19), // Time of Day
.tx_time_of_day_64b_data_19(tx_time_of_day_64b_data_19), // Time of Day
.tx_egress_timestamp_96b_valid_19(tx_egress_timestamp_96b_valid_19), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_19(tx_egress_timestamp_96b_data_19), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_19(tx_egress_timestamp_96b_fingerprint_19), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_19(tx_egress_timestamp_64b_valid_19), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_19(tx_egress_timestamp_64b_data_19), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_19(tx_egress_timestamp_64b_fingerprint_19), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_19(rx_ingress_timestamp_96b_valid_19), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_19(rx_ingress_timestamp_96b_data_19), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_19(rx_ingress_timestamp_64b_valid_19), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_19(rx_ingress_timestamp_64b_data_19), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_19(rx_time_of_day_96b_data_19), // Time of Day
.rx_time_of_day_64b_data_19(rx_time_of_day_64b_data_19), //INPUT: Time of Day
// Channel 20
.rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
.rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
.rx_clkout_20(rx_pcs_clk_c20), //INPUT : Receive Clock
.tx_clkout_20(tx_pcs_clk_c20), //INPUT : Transmit Clock
.rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
.tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
.rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
.tx_frame_20(tx_frame_20), //OUTPUT : Frame
.wa_boundary_20(wa_boundary_20), //OUTPUT : Word Aligner Boundary
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(link_status[20]), //INPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_20(tx_egress_timestamp_request_valid_20), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_20(tx_egress_timestamp_request_fingerprint_20), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_20(tx_etstamp_ins_ctrl_ingress_timestamp_96b_20), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_20(tx_etstamp_ins_ctrl_ingress_timestamp_64b_20), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_20(tx_etstamp_ins_ctrl_timestamp_insert_20), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_20(tx_etstamp_ins_ctrl_residence_time_update_20), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_20(tx_etstamp_ins_ctrl_checksum_zero_20), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_20(tx_etstamp_ins_ctrl_checksum_correct_20), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_20(tx_etstamp_ins_ctrl_residence_time_calc_format_20), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_20(tx_etstamp_ins_ctrl_timestamp_format_20), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_20(tx_etstamp_ins_ctrl_offset_timestamp_20), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_20(tx_etstamp_ins_ctrl_offset_correction_field_20), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_20(tx_etstamp_ins_ctrl_offset_checksum_field_20), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_20(tx_etstamp_ins_ctrl_offset_checksum_correction_20), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_20(tx_time_of_day_96b_data_20), // Time of Day
.tx_time_of_day_64b_data_20(tx_time_of_day_64b_data_20), // Time of Day
.tx_egress_timestamp_96b_valid_20(tx_egress_timestamp_96b_valid_20), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_20(tx_egress_timestamp_96b_data_20), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_20(tx_egress_timestamp_96b_fingerprint_20), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_20(tx_egress_timestamp_64b_valid_20), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_20(tx_egress_timestamp_64b_data_20), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_20(tx_egress_timestamp_64b_fingerprint_20), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_20(rx_ingress_timestamp_96b_valid_20), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_20(rx_ingress_timestamp_96b_data_20), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_20(rx_ingress_timestamp_64b_valid_20), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_20(rx_ingress_timestamp_64b_data_20), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_20(rx_time_of_day_96b_data_20), // Time of Day
.rx_time_of_day_64b_data_20(rx_time_of_day_64b_data_20), //INPUT: Time of Day
// Channel 21
.rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
.rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
.rx_clkout_21(rx_pcs_clk_c21), //INPUT : Receive Clock
.tx_clkout_21(tx_pcs_clk_c21), //INPUT : Transmit Clock
.rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
.tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
.rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
.tx_frame_21(tx_frame_21), //OUTPUT : Frame
.wa_boundary_21(wa_boundary_21), //OUTPUT : Word Aligner Boundary
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(link_status[21]), //INPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_21(tx_egress_timestamp_request_valid_21), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_21(tx_egress_timestamp_request_fingerprint_21), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_21(tx_etstamp_ins_ctrl_ingress_timestamp_96b_21), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_21(tx_etstamp_ins_ctrl_ingress_timestamp_64b_21), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_21(tx_etstamp_ins_ctrl_timestamp_insert_21), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_21(tx_etstamp_ins_ctrl_residence_time_update_21), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_21(tx_etstamp_ins_ctrl_checksum_zero_21), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_21(tx_etstamp_ins_ctrl_checksum_correct_21), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_21(tx_etstamp_ins_ctrl_residence_time_calc_format_21), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_21(tx_etstamp_ins_ctrl_timestamp_format_21), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_21(tx_etstamp_ins_ctrl_offset_timestamp_21), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_21(tx_etstamp_ins_ctrl_offset_correction_field_21), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_21(tx_etstamp_ins_ctrl_offset_checksum_field_21), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_21(tx_etstamp_ins_ctrl_offset_checksum_correction_21), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_21(tx_time_of_day_96b_data_21), // Time of Day
.tx_time_of_day_64b_data_21(tx_time_of_day_64b_data_21), // Time of Day
.tx_egress_timestamp_96b_valid_21(tx_egress_timestamp_96b_valid_21), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_21(tx_egress_timestamp_96b_data_21), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_21(tx_egress_timestamp_96b_fingerprint_21), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_21(tx_egress_timestamp_64b_valid_21), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_21(tx_egress_timestamp_64b_data_21), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_21(tx_egress_timestamp_64b_fingerprint_21), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_21(rx_ingress_timestamp_96b_valid_21), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_21(rx_ingress_timestamp_96b_data_21), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_21(rx_ingress_timestamp_64b_valid_21), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_21(rx_ingress_timestamp_64b_data_21), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_21(rx_time_of_day_96b_data_21), // Time of Day
.rx_time_of_day_64b_data_21(rx_time_of_day_64b_data_21), //INPUT: Time of Day
// Channel 22
.rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
.rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
.rx_clkout_22(rx_pcs_clk_c22), //INPUT : Receive Clock
.tx_clkout_22(tx_pcs_clk_c22), //INPUT : Transmit Clock
.rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
.tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
.rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
.tx_frame_22(tx_frame_22), //OUTPUT : Frame
.wa_boundary_22(wa_boundary_22), //OUTPUT : Word Aligner Boundary
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(link_status[22]), //INPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_22(tx_egress_timestamp_request_valid_22), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_22(tx_egress_timestamp_request_fingerprint_22), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_22(tx_etstamp_ins_ctrl_ingress_timestamp_96b_22), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_22(tx_etstamp_ins_ctrl_ingress_timestamp_64b_22), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_22(tx_etstamp_ins_ctrl_timestamp_insert_22), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_22(tx_etstamp_ins_ctrl_residence_time_update_22), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_22(tx_etstamp_ins_ctrl_checksum_zero_22), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_22(tx_etstamp_ins_ctrl_checksum_correct_22), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_22(tx_etstamp_ins_ctrl_residence_time_calc_format_22), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_22(tx_etstamp_ins_ctrl_timestamp_format_22), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_22(tx_etstamp_ins_ctrl_offset_timestamp_22), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_22(tx_etstamp_ins_ctrl_offset_correction_field_22), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_22(tx_etstamp_ins_ctrl_offset_checksum_field_22), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_22(tx_etstamp_ins_ctrl_offset_checksum_correction_22), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_22(tx_time_of_day_96b_data_22), // Time of Day
.tx_time_of_day_64b_data_22(tx_time_of_day_64b_data_22), // Time of Day
.tx_egress_timestamp_96b_valid_22(tx_egress_timestamp_96b_valid_22), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_22(tx_egress_timestamp_96b_data_22), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_22(tx_egress_timestamp_96b_fingerprint_22), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_22(tx_egress_timestamp_64b_valid_22), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_22(tx_egress_timestamp_64b_data_22), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_22(tx_egress_timestamp_64b_fingerprint_22), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_22(rx_ingress_timestamp_96b_valid_22), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_22(rx_ingress_timestamp_96b_data_22), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_22(rx_ingress_timestamp_64b_valid_22), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_22(rx_ingress_timestamp_64b_data_22), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_22(rx_time_of_day_96b_data_22), // Time of Day
.rx_time_of_day_64b_data_22(rx_time_of_day_64b_data_22), //INPUT: Time of Day
// Channel 23
.rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
.rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
.rx_clkout_23(rx_pcs_clk_c23), //INPUT : Receive Clock
.tx_clkout_23(tx_pcs_clk_c23), //INPUT : Transmit Clock
.rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
.tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
.rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
.tx_frame_23(tx_frame_23), //OUTPUT : Frame
.wa_boundary_23(wa_boundary_23), //OUTPUT : Word Aligner Boundary
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(link_status[23]), //INPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23), //OUTPUT : MAC WAKE-UP INDICATION
//IEEE1588's code
.tx_egress_timestamp_request_valid_23(tx_egress_timestamp_request_valid_23), // Timestamp request valid from user
.tx_egress_timestamp_request_fingerprint_23(tx_egress_timestamp_request_fingerprint_23), // Fingerprint associated to the timestamp request
.tx_etstamp_ins_ctrl_ingress_timestamp_96b_23(tx_etstamp_ins_ctrl_ingress_timestamp_96b_23), // Ingress timestamp
.tx_etstamp_ins_ctrl_ingress_timestamp_64b_23(tx_etstamp_ins_ctrl_ingress_timestamp_64b_23), // Ingress timestamp
.tx_etstamp_ins_ctrl_timestamp_insert_23(tx_etstamp_ins_ctrl_timestamp_insert_23), // Timestamp insert
.tx_etstamp_ins_ctrl_residence_time_update_23(tx_etstamp_ins_ctrl_residence_time_update_23), // Residence time update
.tx_etstamp_ins_ctrl_checksum_zero_23(tx_etstamp_ins_ctrl_checksum_zero_23), // Set checksum field to zero
.tx_etstamp_ins_ctrl_checksum_correct_23(tx_etstamp_ins_ctrl_checksum_correct_23), // Correct extended 2bytes
.tx_etstamp_ins_ctrl_residence_time_calc_format_23(tx_etstamp_ins_ctrl_residence_time_calc_format_23), // Residence time calculation timestamp format -96/64
.tx_etstamp_ins_ctrl_timestamp_format_23(tx_etstamp_ins_ctrl_timestamp_format_23), // Timestamp format - v1 or v2
.tx_etstamp_ins_ctrl_offset_timestamp_23(tx_etstamp_ins_ctrl_offset_timestamp_23), // Timestamp field offset
.tx_etstamp_ins_ctrl_offset_correction_field_23(tx_etstamp_ins_ctrl_offset_correction_field_23), // Correction field offset
.tx_etstamp_ins_ctrl_offset_checksum_field_23(tx_etstamp_ins_ctrl_offset_checksum_field_23), // Udp checksum field offset
.tx_etstamp_ins_ctrl_offset_checksum_correction_23(tx_etstamp_ins_ctrl_offset_checksum_correction_23), // Extended 2 bytes field offset
.tx_time_of_day_96b_data_23(tx_time_of_day_96b_data_23), // Time of Day
.tx_time_of_day_64b_data_23(tx_time_of_day_64b_data_23), // Time of Day
.tx_egress_timestamp_96b_valid_23(tx_egress_timestamp_96b_valid_23), // tx 96bit egress timestamp valid
.tx_egress_timestamp_96b_data_23(tx_egress_timestamp_96b_data_23), // tx 96bit egress timestamp data
.tx_egress_timestamp_96b_fingerprint_23(tx_egress_timestamp_96b_fingerprint_23), // tx 96bit fingerprint
.tx_egress_timestamp_64b_valid_23(tx_egress_timestamp_64b_valid_23), // tx 64bit egress timestamp valid
.tx_egress_timestamp_64b_data_23(tx_egress_timestamp_64b_data_23), // tx 64bit egress timestamp data
.tx_egress_timestamp_64b_fingerprint_23(tx_egress_timestamp_64b_fingerprint_23), // tx 64bit fingerprint
.rx_ingress_timestamp_96b_valid_23(rx_ingress_timestamp_96b_valid_23), // rx 96bit egress timestamp valid
.rx_ingress_timestamp_96b_data_23(rx_ingress_timestamp_96b_data_23), // rx 96bit egress timestamp data
.rx_ingress_timestamp_64b_valid_23(rx_ingress_timestamp_64b_valid_23), // rx 64bit egress timestamp valid
.rx_ingress_timestamp_64b_data_23(rx_ingress_timestamp_64b_data_23), // rx 64bit egress timestamp data
.rx_time_of_day_96b_data_23(rx_time_of_day_96b_data_23), // Time of Day
.rx_time_of_day_64b_data_23(rx_time_of_day_64b_data_23)); //INPUT: Time of Day
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING,
U_MULTI_MAC_PCS.DEVICE_FAMILY = DEVICE_FAMILY,
U_MULTI_MAC_PCS.TSTAMP_FP_WIDTH = TSTAMP_FP_WIDTH,
U_MULTI_MAC_PCS.ENABLE_TIMESTAMPING = ENABLE_TIMESTAMPING,
U_MULTI_MAC_PCS.ENABLE_PTP_1STEP = ENABLE_PTP_1STEP;
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 0)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch0_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c0_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
(
.clk(rx_pcs_clk_c0),
.reset(reset_rx_pcs_clk_c0_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_0),
.alt_sync(rx_syncstatus[0]),
.alt_disperr(rx_disp_err[0]),
.alt_ctrldetect(rx_kchar_0),
.alt_errdetect(rx_char_err_gx[0]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
.alt_runlengthviolation(rx_runlengthviolation[0]),
.alt_patterndetect(rx_patterndetect[0]),
.alt_runningdisp(rx_runningdisp[0]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_0),
.altpcs_sync(link_status[0]),
.altpcs_disperr(led_disp_err_0),
.altpcs_ctrldetect(pcs_rx_kchar_0),
.altpcs_errdetect(led_char_err_gx[0]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[0])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_0
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_0),
.phy_mgmt_read(phy_mgmt_read_0),
.phy_mgmt_readdata(phy_mgmt_readdata_0),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_0),
.phy_mgmt_write(phy_mgmt_write_0),
.phy_mgmt_writedata(phy_mgmt_writedata_0),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_0),
.rx_serial_data(rxp_0),
.rx_runningdisp(rx_runningdisp[0]),
.rx_disperr(rx_disp_err[0]),
.rx_errdetect(rx_char_err_gx[0]),
.rx_patterndetect(rx_patterndetect[0]),
.rx_syncstatus(rx_syncstatus[0]),
.tx_clkout(tx_pcs_clk_c0),
.rx_clkout(rx_pcs_clk_c0),
.tx_parallel_data(tx_frame_0),
.tx_datak(tx_kchar_0),
.rx_parallel_data(rx_frame_0),
.rx_datak(rx_kchar_0),
.rx_rlv(rx_runlengthviolation[0]),
.rx_recovclkout(rx_recovclkout_0),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
.reconfig_togxb(reconfig_togxb_0),
.reconfig_fromgxb(reconfig_fromgxb_0),
.wa_boundary(wa_boundary_0)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_0 = {92{1'b0}};
assign led_char_err_gx[0] = 1'b0;
assign link_status[0] = 1'b0;
assign led_disp_err_0 = 1'b0;
assign txp_0 = 1'b0;
assign rx_recovclkout_0= 1'b0;
assign phy_mgmt_readdata_0 = 32'b0;
assign phy_mgmt_waitrequest_0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 1)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch1_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c1_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
(
.clk(rx_pcs_clk_c1),
.reset(reset_rx_pcs_clk_c1_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_1),
.alt_sync(rx_syncstatus[1]),
.alt_disperr(rx_disp_err[1]),
.alt_ctrldetect(rx_kchar_1),
.alt_errdetect(rx_char_err_gx[1]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
.alt_runlengthviolation(rx_runlengthviolation[1]),
.alt_patterndetect(rx_patterndetect[1]),
.alt_runningdisp(rx_runningdisp[1]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_1),
.altpcs_sync(link_status[1]),
.altpcs_disperr(led_disp_err_1),
.altpcs_ctrldetect(pcs_rx_kchar_1),
.altpcs_errdetect(led_char_err_gx[1]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[1])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_1
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_1),
.phy_mgmt_read(phy_mgmt_read_1),
.phy_mgmt_readdata(phy_mgmt_readdata_1),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_1),
.phy_mgmt_write(phy_mgmt_write_1),
.phy_mgmt_writedata(phy_mgmt_writedata_1),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_1),
.rx_serial_data(rxp_1),
.rx_runningdisp(rx_runningdisp[1]),
.rx_disperr(rx_disp_err[1]),
.rx_errdetect(rx_char_err_gx[1]),
.rx_patterndetect(rx_patterndetect[1]),
.rx_syncstatus(rx_syncstatus[1]),
.tx_clkout(tx_pcs_clk_c1),
.rx_clkout(rx_pcs_clk_c1),
.tx_parallel_data(tx_frame_1),
.tx_datak(tx_kchar_1),
.rx_parallel_data(rx_frame_1),
.rx_datak(rx_kchar_1),
.rx_rlv(rx_runlengthviolation[1]),
.rx_recovclkout(rx_recovclkout_1),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
.reconfig_togxb(reconfig_togxb_1),
.reconfig_fromgxb(reconfig_fromgxb_1),
.wa_boundary(wa_boundary_1)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_1 = {92{1'b0}};
assign led_char_err_gx[1] = 1'b0;
assign link_status[1] = 1'b0;
assign led_disp_err_1 = 1'b0;
assign txp_1 = 1'b0;
assign rx_recovclkout_1= 1'b0;
assign phy_mgmt_readdata_1 = 32'b0;
assign phy_mgmt_waitrequest_1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 2)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch2_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c2_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
(
.clk(rx_pcs_clk_c2),
.reset(reset_rx_pcs_clk_c2_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_2),
.alt_sync(rx_syncstatus[2]),
.alt_disperr(rx_disp_err[2]),
.alt_ctrldetect(rx_kchar_2),
.alt_errdetect(rx_char_err_gx[2]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
.alt_runlengthviolation(rx_runlengthviolation[2]),
.alt_patterndetect(rx_patterndetect[2]),
.alt_runningdisp(rx_runningdisp[2]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_2),
.altpcs_sync(link_status[2]),
.altpcs_disperr(led_disp_err_2),
.altpcs_ctrldetect(pcs_rx_kchar_2),
.altpcs_errdetect(led_char_err_gx[2]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[2])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_2
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_2),
.phy_mgmt_read(phy_mgmt_read_2),
.phy_mgmt_readdata(phy_mgmt_readdata_2),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_2),
.phy_mgmt_write(phy_mgmt_write_2),
.phy_mgmt_writedata(phy_mgmt_writedata_2),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_2),
.rx_serial_data(rxp_2),
.rx_runningdisp(rx_runningdisp[2]),
.rx_disperr(rx_disp_err[2]),
.rx_errdetect(rx_char_err_gx[2]),
.rx_patterndetect(rx_patterndetect[2]),
.rx_syncstatus(rx_syncstatus[2]),
.tx_clkout(tx_pcs_clk_c2),
.rx_clkout(rx_pcs_clk_c2),
.tx_parallel_data(tx_frame_2),
.tx_datak(tx_kchar_2),
.rx_parallel_data(rx_frame_2),
.rx_datak(rx_kchar_2),
.rx_rlv(rx_runlengthviolation[2]),
.rx_recovclkout(rx_recovclkout_2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
.reconfig_togxb(reconfig_togxb_2),
.reconfig_fromgxb(reconfig_fromgxb_2),
.wa_boundary(wa_boundary_2)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_2 = {92{1'b0}};
assign led_char_err_gx[2] = 1'b0;
assign link_status[2] = 1'b0;
assign led_disp_err_2 = 1'b0;
assign txp_2 = 1'b0;
assign rx_recovclkout_2= 1'b0;
assign phy_mgmt_readdata_2 = 32'b0;
assign phy_mgmt_waitrequest_2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 3)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch3_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c3_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
(
.clk(rx_pcs_clk_c3),
.reset(reset_rx_pcs_clk_c3_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_3),
.alt_sync(rx_syncstatus[3]),
.alt_disperr(rx_disp_err[3]),
.alt_ctrldetect(rx_kchar_3),
.alt_errdetect(rx_char_err_gx[3]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
.alt_runlengthviolation(rx_runlengthviolation[3]),
.alt_patterndetect(rx_patterndetect[3]),
.alt_runningdisp(rx_runningdisp[3]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_3),
.altpcs_sync(link_status[3]),
.altpcs_disperr(led_disp_err_3),
.altpcs_ctrldetect(pcs_rx_kchar_3),
.altpcs_errdetect(led_char_err_gx[3]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[3])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_3
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_3),
.phy_mgmt_read(phy_mgmt_read_3),
.phy_mgmt_readdata(phy_mgmt_readdata_3),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_3),
.phy_mgmt_write(phy_mgmt_write_3),
.phy_mgmt_writedata(phy_mgmt_writedata_3),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_3),
.rx_serial_data(rxp_3),
.rx_runningdisp(rx_runningdisp[3]),
.rx_disperr(rx_disp_err[3]),
.rx_errdetect(rx_char_err_gx[3]),
.rx_patterndetect(rx_patterndetect[3]),
.rx_syncstatus(rx_syncstatus[3]),
.tx_clkout(tx_pcs_clk_c3),
.rx_clkout(rx_pcs_clk_c3),
.tx_parallel_data(tx_frame_3),
.tx_datak(tx_kchar_3),
.rx_parallel_data(rx_frame_3),
.rx_datak(rx_kchar_3),
.rx_rlv(rx_runlengthviolation[3]),
.rx_recovclkout(rx_recovclkout_3),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
.reconfig_togxb(reconfig_togxb_3),
.reconfig_fromgxb(reconfig_fromgxb_3),
.wa_boundary(wa_boundary_3)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_3 = {92{1'b0}};
assign led_char_err_gx[3] = 1'b0;
assign link_status[3] = 1'b0;
assign led_disp_err_3 = 1'b0;
assign txp_3 = 1'b0;
assign rx_recovclkout_3= 1'b0;
assign phy_mgmt_readdata_3 = 32'b0;
assign phy_mgmt_waitrequest_3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 4)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch4_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c4_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
(
.clk(rx_pcs_clk_c4),
.reset(reset_rx_pcs_clk_c4_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_4),
.alt_sync(rx_syncstatus[4]),
.alt_disperr(rx_disp_err[4]),
.alt_ctrldetect(rx_kchar_4),
.alt_errdetect(rx_char_err_gx[4]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
.alt_runlengthviolation(rx_runlengthviolation[4]),
.alt_patterndetect(rx_patterndetect[4]),
.alt_runningdisp(rx_runningdisp[4]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_4),
.altpcs_sync(link_status[4]),
.altpcs_disperr(led_disp_err_4),
.altpcs_ctrldetect(pcs_rx_kchar_4),
.altpcs_errdetect(led_char_err_gx[4]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[4])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_4
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_4),
.phy_mgmt_read(phy_mgmt_read_4),
.phy_mgmt_readdata(phy_mgmt_readdata_4),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_4),
.phy_mgmt_write(phy_mgmt_write_4),
.phy_mgmt_writedata(phy_mgmt_writedata_4),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_4),
.rx_serial_data(rxp_4),
.rx_runningdisp(rx_runningdisp[4]),
.rx_disperr(rx_disp_err[4]),
.rx_errdetect(rx_char_err_gx[4]),
.rx_patterndetect(rx_patterndetect[4]),
.rx_syncstatus(rx_syncstatus[4]),
.tx_clkout(tx_pcs_clk_c4),
.rx_clkout(rx_pcs_clk_c4),
.tx_parallel_data(tx_frame_4),
.tx_datak(tx_kchar_4),
.rx_parallel_data(rx_frame_4),
.rx_datak(rx_kchar_4),
.rx_rlv(rx_runlengthviolation[4]),
.rx_recovclkout(rx_recovclkout_4),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
.reconfig_togxb(reconfig_togxb_4),
.reconfig_fromgxb(reconfig_fromgxb_4),
.wa_boundary(wa_boundary_4)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_4 = {92{1'b0}};
assign led_char_err_gx[4] = 1'b0;
assign link_status[4] = 1'b0;
assign led_disp_err_4 = 1'b0;
assign txp_4 = 1'b0;
assign rx_recovclkout_4= 1'b0;
assign phy_mgmt_readdata_4 = 32'b0;
assign phy_mgmt_waitrequest_4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 5)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch5_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c5_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
(
.clk(rx_pcs_clk_c5),
.reset(reset_rx_pcs_clk_c5_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_5),
.alt_sync(rx_syncstatus[5]),
.alt_disperr(rx_disp_err[5]),
.alt_ctrldetect(rx_kchar_5),
.alt_errdetect(rx_char_err_gx[5]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
.alt_runlengthviolation(rx_runlengthviolation[5]),
.alt_patterndetect(rx_patterndetect[5]),
.alt_runningdisp(rx_runningdisp[5]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_5),
.altpcs_sync(link_status[5]),
.altpcs_disperr(led_disp_err_5),
.altpcs_ctrldetect(pcs_rx_kchar_5),
.altpcs_errdetect(led_char_err_gx[5]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[5])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_5
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_5),
.phy_mgmt_read(phy_mgmt_read_5),
.phy_mgmt_readdata(phy_mgmt_readdata_5),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_5),
.phy_mgmt_write(phy_mgmt_write_5),
.phy_mgmt_writedata(phy_mgmt_writedata_5),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_5),
.rx_serial_data(rxp_5),
.rx_runningdisp(rx_runningdisp[5]),
.rx_disperr(rx_disp_err[5]),
.rx_errdetect(rx_char_err_gx[5]),
.rx_patterndetect(rx_patterndetect[5]),
.rx_syncstatus(rx_syncstatus[5]),
.tx_clkout(tx_pcs_clk_c5),
.rx_clkout(rx_pcs_clk_c5),
.tx_parallel_data(tx_frame_5),
.tx_datak(tx_kchar_5),
.rx_parallel_data(rx_frame_5),
.rx_datak(rx_kchar_5),
.rx_rlv(rx_runlengthviolation[5]),
.rx_recovclkout(rx_recovclkout_5),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
.reconfig_togxb(reconfig_togxb_5),
.reconfig_fromgxb(reconfig_fromgxb_5),
.wa_boundary(wa_boundary_5)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_5 = {92{1'b0}};
assign led_char_err_gx[5] = 1'b0;
assign link_status[5] = 1'b0;
assign led_disp_err_5 = 1'b0;
assign txp_5 = 1'b0;
assign rx_recovclkout_5= 1'b0;
assign phy_mgmt_readdata_5 = 32'b0;
assign phy_mgmt_waitrequest_5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 6)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch6_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c6_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
(
.clk(rx_pcs_clk_c6),
.reset(reset_rx_pcs_clk_c6_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_6),
.alt_sync(rx_syncstatus[6]),
.alt_disperr(rx_disp_err[6]),
.alt_ctrldetect(rx_kchar_6),
.alt_errdetect(rx_char_err_gx[6]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
.alt_runlengthviolation(rx_runlengthviolation[6]),
.alt_patterndetect(rx_patterndetect[6]),
.alt_runningdisp(rx_runningdisp[6]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_6),
.altpcs_sync(link_status[6]),
.altpcs_disperr(led_disp_err_6),
.altpcs_ctrldetect(pcs_rx_kchar_6),
.altpcs_errdetect(led_char_err_gx[6]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[6])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_6
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_6),
.phy_mgmt_read(phy_mgmt_read_6),
.phy_mgmt_readdata(phy_mgmt_readdata_6),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_6),
.phy_mgmt_write(phy_mgmt_write_6),
.phy_mgmt_writedata(phy_mgmt_writedata_6),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_6),
.rx_serial_data(rxp_6),
.rx_runningdisp(rx_runningdisp[6]),
.rx_disperr(rx_disp_err[6]),
.rx_errdetect(rx_char_err_gx[6]),
.rx_patterndetect(rx_patterndetect[6]),
.rx_syncstatus(rx_syncstatus[6]),
.tx_clkout(tx_pcs_clk_c6),
.rx_clkout(rx_pcs_clk_c6),
.tx_parallel_data(tx_frame_6),
.tx_datak(tx_kchar_6),
.rx_parallel_data(rx_frame_6),
.rx_datak(rx_kchar_6),
.rx_rlv(rx_runlengthviolation[6]),
.rx_recovclkout(rx_recovclkout_6),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
.reconfig_togxb(reconfig_togxb_6),
.reconfig_fromgxb(reconfig_fromgxb_6),
.wa_boundary(wa_boundary_6)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_6 = {92{1'b0}};
assign led_char_err_gx[6] = 1'b0;
assign link_status[6] = 1'b0;
assign led_disp_err_6 = 1'b0;
assign txp_6 = 1'b0;
assign rx_recovclkout_6= 1'b0;
assign phy_mgmt_readdata_6 = 32'b0;
assign phy_mgmt_waitrequest_6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 7)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch7_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c7_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
(
.clk(rx_pcs_clk_c7),
.reset(reset_rx_pcs_clk_c7_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_7),
.alt_sync(rx_syncstatus[7]),
.alt_disperr(rx_disp_err[7]),
.alt_ctrldetect(rx_kchar_7),
.alt_errdetect(rx_char_err_gx[7]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
.alt_runlengthviolation(rx_runlengthviolation[7]),
.alt_patterndetect(rx_patterndetect[7]),
.alt_runningdisp(rx_runningdisp[7]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_7),
.altpcs_sync(link_status[7]),
.altpcs_disperr(led_disp_err_7),
.altpcs_ctrldetect(pcs_rx_kchar_7),
.altpcs_errdetect(led_char_err_gx[7]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[7])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_7
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_7),
.phy_mgmt_read(phy_mgmt_read_7),
.phy_mgmt_readdata(phy_mgmt_readdata_7),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_7),
.phy_mgmt_write(phy_mgmt_write_7),
.phy_mgmt_writedata(phy_mgmt_writedata_7),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_7),
.rx_serial_data(rxp_7),
.rx_runningdisp(rx_runningdisp[7]),
.rx_disperr(rx_disp_err[7]),
.rx_errdetect(rx_char_err_gx[7]),
.rx_patterndetect(rx_patterndetect[7]),
.rx_syncstatus(rx_syncstatus[7]),
.tx_clkout(tx_pcs_clk_c7),
.rx_clkout(rx_pcs_clk_c7),
.tx_parallel_data(tx_frame_7),
.tx_datak(tx_kchar_7),
.rx_parallel_data(rx_frame_7),
.rx_datak(rx_kchar_7),
.rx_rlv(rx_runlengthviolation[7]),
.rx_recovclkout(rx_recovclkout_7),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
.reconfig_togxb(reconfig_togxb_7),
.reconfig_fromgxb(reconfig_fromgxb_7),
.wa_boundary(wa_boundary_7)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_7 = {92{1'b0}};
assign led_char_err_gx[7] = 1'b0;
assign link_status[7] = 1'b0;
assign led_disp_err_7 = 1'b0;
assign txp_7 = 1'b0;
assign rx_recovclkout_7= 1'b0;
assign phy_mgmt_readdata_7 = 32'b0;
assign phy_mgmt_waitrequest_7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 8)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch8_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c8_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
(
.clk(rx_pcs_clk_c8),
.reset(reset_rx_pcs_clk_c8_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_8),
.alt_sync(rx_syncstatus[8]),
.alt_disperr(rx_disp_err[8]),
.alt_ctrldetect(rx_kchar_8),
.alt_errdetect(rx_char_err_gx[8]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
.alt_runlengthviolation(rx_runlengthviolation[8]),
.alt_patterndetect(rx_patterndetect[8]),
.alt_runningdisp(rx_runningdisp[8]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_8),
.altpcs_sync(link_status[8]),
.altpcs_disperr(led_disp_err_8),
.altpcs_ctrldetect(pcs_rx_kchar_8),
.altpcs_errdetect(led_char_err_gx[8]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[8])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_8
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_8),
.phy_mgmt_read(phy_mgmt_read_8),
.phy_mgmt_readdata(phy_mgmt_readdata_8),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_8),
.phy_mgmt_write(phy_mgmt_write_8),
.phy_mgmt_writedata(phy_mgmt_writedata_8),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_8),
.rx_serial_data(rxp_8),
.rx_runningdisp(rx_runningdisp[8]),
.rx_disperr(rx_disp_err[8]),
.rx_errdetect(rx_char_err_gx[8]),
.rx_patterndetect(rx_patterndetect[8]),
.rx_syncstatus(rx_syncstatus[8]),
.tx_clkout(tx_pcs_clk_c8),
.rx_clkout(rx_pcs_clk_c8),
.tx_parallel_data(tx_frame_8),
.tx_datak(tx_kchar_8),
.rx_parallel_data(rx_frame_8),
.rx_datak(rx_kchar_8),
.rx_rlv(rx_runlengthviolation[8]),
.rx_recovclkout(rx_recovclkout_8),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
.reconfig_togxb(reconfig_togxb_8),
.reconfig_fromgxb(reconfig_fromgxb_8),
.wa_boundary(wa_boundary_8)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_8 = {92{1'b0}};
assign led_char_err_gx[8] = 1'b0;
assign link_status[8] = 1'b0;
assign led_disp_err_8 = 1'b0;
assign txp_8 = 1'b0;
assign rx_recovclkout_8= 1'b0;
assign phy_mgmt_readdata_8 = 32'b0;
assign phy_mgmt_waitrequest_8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 9)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch9_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c9_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
(
.clk(rx_pcs_clk_c9),
.reset(reset_rx_pcs_clk_c9_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_9),
.alt_sync(rx_syncstatus[9]),
.alt_disperr(rx_disp_err[9]),
.alt_ctrldetect(rx_kchar_9),
.alt_errdetect(rx_char_err_gx[9]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
.alt_runlengthviolation(rx_runlengthviolation[9]),
.alt_patterndetect(rx_patterndetect[9]),
.alt_runningdisp(rx_runningdisp[9]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_9),
.altpcs_sync(link_status[9]),
.altpcs_disperr(led_disp_err_9),
.altpcs_ctrldetect(pcs_rx_kchar_9),
.altpcs_errdetect(led_char_err_gx[9]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[9])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_9
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_9),
.phy_mgmt_read(phy_mgmt_read_9),
.phy_mgmt_readdata(phy_mgmt_readdata_9),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_9),
.phy_mgmt_write(phy_mgmt_write_9),
.phy_mgmt_writedata(phy_mgmt_writedata_9),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_9),
.rx_serial_data(rxp_9),
.rx_runningdisp(rx_runningdisp[9]),
.rx_disperr(rx_disp_err[9]),
.rx_errdetect(rx_char_err_gx[9]),
.rx_patterndetect(rx_patterndetect[9]),
.rx_syncstatus(rx_syncstatus[9]),
.tx_clkout(tx_pcs_clk_c9),
.rx_clkout(rx_pcs_clk_c9),
.tx_parallel_data(tx_frame_9),
.tx_datak(tx_kchar_9),
.rx_parallel_data(rx_frame_9),
.rx_datak(rx_kchar_9),
.rx_rlv(rx_runlengthviolation[9]),
.rx_recovclkout(rx_recovclkout_9),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
.reconfig_togxb(reconfig_togxb_9),
.reconfig_fromgxb(reconfig_fromgxb_9),
.wa_boundary(wa_boundary_9)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_9 = {92{1'b0}};
assign led_char_err_gx[9] = 1'b0;
assign link_status[9] = 1'b0;
assign led_disp_err_9 = 1'b0;
assign txp_9 = 1'b0;
assign rx_recovclkout_9= 1'b0;
assign phy_mgmt_readdata_9 = 32'b0;
assign phy_mgmt_waitrequest_9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 10)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch10_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c10_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
(
.clk(rx_pcs_clk_c10),
.reset(reset_rx_pcs_clk_c10_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_10),
.alt_sync(rx_syncstatus[10]),
.alt_disperr(rx_disp_err[10]),
.alt_ctrldetect(rx_kchar_10),
.alt_errdetect(rx_char_err_gx[10]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
.alt_runlengthviolation(rx_runlengthviolation[10]),
.alt_patterndetect(rx_patterndetect[10]),
.alt_runningdisp(rx_runningdisp[10]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_10),
.altpcs_sync(link_status[10]),
.altpcs_disperr(led_disp_err_10),
.altpcs_ctrldetect(pcs_rx_kchar_10),
.altpcs_errdetect(led_char_err_gx[10]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[10])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_10
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_10),
.phy_mgmt_read(phy_mgmt_read_10),
.phy_mgmt_readdata(phy_mgmt_readdata_10),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_10),
.phy_mgmt_write(phy_mgmt_write_10),
.phy_mgmt_writedata(phy_mgmt_writedata_10),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_10),
.rx_serial_data(rxp_10),
.rx_runningdisp(rx_runningdisp[10]),
.rx_disperr(rx_disp_err[10]),
.rx_errdetect(rx_char_err_gx[10]),
.rx_patterndetect(rx_patterndetect[10]),
.rx_syncstatus(rx_syncstatus[10]),
.tx_clkout(tx_pcs_clk_c10),
.rx_clkout(rx_pcs_clk_c10),
.tx_parallel_data(tx_frame_10),
.tx_datak(tx_kchar_10),
.rx_parallel_data(rx_frame_10),
.rx_datak(rx_kchar_10),
.rx_rlv(rx_runlengthviolation[10]),
.rx_recovclkout(rx_recovclkout_10),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
.reconfig_togxb(reconfig_togxb_10),
.reconfig_fromgxb(reconfig_fromgxb_10),
.wa_boundary(wa_boundary_10)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_10 = {92{1'b0}};
assign led_char_err_gx[10] = 1'b0;
assign link_status[10] = 1'b0;
assign led_disp_err_10 = 1'b0;
assign txp_10 = 1'b0;
assign rx_recovclkout_10= 1'b0;
assign phy_mgmt_readdata_10 = 32'b0;
assign phy_mgmt_waitrequest_10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 11)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch11_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c11_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
(
.clk(rx_pcs_clk_c11),
.reset(reset_rx_pcs_clk_c11_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_11),
.alt_sync(rx_syncstatus[11]),
.alt_disperr(rx_disp_err[11]),
.alt_ctrldetect(rx_kchar_11),
.alt_errdetect(rx_char_err_gx[11]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
.alt_runlengthviolation(rx_runlengthviolation[11]),
.alt_patterndetect(rx_patterndetect[11]),
.alt_runningdisp(rx_runningdisp[11]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_11),
.altpcs_sync(link_status[11]),
.altpcs_disperr(led_disp_err_11),
.altpcs_ctrldetect(pcs_rx_kchar_11),
.altpcs_errdetect(led_char_err_gx[11]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[11])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_11
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_11),
.phy_mgmt_read(phy_mgmt_read_11),
.phy_mgmt_readdata(phy_mgmt_readdata_11),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_11),
.phy_mgmt_write(phy_mgmt_write_11),
.phy_mgmt_writedata(phy_mgmt_writedata_11),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_11),
.rx_serial_data(rxp_11),
.rx_runningdisp(rx_runningdisp[11]),
.rx_disperr(rx_disp_err[11]),
.rx_errdetect(rx_char_err_gx[11]),
.rx_patterndetect(rx_patterndetect[11]),
.rx_syncstatus(rx_syncstatus[11]),
.tx_clkout(tx_pcs_clk_c11),
.rx_clkout(rx_pcs_clk_c11),
.tx_parallel_data(tx_frame_11),
.tx_datak(tx_kchar_11),
.rx_parallel_data(rx_frame_11),
.rx_datak(rx_kchar_11),
.rx_rlv(rx_runlengthviolation[11]),
.rx_recovclkout(rx_recovclkout_11),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
.reconfig_togxb(reconfig_togxb_11),
.reconfig_fromgxb(reconfig_fromgxb_11),
.wa_boundary(wa_boundary_11)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_11 = {92{1'b0}};
assign led_char_err_gx[11] = 1'b0;
assign link_status[11] = 1'b0;
assign led_disp_err_11 = 1'b0;
assign txp_11 = 1'b0;
assign rx_recovclkout_11= 1'b0;
assign phy_mgmt_readdata_11 = 32'b0;
assign phy_mgmt_waitrequest_11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 12)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch12_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c12_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
(
.clk(rx_pcs_clk_c12),
.reset(reset_rx_pcs_clk_c12_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_12),
.alt_sync(rx_syncstatus[12]),
.alt_disperr(rx_disp_err[12]),
.alt_ctrldetect(rx_kchar_12),
.alt_errdetect(rx_char_err_gx[12]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
.alt_runlengthviolation(rx_runlengthviolation[12]),
.alt_patterndetect(rx_patterndetect[12]),
.alt_runningdisp(rx_runningdisp[12]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_12),
.altpcs_sync(link_status[12]),
.altpcs_disperr(led_disp_err_12),
.altpcs_ctrldetect(pcs_rx_kchar_12),
.altpcs_errdetect(led_char_err_gx[12]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[12])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_12
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_12),
.phy_mgmt_read(phy_mgmt_read_12),
.phy_mgmt_readdata(phy_mgmt_readdata_12),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_12),
.phy_mgmt_write(phy_mgmt_write_12),
.phy_mgmt_writedata(phy_mgmt_writedata_12),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_12),
.rx_serial_data(rxp_12),
.rx_runningdisp(rx_runningdisp[12]),
.rx_disperr(rx_disp_err[12]),
.rx_errdetect(rx_char_err_gx[12]),
.rx_patterndetect(rx_patterndetect[12]),
.rx_syncstatus(rx_syncstatus[12]),
.tx_clkout(tx_pcs_clk_c12),
.rx_clkout(rx_pcs_clk_c12),
.tx_parallel_data(tx_frame_12),
.tx_datak(tx_kchar_12),
.rx_parallel_data(rx_frame_12),
.rx_datak(rx_kchar_12),
.rx_rlv(rx_runlengthviolation[12]),
.rx_recovclkout(rx_recovclkout_12),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
.reconfig_togxb(reconfig_togxb_12),
.reconfig_fromgxb(reconfig_fromgxb_12),
.wa_boundary(wa_boundary_12)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_12 = {92{1'b0}};
assign led_char_err_gx[12] = 1'b0;
assign link_status[12] = 1'b0;
assign led_disp_err_12 = 1'b0;
assign txp_12 = 1'b0;
assign rx_recovclkout_12= 1'b0;
assign phy_mgmt_readdata_12 = 32'b0;
assign phy_mgmt_waitrequest_12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 13)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch13_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c13_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
(
.clk(rx_pcs_clk_c13),
.reset(reset_rx_pcs_clk_c13_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_13),
.alt_sync(rx_syncstatus[13]),
.alt_disperr(rx_disp_err[13]),
.alt_ctrldetect(rx_kchar_13),
.alt_errdetect(rx_char_err_gx[13]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
.alt_runlengthviolation(rx_runlengthviolation[13]),
.alt_patterndetect(rx_patterndetect[13]),
.alt_runningdisp(rx_runningdisp[13]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_13),
.altpcs_sync(link_status[13]),
.altpcs_disperr(led_disp_err_13),
.altpcs_ctrldetect(pcs_rx_kchar_13),
.altpcs_errdetect(led_char_err_gx[13]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[13])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_13
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_13),
.phy_mgmt_read(phy_mgmt_read_13),
.phy_mgmt_readdata(phy_mgmt_readdata_13),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_13),
.phy_mgmt_write(phy_mgmt_write_13),
.phy_mgmt_writedata(phy_mgmt_writedata_13),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_13),
.rx_serial_data(rxp_13),
.rx_runningdisp(rx_runningdisp[13]),
.rx_disperr(rx_disp_err[13]),
.rx_errdetect(rx_char_err_gx[13]),
.rx_patterndetect(rx_patterndetect[13]),
.rx_syncstatus(rx_syncstatus[13]),
.tx_clkout(tx_pcs_clk_c13),
.rx_clkout(rx_pcs_clk_c13),
.tx_parallel_data(tx_frame_13),
.tx_datak(tx_kchar_13),
.rx_parallel_data(rx_frame_13),
.rx_datak(rx_kchar_13),
.rx_rlv(rx_runlengthviolation[13]),
.rx_recovclkout(rx_recovclkout_13),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
.reconfig_togxb(reconfig_togxb_13),
.reconfig_fromgxb(reconfig_fromgxb_13),
.wa_boundary(wa_boundary_13)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_13 = {92{1'b0}};
assign led_char_err_gx[13] = 1'b0;
assign link_status[13] = 1'b0;
assign led_disp_err_13 = 1'b0;
assign txp_13 = 1'b0;
assign rx_recovclkout_13= 1'b0;
assign phy_mgmt_readdata_13 = 32'b0;
assign phy_mgmt_waitrequest_13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 14)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch14_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c14_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
(
.clk(rx_pcs_clk_c14),
.reset(reset_rx_pcs_clk_c14_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_14),
.alt_sync(rx_syncstatus[14]),
.alt_disperr(rx_disp_err[14]),
.alt_ctrldetect(rx_kchar_14),
.alt_errdetect(rx_char_err_gx[14]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
.alt_runlengthviolation(rx_runlengthviolation[14]),
.alt_patterndetect(rx_patterndetect[14]),
.alt_runningdisp(rx_runningdisp[14]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_14),
.altpcs_sync(link_status[14]),
.altpcs_disperr(led_disp_err_14),
.altpcs_ctrldetect(pcs_rx_kchar_14),
.altpcs_errdetect(led_char_err_gx[14]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[14])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_14
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_14),
.phy_mgmt_read(phy_mgmt_read_14),
.phy_mgmt_readdata(phy_mgmt_readdata_14),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_14),
.phy_mgmt_write(phy_mgmt_write_14),
.phy_mgmt_writedata(phy_mgmt_writedata_14),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_14),
.rx_serial_data(rxp_14),
.rx_runningdisp(rx_runningdisp[14]),
.rx_disperr(rx_disp_err[14]),
.rx_errdetect(rx_char_err_gx[14]),
.rx_patterndetect(rx_patterndetect[14]),
.rx_syncstatus(rx_syncstatus[14]),
.tx_clkout(tx_pcs_clk_c14),
.rx_clkout(rx_pcs_clk_c14),
.tx_parallel_data(tx_frame_14),
.tx_datak(tx_kchar_14),
.rx_parallel_data(rx_frame_14),
.rx_datak(rx_kchar_14),
.rx_rlv(rx_runlengthviolation[14]),
.rx_recovclkout(rx_recovclkout_14),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
.reconfig_togxb(reconfig_togxb_14),
.reconfig_fromgxb(reconfig_fromgxb_14),
.wa_boundary(wa_boundary_14)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_14 = {92{1'b0}};
assign led_char_err_gx[14] = 1'b0;
assign link_status[14] = 1'b0;
assign led_disp_err_14 = 1'b0;
assign txp_14 = 1'b0;
assign rx_recovclkout_14= 1'b0;
assign phy_mgmt_readdata_14 = 32'b0;
assign phy_mgmt_waitrequest_14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 15)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch15_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c15_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
(
.clk(rx_pcs_clk_c15),
.reset(reset_rx_pcs_clk_c15_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_15),
.alt_sync(rx_syncstatus[15]),
.alt_disperr(rx_disp_err[15]),
.alt_ctrldetect(rx_kchar_15),
.alt_errdetect(rx_char_err_gx[15]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
.alt_runlengthviolation(rx_runlengthviolation[15]),
.alt_patterndetect(rx_patterndetect[15]),
.alt_runningdisp(rx_runningdisp[15]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_15),
.altpcs_sync(link_status[15]),
.altpcs_disperr(led_disp_err_15),
.altpcs_ctrldetect(pcs_rx_kchar_15),
.altpcs_errdetect(led_char_err_gx[15]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[15])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_15
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_15),
.phy_mgmt_read(phy_mgmt_read_15),
.phy_mgmt_readdata(phy_mgmt_readdata_15),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_15),
.phy_mgmt_write(phy_mgmt_write_15),
.phy_mgmt_writedata(phy_mgmt_writedata_15),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_15),
.rx_serial_data(rxp_15),
.rx_runningdisp(rx_runningdisp[15]),
.rx_disperr(rx_disp_err[15]),
.rx_errdetect(rx_char_err_gx[15]),
.rx_patterndetect(rx_patterndetect[15]),
.rx_syncstatus(rx_syncstatus[15]),
.tx_clkout(tx_pcs_clk_c15),
.rx_clkout(rx_pcs_clk_c15),
.tx_parallel_data(tx_frame_15),
.tx_datak(tx_kchar_15),
.rx_parallel_data(rx_frame_15),
.rx_datak(rx_kchar_15),
.rx_rlv(rx_runlengthviolation[15]),
.rx_recovclkout(rx_recovclkout_15),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
.reconfig_togxb(reconfig_togxb_15),
.reconfig_fromgxb(reconfig_fromgxb_15),
.wa_boundary(wa_boundary_15)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_15 = {92{1'b0}};
assign led_char_err_gx[15] = 1'b0;
assign link_status[15] = 1'b0;
assign led_disp_err_15 = 1'b0;
assign txp_15 = 1'b0;
assign rx_recovclkout_15= 1'b0;
assign phy_mgmt_readdata_15 = 32'b0;
assign phy_mgmt_waitrequest_15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 16)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch16_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c16_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
(
.clk(rx_pcs_clk_c16),
.reset(reset_rx_pcs_clk_c16_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_16),
.alt_sync(rx_syncstatus[16]),
.alt_disperr(rx_disp_err[16]),
.alt_ctrldetect(rx_kchar_16),
.alt_errdetect(rx_char_err_gx[16]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
.alt_runlengthviolation(rx_runlengthviolation[16]),
.alt_patterndetect(rx_patterndetect[16]),
.alt_runningdisp(rx_runningdisp[16]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_16),
.altpcs_sync(link_status[16]),
.altpcs_disperr(led_disp_err_16),
.altpcs_ctrldetect(pcs_rx_kchar_16),
.altpcs_errdetect(led_char_err_gx[16]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[16])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_16
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_16),
.phy_mgmt_read(phy_mgmt_read_16),
.phy_mgmt_readdata(phy_mgmt_readdata_16),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_16),
.phy_mgmt_write(phy_mgmt_write_16),
.phy_mgmt_writedata(phy_mgmt_writedata_16),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_16),
.rx_serial_data(rxp_16),
.rx_runningdisp(rx_runningdisp[16]),
.rx_disperr(rx_disp_err[16]),
.rx_errdetect(rx_char_err_gx[16]),
.rx_patterndetect(rx_patterndetect[16]),
.rx_syncstatus(rx_syncstatus[16]),
.tx_clkout(tx_pcs_clk_c16),
.rx_clkout(rx_pcs_clk_c16),
.tx_parallel_data(tx_frame_16),
.tx_datak(tx_kchar_16),
.rx_parallel_data(rx_frame_16),
.rx_datak(rx_kchar_16),
.rx_rlv(rx_runlengthviolation[16]),
.rx_recovclkout(rx_recovclkout_16),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
.reconfig_togxb(reconfig_togxb_16),
.reconfig_fromgxb(reconfig_fromgxb_16),
.wa_boundary(wa_boundary_16)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_16 = {92{1'b0}};
assign led_char_err_gx[16] = 1'b0;
assign link_status[16] = 1'b0;
assign led_disp_err_16 = 1'b0;
assign txp_16 = 1'b0;
assign rx_recovclkout_16= 1'b0;
assign phy_mgmt_readdata_16 = 32'b0;
assign phy_mgmt_waitrequest_16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 17)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch17_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c17_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
(
.clk(rx_pcs_clk_c17),
.reset(reset_rx_pcs_clk_c17_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_17),
.alt_sync(rx_syncstatus[17]),
.alt_disperr(rx_disp_err[17]),
.alt_ctrldetect(rx_kchar_17),
.alt_errdetect(rx_char_err_gx[17]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
.alt_runlengthviolation(rx_runlengthviolation[17]),
.alt_patterndetect(rx_patterndetect[17]),
.alt_runningdisp(rx_runningdisp[17]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_17),
.altpcs_sync(link_status[17]),
.altpcs_disperr(led_disp_err_17),
.altpcs_ctrldetect(pcs_rx_kchar_17),
.altpcs_errdetect(led_char_err_gx[17]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[17])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_17
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_17),
.phy_mgmt_read(phy_mgmt_read_17),
.phy_mgmt_readdata(phy_mgmt_readdata_17),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_17),
.phy_mgmt_write(phy_mgmt_write_17),
.phy_mgmt_writedata(phy_mgmt_writedata_17),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_17),
.rx_serial_data(rxp_17),
.rx_runningdisp(rx_runningdisp[17]),
.rx_disperr(rx_disp_err[17]),
.rx_errdetect(rx_char_err_gx[17]),
.rx_patterndetect(rx_patterndetect[17]),
.rx_syncstatus(rx_syncstatus[17]),
.tx_clkout(tx_pcs_clk_c17),
.rx_clkout(rx_pcs_clk_c17),
.tx_parallel_data(tx_frame_17),
.tx_datak(tx_kchar_17),
.rx_parallel_data(rx_frame_17),
.rx_datak(rx_kchar_17),
.rx_rlv(rx_runlengthviolation[17]),
.rx_recovclkout(rx_recovclkout_17),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
.reconfig_togxb(reconfig_togxb_17),
.reconfig_fromgxb(reconfig_fromgxb_17),
.wa_boundary(wa_boundary_17)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_17 = {92{1'b0}};
assign led_char_err_gx[17] = 1'b0;
assign link_status[17] = 1'b0;
assign led_disp_err_17 = 1'b0;
assign txp_17 = 1'b0;
assign rx_recovclkout_17= 1'b0;
assign phy_mgmt_readdata_17 = 32'b0;
assign phy_mgmt_waitrequest_17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 18)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch18_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c18_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
(
.clk(rx_pcs_clk_c18),
.reset(reset_rx_pcs_clk_c18_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_18),
.alt_sync(rx_syncstatus[18]),
.alt_disperr(rx_disp_err[18]),
.alt_ctrldetect(rx_kchar_18),
.alt_errdetect(rx_char_err_gx[18]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
.alt_runlengthviolation(rx_runlengthviolation[18]),
.alt_patterndetect(rx_patterndetect[18]),
.alt_runningdisp(rx_runningdisp[18]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_18),
.altpcs_sync(link_status[18]),
.altpcs_disperr(led_disp_err_18),
.altpcs_ctrldetect(pcs_rx_kchar_18),
.altpcs_errdetect(led_char_err_gx[18]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[18])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_18
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_18),
.phy_mgmt_read(phy_mgmt_read_18),
.phy_mgmt_readdata(phy_mgmt_readdata_18),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_18),
.phy_mgmt_write(phy_mgmt_write_18),
.phy_mgmt_writedata(phy_mgmt_writedata_18),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_18),
.rx_serial_data(rxp_18),
.rx_runningdisp(rx_runningdisp[18]),
.rx_disperr(rx_disp_err[18]),
.rx_errdetect(rx_char_err_gx[18]),
.rx_patterndetect(rx_patterndetect[18]),
.rx_syncstatus(rx_syncstatus[18]),
.tx_clkout(tx_pcs_clk_c18),
.rx_clkout(rx_pcs_clk_c18),
.tx_parallel_data(tx_frame_18),
.tx_datak(tx_kchar_18),
.rx_parallel_data(rx_frame_18),
.rx_datak(rx_kchar_18),
.rx_rlv(rx_runlengthviolation[18]),
.rx_recovclkout(rx_recovclkout_18),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
.reconfig_togxb(reconfig_togxb_18),
.reconfig_fromgxb(reconfig_fromgxb_18),
.wa_boundary(wa_boundary_18)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_18 = {92{1'b0}};
assign led_char_err_gx[18] = 1'b0;
assign link_status[18] = 1'b0;
assign led_disp_err_18 = 1'b0;
assign txp_18 = 1'b0;
assign rx_recovclkout_18= 1'b0;
assign phy_mgmt_readdata_18 = 32'b0;
assign phy_mgmt_waitrequest_18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 19)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch19_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c19_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
(
.clk(rx_pcs_clk_c19),
.reset(reset_rx_pcs_clk_c19_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_19),
.alt_sync(rx_syncstatus[19]),
.alt_disperr(rx_disp_err[19]),
.alt_ctrldetect(rx_kchar_19),
.alt_errdetect(rx_char_err_gx[19]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
.alt_runlengthviolation(rx_runlengthviolation[19]),
.alt_patterndetect(rx_patterndetect[19]),
.alt_runningdisp(rx_runningdisp[19]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_19),
.altpcs_sync(link_status[19]),
.altpcs_disperr(led_disp_err_19),
.altpcs_ctrldetect(pcs_rx_kchar_19),
.altpcs_errdetect(led_char_err_gx[19]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[19])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_19
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_19),
.phy_mgmt_read(phy_mgmt_read_19),
.phy_mgmt_readdata(phy_mgmt_readdata_19),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_19),
.phy_mgmt_write(phy_mgmt_write_19),
.phy_mgmt_writedata(phy_mgmt_writedata_19),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_19),
.rx_serial_data(rxp_19),
.rx_runningdisp(rx_runningdisp[19]),
.rx_disperr(rx_disp_err[19]),
.rx_errdetect(rx_char_err_gx[19]),
.rx_patterndetect(rx_patterndetect[19]),
.rx_syncstatus(rx_syncstatus[19]),
.tx_clkout(tx_pcs_clk_c19),
.rx_clkout(rx_pcs_clk_c19),
.tx_parallel_data(tx_frame_19),
.tx_datak(tx_kchar_19),
.rx_parallel_data(rx_frame_19),
.rx_datak(rx_kchar_19),
.rx_rlv(rx_runlengthviolation[19]),
.rx_recovclkout(rx_recovclkout_19),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
.reconfig_togxb(reconfig_togxb_19),
.reconfig_fromgxb(reconfig_fromgxb_19),
.wa_boundary(wa_boundary_19)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_19 = {92{1'b0}};
assign led_char_err_gx[19] = 1'b0;
assign link_status[19] = 1'b0;
assign led_disp_err_19 = 1'b0;
assign txp_19 = 1'b0;
assign rx_recovclkout_19= 1'b0;
assign phy_mgmt_readdata_19 = 32'b0;
assign phy_mgmt_waitrequest_19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 20)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch20_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c20_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
(
.clk(rx_pcs_clk_c20),
.reset(reset_rx_pcs_clk_c20_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_20),
.alt_sync(rx_syncstatus[20]),
.alt_disperr(rx_disp_err[20]),
.alt_ctrldetect(rx_kchar_20),
.alt_errdetect(rx_char_err_gx[20]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
.alt_runlengthviolation(rx_runlengthviolation[20]),
.alt_patterndetect(rx_patterndetect[20]),
.alt_runningdisp(rx_runningdisp[20]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_20),
.altpcs_sync(link_status[20]),
.altpcs_disperr(led_disp_err_20),
.altpcs_ctrldetect(pcs_rx_kchar_20),
.altpcs_errdetect(led_char_err_gx[20]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[20])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_20
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_20),
.phy_mgmt_read(phy_mgmt_read_20),
.phy_mgmt_readdata(phy_mgmt_readdata_20),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_20),
.phy_mgmt_write(phy_mgmt_write_20),
.phy_mgmt_writedata(phy_mgmt_writedata_20),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_20),
.rx_serial_data(rxp_20),
.rx_runningdisp(rx_runningdisp[20]),
.rx_disperr(rx_disp_err[20]),
.rx_errdetect(rx_char_err_gx[20]),
.rx_patterndetect(rx_patterndetect[20]),
.rx_syncstatus(rx_syncstatus[20]),
.tx_clkout(tx_pcs_clk_c20),
.rx_clkout(rx_pcs_clk_c20),
.tx_parallel_data(tx_frame_20),
.tx_datak(tx_kchar_20),
.rx_parallel_data(rx_frame_20),
.rx_datak(rx_kchar_20),
.rx_rlv(rx_runlengthviolation[20]),
.rx_recovclkout(rx_recovclkout_20),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
.reconfig_togxb(reconfig_togxb_20),
.reconfig_fromgxb(reconfig_fromgxb_20),
.wa_boundary(wa_boundary_20)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_20 = {92{1'b0}};
assign led_char_err_gx[20] = 1'b0;
assign link_status[20] = 1'b0;
assign led_disp_err_20 = 1'b0;
assign txp_20 = 1'b0;
assign rx_recovclkout_20= 1'b0;
assign phy_mgmt_readdata_20 = 32'b0;
assign phy_mgmt_waitrequest_20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 21)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch21_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c21_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
(
.clk(rx_pcs_clk_c21),
.reset(reset_rx_pcs_clk_c21_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_21),
.alt_sync(rx_syncstatus[21]),
.alt_disperr(rx_disp_err[21]),
.alt_ctrldetect(rx_kchar_21),
.alt_errdetect(rx_char_err_gx[21]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
.alt_runlengthviolation(rx_runlengthviolation[21]),
.alt_patterndetect(rx_patterndetect[21]),
.alt_runningdisp(rx_runningdisp[21]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_21),
.altpcs_sync(link_status[21]),
.altpcs_disperr(led_disp_err_21),
.altpcs_ctrldetect(pcs_rx_kchar_21),
.altpcs_errdetect(led_char_err_gx[21]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[21])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_21
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_21),
.phy_mgmt_read(phy_mgmt_read_21),
.phy_mgmt_readdata(phy_mgmt_readdata_21),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_21),
.phy_mgmt_write(phy_mgmt_write_21),
.phy_mgmt_writedata(phy_mgmt_writedata_21),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_21),
.rx_serial_data(rxp_21),
.rx_runningdisp(rx_runningdisp[21]),
.rx_disperr(rx_disp_err[21]),
.rx_errdetect(rx_char_err_gx[21]),
.rx_patterndetect(rx_patterndetect[21]),
.rx_syncstatus(rx_syncstatus[21]),
.tx_clkout(tx_pcs_clk_c21),
.rx_clkout(rx_pcs_clk_c21),
.tx_parallel_data(tx_frame_21),
.tx_datak(tx_kchar_21),
.rx_parallel_data(rx_frame_21),
.rx_datak(rx_kchar_21),
.rx_rlv(rx_runlengthviolation[21]),
.rx_recovclkout(rx_recovclkout_21),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
.reconfig_togxb(reconfig_togxb_21),
.reconfig_fromgxb(reconfig_fromgxb_21),
.wa_boundary(wa_boundary_21)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_21 = {92{1'b0}};
assign led_char_err_gx[21] = 1'b0;
assign link_status[21] = 1'b0;
assign led_disp_err_21 = 1'b0;
assign txp_21 = 1'b0;
assign rx_recovclkout_21= 1'b0;
assign phy_mgmt_readdata_21 = 32'b0;
assign phy_mgmt_waitrequest_21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 22)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch22_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c22_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
(
.clk(rx_pcs_clk_c22),
.reset(reset_rx_pcs_clk_c22_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_22),
.alt_sync(rx_syncstatus[22]),
.alt_disperr(rx_disp_err[22]),
.alt_ctrldetect(rx_kchar_22),
.alt_errdetect(rx_char_err_gx[22]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
.alt_runlengthviolation(rx_runlengthviolation[22]),
.alt_patterndetect(rx_patterndetect[22]),
.alt_runningdisp(rx_runningdisp[22]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_22),
.altpcs_sync(link_status[22]),
.altpcs_disperr(led_disp_err_22),
.altpcs_ctrldetect(pcs_rx_kchar_22),
.altpcs_errdetect(led_char_err_gx[22]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[22])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_22
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_22),
.phy_mgmt_read(phy_mgmt_read_22),
.phy_mgmt_readdata(phy_mgmt_readdata_22),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_22),
.phy_mgmt_write(phy_mgmt_write_22),
.phy_mgmt_writedata(phy_mgmt_writedata_22),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_22),
.rx_serial_data(rxp_22),
.rx_runningdisp(rx_runningdisp[22]),
.rx_disperr(rx_disp_err[22]),
.rx_errdetect(rx_char_err_gx[22]),
.rx_patterndetect(rx_patterndetect[22]),
.rx_syncstatus(rx_syncstatus[22]),
.tx_clkout(tx_pcs_clk_c22),
.rx_clkout(rx_pcs_clk_c22),
.tx_parallel_data(tx_frame_22),
.tx_datak(tx_kchar_22),
.rx_parallel_data(rx_frame_22),
.rx_datak(rx_kchar_22),
.rx_rlv(rx_runlengthviolation[22]),
.rx_recovclkout(rx_recovclkout_22),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
.reconfig_togxb(reconfig_togxb_22),
.reconfig_fromgxb(reconfig_fromgxb_22),
.wa_boundary(wa_boundary_22)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_22 = {92{1'b0}};
assign led_char_err_gx[22] = 1'b0;
assign link_status[22] = 1'b0;
assign led_disp_err_22 = 1'b0;
assign txp_22 = 1'b0;
assign rx_recovclkout_22= 1'b0;
assign phy_mgmt_readdata_22 = 32'b0;
assign phy_mgmt_waitrequest_22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 23)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch23_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c23_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
(
.clk(rx_pcs_clk_c23),
.reset(reset_rx_pcs_clk_c23_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_23),
.alt_sync(rx_syncstatus[23]),
.alt_disperr(rx_disp_err[23]),
.alt_ctrldetect(rx_kchar_23),
.alt_errdetect(rx_char_err_gx[23]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
.alt_runlengthviolation(rx_runlengthviolation[23]),
.alt_patterndetect(rx_patterndetect[23]),
.alt_runningdisp(rx_runningdisp[23]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_23),
.altpcs_sync(link_status[23]),
.altpcs_disperr(led_disp_err_23),
.altpcs_ctrldetect(pcs_rx_kchar_23),
.altpcs_errdetect(led_char_err_gx[23]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[23])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_23
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_23),
.phy_mgmt_read(phy_mgmt_read_23),
.phy_mgmt_readdata(phy_mgmt_readdata_23),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_23),
.phy_mgmt_write(phy_mgmt_write_23),
.phy_mgmt_writedata(phy_mgmt_writedata_23),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_23),
.rx_serial_data(rxp_23),
.rx_runningdisp(rx_runningdisp[23]),
.rx_disperr(rx_disp_err[23]),
.rx_errdetect(rx_char_err_gx[23]),
.rx_patterndetect(rx_patterndetect[23]),
.rx_syncstatus(rx_syncstatus[23]),
.tx_clkout(tx_pcs_clk_c23),
.rx_clkout(rx_pcs_clk_c23),
.tx_parallel_data(tx_frame_23),
.tx_datak(tx_kchar_23),
.rx_parallel_data(rx_frame_23),
.rx_datak(rx_kchar_23),
.rx_rlv(rx_runlengthviolation[23]),
.rx_recovclkout(rx_recovclkout_23),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
.reconfig_togxb(reconfig_togxb_23),
.reconfig_fromgxb(reconfig_fromgxb_23),
.wa_boundary(wa_boundary_23)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_23 = {92{1'b0}};
assign led_char_err_gx[23] = 1'b0;
assign link_status[23] = 1'b0;
assign led_disp_err_23 = 1'b0;
assign txp_23 = 1'b0;
assign rx_recovclkout_23= 1'b0;
assign phy_mgmt_readdata_23 = 32'b0;
assign phy_mgmt_waitrequest_23 = 1'b0;
end
endgenerate
endmodule // module altera_tse_multi_mac_pcs_pma_gige_phyip
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet PCS
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
reg_clk, // Avalon slave - clock
reg_rd, // Avalon slave - read
reg_wr, // Avalon slave - write
reg_addr, // Avalon slave - address
reg_data_in, // Avalon slave - writedata
reg_data_out, // Avalon slave - readdata
reg_busy, // Avalon slave - waitrequest
reset_reg_clk, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
rx_clk,
tx_clk,
rx_clkena,
tx_clkena,
gmii_rx_dv,
gmii_rx_d,
gmii_rx_err,
gmii_tx_en,
gmii_tx_d,
gmii_tx_err,
mii_rx_dv,
mii_rx_d,
mii_rx_err,
mii_tx_en,
mii_tx_d,
mii_tx_err,
mii_col,
mii_crs,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
set_10,
set_100,
set_1000,
hd_ena,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link);
parameter PHY_IDENTIFIER = 32'h 00000000 ;
parameter DEV_VERSION = 16'h 0001 ;
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_reg_clk; // Asynchronous Reset - clk Domain
output rx_clk; // MAC Receive clock
output tx_clk; // MAC Transmit clock
output rx_clkena; // MAC Receive Clock Enable
output tx_clkena; // MAC Transmit Clock Enable
output gmii_rx_dv; // GMII Receive Enable
output [7:0] gmii_rx_d; // GMII Receive Data
output gmii_rx_err; // GMII Receive Error
input gmii_tx_en; // GMII Transmit Enable
input [7:0] gmii_tx_d; // GMII Transmit Data
input gmii_tx_err; // GMII Transmit Error
output mii_rx_dv; // MII Receive Enable
output [3:0] mii_rx_d; // MII Receive Data
output mii_rx_err; // MII Receive Error
input mii_tx_en; // MII Transmit Enable
input [3:0] mii_tx_d; // MII Transmit Data
input mii_tx_err; // MII Transmit Error
output mii_col; // MII Collision
output mii_crs; // MII Carrier Sense
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
input reg_clk; // Register Interface Clock
input reg_rd; // Register Read Enable
input reg_wr; // Register Write Enable
input [4:0] reg_addr; // Register Address
input [15:0] reg_data_in; // Register Input Data
output [15:0] reg_data_out; // Register Output Data
output reg_busy; // Access Busy
output led_crs; // Carrier Sense
output led_link; // Valid Link
output hd_ena; // Half-Duplex Enable
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
output set_10; // 10Mbps Link Indication
output set_100; // 100Mbps Link Indication
output set_1000; // Gigabit Link Indication
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire gmii_rx_dv;
wire [7:0] gmii_rx_d;
wire gmii_rx_err;
wire mii_rx_dv;
wire [3:0] mii_rx_d;
wire mii_rx_err;
wire mii_col;
wire mii_crs;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire [15:0] reg_data_out;
wire reg_busy;
wire led_crs;
wire led_link;
wire hd_ena;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire set_10;
wire set_100;
wire set_1000;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk),
.reset_tx_clk(reset_tx_clk),
.reset_reg_clk(reset_reg_clk),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_d(gmii_rx_d),
.gmii_rx_err(gmii_rx_err),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_d(gmii_tx_d),
.gmii_tx_err(gmii_tx_err),
.mii_rx_dv(mii_rx_dv),
.mii_rx_d(mii_rx_d),
.mii_rx_err(mii_rx_err),
.mii_tx_en(mii_tx_en),
.mii_tx_d(mii_tx_d),
.mii_tx_err(mii_tx_err),
.mii_col(mii_col),
.mii_crs(mii_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(reg_clk),
.reg_rd(reg_rd),
.reg_wr(reg_wr),
.reg_addr(reg_addr),
.reg_data_in(reg_data_in),
.reg_data_out(reg_data_out),
.reg_busy(reg_busy),
.powerdown(powerdown),
.set_10(set_10),
.set_100(set_100),
.set_1000(set_1000),
.hd_ena(hd_ena),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_pcs_pma.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs_pma.v,v $
//
// $Revision: #2 $
// $Date: 2012/08/15 $
// Check in by : $Author: ksting $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level PCS + PMA module for Triple Speed Ethernet PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
gmii_tx_d,
gmii_tx_en,
gmii_tx_err,
gxb_cal_blk_clk,
gxb_pwrdn_in,
mii_tx_d,
mii_tx_en,
mii_tx_err,
read,
ref_clk,
reset,
reset_rx_clk,
reset_tx_clk,
rxp,
write,
writedata,
// outputs:
gmii_rx_d,
gmii_rx_dv,
gmii_rx_err,
hd_ena,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
mii_col,
mii_crs,
mii_rx_d,
mii_rx_dv,
mii_rx_err,
pcs_pwrdn_out,
readdata,
rx_clk,
rx_clkena,
tx_clkena,
set_10,
set_100,
set_1000,
tx_clk,
txp,
rx_recovclkout,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter PHY_IDENTIFIER = 32'h 00000000; // PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
parameter ENABLE_REV_LOOPBACK = 0; // Enable PHY Reverse Loopback
output [7:0] gmii_rx_d;
output gmii_rx_dv;
output gmii_rx_err;
output hd_ena;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output mii_col;
output mii_crs;
output [3:0] mii_rx_d;
output mii_rx_dv;
output mii_rx_err;
output pcs_pwrdn_out;
output [15:0] readdata;
output rx_clk;
output set_10;
output set_100;
output set_1000;
output tx_clk;
output rx_clkena;
output tx_clkena;
output txp;
output rx_recovclkout;
output waitrequest;
input [4:0] address;
input clk;
input [7:0] gmii_tx_d;
input gmii_tx_en;
input gmii_tx_err;
input gxb_pwrdn_in;
input gxb_cal_blk_clk;
input [3:0] mii_tx_d;
input mii_tx_en;
input mii_tx_err;
input read;
input ref_clk;
input reset;
input reset_rx_clk;
input reset_tx_clk;
input rxp;
input write;
input [15:0] writedata;
wire PCS_rx_reset;
wire PCS_tx_reset;
wire PCS_reset;
wire [7:0] gmii_rx_d;
wire gmii_rx_dv;
wire gmii_rx_err;
wire hd_ena;
wire led_an;
wire led_char_err;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire mii_col;
wire mii_crs;
wire [3:0] mii_rx_d;
wire mii_rx_dv;
wire mii_rx_err;
wire [15:0] readdata;
wire rx_clk;
wire set_10;
wire set_100;
wire set_1000;
wire tbi_rx_clk;
wire [9:0] tbi_rx_d;
wire [9:0] tbi_tx_d;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire txp;
wire waitrequest;
wire sd_loopback;
wire rev_loopback_ena;
wire rev_loopback_ena_ref_clk;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire [9:0] tbi_rx_d_lvds;
reg [9:0] tbi_rx_d_flip;
reg [9:0] tbi_tx_d_flip;
wire [9:0] tbi_tx_d_muxed;
wire [9:0] tbi_tx_d_loopback;
wire pll_areset,rx_cda_reset,rx_channel_data_align,rx_locked,rx_reset_sequence_done;
wire reset_pma_tx_clk,reset_pma_rx_clk,rx_reset;
wire reset_ref_clk_int;
wire reset_tbi_rx_clk_int;
// Export receive recovered clock
assign rx_recovclkout = tbi_rx_clk;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// Assign the digital reset of the PMA to the PCS logic
// --------------------------------------------------------
altera_tse_reset_synchronizer reset_sync_tx (
.clk(tx_clk),
.reset_in(rx_reset),
.reset_out(reset_pma_tx_clk)
);
altera_tse_reset_synchronizer reset_sync_rx (
.clk(rx_clk),
.reset_in(rx_reset),
.reset_out(reset_pma_rx_clk)
);
assign PCS_rx_reset = reset_rx_clk | reset_pma_rx_clk;
assign PCS_tx_reset = reset_tx_clk | reset_pma_tx_clk;
assign PCS_reset = reset | rx_reset;
// Instantiation of the PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_1000_base_x altera_tse_top_1000_base_x_inst
(
.gmii_rx_d (gmii_rx_d),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_err (gmii_rx_err),
.gmii_tx_d (gmii_tx_d),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_err (gmii_tx_err),
.hd_ena (hd_ena),
.led_an (led_an),
.led_char_err (led_char_err),
.led_col (led_col),
.led_crs (led_crs),
.led_disp_err (led_disp_err),
.led_link (led_link),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rx_d (mii_rx_d),
.mii_rx_dv (mii_rx_dv),
.mii_rx_err (mii_rx_err),
.mii_tx_d (mii_tx_d),
.mii_tx_en (mii_tx_en),
.mii_tx_err (mii_tx_err),
.reg_addr (address),
.reg_busy (waitrequest),
.reg_clk (clk),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_rd (read),
.reg_wr (write),
.reset_reg_clk (PCS_reset),
.reset_rx_clk (PCS_rx_reset),
.reset_tx_clk (PCS_tx_reset),
.rx_clk (rx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.set_10 (set_10),
.set_100 (set_100),
.set_1000 (set_1000),
.sd_loopback(sd_loopback),
.rev_loopback_ena(rev_loopback_ena),
.powerdown(pcs_pwrdn_out_sig),
.tbi_rx_clk (tbi_rx_clk),
.tbi_rx_d (tbi_rx_d),
.tbi_tx_clk (tbi_tx_clk),
.tbi_tx_d (tbi_tx_d),
.tx_clk (tx_clk)
);
defparam
altera_tse_top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
altera_tse_top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the Alt2gxb block as the PMA for Stratix II GX devices
// -----------------------------------------------------------------------
// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
// ----------------------------------------------------------------
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
begin
// Reverse Loopback Logic
if (ENABLE_REV_LOOPBACK == 1)
begin
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_REV_LOOPBACK_TX(
.clk(ref_clk), // INPUT
.reset_n(~reset_ref_clk_int), //INPUT
.din(rev_loopback_ena), //INPUT
.dout(rev_loopback_ena_ref_clk));//OUTPUT
altera_tse_lvds_reverse_loopback U_LVDS_REV_LOOPBACK (
.reset_wclk(reset_tbi_rx_clk_int),
.reset_rclk(reset_ref_clk_int),
.wclk(tbi_rx_clk),
.rclk(ref_clk),
.tbi_rx_clk (tbi_rx_d_lvds),
.tbi_tx_clk (tbi_tx_d_loopback)
);
assign tbi_tx_d_muxed = rev_loopback_ena_ref_clk ? tbi_tx_d_loopback: tbi_tx_d_flip;
end
else
begin
assign tbi_tx_d_muxed = tbi_tx_d_flip;
// Unused wires
assign tbi_tx_d_loopback = 10'd0;
assign rev_loopback_ena_ref_clk = 1'b0;
end
assign tbi_tx_clk = ref_clk;
assign tbi_rx_d = tbi_rx_d_flip;
// Reset Synchronizer
altera_tse_reset_synchronizer reset_sync_0 (
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_ref_clk_int)
);
altera_tse_reset_synchronizer reset_sync_1 (
.clk(tbi_rx_clk),
.reset_in(reset),
.reset_out(reset_tbi_rx_clk_int)
);
always @(posedge tbi_rx_clk or posedge reset_tbi_rx_clk_int)
begin
if (reset_tbi_rx_clk_int == 1)
tbi_rx_d_flip <= 0;
else
begin
if (rx_reset_sequence_done == 1)
begin
tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
end
end
end
always @(posedge ref_clk or posedge reset_ref_clk_int)
begin
if (reset_ref_clk_int == 1)
tbi_tx_d_flip <= 0;
else
begin
tbi_tx_d_flip[0] <= tbi_tx_d[9];
tbi_tx_d_flip[1] <= tbi_tx_d[8];
tbi_tx_d_flip[2] <= tbi_tx_d[7];
tbi_tx_d_flip[3] <= tbi_tx_d[6];
tbi_tx_d_flip[4] <= tbi_tx_d[5];
tbi_tx_d_flip[5] <= tbi_tx_d[4];
tbi_tx_d_flip[6] <= tbi_tx_d[3];
tbi_tx_d_flip[7] <= tbi_tx_d[2];
tbi_tx_d_flip[8] <= tbi_tx_d[1];
tbi_tx_d_flip[9] <= tbi_tx_d[0];
end
end
if (DEVICE_FAMILY == "ARRIAV")
begin
altera_tse_pma_lvds_rx_av the_altera_tse_pma_lvds_rx
(
.pll_areset ( reset ),
.rx_channel_data_align ( rx_channel_data_align ),
.rx_locked ( rx_locked ),
.rx_divfwdclk (tbi_rx_clk),
.rx_in (rxp),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds),
.rx_outclock (),
.rx_reset (rx_reset)
);
end
else
begin
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
(
.pll_areset ( reset ),
.rx_cda_reset ( rx_cda_reset ),
.rx_channel_data_align ( rx_channel_data_align ),
.rx_locked ( rx_locked ),
.rx_divfwdclk (tbi_rx_clk),
.rx_in (rxp),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds),
.rx_outclock (),
.rx_reset (rx_reset)
);
end
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer (
.clk ( clk ),
.reset ( reset ),
.rx_locked ( rx_locked ),
.rx_channel_data_align ( rx_channel_data_align ),
.pll_areset ( pll_areset ),
.rx_reset ( rx_reset ),
.rx_cda_reset ( rx_cda_reset ),
.rx_reset_sequence_done ( rx_reset_sequence_done )
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
(
.tx_in (tbi_tx_d_muxed),
.pll_areset ( reset ),
.tx_inclock (ref_clk),
.tx_out (txp)
);
end
endgenerate
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs_pma_gige.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level PCS + PMA module for Triple Speed Ethernet PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF;SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" } *)
module altera_tse_pcs_pma_gige (
// inputs:
address,
clk,
gmii_tx_d,
gmii_tx_en,
gmii_tx_err,
gxb_cal_blk_clk,
gxb_pwrdn_in,
mii_tx_d,
mii_tx_en,
mii_tx_err,
read,
reconfig_clk,
reconfig_togxb,
reconfig_busy,
ref_clk,
reset,
reset_rx_clk,
reset_tx_clk,
rxp,
write,
writedata,
// outputs:
gmii_rx_d,
gmii_rx_dv,
gmii_rx_err,
hd_ena,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
mii_col,
mii_crs,
mii_rx_d,
mii_rx_dv,
mii_rx_err,
pcs_pwrdn_out,
readdata,
reconfig_fromgxb,
rx_clk,
set_10,
set_100,
set_1000,
tx_clk,
rx_clkena,
tx_clkena,
txp,
rx_recovclkout,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter PHY_IDENTIFIER = 32'h 00000000; // PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation.
// Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O.
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter ENABLE_ALT_RECONFIG = 0; // Option to expose the alt_reconfig ports
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [7:0] gmii_rx_d;
output gmii_rx_dv;
output gmii_rx_err;
output hd_ena;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output mii_col;
output mii_crs;
output [3:0] mii_rx_d;
output mii_rx_dv;
output mii_rx_err;
output pcs_pwrdn_out;
output [15:0] readdata;
output [16:0] reconfig_fromgxb;
output rx_clk;
output set_10;
output set_100;
output set_1000;
output tx_clk;
output rx_clkena;
output tx_clkena;
output txp;
output rx_recovclkout;
output waitrequest;
input [4:0] address;
input clk;
input [7:0] gmii_tx_d;
input gmii_tx_en;
input gmii_tx_err;
input gxb_pwrdn_in;
input gxb_cal_blk_clk;
input [3:0] mii_tx_d;
input mii_tx_en;
input mii_tx_err;
input read;
input reconfig_clk;
input [3:0] reconfig_togxb;
input reconfig_busy;
input ref_clk;
input reset;
input reset_rx_clk;
input reset_tx_clk;
input rxp;
input write;
input [15:0] writedata;
wire PCS_rx_reset;
wire PCS_tx_reset;
wire PCS_reset;
wire gige_pma_reset;
wire [7:0] gmii_rx_d;
wire gmii_rx_dv;
wire gmii_rx_err;
wire hd_ena;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire mii_col;
wire mii_crs;
wire [3:0] mii_rx_d;
wire mii_rx_dv;
wire mii_rx_err;
wire rx_pcs_clk;
wire tx_pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire [15:0] readdata;
wire rx_char_err_gx;
wire rx_clk;
wire rx_disp_err;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire set_10;
wire set_100;
wire set_1000;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire waitrequest;
wire sd_loopback;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
wire [16:0] reconfig_fromgxb;
wire reset_ref_clk;
wire reset_rx_pcs_clk_int;
wire pll_powerdown_sqcnr,tx_digitalreset_sqcnr,rx_analogreset_sqcnr,rx_digitalreset_sqcnr,gxb_powerdown_sqcnr,pll_locked;
wire rx_digitalreset_sqcnr_rx_clk,tx_digitalreset_sqcnr_tx_clk,rx_digitalreset_sqcnr_clk;
wire rx_freqlocked;
wire locked_signal;
// Assign the digital reset of the PMA to the PCS logic
// --------------------------------------------------------
altera_tse_reset_synchronizer reset_sync_2 (
.clk(rx_clk),
.reset_in(rx_digitalreset_sqcnr),
.reset_out(rx_digitalreset_sqcnr_rx_clk)
);
altera_tse_reset_synchronizer reset_sync_3 (
.clk(tx_clk),
.reset_in(tx_digitalreset_sqcnr),
.reset_out(tx_digitalreset_sqcnr_tx_clk)
);
altera_tse_reset_synchronizer reset_sync_4 (
.clk(clk),
.reset_in(rx_digitalreset_sqcnr),
.reset_out(rx_digitalreset_sqcnr_clk)
);
assign PCS_rx_reset = reset_rx_clk | rx_digitalreset_sqcnr_rx_clk;
assign PCS_tx_reset = reset_tx_clk | tx_digitalreset_sqcnr_tx_clk;
assign PCS_reset = reset;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_1000_base_x_strx_gx altera_tse_top_1000_base_x_strx_gx_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.gmii_rx_d (gmii_rx_d),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_err (gmii_rx_err),
.gmii_tx_d (gmii_tx_d),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_err (gmii_tx_err),
.hd_ena (hd_ena),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rx_d (mii_rx_d),
.mii_rx_dv (mii_rx_dv),
.mii_rx_err (mii_rx_err),
.mii_tx_d (mii_tx_d),
.mii_tx_en (mii_tx_en),
.mii_tx_err (mii_tx_err),
.powerdown (pcs_pwrdn_out_sig),
.reg_addr (address),
.reg_busy (waitrequest),
.reg_clk (clk),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_rd (read),
.reg_wr (write),
.reset_reg_clk (PCS_reset),
.reset_rx_clk (PCS_rx_reset),
.reset_tx_clk (PCS_tx_reset),
.rx_clk (rx_clk),
.rx_clkout (rx_pcs_clk),
.rx_frame (pcs_rx_frame),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.set_10 (set_10),
.set_100 (set_100),
.set_1000 (set_1000),
.tx_clk (tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.tx_clkout (tx_pcs_clk),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar)
);
defparam
altera_tse_top_1000_base_x_strx_gx_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_top_1000_base_x_strx_gx_inst.DEV_VERSION = DEV_VERSION,
altera_tse_top_1000_base_x_strx_gx_inst.ENABLE_SGMII = ENABLE_SGMII;
// Based on PHYIP , when user assert reset - it hold the reset sequencer block in reset.
// , reset sequencing only start then reset_sequnece end.
wire reset_sync;
reg reset_start;
altera_tse_reset_synchronizer reset_sync_u0 (
.clk(clk),
.reset_in(reset),
.reset_out(reset_sync)
);
always@(posedge clk or posedge reset_sync) begin
if (reset_sync) begin
reset_start <= 1'b1;
end
else begin
reset_start <= 1'b0;
end
end
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_d1,gxb_pwrdn_in_sig_clk;
generate if (EXPORT_PWRDN == 1)
begin
always @(posedge clk or posedge gxb_pwrdn_in)
begin
if (gxb_pwrdn_in == 1) begin
data_in_d1 <= 1;
gxb_pwrdn_in_sig_clk <= 1;
end else begin
data_in_d1 <= 1'b0;
gxb_pwrdn_in_sig_clk <= data_in_d1;
end
end
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk = gxb_pwrdn_in_sig;
end
end
endgenerate
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst(
// User inputs and outputs
.clock(clk),
.reset_all(reset_start | gxb_pwrdn_in_sig_clk),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_sync),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr),// output
.tx_digitalreset(tx_digitalreset_sqcnr),// output
.rx_analogreset(rx_analogreset_sqcnr),// output
.rx_digitalreset(rx_digitalreset_sqcnr),// output
.gxb_powerdown(gxb_powerdown_sqcnr),// output
.pll_is_locked(locked_signal),
.rx_is_lockedtodata(rx_freqlocked),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy)
);
assign locked_signal = (reset? 1'b0: pll_locked);
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk),
.reset_in(rx_digitalreset_sqcnr),
.reset_out(reset_rx_pcs_clk_int)
);
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(rx_pcs_clk),
.reset(reset_rx_pcs_clk_int),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb),
.rx_analogreset (rx_analogreset_sqcnr),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar),
.rx_clkout (rx_pcs_clk),
.rx_datain (rxp),
.rx_dataout (rx_frame),
.rx_digitalreset (rx_digitalreset_sqcnr_rx_clk),
.rx_disperr (rx_disp_err),
.rx_errdetect (rx_char_err_gx),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_runlengthviolation),
.rx_seriallpbken (sd_loopback),
.rx_syncstatus (rx_syncstatus),
.rx_recovclkout(rx_recovclkout),
.tx_clkout (tx_pcs_clk),
.tx_ctrlenable (tx_kchar),
.tx_datain (tx_frame),
.rx_freqlocked (rx_freqlocked),
.tx_dataout (txp),
.tx_digitalreset (tx_digitalreset_sqcnr_tx_clk),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp),
.pll_powerdown(gxb_pwrdn_in_sig),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY,
the_altera_tse_gxb_gige_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs_pma_gige_phyip.v,v $
//
// $Revision: #13 $
// $Date: 2010/10/19 $
// Check in by : $Author: aishak $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level PCS + PMA module for Triple Speed Ethernet PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF;SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" } *)
module altera_tse_pcs_pma_gige_phyip (
// inputs:
address,
clk,
gmii_tx_d,
gmii_tx_en,
gmii_tx_err,
mii_tx_d,
mii_tx_en,
mii_tx_err,
read,
reconfig_togxb,
ref_clk,
reset,
reset_rx_clk,
reset_tx_clk,
rxp,
write,
writedata,
// outputs:
gmii_rx_d,
gmii_rx_dv,
gmii_rx_err,
hd_ena,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
mii_col,
mii_crs,
mii_rx_d,
mii_rx_dv,
mii_rx_err,
readdata,
reconfig_fromgxb,
rx_clk,
set_10,
set_100,
set_1000,
tx_clk,
rx_clkena,
tx_clkena,
txp,
rx_recovclkout,
waitrequest,
// phy_mgmt_interface
phy_mgmt_address,
phy_mgmt_read,
phy_mgmt_readdata,
phy_mgmt_waitrequest,
phy_mgmt_write,
phy_mgmt_writedata
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter PHY_IDENTIFIER = 32'h 00000000; // PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation.
// Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O.
//parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter ENABLE_ALT_RECONFIG = 0; // Option to expose the alt_reconfig ports
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [7:0] gmii_rx_d;
output gmii_rx_dv;
output gmii_rx_err;
output hd_ena;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output mii_col;
output mii_crs;
output [3:0] mii_rx_d;
output mii_rx_dv;
output mii_rx_err;
output [15:0] readdata;
output [91:0] reconfig_fromgxb;
output rx_clk;
output set_10;
output set_100;
output set_1000;
output tx_clk;
output rx_clkena;
output tx_clkena;
output txp;
output rx_recovclkout;
output waitrequest;
input [4:0] address;
input clk;
input [7:0] gmii_tx_d;
input gmii_tx_en;
input gmii_tx_err;
input [3:0] mii_tx_d;
input mii_tx_en;
input mii_tx_err;
input read;
input [139:0] reconfig_togxb;
input ref_clk;
input reset;
input reset_rx_clk;
input reset_tx_clk;
input rxp;
input write;
input [15:0] writedata;
input [8:0] phy_mgmt_address;
input phy_mgmt_read;
output [31:0] phy_mgmt_readdata;
output phy_mgmt_waitrequest;
input phy_mgmt_write;
input [31:0]phy_mgmt_writedata;
wire PCS_rx_reset;
wire PCS_tx_reset;
wire PCS_reset;
wire gige_pma_reset;
wire [7:0] gmii_rx_d;
wire gmii_rx_dv;
wire gmii_rx_err;
wire hd_ena;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire mii_col;
wire mii_crs;
wire [3:0] mii_rx_d;
wire mii_rx_dv;
wire mii_rx_err;
wire rx_pcs_clk;
wire tx_pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire [15:0] readdata;
wire rx_char_err_gx;
wire rx_clk;
wire rx_disp_err;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire set_10;
wire set_100;
wire set_1000;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire waitrequest;
wire sd_loopback;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire [91:0] reconfig_fromgxb;
wire reset_rx_pcs_clk_int;
wire reset_reset_rx_clk;
wire reset_reset_tx_clk;
altera_tse_reset_synchronizer reset_sync_2 (
.clk(rx_clk),
.reset_in(reset),
.reset_out(reset_reset_rx_clk)
);
altera_tse_reset_synchronizer reset_sync_3 (
.clk(tx_clk),
.reset_in(reset),
.reset_out(reset_reset_tx_clk)
);
assign PCS_rx_reset = reset_rx_clk | reset_reset_rx_clk;
assign PCS_tx_reset = reset_tx_clk | reset_reset_tx_clk;
assign PCS_reset = reset;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_1000_base_x_strx_gx altera_tse_top_1000_base_x_strx_gx_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.gmii_rx_d (gmii_rx_d),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_err (gmii_rx_err),
.gmii_tx_d (gmii_tx_d),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_err (gmii_tx_err),
.hd_ena (hd_ena),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rx_d (mii_rx_d),
.mii_rx_dv (mii_rx_dv),
.mii_rx_err (mii_rx_err),
.mii_tx_d (mii_tx_d),
.mii_tx_en (mii_tx_en),
.mii_tx_err (mii_tx_err),
.powerdown (),
.reg_addr (address),
.reg_busy (waitrequest),
.reg_clk (clk),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_rd (read),
.reg_wr (write),
.reset_reg_clk (PCS_reset),
.reset_rx_clk (PCS_rx_reset),
.reset_tx_clk (PCS_tx_reset),
.rx_clk (rx_clk),
.rx_clkout (rx_pcs_clk),
.rx_frame (pcs_rx_frame),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.set_10 (set_10),
.set_100 (set_100),
.set_1000 (set_1000),
.tx_clk (tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.tx_clkout (tx_pcs_clk),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar)
);
defparam
altera_tse_top_1000_base_x_strx_gx_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_top_1000_base_x_strx_gx_inst.DEV_VERSION = DEV_VERSION,
altera_tse_top_1000_base_x_strx_gx_inst.ENABLE_SGMII = ENABLE_SGMII;
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk),
//.reset_in(rx_digitalreset_sqcnr),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_int)
);
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(rx_pcs_clk),
.reset(reset_rx_pcs_clk_int),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Custom PhyIP
// ------------------------------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst(
.phy_mgmt_clk(clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset(reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
.phy_mgmt_read(phy_mgmt_read), // .read
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
.phy_mgmt_write(phy_mgmt_write), // .write
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
.tx_ready(), // tx_ready.export
.rx_ready(), // rx_ready.export
.pll_ref_clk(ref_clk), // pll_ref_clk.clk
.pll_locked(), // pll_locked.export
.tx_serial_data(txp), // tx_serial_data.export
.rx_serial_data(rxp), // rx_serial_data.export
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
.rx_disperr(rx_disp_err), // rx_disperr.export
.rx_errdetect(rx_char_err_gx), // rx_errdetect.export
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
.tx_clkout(tx_pcs_clk), // tx_clkout0.clk
.rx_clkout(rx_pcs_clk), // rx_clkout0.clk
.tx_parallel_data(tx_frame), // tx_parallel_data0.data
.tx_datak(tx_kchar), // tx_datak0.data
.rx_parallel_data(rx_frame), // rx_parallel_data0.data
.rx_datak(rx_kchar), // rx_datak0.data
.rx_rlv(rx_runlengthviolation),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb)
);
defparam
the_altera_tse_gxb_gige_phyip_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst.DEVICE_FAMILY = DEVICE_FAMILY,
the_altera_tse_gxb_gige_phyip_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
// megafunction wizard: %ALTLVDS_RX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTLVDS_RX
// ============================================================
// File Name: altera_tse_pma_lvds_rx.v
// Megafunction Name(s):
// ALTLVDS_RX
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Internal Build 120 09/23/2010 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_pma_lvds_rx (
pll_areset,
rx_cda_reset,
rx_channel_data_align,
rx_in,
rx_inclock,
rx_reset,
rx_divfwdclk,
rx_locked,
rx_out,
rx_outclock);
input pll_areset;
input [0:0] rx_cda_reset;
input [0:0] rx_channel_data_align;
input [0:0] rx_in;
input rx_inclock;
input [0:0] rx_reset;
output [0:0] rx_divfwdclk;
output rx_locked;
output [9:0] rx_out;
output rx_outclock;
wire [0:0] sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire sub_wire3;
wire [0:0] rx_divfwdclk = sub_wire0[0:0];
wire rx_locked = sub_wire1;
wire [9:0] rx_out = sub_wire2[9:0];
wire rx_outclock = sub_wire3;
altlvds_rx ALTLVDS_RX_component (
.rx_in (rx_in),
.rx_inclock (rx_inclock),
.rx_reset (rx_reset),
.pll_areset (pll_areset),
.rx_cda_reset (rx_cda_reset),
.rx_channel_data_align (rx_channel_data_align),
.rx_divfwdclk (sub_wire0),
.rx_locked (sub_wire1),
.rx_out (sub_wire2),
.rx_outclock (sub_wire3),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_dpa_lock_reset (1'b0),
.rx_dpa_locked (),
.rx_dpll_enable (1'b1),
.rx_dpll_hold (1'b0),
.rx_dpll_reset (1'b0),
.rx_enable (1'b1),
.rx_fifo_reset (1'b0),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_syncclock (1'b0));
defparam
ALTLVDS_RX_component.buffer_implementation = "RAM",
ALTLVDS_RX_component.cds_mode = "UNUSED",
ALTLVDS_RX_component.common_rx_tx_pll = "ON",
ALTLVDS_RX_component.data_align_rollover = 10,
ALTLVDS_RX_component.data_rate = "1250.0 Mbps",
ALTLVDS_RX_component.deserialization_factor = 10,
ALTLVDS_RX_component.dpa_initial_phase_value = 0,
ALTLVDS_RX_component.dpll_lock_count = 0,
ALTLVDS_RX_component.dpll_lock_window = 0,
ALTLVDS_RX_component.enable_dpa_align_to_rising_edge_only = "OFF",
ALTLVDS_RX_component.enable_dpa_calibration = "ON",
ALTLVDS_RX_component.enable_dpa_fifo = "UNUSED",
ALTLVDS_RX_component.enable_dpa_initial_phase_selection = "OFF",
ALTLVDS_RX_component.enable_dpa_mode = "ON",
ALTLVDS_RX_component.enable_dpa_pll_calibration = "OFF",
ALTLVDS_RX_component.enable_soft_cdr_mode = "ON",
ALTLVDS_RX_component.implement_in_les = "OFF",
ALTLVDS_RX_component.inclock_boost = 0,
ALTLVDS_RX_component.inclock_data_alignment = "EDGE_ALIGNED",
ALTLVDS_RX_component.inclock_period = 8000,
ALTLVDS_RX_component.inclock_phase_shift = 0,
ALTLVDS_RX_component.input_data_rate = 1250,
ALTLVDS_RX_component.intended_device_family = "Stratix III",
ALTLVDS_RX_component.lose_lock_on_one_change = "UNUSED",
ALTLVDS_RX_component.lpm_hint = "UNUSED",
ALTLVDS_RX_component.lpm_type = "altlvds_rx",
ALTLVDS_RX_component.number_of_channels = 1,
ALTLVDS_RX_component.outclock_resource = "AUTO",
ALTLVDS_RX_component.pll_operation_mode = "UNUSED",
ALTLVDS_RX_component.pll_self_reset_on_loss_lock = "UNUSED",
ALTLVDS_RX_component.port_rx_channel_data_align = "PORT_USED",
ALTLVDS_RX_component.port_rx_data_align = "PORT_UNUSED",
ALTLVDS_RX_component.refclk_frequency = "125.00 MHz",
ALTLVDS_RX_component.registered_data_align_input = "UNUSED",
ALTLVDS_RX_component.registered_output = "ON",
ALTLVDS_RX_component.reset_fifo_at_first_lock = "UNUSED",
ALTLVDS_RX_component.rx_align_data_reg = "UNUSED",
ALTLVDS_RX_component.sim_dpa_is_negative_ppm_drift = "OFF",
ALTLVDS_RX_component.sim_dpa_net_ppm_variation = 0,
ALTLVDS_RX_component.sim_dpa_output_clock_phase_shift = 0,
ALTLVDS_RX_component.use_coreclock_input = "OFF",
ALTLVDS_RX_component.use_dpll_rawperror = "OFF",
ALTLVDS_RX_component.use_external_pll = "OFF",
ALTLVDS_RX_component.use_no_phase_shift = "ON",
ALTLVDS_RX_component.x_on_bitslip = "OFF",
ALTLVDS_RX_component.clk_src_is_pll = "off";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: Bitslip NUMERIC "10"
// Retrieval info: PRIVATE: Clock_Choices STRING "tx_coreclock"
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "1250.0"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
// Retrieval info: PRIVATE: Dpll_Lock_Count STRING ""
// Retrieval info: PRIVATE: Dpll_Lock_Window STRING ""
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "ON"
// Retrieval info: PRIVATE: Enable_FIFO_DPA_Channels STRING ""
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
// Retrieval info: PRIVATE: Outclock_Divide_By STRING ""
// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN STRING ""
// Retrieval info: PRIVATE: pINCLOCK_PHASE_SHIFT STRING ""
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "125.00"
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT STRING ""
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: PRIVATE: Use_Rawperror STRING ""
// Retrieval info: PRIVATE: Use_Tx_Out_Phase STRING ""
// Retrieval info: CONSTANT: BUFFER_IMPLEMENTATION STRING "RAM"
// Retrieval info: CONSTANT: CDS_MODE STRING "UNUSED"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
// Retrieval info: CONSTANT: DATA_ALIGN_ROLLOVER NUMERIC "10"
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
// Retrieval info: CONSTANT: DPA_INITIAL_PHASE_VALUE NUMERIC "0"
// Retrieval info: CONSTANT: DPLL_LOCK_COUNT NUMERIC "0"
// Retrieval info: CONSTANT: DPLL_LOCK_WINDOW NUMERIC "0"
// Retrieval info: CONSTANT: ENABLE_DPA_ALIGN_TO_RISING_EDGE_ONLY STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_DPA_CALIBRATION STRING "ON"
// Retrieval info: CONSTANT: ENABLE_DPA_FIFO STRING "UNUSED"
// Retrieval info: CONSTANT: ENABLE_DPA_INITIAL_PHASE_SELECTION STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_DPA_MODE STRING "ON"
// Retrieval info: CONSTANT: ENABLE_DPA_PLL_CALIBRATION STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_SOFT_CDR_MODE STRING "ON"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_BOOST NUMERIC "0"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: INPUT_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LOSE_LOCK_ON_ONE_CHANGE STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_rx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: CONSTANT: PLL_OPERATION_MODE STRING "UNUSED"
// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "UNUSED"
// Retrieval info: CONSTANT: PORT_RX_CHANNEL_DATA_ALIGN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_RX_DATA_ALIGN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REFCLK_FREQUENCY STRING "125.00 MHz"
// Retrieval info: CONSTANT: REGISTERED_DATA_ALIGN_INPUT STRING "UNUSED"
// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
// Retrieval info: CONSTANT: RESET_FIFO_AT_FIRST_LOCK STRING "UNUSED"
// Retrieval info: CONSTANT: RX_ALIGN_DATA_REG STRING "UNUSED"
// Retrieval info: CONSTANT: SIM_DPA_IS_NEGATIVE_PPM_DRIFT STRING "OFF"
// Retrieval info: CONSTANT: SIM_DPA_NET_PPM_VARIATION NUMERIC "0"
// Retrieval info: CONSTANT: SIM_DPA_OUTPUT_CLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: USE_CORECLOCK_INPUT STRING "OFF"
// Retrieval info: CONSTANT: USE_DPLL_RAWPERROR STRING "OFF"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
// Retrieval info: CONSTANT: X_ON_BITSLIP STRING "OFF"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
// Retrieval info: USED_PORT: rx_cda_reset 0 0 1 0 INPUT NODEFVAL "rx_cda_reset[0..0]"
// Retrieval info: CONNECT: @rx_cda_reset 0 0 1 0 rx_cda_reset 0 0 1 0
// Retrieval info: USED_PORT: rx_channel_data_align 0 0 1 0 INPUT NODEFVAL "rx_channel_data_align[0..0]"
// Retrieval info: CONNECT: @rx_channel_data_align 0 0 1 0 rx_channel_data_align 0 0 1 0
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL "rx_divfwdclk[0..0]"
// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL "rx_in[0..0]"
// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT NODEFVAL "rx_inclock"
// Retrieval info: CONNECT: @rx_inclock 0 0 0 0 rx_inclock 0 0 0 0
// Retrieval info: USED_PORT: rx_locked 0 0 0 0 OUTPUT NODEFVAL "rx_locked"
// Retrieval info: CONNECT: rx_locked 0 0 0 0 @rx_locked 0 0 0 0
// Retrieval info: USED_PORT: rx_out 0 0 10 0 OUTPUT NODEFVAL "rx_out[9..0]"
// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL "rx_outclock"
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
// Retrieval info: USED_PORT: rx_reset 0 0 1 0 INPUT NODEFVAL "rx_reset[0..0]"
// Retrieval info: CONNECT: @rx_reset 0 0 1 0 rx_reset 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.cmp FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTLVDS_RX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTLVDS_RX
// ============================================================
// File Name: altera_tse_pma_lvds_rx_av.v
// Megafunction Name(s):
// ALTLVDS_RX
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Internal Build 131 08/10/2012 PN Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_pma_lvds_rx_av (
pll_areset,
rx_channel_data_align,
rx_in,
rx_inclock,
rx_reset,
rx_divfwdclk,
rx_locked,
rx_out,
rx_outclock);
input pll_areset;
input [0:0] rx_channel_data_align;
input [0:0] rx_in;
input rx_inclock;
input [0:0] rx_reset;
output [0:0] rx_divfwdclk;
output rx_locked;
output [9:0] rx_out;
output rx_outclock;
wire [0:0] sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire sub_wire3;
wire [0:0] rx_divfwdclk = sub_wire0[0:0];
wire rx_locked = sub_wire1;
wire [9:0] rx_out = sub_wire2[9:0];
wire rx_outclock = sub_wire3;
altlvds_rx ALTLVDS_RX_component (
.rx_in (rx_in),
.rx_inclock (rx_inclock),
.rx_reset (rx_reset),
.pll_areset (pll_areset),
.rx_channel_data_align (rx_channel_data_align),
.rx_divfwdclk (sub_wire0),
.rx_locked (sub_wire1),
.rx_out (sub_wire2),
.rx_outclock (sub_wire3),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset (1'b0),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_dpa_lock_reset (1'b0),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable (1'b1),
.rx_dpll_hold (1'b0),
.rx_dpll_reset (1'b0),
.rx_enable (1'b1),
.rx_fifo_reset (1'b0),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_syncclock (1'b0));
defparam
ALTLVDS_RX_component.buffer_implementation = "RAM",
ALTLVDS_RX_component.cds_mode = "UNUSED",
ALTLVDS_RX_component.common_rx_tx_pll = "ON",
ALTLVDS_RX_component.data_align_rollover = 10,
ALTLVDS_RX_component.data_rate = "1250.0 Mbps",
ALTLVDS_RX_component.deserialization_factor = 10,
ALTLVDS_RX_component.dpa_initial_phase_value = 0,
ALTLVDS_RX_component.dpll_lock_count = 0,
ALTLVDS_RX_component.dpll_lock_window = 0,
ALTLVDS_RX_component.enable_clock_pin_mode = "UNUSED",
ALTLVDS_RX_component.enable_dpa_align_to_rising_edge_only = "OFF",
ALTLVDS_RX_component.enable_dpa_calibration = "ON",
ALTLVDS_RX_component.enable_dpa_fifo = "UNUSED",
ALTLVDS_RX_component.enable_dpa_initial_phase_selection = "OFF",
ALTLVDS_RX_component.enable_dpa_mode = "ON",
ALTLVDS_RX_component.enable_dpa_pll_calibration = "OFF",
ALTLVDS_RX_component.enable_soft_cdr_mode = "ON",
ALTLVDS_RX_component.implement_in_les = "OFF",
ALTLVDS_RX_component.inclock_boost = 0,
ALTLVDS_RX_component.inclock_data_alignment = "EDGE_ALIGNED",
ALTLVDS_RX_component.inclock_period = 8000,
ALTLVDS_RX_component.inclock_phase_shift = 0,
ALTLVDS_RX_component.input_data_rate = 1250,
ALTLVDS_RX_component.intended_device_family = "Arria V",
ALTLVDS_RX_component.lose_lock_on_one_change = "UNUSED",
ALTLVDS_RX_component.lpm_hint = "CBX_MODULE_PREFIX=altera_tse_pma_lvds_rx_av",
ALTLVDS_RX_component.lpm_type = "altlvds_rx",
ALTLVDS_RX_component.number_of_channels = 1,
ALTLVDS_RX_component.outclock_resource = "AUTO",
ALTLVDS_RX_component.pll_operation_mode = "UNUSED",
ALTLVDS_RX_component.pll_self_reset_on_loss_lock = "UNUSED",
ALTLVDS_RX_component.port_rx_channel_data_align = "PORT_USED",
ALTLVDS_RX_component.port_rx_data_align = "PORT_UNUSED",
ALTLVDS_RX_component.refclk_frequency = "125.000000 MHz",
ALTLVDS_RX_component.registered_data_align_input = "UNUSED",
ALTLVDS_RX_component.registered_output = "ON",
ALTLVDS_RX_component.reset_fifo_at_first_lock = "UNUSED",
ALTLVDS_RX_component.rx_align_data_reg = "UNUSED",
ALTLVDS_RX_component.sim_dpa_is_negative_ppm_drift = "OFF",
ALTLVDS_RX_component.sim_dpa_net_ppm_variation = 0,
ALTLVDS_RX_component.sim_dpa_output_clock_phase_shift = 0,
ALTLVDS_RX_component.use_coreclock_input = "OFF",
ALTLVDS_RX_component.use_dpll_rawperror = "OFF",
ALTLVDS_RX_component.use_external_pll = "OFF",
ALTLVDS_RX_component.use_no_phase_shift = "ON",
ALTLVDS_RX_component.x_on_bitslip = "ON",
ALTLVDS_RX_component.clk_src_is_pll = "off";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: Bitslip NUMERIC "10"
// Retrieval info: PRIVATE: Clock_Choices STRING "tx_coreclock"
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "1250.0"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
// Retrieval info: PRIVATE: Dpll_Lock_Count NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Lock_Window NUMERIC "0"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "ON"
// Retrieval info: PRIVATE: Enable_FIFO_DPA_Channels NUMERIC "0"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
// Retrieval info: PRIVATE: Outclock_Divide_By NUMERIC "0"
// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN NUMERIC "0"
// Retrieval info: PRIVATE: pINCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "125.000000"
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Use_Cda_Reset NUMERIC "0"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "1"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "1"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "1"
// Retrieval info: PRIVATE: Use_Rawperror NUMERIC "0"
// Retrieval info: PRIVATE: Use_Tx_Out_Phase NUMERIC "0"
// Retrieval info: CONSTANT: BUFFER_IMPLEMENTATION STRING "RAM"
// Retrieval info: CONSTANT: CDS_MODE STRING "UNUSED"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
// Retrieval info: CONSTANT: DATA_ALIGN_ROLLOVER NUMERIC "10"
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
// Retrieval info: CONSTANT: DPA_INITIAL_PHASE_VALUE NUMERIC "0"
// Retrieval info: CONSTANT: DPLL_LOCK_COUNT NUMERIC "0"
// Retrieval info: CONSTANT: DPLL_LOCK_WINDOW NUMERIC "0"
// Retrieval info: CONSTANT: ENABLE_CLOCK_PIN_MODE STRING "UNUSED"
// Retrieval info: CONSTANT: ENABLE_DPA_ALIGN_TO_RISING_EDGE_ONLY STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_DPA_CALIBRATION STRING "ON"
// Retrieval info: CONSTANT: ENABLE_DPA_FIFO STRING "UNUSED"
// Retrieval info: CONSTANT: ENABLE_DPA_INITIAL_PHASE_SELECTION STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_DPA_MODE STRING "ON"
// Retrieval info: CONSTANT: ENABLE_DPA_PLL_CALIBRATION STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_SOFT_CDR_MODE STRING "ON"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_BOOST NUMERIC "0"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: INPUT_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: CONSTANT: LOSE_LOCK_ON_ONE_CHANGE STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_rx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: CONSTANT: PLL_OPERATION_MODE STRING "UNUSED"
// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "UNUSED"
// Retrieval info: CONSTANT: PORT_RX_CHANNEL_DATA_ALIGN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_RX_DATA_ALIGN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REFCLK_FREQUENCY STRING "125.000000 MHz"
// Retrieval info: CONSTANT: REGISTERED_DATA_ALIGN_INPUT STRING "UNUSED"
// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
// Retrieval info: CONSTANT: RESET_FIFO_AT_FIRST_LOCK STRING "UNUSED"
// Retrieval info: CONSTANT: RX_ALIGN_DATA_REG STRING "UNUSED"
// Retrieval info: CONSTANT: SIM_DPA_IS_NEGATIVE_PPM_DRIFT STRING "OFF"
// Retrieval info: CONSTANT: SIM_DPA_NET_PPM_VARIATION NUMERIC "0"
// Retrieval info: CONSTANT: SIM_DPA_OUTPUT_CLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: USE_CORECLOCK_INPUT STRING "OFF"
// Retrieval info: CONSTANT: USE_DPLL_RAWPERROR STRING "OFF"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
// Retrieval info: CONSTANT: X_ON_BITSLIP STRING "ON"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
// Retrieval info: USED_PORT: rx_channel_data_align 0 0 1 0 INPUT NODEFVAL "rx_channel_data_align[0..0]"
// Retrieval info: CONNECT: @rx_channel_data_align 0 0 1 0 rx_channel_data_align 0 0 1 0
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL "rx_divfwdclk[0..0]"
// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL "rx_in[0..0]"
// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT NODEFVAL "rx_inclock"
// Retrieval info: CONNECT: @rx_inclock 0 0 0 0 rx_inclock 0 0 0 0
// Retrieval info: USED_PORT: rx_locked 0 0 0 0 OUTPUT NODEFVAL "rx_locked"
// Retrieval info: CONNECT: rx_locked 0 0 0 0 @rx_locked 0 0 0 0
// Retrieval info: USED_PORT: rx_out 0 0 10 0 OUTPUT NODEFVAL "rx_out[9..0]"
// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL "rx_outclock"
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
// Retrieval info: USED_PORT: rx_reset 0 0 1 0 INPUT NODEFVAL "rx_reset[0..0]"
// Retrieval info: CONNECT: @rx_reset 0 0 1 0 rx_reset 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av.cmp FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_av.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %ALTLVDS_TX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTLVDS_TX
// ============================================================
// File Name: altera_tse_pma_lvds_tx.v
// Megafunction Name(s):
// ALTLVDS_TX
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Internal Build 151 04/02/2011 PN Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_pma_lvds_tx (
pll_areset,
tx_in,
tx_inclock,
tx_out);
input pll_areset;
input [9:0] tx_in;
input tx_inclock;
output [0:0] tx_out;
wire [0:0] sub_wire0;
wire [0:0] tx_out = sub_wire0[0:0];
altlvds_tx ALTLVDS_TX_component (
.pll_areset (pll_areset),
.tx_in (tx_in),
.tx_inclock (tx_inclock),
.tx_out (sub_wire0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_locked (),
.tx_outclock (),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
defparam
ALTLVDS_TX_component.center_align_msb = "UNUSED",
ALTLVDS_TX_component.common_rx_tx_pll = "ON",
ALTLVDS_TX_component.coreclock_divide_by = 1,
ALTLVDS_TX_component.data_rate = "1250.0 Mbps",
ALTLVDS_TX_component.deserialization_factor = 10,
ALTLVDS_TX_component.differential_drive = 0,
ALTLVDS_TX_component.implement_in_les = "OFF",
ALTLVDS_TX_component.inclock_boost = 0,
ALTLVDS_TX_component.inclock_data_alignment = "EDGE_ALIGNED",
ALTLVDS_TX_component.inclock_period = 8000,
ALTLVDS_TX_component.inclock_phase_shift = 0,
ALTLVDS_TX_component.intended_device_family = "Stratix III",
ALTLVDS_TX_component.lpm_hint = "UNUSED",
ALTLVDS_TX_component.lpm_type = "altlvds_tx",
ALTLVDS_TX_component.multi_clock = "OFF",
ALTLVDS_TX_component.number_of_channels = 1,
ALTLVDS_TX_component.outclock_alignment = "EDGE_ALIGNED",
ALTLVDS_TX_component.outclock_divide_by = 10,
ALTLVDS_TX_component.outclock_duty_cycle = 50,
ALTLVDS_TX_component.outclock_multiply_by = 1,
ALTLVDS_TX_component.outclock_phase_shift = 0,
ALTLVDS_TX_component.outclock_resource = "AUTO",
ALTLVDS_TX_component.output_data_rate = 1250,
ALTLVDS_TX_component.pll_self_reset_on_loss_lock = "OFF",
ALTLVDS_TX_component.preemphasis_setting = 0,
ALTLVDS_TX_component.refclk_frequency = "125.00 MHz",
ALTLVDS_TX_component.registered_input = "TX_CLKIN",
ALTLVDS_TX_component.use_external_pll = "OFF",
ALTLVDS_TX_component.use_no_phase_shift = "ON",
ALTLVDS_TX_component.vod_setting = 0,
ALTLVDS_TX_component.clk_src_is_pll = "off";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: CNX_CLOCK_CHOICES STRING "none"
// Retrieval info: PRIVATE: CNX_CLOCK_MODE NUMERIC "1"
// Retrieval info: PRIVATE: CNX_COMMON_PLL NUMERIC "1"
// Retrieval info: PRIVATE: CNX_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: CNX_DESER_FACTOR NUMERIC "10"
// Retrieval info: PRIVATE: CNX_EXT_PLL STRING "OFF"
// Retrieval info: PRIVATE: CNX_LE_SERDES STRING "OFF"
// Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "1"
// Retrieval info: PRIVATE: CNX_OUTCLOCK_DIVIDE_BY NUMERIC "10"
// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "1"
// Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "125.00"
// Retrieval info: PRIVATE: CNX_PLL_PERIOD STRING "8.000"
// Retrieval info: PRIVATE: CNX_REG_INOUT NUMERIC "1"
// Retrieval info: PRIVATE: CNX_TX_CORECLOCK STRING "OFF"
// Retrieval info: PRIVATE: CNX_TX_LOCKED STRING "OFF"
// Retrieval info: PRIVATE: CNX_TX_OUTCLOCK STRING "OFF"
// Retrieval info: PRIVATE: CNX_USE_CLOCK_RESC STRING "Auto selection"
// Retrieval info: PRIVATE: CNX_USE_PLL_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: CNX_USE_TX_OUT_PHASE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN STRING "UNUSED"
// Retrieval info: PRIVATE: pINCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: CONSTANT: CENTER_ALIGN_MSB STRING "UNUSED"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: CORECLOCK_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
// Retrieval info: CONSTANT: DIFFERENTIAL_DRIVE NUMERIC "0"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_BOOST NUMERIC "0"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
// Retrieval info: CONSTANT: MULTI_CLOCK STRING "OFF"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: OUTCLOCK_DIVIDE_BY NUMERIC "10"
// Retrieval info: CONSTANT: OUTCLOCK_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: OUTCLOCK_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: PREEMPHASIS_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: REFCLK_FREQUENCY STRING "125.00 MHz"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CLKIN"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
// Retrieval info: CONSTANT: VOD_SETTING NUMERIC "0"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
// Retrieval info: USED_PORT: tx_in 0 0 10 0 INPUT NODEFVAL "tx_in[9..0]"
// Retrieval info: CONNECT: @tx_in 0 0 10 0 tx_in 0 0 10 0
// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT NODEFVAL "tx_inclock"
// Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
// Retrieval info: USED_PORT: tx_out 0 0 1 0 OUTPUT NODEFVAL "tx_out[0..0]"
// Retrieval info: CONNECT: tx_out 0 0 1 0 @tx_out 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.cmp FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
// $Revision: #7 $
// $Date: 2010/04/27 $
// $Author: jyeap $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(* ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \" set_false_path -to [get_pins -compatibility_mode -nocase *altera_tse_reset_synchronizer_chain*|aclr]; set_false_path -to [get_pins -compatibility_mode -nocase *altera_tse_reset_synchronizer_chain*|clrn] \"" *) (*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
reg altera_tse_reset_synchronizer_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
altera_tse_reset_synchronizer_chain_out <= 1'b1;
end
else begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end
endgenerate
endmodule
|
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in1.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
|
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in4.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_rgmii_module.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
//
// $Revision: #1 $
// $Date: 2012/08/12 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top level RGMII interface (receive and transmit) module.
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ ( // new ports to cater for mii with RGMII interface are added
// inputs
rgmii_in,
speed,
//data
gm_tx_d,
m_tx_d,
//control
gm_tx_en,
m_tx_en,
gm_tx_err,
m_tx_err,
reset_rx_clk,
reset_tx_clk,
rx_clk,
rx_control,
tx_clk,
// outputs:
rgmii_out,
gm_rx_d,
m_rx_d,
gm_rx_dv,
m_rx_en,
gm_rx_err,
m_rx_err,
m_rx_col,
m_rx_crs,
tx_control
);
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [ 3: 0] rgmii_out;
output [ 7: 0] gm_rx_d;
output [ 3: 0] m_rx_d;
output gm_rx_dv;
output m_rx_en;
output gm_rx_err;
output m_rx_err;
output m_rx_col;
output m_rx_crs;
output tx_control;
input [ 3: 0] rgmii_in;
input speed;
input [ 7: 0] gm_tx_d;
input [ 3: 0] m_tx_d;
input gm_tx_en;
input m_tx_en;
input gm_tx_err;
input m_tx_err;
input reset_rx_clk;
input reset_tx_clk;
input rx_clk;
input rx_control;
input tx_clk;
wire [ 3: 0] rgmii_out;
wire [ 7: 0] gm_rx_d;
wire gm_rx_dv;
wire m_rx_en;
wire gm_rx_err;
wire m_rx_err;
wire m_rx_col;
reg m_rx_col_reg;
reg m_rx_crs;
reg rx_dv;
reg rx_err;
wire tx_control;
//wire tx_err;
reg [ 7: 0] rgmii_out_4_wire;
reg rgmii_out_1_wire_inp1;
reg rgmii_out_1_wire_inp2;
wire [ 7:0 ] rgmii_in_4_wire;
reg [ 7:0 ] rgmii_in_4_reg;
reg [ 7:0 ] rgmii_in_4_temp_reg;
wire [ 1:0 ] rgmii_in_1_wire;
reg [ 1:0 ] rgmii_in_1_temp_reg;
reg m_tx_en_reg1;
reg m_tx_en_reg2;
reg m_tx_en_reg3;
reg m_tx_en_reg4;
assign gm_rx_d = rgmii_in_4_reg;
assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
altera_tse_rgmii_in4 the_rgmii_in4
(
.aclr (), //INPUT
.datain (rgmii_in), //INPUT
.dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
.dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
.inclock (rx_clk) //OUTPUT
);
altera_tse_rgmii_in1 the_rgmii_in1
(
.aclr (), //INPUT
.datain (rx_control), //INPUT
.dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
.dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
.inclock (rx_clk) //OUTPUT
);
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_temp_reg <= {8{1'b0}};
rgmii_in_1_temp_reg <= {2{1'b0}};
end
else begin
rgmii_in_4_temp_reg <= rgmii_in_4_wire;
rgmii_in_1_temp_reg <= rgmii_in_1_wire;
end
end
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_reg <= {8{1'b0}};
rx_err <= 1'b0;
rx_dv <= 1'b0;
end
else begin
rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
rx_err <= rgmii_in_1_wire[0];
rx_dv <= rgmii_in_1_temp_reg[1];
end
end
always @(rx_dv or rx_err or rgmii_in_4_reg)
begin
m_rx_crs = 1'b0;
if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
begin
m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
end
end
always @(posedge tx_clk or posedge reset_tx_clk)
begin
if(reset_tx_clk == 1'b1)
begin
m_tx_en_reg1 <= 1'b0;
m_tx_en_reg2 <= 1'b0;
m_tx_en_reg3 <= 1'b0;
m_tx_en_reg4 <= 1'b0;
end
else
begin
m_tx_en_reg1 <= m_tx_en;
m_tx_en_reg2 <= m_tx_en_reg1;
m_tx_en_reg3 <= m_tx_en_reg2;
m_tx_en_reg4 <= m_tx_en_reg3;
end
end
always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
begin
m_rx_col_reg = 1'b0;
if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
begin
m_rx_col_reg = 1'b1;
end
end
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(m_rx_col_reg), //INPUT
.dout(m_rx_col));// OUTPUT
assign gm_rx_err = rx_err ^ rx_dv;
assign gm_rx_dv = rx_dv;
assign m_rx_err = rx_err ^ rx_dv;
assign m_rx_en = rx_dv;
// mux for Out 4
always @(*)
begin
case (speed)
1'b1: rgmii_out_4_wire = gm_tx_d;
1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
endcase
end
// mux for Out 1
always @(*)
begin
case (speed)
1'b1:
begin
rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
end
1'b0:
begin
rgmii_out_1_wire_inp1 = m_tx_en;
rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
end
endcase
end
altera_tse_rgmii_out4 the_rgmii_out4
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
.datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
.dataout (rgmii_out), //INPUT
.outclock (tx_clk) //OUTPUT
);
//assign tx_err = gm_tx_en ^ gm_tx_err;
altera_tse_rgmii_out1 the_rgmii_out1
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_1_wire_inp1), //INPUT
.datain_l (rgmii_out_1_wire_inp2), //INPUT
.dataout (tx_control), //INPUT
.outclock (tx_clk) //OUTPUT
);
endmodule
|
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: rgmii_out1.v
// Megafunction Name(s):
// altddio_out
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_out1 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input datain_h;
input datain_l;
input outclock;
output dataout;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout = sub_wire1;
wire sub_wire2 = datain_h;
wire sub_wire3 = sub_wire2;
wire sub_wire4 = datain_l;
wire sub_wire5 = sub_wire4;
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (sub_wire3),
.aclr (aclr),
.datain_l (sub_wire5),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_bb.v TRUE
|
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: rgmii_out4.v
// Megafunction Name(s):
// altddio_out
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_out4 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_bb.v TRUE
|
// Module: altera_tse_xcvr_resync
//
// Description:
// A general purpose resynchronization module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
//
module altera_tse_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0 // See description above
) (
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
wire [INT_LEN :0] next_r; // One larger real chain
assign q[ig] = r[INT_LEN-1]; // Output signal
assign next_r = {r,d_in};
always @(posedge clk)
r <= next_r[INT_LEN-1:0];
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r;
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : (DDR1/2/3,LPDDR1) address and command decoder
//
// File : alt_mem_ddrx_addr_cmd.v
//
// Abstract : Address and command decoder
///////////////////////////////////////////////////////////////////////////////
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits (For ddr3 >=13 even if row=12)
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_CTL_RATE = "FULL",
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_type,
cfg_output_regd,
cfg_enable_chipsel_for_sideband, // to indicate should we de-assert cs_n for sideband signal (self refresh and deep power down specific)
// AFI interface (Signals from Arbiter block)
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_zq_cal,
bg_do_lmr,
bg_do_burst_terminate, //Currently does not exist in arbiter
bg_do_deep_pdown, //Currently does not exist in arbiter
// address information
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr, //Currently doesn not exist in arbiter
lmr_opcode,
//output to PHY
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n
);
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
input cfg_enable_chipsel_for_sideband;
// Arbiter command inputs
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
input bg_do_auto_precharge;
input bg_do_activate;
input bg_do_precharge;
input [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] bg_do_refresh;
input [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] bg_do_power_down;
input [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal;
input bg_do_lmr;
input bg_do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown;
input [CFG_MEM_IF_CHIP-1:0] bg_to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] bg_to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] bg_to_col;
input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_lmr;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
wire bg_do_read;
wire bg_do_burst_chop;
wire bg_do_auto_precharge;
wire bg_do_activate;
wire bg_do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal;
wire bg_do_lmr;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown;
wire bg_do_burst_terminate;
reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down_r;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown_r;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg int_ras_n;
reg int_cas_n;
reg int_we_n;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] int_ba;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke ;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n ;
reg combi_ras_n;
reg combi_cas_n;
reg combi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr ;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r ;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r ;
reg combi_ras_n_r;
reg combi_cas_n_r;
reg combi_we_n_r ;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba_r ;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r ;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_row;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] temp_col;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col;
wire col12;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col_r;
reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh;
//=================================================================================================//
generate
if (CFG_MEM_IF_ADDR_WIDTH > CFG_MEM_IF_ROW_WIDTH)
begin
assign int_row = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_ROW_WIDTH){1'b0}},bg_to_row};
end
else
begin
assign int_row = bg_to_row;
end
endgenerate
assign temp_col = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_COL_WIDTH){1'b0}},bg_to_col};
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
assign col12 = (cfg_type == `MMR_TYPE_DDR3) ? ~bg_do_burst_chop : temp_col[11]; //DDR3
generate
if (CFG_MEM_IF_ADDR_WIDTH < 13)
begin
assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-1:10],bg_do_auto_precharge,temp_col[9:0]};
end
else if (CFG_MEM_IF_ADDR_WIDTH == 13)
begin
assign int_col = {col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
end
else
begin
assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-3:11],col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
end
endgenerate
generate
if (CFG_DWIDTH_RATIO == 2)
begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_ras_n = int_ras_n;
assign afi_cas_n = int_cas_n;
assign afi_we_n = int_we_n;
assign afi_ba = int_ba;
assign afi_addr = int_addr;
end
else
begin
assign afi_cke = {int_cke,int_cke_r};
assign afi_cs_n = {int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}}; // to provide time for addr bus to settle at high freq, cs sent on 2nd phase
assign afi_ras_n = {int_ras_n,int_ras_n};
assign afi_cas_n = {int_cas_n,int_cas_n};
assign afi_we_n = {int_we_n,int_we_n};
assign afi_ba = {int_ba,int_ba};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n) // aligns cke with cs for slf rfsh & pwrdwn(lpddr1)which is defined only when cs_n goes low
begin
if (!ctl_reset_n)
int_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b0}};
else
int_cke_r <= int_cke;
end
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
begin
if (!ctl_reset_n)
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
else
if ((bg_do_self_refresh) || (bg_do_deep_pdown && cfg_type == `MMR_TYPE_LPDDR1)) //LPDDDR1
chip_in_self_refresh <= bg_to_chip;
else
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
combi_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n_r <= {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n_r <= 1'b1;
combi_cas_n_r <= 1'b1;
combi_we_n_r <= 1'b1;
combi_ba_r <= {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr_r <= {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else
begin
combi_cke_r <= combi_cke;
combi_cs_n_r <= combi_cs_n;
combi_ras_n_r <= combi_ras_n;
combi_cas_n_r <= combi_cas_n;
combi_we_n_r <= combi_we_n;
combi_ba_r <= combi_ba;
combi_addr_r <= combi_addr;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_ras_n = combi_ras_n_r;
int_cas_n = combi_cas_n_r;
int_we_n = combi_we_n_r;
int_ba = combi_ba_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_ras_n = combi_ras_n;
int_cas_n = combi_cas_n;
int_we_n = combi_we_n;
int_ba = combi_ba;
int_addr = combi_addr;
end
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(bg_do_self_refresh | bg_do_power_down | bg_do_deep_pdown);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
//Pulse generator for self refresh, power down and deep power down
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_self_refresh_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_power_down_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_deep_pdown_r <= {(CFG_MEM_IF_CHIP){1'b0}};
end
else
begin
do_self_refresh_r <= ~bg_do_self_refresh;
do_power_down_r <= ~bg_do_power_down;
do_deep_pdown_r <= ~bg_do_deep_pdown;
end
end
always @(*)
begin
do_self_refresh = bg_do_self_refresh & do_self_refresh_r;
do_power_down = bg_do_power_down & do_power_down_r;
do_deep_pdown = bg_do_deep_pdown & do_deep_pdown_r;
end
always @(*) //All Command inputs are mutually exclusive
begin
if (ctl_cal_success)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; //Should we put default condition into if(!bg_do_refresh && !bg_do_activate....)??
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|bg_do_refresh)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_refresh;
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|bg_do_precharge_all)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_precharge_all;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr[10]= 1'b1;
end
if (bg_do_activate)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = bg_to_bank;
combi_addr = int_row;
end
if (bg_do_precharge)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (bg_do_write)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr = int_col;
end
if (bg_do_read)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = bg_to_bank;
combi_addr = int_col;
end
if (|do_power_down)
begin
// combi_cke = ~bg_to_chip;
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|do_deep_pdown) //Put assertion for memory type ddr2 and ddr3 as an error
begin
// combi_cke = ~bg_to_chip;
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~do_deep_pdown; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|do_self_refresh)
begin
// combi_cke = ~bg_to_chip;
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|bg_do_zq_cal) // Only short zqcal supported
begin
if (cfg_type == `MMR_TYPE_DDR3) //DDR3
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_zq_cal;
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else // Should we flag error or issue as NOP
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
if (bg_do_lmr)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; // to support chng rfsh time based on temp
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b0;
combi_ba = bg_to_lmr;
combi_addr = lmr_opcode;
end
if (bg_do_burst_terminate)
begin
if (cfg_type == `MMR_TYPE_LPDDR1) //lpddr1
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
end
else
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
module alt_mem_ddrx_addr_cmd_wrap
# ( parameter
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CKE_WIDTH = 2, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_LPDDR2_ENABLED = 1,
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_LOCAL_ID_WIDTH = 8,
CFG_DATA_ID_WIDTH = 4,
CFG_INT_SIZE_WIDTH = 4,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_CAS_WR_LAT = 5,
CFG_PORT_WIDTH_TCL = 5,
CFG_PORT_WIDTH_ADD_LAT = 5,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 1
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd_for_afi_output,
// burst generator command signals
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_lmr_read,
bg_do_refresh_1bank,
bg_do_zq_cal,
bg_do_lmr,
bg_localid,
bg_dataid,
bg_size,
// burst generator address signals
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_rst_n,
afi_odt
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam CFG_FR_DWIDTH_RATIO = 2;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk ;
input ctl_reset_n ;
input ctl_cal_success ;
//run-time csr chain input
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type ;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl ;
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat ;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat ;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip ;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip ;
input [4:0] cfg_burst_length ;
//output regd signal from rdwr_tmg block
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
//command inputs
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col ;
input bg_do_lmr_read ;
input bg_do_refresh_1bank ;
input [7:0] bg_to_lmr ;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid ;
input [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid ;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size ;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode ;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// port type declaration
// -----------------------------
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
reg [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
reg [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// signal declaration
// -----------------------------
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_correct ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_partial ;
wire [CFG_MEM_IF_CKE_WIDTH- 1:0] int_afi_cke [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_ras_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_cas_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_we_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_ADDR_WIDTH:0] int_afi_addr [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rst_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_correct [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_partial [(CFG_DWIDTH_RATIO/2)-1:0];
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cke ;
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cs_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_ras_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_cas_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_we_n ;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_ba ;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_addr ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rst_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_correct ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_partial ;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_rst_n;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_write ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_read ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_chop ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_terminate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_auto_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_activate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct_r ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_precharge_all [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_self_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_power_down [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_deep_pdown [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_zq_cal [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_lmr ;
reg [CFG_MEM_IF_CHIP -1:0] int_bg_to_chip [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_col [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] int_bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_bg_size;
reg int_bg_do_lmr_read;
reg int_bg_do_refresh_1bank;
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] cfg_enable_chipsel_for_sideband;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh_r;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown_r;
wire one = 1'b1;
wire zero = 1'b0;
// -----------------------------
// module definition
// -----------------------------
genvar afi_j, afi_n;
generate
// map int_afi_* multi-dimensional array signals to afi_* output port signals
for (afi_n = 0; afi_n < (CFG_DWIDTH_RATIO/2); afi_n = afi_n + 1'b1)
begin : gen_afi_signals
always @ (*)
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n [afi_n] ;
//afi_odt [((afi_n+1) * CFG_MEM_IF_ODT_WIDTH) -1 : (afi_n * CFG_MEM_IF_ODT_WIDTH)] = int_afi_odt [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial [afi_n] ;
end
end
// generate int_afi_* signals based on CFG_DWIDTH_RATIO & CFG_AFI_INTF_PHASE_NUM
if (CFG_DWIDTH_RATIO == 2)
begin
// full rate, with any phase
assign int_afi_cke [0] = fr_afi_cke ;
assign int_afi_cs_n [0] = fr_afi_cs_n ;
assign int_afi_ras_n [0] = fr_afi_ras_n ;
assign int_afi_cas_n [0] = fr_afi_cas_n ;
assign int_afi_we_n [0] = fr_afi_we_n ;
assign int_afi_ba [0] = fr_afi_ba ;
assign int_afi_addr [0] = fr_afi_addr ;
assign int_afi_rst_n [0] = fr_afi_rst_n ;
assign int_afi_rmw_correct [0] = fr_afi_rmw_correct ;
assign int_afi_rmw_partial [0] = fr_afi_rmw_partial ;
end
else if ((CFG_DWIDTH_RATIO/2) == CFG_AFI_INTF_PHASE_NUM)
begin
// map phase_afi_* signals to int_afi_* signals
// half rate , with phase=2
// quarter rate, with phase=4
for (afi_j = 0; afi_j < CFG_AFI_INTF_PHASE_NUM; afi_j = afi_j + 1'b1)
begin : gen_afi_signals_0
assign int_afi_cke [afi_j] = phase_afi_cke [afi_j] ;
assign int_afi_cs_n [afi_j] = phase_afi_cs_n [afi_j] ;
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j] ;
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j] ;
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j] ;
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j] ;
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j] ;
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j] ;
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j] ;
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j] ;
end
end
else // only supports case CFG_AFI_INTF_PHASE_NUM < (CFG_DWIDTH_RATIO/2)
begin
// map phase_afi_* signals to selected int_afi_* signals, and drive the rest to default values
// for cs_n signals:
// half rate , with phase=1, drives int_afi_* 1 only
// quarter rate , with phase=2, drives int_afi_* 1 & 3
// for other signals:
// half rate , with phase=1, drives int_afi_* 0 & 1 with the same value
// quarter rate , with phase=2, drives int_afi_* 0 & 1 or 2 & 3 with the same value
// Why? to improve timing margin on PHY side
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_1
// Assign even phase with '1' because we only issue on odd phase (2T timing)
assign int_afi_cs_n [afi_j] = ((afi_j % CFG_AFI_INTF_PHASE_NUM) == 1) ? phase_afi_cs_n [afi_j / CFG_AFI_INTF_PHASE_NUM] : { CFG_MEM_IF_CHIP {1'b1} };
// Assign the last CKE with phase_afi_cs_n[1], the rest with phase_afi_cs_n[0]
assign int_afi_cke [afi_j] = (afi_j == ((CFG_DWIDTH_RATIO/2) - 1)) ? phase_afi_cke [1] : phase_afi_cke [0];
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j / CFG_AFI_INTF_PHASE_NUM];
end
end
endgenerate
// phase_afi_* signal generation
// instantiates an alt_mem_ddrx_addr_cmd for every phase
// maps bg_* signals to the correct instantiation
genvar afi_k;
generate
for (afi_k = 0; afi_k < CFG_AFI_INTF_PHASE_NUM; afi_k = afi_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_write [afi_k] = bg_do_write [afi_k];
int_bg_do_read [afi_k] = bg_do_read [afi_k];
int_bg_do_burst_chop [afi_k] = bg_do_burst_chop [afi_k];
int_bg_do_burst_terminate [afi_k] = bg_do_burst_terminate [afi_k];
int_bg_do_auto_precharge [afi_k] = bg_do_auto_precharge [afi_k];
int_bg_do_rmw_correct [afi_k] = bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial [afi_k] = bg_do_rmw_partial [afi_k];
int_bg_do_activate [afi_k] = bg_do_activate [afi_k];
int_bg_do_precharge [afi_k] = bg_do_precharge [afi_k];
int_bg_to_chip [afi_k] = bg_to_chip [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_to_bank [afi_k] = bg_to_bank [(((afi_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(afi_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [afi_k] = bg_to_row [(((afi_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(afi_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_col [afi_k] = bg_to_col [(((afi_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(afi_k*CFG_MEM_IF_COL_WIDTH)];
end
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_refresh [afi_k] = bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_self_refresh [afi_k] = bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_deep_pdown [afi_k] = bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_zq_cal [afi_k] = bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_lmr [afi_k] = bg_do_lmr [afi_k];
end
always @ (*)
begin
cfg_enable_chipsel_for_sideband [afi_k] = one;
end
end
else // half and quarter rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : 0;
int_bg_do_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : 0;
int_bg_do_zq_cal [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : 0;
int_bg_do_lmr [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_lmr [afi_k ] : 0;
// We need to assign these command to all phase
// because these command might take one or more controller clock cycles
// and we want to prevent CKE from toggling due to prolong commands
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_self_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_self_refresh_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_deep_pdown [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_deep_pdown_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
end
always @ (*)
begin
// We need to disable one phase of chipsel logic for sideband in half/quarter rate
// in order to prevent CS_N from going low for 2 clock cycles (deep power down and self refresh only)
cfg_enable_chipsel_for_sideband [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? one : zero;
end
end
// addresss command block instantiated based on number of phases
alt_mem_ddrx_addr_cmd # (
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO ( CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_addr_cmd_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_cal_success ( ctl_cal_success ),
.cfg_type ( cfg_type ),
.cfg_output_regd ( cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband ( cfg_enable_chipsel_for_sideband [afi_k] ),
.bg_do_write ( int_bg_do_write [afi_k] ),
.bg_do_read ( int_bg_do_read [afi_k] ),
.bg_do_auto_precharge ( int_bg_do_auto_precharge [afi_k] ),
.bg_do_burst_chop ( int_bg_do_burst_chop [afi_k] ),
.bg_do_activate ( int_bg_do_activate [afi_k] ),
.bg_do_precharge ( int_bg_do_precharge [afi_k] ),
.bg_do_refresh ( int_bg_do_refresh [afi_k] ),
.bg_do_power_down ( int_bg_do_power_down [afi_k] ),
.bg_do_self_refresh ( int_bg_do_self_refresh [afi_k] ),
.bg_do_lmr ( int_bg_do_lmr [afi_k] ),
.bg_do_precharge_all ( int_bg_do_precharge_all [afi_k] ),
.bg_do_zq_cal ( int_bg_do_zq_cal [afi_k] ),
.bg_do_deep_pdown ( int_bg_do_deep_pdown [afi_k] ),
.bg_do_burst_terminate ( int_bg_do_burst_terminate [afi_k] ),
.bg_to_chip ( int_bg_to_chip [afi_k] ),
.bg_to_bank ( int_bg_to_bank [afi_k] ),
.bg_to_row ( int_bg_to_row [afi_k] ),
.bg_to_col ( int_bg_to_col [afi_k] ),
.bg_to_lmr ( ),
.lmr_opcode ( lmr_opcode ),
.afi_cke ( int_ddrx_afi_cke [afi_k] ),
.afi_cs_n ( int_ddrx_afi_cs_n [afi_k] ),
.afi_ras_n ( int_ddrx_afi_ras_n [afi_k] ),
.afi_cas_n ( int_ddrx_afi_cas_n [afi_k] ),
.afi_we_n ( int_ddrx_afi_we_n [afi_k] ),
.afi_ba ( int_ddrx_afi_ba [afi_k] ),
.afi_addr ( int_ddrx_afi_addr [afi_k] ),
.afi_rst_n ( int_ddrx_afi_rst_n [afi_k] )
);
if (CFG_LPDDR2_ENABLED)
begin
alt_mem_ddrx_lpddr2_addr_cmd # (
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_lpddr2_addr_cmd_inst (
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.do_write (int_bg_do_write [afi_k] ),
.do_read (int_bg_do_read [afi_k] ),
.do_auto_precharge (int_bg_do_auto_precharge [afi_k] ),
.do_activate (int_bg_do_activate [afi_k] ),
.do_precharge (int_bg_do_precharge [afi_k] ),
.do_refresh (int_bg_do_refresh [afi_k] ),
.do_power_down (int_bg_do_power_down [afi_k] ),
.do_self_refresh (int_bg_do_self_refresh [afi_k] ),
.do_lmr (int_bg_do_lmr [afi_k] ),
.do_precharge_all (int_bg_do_precharge_all [afi_k] ),
.do_deep_pwrdwn (int_bg_do_deep_pdown [afi_k] ),
.do_burst_terminate (int_bg_do_burst_terminate [afi_k] ),
.do_lmr_read (int_bg_do_lmr_read ),
.do_refresh_1bank (int_bg_do_refresh_1bank ),
.to_chip (int_bg_to_chip [afi_k] ),
.to_bank (int_bg_to_bank [afi_k] ),
.to_row (int_bg_to_row [afi_k] ),
.to_col (int_bg_to_col [afi_k] ),
.to_lmr ( ),
.lmr_opcode (lmr_opcode[7:0] ),
.afi_cke (int_lpddr2_afi_cke [afi_k] ),
.afi_cs_n (int_lpddr2_afi_cs_n [afi_k] ),
.afi_addr (int_lpddr2_afi_addr [afi_k] ),
.afi_rst_n (int_lpddr2_afi_rst_n [afi_k] )
);
end
else
begin
assign int_lpddr2_afi_cke [afi_k] = {(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_cs_n [afi_k] = {(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_addr [afi_k] = {(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_rst_n [afi_k] = { (CFG_FR_DWIDTH_RATIO/2) {1'b0}};
end
always @ (*)
begin
// Mux to select ddrx or lpddr2 addrcmd decoder blocks
if (cfg_type == `MMR_TYPE_LPDDR2)
begin
phase_afi_cke [afi_k] = int_lpddr2_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_lpddr2_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_cas_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_we_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_ba [afi_k] = {(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
phase_afi_addr [afi_k] = int_lpddr2_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_lpddr2_afi_rst_n[afi_k] ;
end
else
begin
phase_afi_cke [afi_k] = int_ddrx_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_ddrx_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = int_ddrx_afi_ras_n [afi_k] ;
phase_afi_cas_n [afi_k] = int_ddrx_afi_cas_n [afi_k] ;
phase_afi_we_n [afi_k] = int_ddrx_afi_we_n [afi_k] ;
phase_afi_ba [afi_k] = int_ddrx_afi_ba [afi_k] ;
phase_afi_addr [afi_k] = int_ddrx_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_ddrx_afi_rst_n [afi_k] ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_bg_do_rmw_correct_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
int_bg_do_rmw_partial_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
end
else
begin
int_bg_do_rmw_correct_r[afi_k] <= int_bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial_r[afi_k] <= int_bg_do_rmw_partial [afi_k];
end
end
always @ (*)
begin
if (cfg_output_regd_for_afi_output)
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct_r [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial_r [afi_k];
end
else
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial [afi_k];
end
end
alt_mem_ddrx_odt_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
odt_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.bg_do_read (int_bg_do_read [afi_k]),
.bg_do_write (int_bg_do_write [afi_k]),
.bg_do_burst_chop (int_bg_do_burst_chop [afi_k]),
.bg_to_chip (int_bg_to_chip [afi_k]),
.afi_odt (afi_odt_h_l [afi_k])
);
end
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
int_bg_do_lmr_read = bg_do_lmr_read;
int_bg_do_refresh_1bank = bg_do_refresh_1bank;
end
endgenerate
// ODT output generation
always @ (*)
begin
afi_odt = mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1];
end
// generate ODT output signal from odt_gen
assign mux_afi_odt_h_l [0] = afi_odt_h_l [0];
genvar afi_m;
generate
for (afi_m = 1; afi_m < CFG_AFI_INTF_PHASE_NUM; afi_m = afi_m + 1)
begin : mux_for_odt
assign mux_afi_odt_h_l [afi_m] = mux_afi_odt_h_l [afi_m-1] | afi_odt_h_l [afi_m];
end
endgenerate
// generate fr_* signals from phase_* signals
assign mux_afi_cke [0] = phase_afi_cke [0];
assign mux_afi_cs_n [0] = phase_afi_cs_n [0];
assign mux_afi_ras_n [0] = phase_afi_ras_n [0];
assign mux_afi_cas_n [0] = phase_afi_cas_n [0];
assign mux_afi_we_n [0] = phase_afi_we_n [0];
assign mux_afi_ba [0] = phase_afi_ba [0];
assign mux_afi_addr [0] = phase_afi_addr [0];
assign mux_afi_rst_n [0] = phase_afi_rst_n [0];
assign mux_afi_rmw_correct [0] = phase_afi_rmw_correct [0];
assign mux_afi_rmw_partial [0] = phase_afi_rmw_partial [0];
genvar afi_l;
generate
for (afi_l = 1; afi_l < CFG_AFI_INTF_PHASE_NUM; afi_l = afi_l + 1)
begin : gen_resolve_phase_for_fullrate
assign mux_afi_cke [afi_l] = mux_afi_cke [(afi_l-1)] & phase_afi_cke [afi_l];
assign mux_afi_cs_n [afi_l] = mux_afi_cs_n [(afi_l-1)] & phase_afi_cs_n [afi_l];
assign mux_afi_ras_n [afi_l] = mux_afi_ras_n [(afi_l-1)] & phase_afi_ras_n [afi_l];
assign mux_afi_cas_n [afi_l] = mux_afi_cas_n [(afi_l-1)] & phase_afi_cas_n [afi_l];
assign mux_afi_we_n [afi_l] = mux_afi_we_n [(afi_l-1)] & phase_afi_we_n [afi_l];
assign mux_afi_ba [afi_l] = mux_afi_ba [(afi_l-1)] | phase_afi_ba [afi_l];
assign mux_afi_addr [afi_l] = mux_afi_addr [(afi_l-1)] | phase_afi_addr [afi_l];
assign mux_afi_rst_n [afi_l] = mux_afi_rst_n [(afi_l-1)] | phase_afi_rst_n [afi_l];
assign mux_afi_rmw_correct [afi_l] = mux_afi_rmw_correct [(afi_l-1)] | phase_afi_rmw_correct [afi_l];
assign mux_afi_rmw_partial [afi_l] = mux_afi_rmw_partial [(afi_l-1)] | phase_afi_rmw_partial [afi_l];
end
endgenerate
assign fr_afi_cke = mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cs_n = mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ras_n = mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cas_n = mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_we_n = mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ba = mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_addr = mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rst_n = mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_correct = mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_partial = mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
// Registered version of self refresh and power down
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bg_do_self_refresh_r <= 0;
bg_do_deep_pdown_r <= 0;
end
else
begin
bg_do_self_refresh_r <= bg_do_self_refresh;
bg_do_deep_pdown_r <= bg_do_deep_pdown;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_arbiter #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_REG_REQ = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_DISABLE_PRIORITY = 1
)
(
ctl_clk,
ctl_reset_n,
// Common
stall_row_arbiter,
stall_col_arbiter,
// Sideband Interface
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
// TBP Interface
row_req,
col_req,
act_req,
pch_req,
rd_req,
wr_req,
row_grant,
col_grant,
act_grant,
pch_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_activate,
tbp_precharge,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_rmw_correct,
tbp_rmw_partial,
tbp_age,
tbp_priority,
// Rank Timer Interface
can_activate,
can_precharge,
can_write,
can_read,
// Arbiter Output Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// Common
input stall_row_arbiter;
input stall_col_arbiter;
// Sideband Interface
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
// TBP Interface
input [CFG_CTL_TBP_NUM - 1 : 0] row_req;
input [CFG_CTL_TBP_NUM - 1 : 0] col_req;
input [CFG_CTL_TBP_NUM - 1 : 0] act_req;
input [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
input [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
input [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
output [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
output or_row_grant;
output or_col_grant;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
input [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
input [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
input [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
input [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
// Rank Timer Interface
input [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] can_write;
input [CFG_CTL_TBP_NUM - 1 : 0] can_read;
// Arbiter Output Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
wire one = 1'b1;
wire zero = 1'b0;
// TBP Interface
reg [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
reg or_row_grant;
reg or_col_grant;
// Arbiter Output Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// Common
reg granted_read [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_write [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_c ;
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_COL_WIDTH - 1 : 0] granted_col [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_INT_SIZE_WIDTH - 1 : 0] granted_size [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_DATA_ID_WIDTH - 1 : 0] granted_dataid [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] granted_localid [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_ap [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_burst_chop [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_correct [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_partial [CFG_CTL_TBP_NUM - 1 : 0];
// Arbiter
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_wr_grant;
reg int_or_row_grant;
reg int_or_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_wr_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] all_grant;
//--------------------------------------------------------------------------------------------------------
//
// [END] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Granted logic specific grant signals
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
granted_row_grant = row_grant;
granted_col_grant = col_grant;
granted_act_grant = act_grant;
granted_pch_grant = pch_grant;
granted_rd_grant = rd_grant;
granted_wr_grant = wr_grant;
log2_granted_row_grant = log2_row_grant;
log2_granted_col_grant = log2_col_grant;
log2_granted_act_grant = log2_act_grant;
log2_granted_pch_grant = log2_pch_grant;
log2_granted_rd_grant = log2_rd_grant;
log2_granted_wr_grant = log2_wr_grant;
end
//----------------------------------------------------------------------------------------------------
// Sideband outputs
//----------------------------------------------------------------------------------------------------
// Precharge all
always @ (*)
begin
arb_do_precharge_all = {CFG_AFI_INTF_PHASE_NUM{sb_do_precharge_all}};
end
// Refresh
always @ (*)
begin
arb_do_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_refresh}};
end
// Self refresh
always @ (*)
begin
arb_do_self_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_self_refresh}};
end
// Power down
always @ (*)
begin
arb_do_power_down = {CFG_AFI_INTF_PHASE_NUM{sb_do_power_down}};
end
// Power down
always @ (*)
begin
arb_do_deep_pdown = {CFG_AFI_INTF_PHASE_NUM{sb_do_deep_pdown}};
end
// ZQ calibration
always @ (*)
begin
arb_do_zq_cal = {CFG_AFI_INTF_PHASE_NUM{sb_do_zq_cal}};
end
// LMR
always @ (*)
begin
arb_do_lmr = {CFG_AFI_INTF_PHASE_NUM{zero}};
end
//----------------------------------------------------------------------------------------------------
// Non arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
// Burst chop
always @ (*)
begin
arb_do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{granted_burst_chop [CFG_CTL_TBP_NUM - 1]}};
end
// Burst terminate
always @ (*)
begin
arb_do_burst_terminate = 0;
end
// RMW Correct
always @ (*)
begin
arb_do_rmw_correct = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_correct [CFG_CTL_TBP_NUM - 1]}};
end
// RMW Partial
always @ (*)
begin
arb_do_rmw_partial = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_partial [CFG_CTL_TBP_NUM - 1]}};
end
// LMR
always @ (*)
begin
arb_do_lmr = 0;
end
// Local ID
always @ (*)
begin
arb_localid = granted_localid [CFG_CTL_TBP_NUM - 1];
end
// Data ID
always @ (*)
begin
arb_dataid = granted_dataid [CFG_CTL_TBP_NUM - 1];
end
// Size
always @ (*)
begin
arb_size = granted_size [CFG_CTL_TBP_NUM - 1];
end
// Column address
// column command will only require column address, therefore there will be no conflcting column addresses
always @ (*)
begin
arb_to_col = {CFG_AFI_INTF_PHASE_NUM{granted_col [CFG_CTL_TBP_NUM - 1]}};
end
//----------------------------------------------------------------------------------------------------
// Arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_LOW_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_LOW_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_LOW_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_HIGH_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_HIGH_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_r [CFG_CTL_TBP_NUM - 1], granted_chipsel_c [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_r, granted_to_chip_c};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_r [CFG_CTL_TBP_NUM - 1], granted_bank_c [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_r [CFG_CTL_TBP_NUM - 1], granted_row_c [CFG_CTL_TBP_NUM - 1]};
end
end
else
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_HIGH_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_HIGH_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_HIGH_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_LOW_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_LOW_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_c [CFG_CTL_TBP_NUM - 1], granted_chipsel_r [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_c, granted_to_chip_r};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_c [CFG_CTL_TBP_NUM - 1], granted_bank_r [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_c [CFG_CTL_TBP_NUM - 1], granted_row_r [CFG_CTL_TBP_NUM - 1]};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Granted outputs
//----------------------------------------------------------------------------------------------------
// Chip address
always @ (*)
begin
granted_chipsel_r [0] = {CFG_MEM_IF_CS_WIDTH {granted_row_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
granted_chipsel_c [0] = {CFG_MEM_IF_CS_WIDTH {granted_col_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
end
// Bank address
always @ (*)
begin
granted_bank_r [0] = {CFG_MEM_IF_BA_WIDTH {granted_row_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
granted_bank_c [0] = {CFG_MEM_IF_BA_WIDTH {granted_col_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
end
// Row address
always @ (*)
begin
granted_row_r [0] = {CFG_MEM_IF_ROW_WIDTH{granted_row_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
granted_row_c [0] = {CFG_MEM_IF_ROW_WIDTH{granted_col_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
end
// Column address
always @ (*)
begin
granted_col [0] = {CFG_MEM_IF_COL_WIDTH{granted_col_grant [0]}} & tbp_col [CFG_MEM_IF_COL_WIDTH - 1 : 0];
end
// Size
always @ (*)
begin
granted_size [0] = {CFG_INT_SIZE_WIDTH {granted_col_grant [0]}} & tbp_size [CFG_INT_SIZE_WIDTH - 1 : 0];
end
// Local ID
always @ (*)
begin
granted_localid [0] = {CFG_LOCAL_ID_WIDTH {granted_col_grant [0]}} & tbp_localid [CFG_LOCAL_ID_WIDTH - 1 : 0];
end
// Data ID
always @ (*)
begin
granted_dataid [0] = {CFG_DATA_ID_WIDTH {granted_col_grant [0]}} & tbp_dataid [CFG_DATA_ID_WIDTH - 1 : 0];
end
// Auto precharge
always @ (*)
begin
granted_ap [0] = granted_col_grant [0] & tbp_ap [ 0];
end
// Burst Chop
always @ (*)
begin
granted_burst_chop [0] = granted_col_grant [0] & tbp_burst_chop [ 0];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [0] = granted_col_grant [0] & tbp_rmw_correct [ 0];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [0] = granted_col_grant [0] & tbp_rmw_partial [ 0];
end
generate
begin
genvar j_tbp;
for (j_tbp = 1;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : granted_information_per_tbp
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] chipsel_addr = tbp_chipsel [(j_tbp + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j_tbp * CFG_MEM_IF_CS_WIDTH ];
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] bank_addr = tbp_bank [(j_tbp + 1) * CFG_MEM_IF_BA_WIDTH - 1 : j_tbp * CFG_MEM_IF_BA_WIDTH ];
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] row_addr = tbp_row [(j_tbp + 1) * CFG_MEM_IF_ROW_WIDTH - 1 : j_tbp * CFG_MEM_IF_ROW_WIDTH];
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] col_addr = tbp_col [(j_tbp + 1) * CFG_MEM_IF_COL_WIDTH - 1 : j_tbp * CFG_MEM_IF_COL_WIDTH];
wire [CFG_INT_SIZE_WIDTH - 1 : 0] size = tbp_size [(j_tbp + 1) * CFG_INT_SIZE_WIDTH - 1 : j_tbp * CFG_INT_SIZE_WIDTH ];
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] localid = tbp_localid [(j_tbp + 1) * CFG_LOCAL_ID_WIDTH - 1 : j_tbp * CFG_LOCAL_ID_WIDTH ];
wire [CFG_DATA_ID_WIDTH - 1 : 0] dataid = tbp_dataid [(j_tbp + 1) * CFG_DATA_ID_WIDTH - 1 : j_tbp * CFG_DATA_ID_WIDTH ];
wire ap = tbp_ap [(j_tbp + 1) - 1 : j_tbp ];
wire burst_chop = tbp_burst_chop [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_correct = tbp_rmw_correct [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_partial = tbp_rmw_partial [(j_tbp + 1) - 1 : j_tbp ];
// Chip address
always @ (*)
begin
granted_chipsel_r [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_row_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_r [j_tbp - 1];
granted_chipsel_c [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_col_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_c [j_tbp - 1];
end
// Bank address
always @ (*)
begin
granted_bank_r [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_row_grant [j_tbp]}} & bank_addr ) | granted_bank_r [j_tbp - 1];
granted_bank_c [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_col_grant [j_tbp]}} & bank_addr ) | granted_bank_c [j_tbp - 1];
end
// Row address
always @ (*)
begin
granted_row_r [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_row_grant [j_tbp]}} & row_addr ) | granted_row_r [j_tbp - 1];
granted_row_c [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_col_grant [j_tbp]}} & row_addr ) | granted_row_c [j_tbp - 1];
end
// Column address
always @ (*)
begin
granted_col [j_tbp] = ({CFG_MEM_IF_COL_WIDTH{granted_col_grant [j_tbp]}} & col_addr ) | granted_col [j_tbp - 1];
end
// Size
always @ (*)
begin
granted_size [j_tbp] = ({CFG_INT_SIZE_WIDTH {granted_col_grant [j_tbp]}} & size ) | granted_size [j_tbp - 1];
end
// Local ID
always @ (*)
begin
granted_localid [j_tbp] = ({CFG_LOCAL_ID_WIDTH {granted_col_grant [j_tbp]}} & localid ) | granted_localid [j_tbp - 1];
end
// Data ID
always @ (*)
begin
granted_dataid [j_tbp] = ({CFG_DATA_ID_WIDTH {granted_col_grant [j_tbp]}} & dataid ) | granted_dataid [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_ap [j_tbp] = ( granted_col_grant [j_tbp] & ap ) | granted_ap [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_burst_chop [j_tbp] = ( granted_col_grant [j_tbp] & burst_chop ) | granted_burst_chop [j_tbp - 1];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [j_tbp] = ( granted_col_grant [j_tbp] & rmw_correct ) | granted_rmw_correct [j_tbp - 1];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [j_tbp] = ( granted_col_grant [j_tbp] & rmw_partial ) | granted_rmw_partial [j_tbp - 1];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Arbiter
//
// Arbitration Rules (Priority Command-Aging Arbiter):
//
// - If only one master is requesting, grant that master immediately ELSE
// - If two of more masters are requesting:
// - Grant the request with priority ELSE
// - Grant read request over write request ELSE
// - Grant oldest request
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common logic
//----------------------------------------------------------------------------------------------------
// Indicate OR of both grant signal
assign all_grant = row_grant | col_grant;
//----------------------------------------------------------------------------------------------------
// Priority Command-aging logic
//----------------------------------------------------------------------------------------------------
// ==========Command-Aging==========
//
// The following logic will check for the oldest requesting commands by cross checking between age dependencies & request
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies will have the following value:
// TBP0 age - 0000
// TBP1 age - 0001
// TBP2 age - 0011
// TBP3 age - 0111
// Let say TBP1 and TBP2 are requesting at the same time, we would want the command-aging logic to pick TBP1 instead of TBP2
// TBP2 have age dependencies on TBP1, this will cause oldest_req[2] signal to be set to '0'
// TBP1 have no age dependencies on TBP2, this will cause oldest_req[1] signal to be set to '1'
// So the oldest_req signal will have "0010"
//
// ==========Priority==========
//
// The following logic will have similar logic as command-aging logic, this logic will pick commands with priority bit set
// if there are more than 1 priority command, it will pick the oldest priority command
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies and priority bit will have the following value:
// TBP0 age - 0000 priority - 0
// TBP1 age - 0001 priority - 1
// TBP2 age - 0011 priority - 1
// TBP3 age - 0111 priority - 0
// Let say all TBPs are requesting at the same time, priority_req [1] will be set to '1' because it is the oldest priority command
// and the rest will be set to '0'
// If there is/are priority command/s, we need to select between those priority command
// if there is no priority command, we set int_priority to all '1'
// this will cause arbiter to select between all commands which will provide with similar result as non-priority command-aging arbiter
always @ (*)
begin
int_act_priority = {CFG_CTL_TBP_NUM{one}};
int_pch_priority = {CFG_CTL_TBP_NUM{one}};
if (CFG_DISABLE_PRIORITY == 1)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
if ((tbp_priority & col_req) == 0)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
int_col_priority = tbp_priority;
end
end
end
generate
begin
genvar k_tbp;
for (k_tbp = 0;k_tbp < CFG_CTL_TBP_NUM;k_tbp = k_tbp + 1)
begin : priority_request_per_tbp
wire [CFG_CTL_TBP_NUM - 1 : 0] current_age = tbp_age [(k_tbp + 1) * CFG_CTL_TBP_NUM - 1 : k_tbp * CFG_CTL_TBP_NUM];
reg pre_calculated_act_info;
reg pre_calculated_pch_info;
reg pre_calculated_rd_info;
reg pre_calculated_wr_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_act_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_pch_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_rd_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_wr_age_info;
if (CFG_REG_REQ)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_info <= 1'b0;
pre_calculated_pch_info <= 1'b0;
pre_calculated_rd_info <= 1'b0;
pre_calculated_wr_info <= 1'b0;
end
else
begin
pre_calculated_act_info <= int_act_priority [k_tbp];
pre_calculated_pch_info <= int_pch_priority [k_tbp];
pre_calculated_rd_info <= int_col_priority [k_tbp];
pre_calculated_wr_info <= int_col_priority [k_tbp];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_age_info <= 0;
pre_calculated_pch_age_info <= 0;
pre_calculated_rd_age_info <= 0;
pre_calculated_wr_age_info <= 0;
end
else
begin
pre_calculated_act_age_info <= current_age & int_act_priority;
pre_calculated_pch_age_info <= current_age & int_pch_priority;
pre_calculated_rd_age_info <= current_age & int_col_priority;
pre_calculated_wr_age_info <= current_age & int_col_priority;
end
end
end
else
begin
always @ (*)
begin
pre_calculated_act_info = int_act_priority [k_tbp];
pre_calculated_pch_info = int_pch_priority [k_tbp];
pre_calculated_rd_info = int_col_priority [k_tbp];
pre_calculated_wr_info = int_col_priority [k_tbp];
end
always @ (*)
begin
pre_calculated_act_age_info = current_age & int_act_priority;
pre_calculated_pch_age_info = current_age & int_pch_priority;
pre_calculated_rd_age_info = current_age & int_col_priority;
pre_calculated_wr_age_info = current_age & int_col_priority;
end
end
always @ (*)
begin
oldest_act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp] & ~|(pre_calculated_act_age_info & act_req & can_activate );
oldest_pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp] & ~|(pre_calculated_pch_age_info & pch_req & can_precharge);
oldest_rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp] & ~|(pre_calculated_rd_age_info & rd_req & can_read );
oldest_wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp] & ~|(pre_calculated_wr_age_info & wr_req & can_write );
end
always @ (*)
begin
act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp];
pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp];
rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp];
wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp];
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Arbiter logic
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
// Full rate arbiter
always @ (*)
begin
int_row_grant = 0;
int_col_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_row_grant = 1'b0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
end
else
begin
// Half and quarter rate arbiter
// Row arbiter
always @ (*)
begin
int_row_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_or_row_grant = 1'b0;
if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
// Column arbiter
always @ (*)
begin
int_col_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
end
end
end
endgenerate
generate
begin
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
row_grant <= 0;
col_grant <= 0;
act_grant <= 0;
pch_grant <= 0;
rd_grant <= 0;
wr_grant <= 0;
or_row_grant <= 0;
or_col_grant <= 0;
end
else
begin
row_grant <= int_row_grant;
col_grant <= int_col_grant;
act_grant <= int_act_grant;
pch_grant <= int_pch_grant;
rd_grant <= int_rd_grant;
wr_grant <= int_wr_grant;
or_row_grant <= int_or_row_grant;
or_col_grant <= int_or_col_grant;
end
end
always @ (*)
begin
log2_row_grant = log2(row_grant);
log2_col_grant = log2(col_grant);
log2_act_grant = log2(act_grant);
log2_pch_grant = log2(pch_grant);
log2_rd_grant = log2(rd_grant );
log2_wr_grant = log2(wr_grant );
end
end
else
begin
always @ (*)
begin
row_grant = int_row_grant;
col_grant = int_col_grant;
act_grant = int_act_grant;
pch_grant = int_pch_grant;
rd_grant = int_rd_grant;
wr_grant = int_wr_grant;
log2_row_grant = log2(int_row_grant);
log2_col_grant = log2(int_col_grant);
log2_act_grant = log2(int_act_grant);
log2_pch_grant = log2(int_pch_grant);
log2_rd_grant = log2(int_rd_grant );
log2_wr_grant = log2(int_wr_grant );
or_row_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
or_col_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Arbiter
//
//--------------------------------------------------------------------------------------------------------
function integer log2;
input [31 : 0] value;
integer i;
begin
log2 = 0;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_axi_st_converter #
( parameter
AXI_ID_WIDTH = 4,
AXI_ADDR_WIDTH = 32,
AXI_LEN_WIDTH = 4,
AXI_SIZE_WIDTH = 3,
AXI_BURST_WIDTH = 2,
AXI_LOCK_WIDTH = 2,
AXI_CACHE_WIDTH = 4,
AXI_PROT_WIDTH = 3,
AXI_DATA_WIDTH = 32,
AXI_RESP_WIDTH = 4,
ST_ADDR_WIDTH = 32,
ST_SIZE_WIDTH = 5,
ST_ID_WIDTH = 4,
ST_DATA_WIDTH = 32,
COMMAND_ARB_TYPE = "ROUND_ROBIN",
REGISTERED = 1
)
(
ctl_clk,
ctl_reset_n,
// AXI Interface
// Write address channel
awid,
awaddr,
awlen,
awsize,
awburst,
awlock,
awcache,
awprot,
awvalid,
awready,
// Write data channel
wid,
wdata,
wstrb,
wlast,
wvalid,
wready,
// Write response channel
bid,
bresp,
bvalid,
bready,
// Read address channel
arid,
araddr,
arlen,
arsize,
arburst,
arlock,
arcache,
arprot,
arvalid,
arready,
// Read data channel
rid,
rdata,
rresp,
rlast,
rvalid,
rready,
// Avalon ST Interface
// Command channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autoprecharge,
itf_cmd_multicast,
// Write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// Read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
input ctl_clk;
input ctl_reset_n;
// AXI Interface
// Write address channel
input [AXI_ID_WIDTH - 1 : 0] awid;
input [AXI_ADDR_WIDTH - 1 : 0] awaddr;
input [AXI_LEN_WIDTH - 1 : 0] awlen;
input [AXI_SIZE_WIDTH - 1 : 0] awsize;
input [AXI_BURST_WIDTH - 1 : 0] awburst;
input [AXI_LOCK_WIDTH - 1 : 0] awlock;
input [AXI_CACHE_WIDTH - 1 : 0] awcache;
input [AXI_PROT_WIDTH - 1 : 0] awprot;
input awvalid;
output awready;
// Write data channel
input [AXI_ID_WIDTH - 1 : 0] wid;
input [AXI_DATA_WIDTH - 1 : 0] wdata;
input [AXI_DATA_WIDTH / 8 - 1 : 0] wstrb;
input wlast;
input wvalid;
output wready;
// Write response channel
output [AXI_ID_WIDTH - 1 : 0] bid;
output [AXI_RESP_WIDTH - 1 : 0] bresp;
output bvalid;
input bready;
// Read address channel
input [AXI_ID_WIDTH - 1 : 0] arid;
input [AXI_ADDR_WIDTH - 1 : 0] araddr;
input [AXI_LEN_WIDTH - 1 : 0] arlen;
input [AXI_SIZE_WIDTH - 1 : 0] arsize;
input [AXI_BURST_WIDTH - 1 : 0] arburst;
input [AXI_LOCK_WIDTH - 1 : 0] arlock;
input [AXI_CACHE_WIDTH - 1 : 0] arcache;
input [AXI_PROT_WIDTH - 1 : 0] arprot;
input arvalid;
output arready;
// Read data channel
output [AXI_ID_WIDTH - 1 : 0] rid;
output [AXI_DATA_WIDTH - 1 : 0] rdata;
output [AXI_RESP_WIDTH - 1 : 0] rresp;
output rlast;
output rvalid;
input rready;
// Avalon ST Interface
// Command channel
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [ST_ADDR_WIDTH - 1 : 0] itf_cmd_address;
output [ST_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
output [ST_ID_WIDTH - 1 : 0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autoprecharge;
output itf_cmd_multicast;
// Write data channel
input itf_wr_data_ready;
output itf_wr_data_valid;
output [ST_DATA_WIDTH - 1 : 0] itf_wr_data;
output [ST_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [ST_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
output itf_rd_data_ready;
input itf_rd_data_valid;
input [ST_DATA_WIDTH - 1 : 0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [ST_ID_WIDTH - 1 : 0] itf_rd_data_id;
//--------------------------------------------------------------------------------------------------------
//
// [START] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
// AXI outputs
reg awready;
reg wready;
reg [AXI_ID_WIDTH - 1 : 0] bid;
reg [AXI_RESP_WIDTH - 1 : 0] bresp;
reg bvalid;
reg arready;
reg [AXI_ID_WIDTH - 1 : 0] rid;
reg [AXI_DATA_WIDTH - 1 : 0] rdata;
reg [AXI_RESP_WIDTH - 1 : 0] rresp;
reg rlast;
reg rvalid;
// ST outputs
reg itf_cmd_valid;
reg itf_cmd;
reg [ST_ADDR_WIDTH - 1 : 0] itf_cmd_address;
reg [ST_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
reg [ST_ID_WIDTH - 1 : 0] itf_cmd_id;
reg itf_cmd_priority;
reg itf_cmd_autoprecharge;
reg itf_cmd_multicast;
reg itf_wr_data_valid;
reg [ST_DATA_WIDTH - 1 : 0] itf_wr_data;
reg [ST_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
reg itf_wr_data_begin;
reg itf_wr_data_last;
reg [ST_ID_WIDTH - 1 : 0] itf_wr_data_id;
reg itf_rd_data_ready;
wire one = 1'b1;
wire zero = 1'b0;
// Command channel
localparam WORD_ADDR_OFFSET = log2(AXI_DATA_WIDTH / 8);
localparam NATIVE_AXI_SIZE = log2(AXI_DATA_WIDTH) - 3;
integer i;
wire [AXI_ADDR_WIDTH - 1 : 0] byte_rd_addr;
wire [AXI_ADDR_WIDTH - 1 : 0] byte_wr_addr;
wire rd_req;
wire wr_req;
wire [1 : 0] cmd_req;
wire rd_grant;
wire wr_grant;
wire [ST_ID_WIDTH - 1 : 0] rd_id;
wire [ST_ID_WIDTH - 1 : 0] wr_id;
reg [AXI_ID_WIDTH - 1 : 0] int_awid;
reg [AXI_ADDR_WIDTH - 1 : 0] int_awaddr;
reg [AXI_LEN_WIDTH - 1 : 0] int_awlen;
reg [AXI_SIZE_WIDTH - 1 : 0] int_awsize;
reg [AXI_BURST_WIDTH - 1 : 0] int_awburst;
reg [AXI_LOCK_WIDTH - 1 : 0] int_awlock;
reg [AXI_CACHE_WIDTH - 1 : 0] int_awcache;
reg [AXI_PROT_WIDTH - 1 : 0] int_awprot;
reg int_awvalid;
reg [AXI_ID_WIDTH - 1 : 0] int_arid;
reg [AXI_ADDR_WIDTH - 1 : 0] int_araddr;
reg [AXI_LEN_WIDTH - 1 : 0] int_arlen;
reg [AXI_SIZE_WIDTH - 1 : 0] int_arsize;
reg [AXI_BURST_WIDTH - 1 : 0] int_arburst;
reg [AXI_LOCK_WIDTH - 1 : 0] int_arlock;
reg [AXI_CACHE_WIDTH - 1 : 0] int_arcache;
reg [AXI_PROT_WIDTH - 1 : 0] int_arprot;
reg int_arvalid;
reg int_cmd_valid;
reg int_cmd;
reg [ST_ADDR_WIDTH - 1 : 0] int_cmd_address;
reg [ST_SIZE_WIDTH - 1 : 0] int_cmd_burstlen;
reg [ST_ID_WIDTH - 1 : 0] int_cmd_id;
reg int_cmd_priority;
reg int_cmd_autoprecharge;
reg int_cmd_multicast;
reg int_awready;
reg int_arready;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] rd_size;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] wr_size;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] current_size;
reg [2 ** AXI_SIZE_WIDTH - 1 : 0] int_size;
reg [AXI_ADDR_WIDTH - 1 : 0] byte_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] byte_addr_counter;
reg [ST_ADDR_WIDTH - 1 : 0] registered_word_addr;
reg [ST_ADDR_WIDTH - 1 : 0] word_rd_addr;
reg [ST_ADDR_WIDTH - 1 : 0] word_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] int_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] int_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_rd_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] boundary_byte_wr_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] int_aligned_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_aligned_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_rd_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_wr_addr_mask;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_rd_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] int_boundary_byte_wr_addr_increment;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] aligned_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] lower_wrap_boundary_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] upper_wrap_boundary_byte_rd_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] lower_wrap_boundary_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] upper_wrap_boundary_byte_wr_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] lower_wrap_boundary_byte_addr;
reg [AXI_ADDR_WIDTH - 1 : 0] upper_wrap_boundary_byte_addr;
reg upper_boundary_reached;
reg [AXI_BURST_WIDTH - 1 : 0] burst_type;
reg doing_write;
reg [1 : 0] cmd_grant;
reg [1 : 0] prev_cmd_grant;
reg split_axi_cmd;
reg doing_split;
reg [ST_SIZE_WIDTH - 1 : 0] split_counter;
reg [ST_SIZE_WIDTH - 1 : 0] rd_burstlen;
reg [ST_SIZE_WIDTH - 1 : 0] wr_burstlen;
reg int_grant;
reg int_rd_grant;
reg int_wr_grant;
reg int_doing_split;
reg [ST_ID_WIDTH - 1 : 0] registered_id;
// Write data channel
reg int_wr_data_valid;
reg [ST_DATA_WIDTH - 1 : 0] int_wr_data;
reg [ST_DATA_WIDTH / 8 - 1 : 0] int_wr_data_byte_en;
reg int_wr_data_begin;
reg int_wr_data_last;
reg [ST_ID_WIDTH - 1 : 0] int_wr_data_id;
reg write_data_begin_n;
// Write response channel
localparam WR_CMD_FIFO_DATA_WIDTH = AXI_ID_WIDTH;
localparam WR_CMD_FIFO_ADDR_WIDTH = 5; // expected to be able to hold 32 in-flight command information
localparam WR_CMD_FIFO_DEPTH = 2 ** WR_CMD_FIFO_ADDR_WIDTH;
localparam WR_DATA_FIFO_DATA_WIDTH = AXI_ID_WIDTH;
localparam WR_DATA_FIFO_ADDR_WIDTH = 5; // expected to be able to hold 32 in-flight command information
localparam WR_DATA_FIFO_DEPTH = 2 ** WR_DATA_FIFO_ADDR_WIDTH;
wire wr_cmd_fifo_write;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_cmd_fifo_write_data;
wire wr_cmd_fifo_read;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_cmd_fifo_read_data;
wire wr_cmd_fifo_read_data_valid;
wire wr_cmd_fifo_empty;
wire wr_cmd_fifo_almost_full;
wire wr_data_fifo_write;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_data_fifo_write_data;
wire wr_data_fifo_read;
wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_data_fifo_read_data;
wire wr_data_fifo_read_data_valid;
wire wr_data_fifo_empty;
wire wr_data_fifo_almost_full;
reg wr_cmd_fifo_ready;
reg wr_data_fifo_ready;
reg id_matched;
reg [AXI_ID_WIDTH - 1 : 0] int_bid;
reg [AXI_RESP_WIDTH - 1 : 0] int_bresp;
reg int_bvalid;
// Read data channel
localparam RD_CMD_FIFO_DATA_WIDTH = AXI_LEN_WIDTH + 1;
localparam RD_CMD_FIFO_ADDR_WIDTH = 5; // expected to be able to hold 32 in-flight command information
localparam RD_CMD_FIFO_DEPTH = 2 ** RD_CMD_FIFO_ADDR_WIDTH;
wire rd_cmd_fifo_write;
wire [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] rd_cmd_fifo_write_data;
wire rd_cmd_fifo_read;
wire [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] rd_cmd_fifo_read_data;
wire rd_cmd_fifo_read_data_valid;
wire rd_cmd_fifo_empty;
wire rd_cmd_fifo_almost_full;
reg rd_cmd_fifo_ready;
reg [AXI_ID_WIDTH - 1 : 0] int_rid;
reg [AXI_DATA_WIDTH - 1 : 0] int_rdata;
reg [AXI_RESP_WIDTH - 1 : 0] int_rresp;
reg int_rlast;
reg int_rvalid;
reg int_rd_data_ready;
reg [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] read_data_counter;
reg read_data_last;
//--------------------------------------------------------------------------------------------------------
//
// [END] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Command Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------
// AXI inputs
//--------------------------------------------------------------------------
always @ (*)
begin
int_awid = awid;
int_awaddr = awaddr;
int_awlen = awlen;
int_awsize = awsize;
int_awburst = awburst;
int_awlock = awlock;
int_awcache = awcache;
int_awprot = awprot;
int_awvalid = awvalid;
int_arid = arid;
int_araddr = araddr;
int_arlen = arlen;
int_arsize = arsize;
int_arburst = arburst;
int_arlock = arlock;
int_arcache = arcache;
int_arprot = arprot;
int_arvalid = arvalid;
end
//--------------------------------------------------------------------------
// Size related logics
//--------------------------------------------------------------------------
always @ (*)
begin
rd_size = (2 ** int_arsize);
wr_size = (2 ** int_awsize);
end
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_size <= 0;
end
else
begin
if (rd_grant)
begin
int_size <= rd_size;
end
else if (wr_grant)
begin
int_size <= wr_size;
end
end
end
end
else
begin
always @ (*)
begin
if (rd_grant)
begin
int_size = rd_size;
end
else if (wr_grant)
begin
int_size = wr_size;
end
else
begin
int_size = 0;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
current_size <= 0;
end
else
begin
if (rd_grant)
begin
current_size <= rd_size;
end
else if (wr_grant)
begin
current_size <= wr_size;
end
end
end
//--------------------------------------------------------------------------
// Address related logics
//--------------------------------------------------------------------------
assign byte_rd_addr = int_araddr;
assign byte_wr_addr = int_awaddr;
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_byte_rd_addr <= 0;
int_byte_wr_addr <= 0;
end
else
begin
if (itf_cmd_ready)
begin
int_byte_rd_addr <= byte_rd_addr;
int_byte_wr_addr <= byte_wr_addr;
end
end
end
end
else
begin
always @ (*)
begin
int_byte_rd_addr = byte_rd_addr;
int_byte_wr_addr = byte_wr_addr;
end
end
end
endgenerate
// Obtain address mask for aligned address
always @ (*)
begin
aligned_byte_rd_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
aligned_byte_wr_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
for (i = 0;i < (2 ** AXI_SIZE_WIDTH);i = i + 1'b1)
begin
if (int_arsize > i)
begin
aligned_byte_rd_addr_mask [i] = 1'b0;
end
if (int_awsize > i)
begin
aligned_byte_wr_addr_mask [i] = 1'b0;
end
end
end
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_aligned_byte_rd_addr_mask <= 0;
int_aligned_byte_wr_addr_mask <= 0;
end
else
begin
if (itf_cmd_ready)
begin
int_aligned_byte_rd_addr_mask <= aligned_byte_rd_addr_mask;
int_aligned_byte_wr_addr_mask <= aligned_byte_wr_addr_mask;
end
end
end
end
else
begin
always @ (*)
begin
int_aligned_byte_rd_addr_mask = aligned_byte_rd_addr_mask;
int_aligned_byte_wr_addr_mask = aligned_byte_wr_addr_mask;
end
end
end
endgenerate
// Obtain aligned address
always @ (*)
begin
aligned_byte_rd_addr = (int_byte_rd_addr & int_aligned_byte_rd_addr_mask);
aligned_byte_wr_addr = (int_byte_wr_addr & int_aligned_byte_wr_addr_mask);
end
always @ (*)
begin
if (int_rd_grant)
begin
aligned_byte_addr = aligned_byte_rd_addr;
end
else if (int_wr_grant)
begin
aligned_byte_addr = aligned_byte_wr_addr;
end
else
begin
aligned_byte_addr = 0;
end
end
// Obtain boundary address mask for wrapping burst
always @ (*)
begin
boundary_byte_rd_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
boundary_byte_wr_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
for (i = 0;i < ((2 ** AXI_SIZE_WIDTH) + 4);i = i + 1'b1) // extend by another 4 because max length for wrapping burst is 16
begin
if ((int_arsize + log2_minus_one(int_arlen[3:0])) > i) // constraint burstlen to 4 bits because max length for wrapping burst is 16
begin
boundary_byte_rd_addr_mask [i] = 1'b0;
end
if ((int_awsize + log2_minus_one(int_awlen[3:0])) > i) // constraint burstlen to 4 bits because max length for wrapping burst is 16
begin
boundary_byte_wr_addr_mask [i] = 1'b0;
end
end
end
// Obtain boundary increment value for wrapping burst
always @ (*)
begin
boundary_byte_rd_addr_increment = aligned_byte_rd_addr_mask & ~boundary_byte_rd_addr_mask;
boundary_byte_wr_addr_increment = aligned_byte_wr_addr_mask & ~boundary_byte_wr_addr_mask;
end
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_boundary_byte_rd_addr_mask <= 0;
int_boundary_byte_wr_addr_mask <= 0;
int_boundary_byte_rd_addr_increment <= 0;
int_boundary_byte_wr_addr_increment <= 0;
end
else
begin
if (itf_cmd_ready)
begin
int_boundary_byte_rd_addr_mask <= boundary_byte_rd_addr_mask;
int_boundary_byte_wr_addr_mask <= boundary_byte_wr_addr_mask;
int_boundary_byte_rd_addr_increment <= boundary_byte_rd_addr_increment;
int_boundary_byte_wr_addr_increment <= boundary_byte_wr_addr_increment;
end
end
end
end
else
begin
always @ (*)
begin
int_boundary_byte_rd_addr_mask = boundary_byte_rd_addr_mask;
int_boundary_byte_wr_addr_mask = boundary_byte_wr_addr_mask;
int_boundary_byte_rd_addr_increment = boundary_byte_rd_addr_increment;
int_boundary_byte_wr_addr_increment = boundary_byte_wr_addr_increment;
end
end
end
endgenerate
// Obtain upper and lower boundary of wrapping burst
always @ (*)
begin
lower_wrap_boundary_byte_rd_addr = (int_byte_rd_addr & int_boundary_byte_rd_addr_mask);
lower_wrap_boundary_byte_wr_addr = (int_byte_wr_addr & int_boundary_byte_wr_addr_mask);
upper_wrap_boundary_byte_rd_addr = (int_byte_rd_addr & int_boundary_byte_rd_addr_mask) + int_boundary_byte_rd_addr_increment;
upper_wrap_boundary_byte_wr_addr = (int_byte_wr_addr & int_boundary_byte_wr_addr_mask) + int_boundary_byte_wr_addr_increment;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
lower_wrap_boundary_byte_addr <= 0;
upper_wrap_boundary_byte_addr <= 0;
end
else
begin
if (int_wr_grant)
begin
lower_wrap_boundary_byte_addr <= lower_wrap_boundary_byte_wr_addr;
upper_wrap_boundary_byte_addr <= upper_wrap_boundary_byte_wr_addr;
end
else if (int_rd_grant)
begin
lower_wrap_boundary_byte_addr <= lower_wrap_boundary_byte_rd_addr;
upper_wrap_boundary_byte_addr <= upper_wrap_boundary_byte_rd_addr;
end
end
end
// Byte address counter, to count up for a AXI command with len larger than 1
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
byte_addr_counter <= 0;
end
else
begin
if (int_grant)
begin
byte_addr_counter <= aligned_byte_addr + int_size;
end
else if (itf_cmd_ready)
begin
byte_addr_counter <= byte_addr + current_size;
end
end
end
// Determine whether current burst reached upper wrap boundary
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
upper_boundary_reached <= 1'b0;
end
else
begin
if (int_rd_grant)
begin
if (aligned_byte_rd_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_rd_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
begin
upper_boundary_reached <= 1'b1;
end
else
begin
upper_boundary_reached <= 1'b0;
end
end
else if (int_wr_grant)
begin
if (aligned_byte_wr_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_wr_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
begin
upper_boundary_reached <= 1'b1;
end
else
begin
upper_boundary_reached <= 1'b0;
end
end
else if (itf_cmd_ready)
begin
if (byte_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
begin
upper_boundary_reached <= 1'b1;
end
else
begin
upper_boundary_reached <= 1'b0;
end
end
end
end
// Byte address for wrapping burst command
always @ (*)
begin
if (burst_type == 2'd2 && upper_boundary_reached)
begin
byte_addr = lower_wrap_boundary_byte_addr;
end
else
begin
byte_addr = byte_addr_counter;
end
end
// Byte to word address conversion logic
always @ (*)
begin
word_rd_addr = 0;
word_wr_addr = 0;
registered_word_addr = 0;
word_rd_addr = int_byte_rd_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
word_wr_addr = int_byte_wr_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
registered_word_addr = byte_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
end
// Command address to Avalon ST interface
always @ (*)
begin
if (int_wr_grant)
begin
int_cmd_address = word_wr_addr;
end
else if (int_rd_grant)
begin
int_cmd_address = word_rd_addr;
end
else if (int_doing_split)
begin
int_cmd_address = registered_word_addr;
end
else
begin
int_cmd_address = 0;
end
end
//--------------------------------------------------------------------------
// Command related logics
//--------------------------------------------------------------------------
assign rd_req = int_arvalid & int_arready;
assign wr_req = int_awvalid & int_awready;
assign cmd_req = {rd_req, wr_req};
assign {rd_grant, wr_grant} = cmd_grant;
// Command arbitration logic
generate
begin
if (COMMAND_ARB_TYPE == "ROUND_ROBIN")
begin
always @ (*)
begin
if (&cmd_req) // both command requesting at the same time
begin
cmd_grant = prev_cmd_grant;
end
else
begin
cmd_grant = cmd_req;
end
end
end
else if (COMMAND_ARB_TYPE == "WRITE_PRIORITY")
begin
always @ (*)
begin
if (&cmd_req) // both command requesting at the same time
begin
cmd_grant = 2'b01; // make sure we always grant write request
end
else
begin
cmd_grant = cmd_req;
end
end
end
else if (COMMAND_ARB_TYPE == "READ_PRIORITY")
begin
always @ (*)
begin
if (&cmd_req) // both command requesting at the same time
begin
cmd_grant = 2'b10; // make sure we always grant read request
end
else
begin
cmd_grant = cmd_req;
end
end
end
end
endgenerate
// Previous command grant
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
prev_cmd_grant <= 2'b01; // default round robin priority
end
else
begin
if (|cmd_grant)
begin
prev_cmd_grant <= ~cmd_grant;
end
end
end
// Grant signal for registered output
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_grant <= 1'b0;
int_wr_grant <= 1'b0;
int_rd_grant <= 1'b0;
int_doing_split <= 1'b0;
end
else
begin
if (itf_cmd_ready)
begin
int_grant <= wr_grant | rd_grant;
int_wr_grant <= wr_grant;
int_rd_grant <= rd_grant;
int_doing_split <= doing_split;
end
end
end
end
else
begin
always @ (*)
begin
int_grant = wr_grant | rd_grant;
int_wr_grant = wr_grant;
int_rd_grant = rd_grant;
int_doing_split = doing_split;
end
end
end
endgenerate
// Doing write logic, indicate what we did last
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write <= 1'b0;
end
else
begin
if (wr_grant)
begin
doing_write <= 1'b1;
end
else if (rd_grant)
begin
doing_write <= 1'b0;
end
end
end
// Command & valid to Avalon ST interface
always @ (*)
begin
if (wr_grant)
begin
int_cmd = 1'b1; // Set command to '1' when there is a write, else '0'
int_cmd_valid = 1'b1;
end
else if (rd_grant)
begin
int_cmd = 1'b0; // Set command to '1' when there is a write, else '0'
int_cmd_valid = 1'b1;
end
else if (doing_split)
begin
int_cmd = doing_write;
int_cmd_valid = 1'b1;
end
else
begin
int_cmd = 1'b0;
int_cmd_valid = 1'b0;
end
end
//--------------------------------------------------------------------------
// Burst related logics
//--------------------------------------------------------------------------
// Splitting logic
// we will split AXI command into multiple smaller Avalon ST commands if size if not equal to data width
// or when burst type is set to WRAP
always @ (*)
begin
if (wr_grant)
begin
split_axi_cmd = ((int_awsize != NATIVE_AXI_SIZE || int_awburst == 2) && int_awlen != 0) ? 1'b1 : 1'b0; // don't need to split when size is '1'
end
else if (rd_grant)
begin
split_axi_cmd = ((int_arsize != NATIVE_AXI_SIZE || int_arburst == 2) && int_arlen != 0) ? 1'b1 : 1'b0; // don't need to split when size is '1'
end
else
begin
split_axi_cmd = 1'b0;
end
end
// Splitting logic
// to keep track of how many commands to split
// also to tell other logic that it's currently doing split now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_counter <= 0;
doing_split <= 1'b0;
end
else
begin
if (wr_grant)
begin
split_counter <= int_awlen;
if (split_axi_cmd)
begin
doing_split <= 1'b1;
end
else
begin
doing_split <= 1'b0;
end
end
else if (rd_grant)
begin
split_counter <= int_arlen;
if (split_axi_cmd)
begin
doing_split <= 1'b1;
end
else
begin
doing_split <= 1'b0;
end
end
else if (itf_cmd_ready)
begin
if (split_counter != {ST_SIZE_WIDTH{1'b0}})
begin
split_counter <= split_counter - 1'b1;
end
if (split_counter == 1'b1)
begin
doing_split <= 1'b0;
end
end
end
end
// Convert AXI len to Avalon ST burst size
always @ (*)
begin
rd_burstlen = int_arlen + 1'b1;
wr_burstlen = int_awlen + 1'b1;
end
// Burst size to Avalon ST interface
always @ (*)
begin
if (wr_grant)
begin
int_cmd_burstlen = (split_axi_cmd) ? 1'b1: wr_burstlen;
end
else if (rd_grant)
begin
int_cmd_burstlen = (split_axi_cmd) ? 1'b1: rd_burstlen;
end
else if (doing_split)
begin
int_cmd_burstlen = 1'b1; // Size will always equal to '1' during spliting process
end
else
begin
int_cmd_burstlen = 0;
end
end
// Burst type
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_type <= 0;
end
else
begin
if (wr_grant)
begin
burst_type <= int_awburst;
end
else if (rd_grant)
begin
burst_type <= int_arburst;
end
end
end
//--------------------------------------------------------------------------
// ID related logics
//--------------------------------------------------------------------------
assign rd_id = int_arid;
assign wr_id = int_awid;
// Registered ID, keep track of previous ID
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
registered_id <= 0;
end
else
begin
if (wr_grant)
begin
registered_id <= wr_id;
end
else if (rd_grant)
begin
registered_id <= rd_id;
end
end
end
// Transfer AXI ID to Avalon ST interface
always @ (*)
begin
if (wr_grant)
begin
int_cmd_id = wr_id;
end
else if (rd_grant)
begin
int_cmd_id = rd_id;
end
else if (doing_split)
begin
int_cmd_id = registered_id;
end
else
begin
int_cmd_id = 0;
end
end
//--------------------------------------------------------------------------
// Others
//--------------------------------------------------------------------------
// Setting inband signals to '0'
always @ (*)
begin
int_cmd_priority = zero;
int_cmd_autoprecharge = zero;
int_cmd_multicast = zero;
end
//--------------------------------------------------------------------------
// Outputs
//--------------------------------------------------------------------------
// AXI command output assignment
always @ (*)
begin
// disable ready signal during split or when FIFO is full
int_awready = itf_cmd_ready & ~doing_split & wr_cmd_fifo_ready;
int_arready = itf_cmd_ready & ~doing_split & rd_cmd_fifo_ready;
end
always @ (*)
begin
// disable ready signal when granting other channel
awready = int_awready & ~rd_grant;
arready = int_arready & ~wr_grant;
end
// Avalon ST command output assignment
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
itf_cmd_valid <= 0;
itf_cmd <= 0;
itf_cmd_burstlen <= 0;
itf_cmd_id <= 0;
itf_cmd_priority <= 0;
itf_cmd_autoprecharge <= 0;
itf_cmd_multicast <= 0;
end
else
begin
if (itf_cmd_ready)
begin
itf_cmd_valid <= int_cmd_valid;
itf_cmd <= int_cmd;
itf_cmd_burstlen <= int_cmd_burstlen;
itf_cmd_id <= int_cmd_id;
itf_cmd_priority <= int_cmd_priority;
itf_cmd_autoprecharge <= int_cmd_autoprecharge;
itf_cmd_multicast <= int_cmd_multicast;
end
end
end
always @ (*)
begin
itf_cmd_address = int_cmd_address;
end
end
else
begin
always @ (*)
begin
itf_cmd_valid = int_cmd_valid;
itf_cmd = int_cmd;
itf_cmd_address = int_cmd_address;
itf_cmd_burstlen = int_cmd_burstlen;
itf_cmd_id = int_cmd_id;
itf_cmd_priority = int_cmd_priority;
itf_cmd_autoprecharge = int_cmd_autoprecharge;
itf_cmd_multicast = int_cmd_multicast;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Command Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Write Data Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Write data begin logic
//--------------------------------------------------------------------------
// Determine write data begin based on write data last information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_data_begin_n <= 1'b0;
end
else
begin
if (wlast & wready)
begin
write_data_begin_n <= 1'b0;
end
else if (wvalid & wready) // received a write data packet
begin
write_data_begin_n <= 1'b1;
end
end
end
// Write data begin logic
always @ (*)
begin
if (wvalid & wready)
begin
int_wr_data_begin = ~write_data_begin_n;
end
else
begin
int_wr_data_begin = 1'b0;
end
end
//--------------------------------------------------------------------------
// Others
//--------------------------------------------------------------------------
always @ (*)
begin
int_wr_data_valid = wvalid & wready;
int_wr_data = wdata;
int_wr_data_byte_en = wstrb;
int_wr_data_last = wlast & wready;
int_wr_data_id = wid;
end
//--------------------------------------------------------------------------
// Outputs
//--------------------------------------------------------------------------
// AXI write data channel output assignment
always @ (*)
begin
wready = itf_wr_data_ready & wr_data_fifo_ready;
end
// Avalon ST data chanel output assignment
generate
begin
if (REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
itf_wr_data_valid <= 0;
itf_wr_data <= 0;
itf_wr_data_byte_en <= 0;
itf_wr_data_begin <= 0;
itf_wr_data_last <= 0;
itf_wr_data_id <= 0;
end
else
begin
if (itf_wr_data_ready)
begin
itf_wr_data_valid <= int_wr_data_valid;
itf_wr_data <= int_wr_data;
itf_wr_data_byte_en <= int_wr_data_byte_en;
itf_wr_data_begin <= int_wr_data_begin;
itf_wr_data_last <= int_wr_data_last;
itf_wr_data_id <= int_wr_data_id;
end
end
end
end
else
begin
always @ (*)
begin
itf_wr_data_valid = int_wr_data_valid;
itf_wr_data = int_wr_data;
itf_wr_data_byte_en = int_wr_data_byte_en;
itf_wr_data_begin = int_wr_data_begin;
itf_wr_data_last = int_wr_data_last;
itf_wr_data_id = int_wr_data_id;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Write Data Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Write Response Channel
//
//--------------------------------------------------------------------------------------------------------
assign wr_cmd_fifo_write = wr_grant; // write into FIFO after receiving write request
assign wr_cmd_fifo_write_data = wr_id;
assign wr_cmd_fifo_read = id_matched; // pop from FIFO when ID from both FIFO is matching
assign wr_cmd_fifo_read_data_valid = ~wr_cmd_fifo_empty;
assign wr_data_fifo_write = int_wr_data_last; // write into FIFO after receiving last data
assign wr_data_fifo_write_data = int_wr_data_id;
assign wr_data_fifo_read = id_matched; // pop from FIFO when ID from both FIFO is matching
assign wr_data_fifo_read_data_valid = ~wr_data_fifo_empty;
// FIFO instantiation to store write command information
scfifo # (
.add_ram_output_register ("ON" ),
.intended_device_family ("Stratix IV" ),
.lpm_numwords (WR_CMD_FIFO_DEPTH ),
.lpm_showahead ("ON" ),
.lpm_type ("scfifo" ),
.lpm_width (WR_CMD_FIFO_DATA_WIDTH ),
.lpm_widthu (WR_CMD_FIFO_ADDR_WIDTH ),
.overflow_checking ("OFF" ),
.underflow_checking ("OFF" ),
.use_eab ("ON" ),
.almost_full_value (WR_CMD_FIFO_DEPTH - 1 )
) wr_cmd_fifo (
.aclr (~ctl_reset_n ),
.clock (ctl_clk ),
.data (wr_cmd_fifo_write_data ),
.rdreq (wr_cmd_fifo_read ),
.wrreq (wr_cmd_fifo_write ),
.empty (wr_cmd_fifo_empty ),
.full ( ),
.q (wr_cmd_fifo_read_data ),
.almost_empty ( ),
.almost_full (wr_cmd_fifo_almost_full ),
.sclr (zero ),
.usedw ( )
);
// FIFO instantiation to store write data information
scfifo # (
.add_ram_output_register ("ON" ),
.intended_device_family ("Stratix IV" ),
.lpm_numwords (WR_DATA_FIFO_DEPTH ),
.lpm_showahead ("ON" ),
.lpm_type ("scfifo" ),
.lpm_width (WR_DATA_FIFO_DATA_WIDTH ),
.lpm_widthu (WR_DATA_FIFO_ADDR_WIDTH ),
.overflow_checking ("OFF" ),
.underflow_checking ("OFF" ),
.use_eab ("ON" ),
.almost_full_value (WR_DATA_FIFO_DEPTH - 1 )
) wr_data_fifo (
.aclr (~ctl_reset_n ),
.clock (ctl_clk ),
.data (wr_data_fifo_write_data ),
.rdreq (wr_data_fifo_read ),
.wrreq (wr_data_fifo_write ),
.empty (wr_data_fifo_empty ),
.full ( ),
.q (wr_data_fifo_read_data ),
.almost_empty ( ),
.almost_full (wr_data_fifo_almost_full ),
.sclr (zero ),
.usedw ( )
);
// FIFO full logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wr_cmd_fifo_ready <= 1'b0;
wr_data_fifo_ready <= 1'b0;
end
else
begin
// Set to '1' when either FIFO almost full, to prevent converter from accepting new commands/data
wr_cmd_fifo_ready <= ~wr_cmd_fifo_almost_full;
wr_data_fifo_ready <= ~wr_data_fifo_almost_full;
end
end
// ID macthing logic
always @ (*)
begin
if (wr_cmd_fifo_read_data == wr_data_fifo_read_data && wr_cmd_fifo_read_data_valid && wr_data_fifo_read_data_valid)
begin
id_matched = 1'b1;
end
else
begin
id_matched = 1'b0;
end
end
// Response logic
// logic will keep valid high till response channel is ready to accept the command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_bid <= 0;
int_bresp <= 0;
int_bvalid <= 1'b0;
end
else
begin
if (id_matched)
begin
int_bid <= wr_cmd_fifo_read_data;
int_bresp <= 0;
int_bvalid <= 1'b1;
end
else if (bready)
begin
int_bid <= 0;
int_bresp <= 0;
int_bvalid <= 0;
end
end
end
// AXI write response channel output assignment
always @ (*)
begin
bid = int_bid;
bresp = int_bresp;
bvalid = int_bvalid;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Write Response Channel
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read Data Channel
//
//--------------------------------------------------------------------------------------------------------
assign rd_cmd_fifo_write = rd_grant; // write into FIFO after receiving read request
assign rd_cmd_fifo_write_data = rd_burstlen;
assign rd_cmd_fifo_read = read_data_last; // pop from FIFO after sending last read data
assign rd_cmd_fifo_read_data_valid = ~rd_cmd_fifo_empty;
// FIFO to store read command information
scfifo # (
.add_ram_output_register ("ON" ),
.intended_device_family ("Stratix IV" ),
.lpm_numwords (RD_CMD_FIFO_DEPTH ),
.lpm_showahead ("ON" ),
.lpm_type ("scfifo" ),
.lpm_width (RD_CMD_FIFO_DATA_WIDTH ),
.lpm_widthu (RD_CMD_FIFO_ADDR_WIDTH ),
.overflow_checking ("OFF" ),
.underflow_checking ("OFF" ),
.use_eab ("ON" ),
.almost_full_value (RD_CMD_FIFO_DEPTH - 1 )
) rd_cmd_fifo (
.aclr (~ctl_reset_n ),
.clock (ctl_clk ),
.data (rd_cmd_fifo_write_data ),
.rdreq (rd_cmd_fifo_read ),
.wrreq (rd_cmd_fifo_write ),
.empty (rd_cmd_fifo_empty ),
.full ( ),
.q (rd_cmd_fifo_read_data ),
.almost_empty ( ),
.almost_full (rd_cmd_fifo_almost_full ),
.sclr (zero ),
.usedw ( )
);
// FIFO full logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_cmd_fifo_ready <= 1'b0;
end
else
begin
// Set to '1' when either FIFO almost full, to prevent converter from accepting new commands/data
rd_cmd_fifo_ready <= ~rd_cmd_fifo_almost_full;
end
end
// Read data counter
// keep tracks of read data count, to be used in read data last logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_data_counter <= 1;
end
else
begin
if (int_rvalid && int_rd_data_ready && read_data_last) // reset counter value after reaching last burst
begin
read_data_counter <= 1;
end
else if (int_rvalid && int_rd_data_ready) // count up when there is a read data begin transfered
begin
read_data_counter <= read_data_counter + 1'b1;
end
end
end
// Read data last logic
// indicate which read data is the last burst
always @ (*)
begin
if (int_rvalid && int_rd_data_ready && read_data_counter == rd_cmd_fifo_read_data) // set last to '1' when counter matches FIFO output
begin
read_data_last = 1'b1;
end
else
begin
read_data_last = 1'b0;
end
end
// Others
always @ (*)
begin
int_rid = itf_rd_data_id;
int_rdata = itf_rd_data;
int_rresp = {itf_rd_data_error, 1'b0}; // If there is an error, it will indicate SLVERR on AXI interface
int_rlast = read_data_last;
int_rvalid = itf_rd_data_valid;
int_rd_data_ready = rready;
end
// AXI read data channel output assignment
always @ (*)
begin
rid = int_rid;
rdata = int_rdata;
rresp = int_rresp;
rlast = int_rlast;
rvalid = int_rvalid;
end
// Avalon ST read data channel output assignment
always @ (*)
begin
itf_rd_data_ready = int_rd_data_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Read Data Channel
//
//--------------------------------------------------------------------------------------------------------
function integer log2;
input [31 : 0] value;
integer i;
begin
log2 = 0;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
function integer log2_minus_one;
input [31 : 0] value;
integer i;
begin
log2_minus_one = 1;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2_minus_one = i + 1;
end
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_gen #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_TCCD = 4,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_BURST_GEN_OUTPUT_REG = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_type,
cfg_burst_length,
cfg_tccd,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// Arbiter Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size,
// AFI Interface
bg_do_write_combi,
bg_do_read_combi,
bg_do_burst_chop_combi,
bg_do_burst_terminate_combi,
bg_do_activate_combi,
bg_do_precharge_combi,
bg_to_chip_combi,
bg_effective_size_combi,
bg_interrupt_ready_combi,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_zq_cal,
bg_do_lmr,
bg_to_chipsel,
bg_to_chip,
bg_to_bank,
bg_to_row,
bg_to_col,
bg_doing_write,
bg_doing_read,
bg_rdwr_data_valid,
bg_interrupt_ready,
bg_localid,
bg_dataid,
bg_size,
bg_effective_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// Arbiter Interface
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
input [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
input [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// AFI Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
output bg_interrupt_ready_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
output bg_doing_write;
output bg_doing_read;
output bg_rdwr_data_valid;
output bg_interrupt_ready;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// AFI Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
reg bg_doing_write;
reg bg_doing_read;
reg bg_rdwr_data_valid;
reg bg_interrupt_ready;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
// Burst generation logic
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
reg [2 : 0] int_col_address;
reg [2 : 0] int_address_left;
reg int_do_row_req;
reg int_do_col_req;
reg int_do_rd_req;
reg int_do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_partial;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
reg [2 : 0] col_address;
reg [2 : 0] address_left;
reg do_row_req;
reg do_col_req;
reg do_rd_req;
reg do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_partial;
reg [3 : 0] max_local_burst_size;
reg [3 : 0] max_local_burst_size_divide_2;
reg [3 : 0] max_local_burst_size_minus_2;
reg [3 : 0] max_local_burst_size_divide_2_and_minus_2;
reg [3 : 0] burst_left;
reg current_valid;
reg delayed_valid;
reg combined_valid;
reg [3 : 0] max_burst_left;
reg delayed_doing;
reg last_is_write;
reg last_is_read;
// Burst interrupt logic
reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
reg int_allow_interrupt;
reg int_interrupt_enable_ready;
reg int_interrupt_disable_ready;
reg int_interrupt_gate;
// Burst terminate logic
reg int_allow_terminate;
reg int_do_burst_terminate;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_do_req;
reg doing_burst_terminate;
reg terminate_doing;
// RMW Info
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
// Data ID
reg [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
// Column address
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
// Common
wire zero = 1'b0;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
reg bg_interrupt_ready_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_terminate;
reg doing_write;
reg doing_read;
reg rdwr_data_valid;
reg interrupt_ready;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
// Do signals
generate
if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (! ctl_reset_n)
begin
bg_do_write <= 0;
bg_do_read <= 0;
bg_do_auto_precharge <= 0;
bg_do_rmw_correct <= 0;
bg_do_rmw_partial <= 0;
bg_do_activate <= 0;
bg_do_precharge <= 0;
bg_do_precharge_all <= 0;
bg_do_refresh <= 0;
bg_do_self_refresh <= 0;
bg_do_power_down <= 0;
bg_do_deep_pdown <= 0;
bg_do_zq_cal <= 0;
bg_do_lmr <= 0;
bg_to_chip <= 0;
bg_to_chipsel <= 0;
bg_to_bank <= 0;
bg_to_row <= 0;
bg_localid <= 0;
bg_size <= 0;
bg_to_col <= 0;
bg_dataid <= 0;
bg_do_burst_chop <= 0;
bg_do_burst_terminate <= 0;
bg_doing_write <= 0;
bg_doing_read <= 0;
bg_rdwr_data_valid <= 0;
bg_interrupt_ready <= 0;
bg_effective_size <= 0;
end
else
begin
bg_do_write <= arb_do_write;
bg_do_read <= arb_do_read;
bg_do_auto_precharge <= arb_do_auto_precharge;
bg_do_rmw_correct <= combined_do_rmw_correct;
bg_do_rmw_partial <= combined_do_rmw_partial;
bg_do_activate <= arb_do_activate;
bg_do_precharge <= arb_do_precharge;
bg_do_precharge_all <= arb_do_precharge_all;
bg_do_refresh <= arb_do_refresh;
bg_do_self_refresh <= arb_do_self_refresh;
bg_do_power_down <= arb_do_power_down;
bg_do_deep_pdown <= arb_do_deep_pdown;
bg_do_zq_cal <= arb_do_zq_cal;
bg_do_lmr <= arb_do_lmr;
bg_to_chip <= arb_to_chip;
bg_to_chipsel <= arb_to_chipsel;
bg_to_bank <= arb_to_bank;
bg_to_row <= arb_to_row;
bg_localid <= arb_localid;
bg_size <= arb_size;
bg_to_col <= modified_to_col;
bg_dataid <= combined_dataid;
bg_do_burst_chop <= do_burst_chop;
bg_do_burst_terminate <= do_burst_terminate;
bg_doing_write <= doing_write;
bg_doing_read <= doing_read;
bg_rdwr_data_valid <= rdwr_data_valid;
bg_interrupt_ready <= interrupt_ready;
bg_effective_size <= effective_size;
end
end
end
else
begin
always @ (*)
begin
bg_do_write = arb_do_write;
bg_do_read = arb_do_read;
bg_do_auto_precharge = arb_do_auto_precharge;
bg_do_activate = arb_do_activate;
bg_do_precharge = arb_do_precharge;
bg_do_precharge_all = arb_do_precharge_all;
bg_do_refresh = arb_do_refresh;
bg_do_self_refresh = arb_do_self_refresh;
bg_do_power_down = arb_do_power_down;
bg_do_deep_pdown = arb_do_deep_pdown;
bg_do_zq_cal = arb_do_zq_cal;
bg_do_lmr = arb_do_lmr;
bg_to_chip = arb_to_chip;
bg_to_chipsel = arb_to_chipsel;
bg_to_bank = arb_to_bank;
bg_to_row = arb_to_row;
bg_localid = arb_localid;
bg_size = arb_size;
bg_do_burst_chop = do_burst_chop;
bg_do_burst_terminate = do_burst_terminate;
bg_doing_write = doing_write;
bg_doing_read = doing_read;
bg_rdwr_data_valid = rdwr_data_valid;
bg_interrupt_ready = interrupt_ready;
bg_effective_size = effective_size;
end
// To column
always @ (*)
begin
bg_to_col = modified_to_col;
end
// RMW info
always @ (*)
begin
bg_do_rmw_correct = combined_do_rmw_correct;
bg_do_rmw_partial = combined_do_rmw_partial;
end
// Data ID
always @ (*)
begin
bg_dataid = combined_dataid;
end
end
endgenerate
// Regardless whether CFG_ENABLE_BURST_GEN_OUTPUT_REG is 1/0
// following signals (inputs to rank_timer) need to be combi
always @ (*)
begin
bg_do_write_combi = arb_do_write;
bg_do_read_combi = arb_do_read;
bg_do_burst_chop_combi = do_burst_chop;
bg_do_burst_terminate_combi = do_burst_terminate;
bg_do_activate_combi = arb_do_activate;
bg_do_precharge_combi = arb_do_precharge;
bg_to_chip_combi = arb_to_chip;
bg_effective_size_combi = effective_size;
bg_interrupt_ready_combi = interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Generation Logic
//
// Doing read/write signal will indicate the "FULL" burst duration of a request
// Data Valid signal will indicate "VALID" burst duration of a request
//
// Example: Without address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Input Size ----X 1 X-----------------X 2 X-----------------X 3 X-----------------X 4 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal ____/ 1 \_________________/ 1 X 2 \___________/ 1 X 2 X 3 \_____/ 1 X 2 X 3 X 4 \_____
//
// Example: With address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 1 X-----------------X 2 X-----------------X 2 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 2 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal __________/ 1 \_______________________/ 1 \_________________/ 1 X 2 \_____
// <-----> <-----------> <----------->
// Offset Offset Offset
//
// Example: Burst chop for DDR3 only (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 1 X-----------------X 2 X-----------------X 3 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 1 X-----------------X 1 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 2 X-----------------X 2 X-----------------------
// Output Burst Chop Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Output Doing Signal ____/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \_________________
// Output Valid Signal ____/ 1 \_______________________/ 1 \___________/ 1 \_______________________/ 1 \_________________
// <-----> <----->
// Offset Offset
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Maximum local burst size
//----------------------------------------------------------------------------------------------------
// Calculate maximum local burst size
// based on burst length and controller rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size_divide_2 <= 0;
max_local_burst_size_minus_2 <= 0;
max_local_burst_size_divide_2_and_minus_2 <= 0;
end
else
begin
max_local_burst_size_divide_2 <= max_local_burst_size / 2;
max_local_burst_size_minus_2 <= max_local_burst_size - 2'd2;
max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
end
end
//----------------------------------------------------------------------------------------------------
// Address shifting
//----------------------------------------------------------------------------------------------------
// Column address
// we only require address [2 - 0] because the maximum supported
// local burst count is 8 which is BL of 16 in full rate
// we only take low phase of arb_to_col address because high and low phase is identical
always @ (*)
begin
int_col_address = 0;
if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop) // DDR3 and burst chop, we don't want address shifting during burst chop
begin
if (max_local_burst_size [2]) // max local burst of 4
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else
// max local burst of 1, 2 - address shifting in burst chop is not possible
// max local burst of 8 - not supported in DDR3, there is no BL 16 support in DDR3
int_col_address = 0;
end
else if (max_local_burst_size [0]) // max local burst of 1
int_col_address = 0;
else if (max_local_burst_size [1]) // max local burst of 2
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [2]) // max local burst of 4
int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [3]) // max local burst of 8
int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
end
always @ (*)
begin
col_address = int_col_address;
end
//----------------------------------------------------------------------------------------------------
// Command Info
//----------------------------------------------------------------------------------------------------
// To col address
always @ (*)
begin
int_to_col = arb_to_col;
end
// Row request
always @ (*)
begin
int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
end
// Column request
always @ (*)
begin
int_do_col_req = (|arb_do_write) | (|arb_do_read);
end
// Read and write request
always @ (*)
begin
int_do_rd_req = |arb_do_read;
int_do_wr_req = |arb_do_write;
end
// Burst chop
always @ (*)
begin
int_do_burst_chop = arb_do_burst_chop;
end
// RMW info
always @ (*)
begin
int_do_rmw_correct = arb_do_rmw_correct;
int_do_rmw_partial = arb_do_rmw_partial;
end
// Other Info: size, dataid
always @ (*)
begin
int_size = arb_size;
int_dataid = arb_dataid;
end
always @ (*)
begin
size = int_size;
dataid = int_dataid;
to_col = int_to_col;
do_row_req = int_do_row_req;
do_col_req = int_do_col_req;
do_rd_req = int_do_rd_req;
do_wr_req = int_do_wr_req;
do_burst_chop = int_do_burst_chop;
do_rmw_correct = int_do_rmw_correct;
do_rmw_partial = int_do_rmw_partial;
end
//----------------------------------------------------------------------------------------------------
// Address Count
//----------------------------------------------------------------------------------------------------
// Address counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
address_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address > 1'b1)
address_left <= col_address - 2'd2;
else
address_left <= 0;
end
else if (address_left != 0)
address_left <= address_left - 1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Valid Signal
//----------------------------------------------------------------------------------------------------
// Burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address == 0) // no shifting required
begin
if (size > 1'b1)
burst_left <= size - 2'd2;
else
burst_left <= 0;
end
else if (col_address == 1'b1) // require shifting
begin
burst_left <= size - 1'b1;
end
else // require shifting
begin
burst_left <= size;
end
end
else if (address_left == 0 && burst_left != 0) // start decreasing only after addres shifting is completed
burst_left <= burst_left - 1'b1;
end
end
// Current valid signal
// when there is a column request and column address is "0"
// valid signal must be asserted along with column request
always @ (*)
begin
if (do_col_req && col_address == 0)
current_valid = 1'b1;
else
current_valid = 1'b0;
end
// Delayed valid signal
// when there is a column request with size larger than "1"
// valid signal will be asserted according to the request size
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_valid <= 0;
end
else
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
delayed_valid <= 1'b1;
else if (address_left == 0 && burst_left > 0)
delayed_valid <= 1'b1;
else
delayed_valid <= 1'b0;
end
end
// Combined valid signal
always @ (*)
begin
combined_valid = current_valid | delayed_valid;
end
// Read write valid signal
always @ (*)
begin
rdwr_data_valid = combined_valid;
end
//----------------------------------------------------------------------------------------------------
// Doing Signal
//----------------------------------------------------------------------------------------------------
// Maximum burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (do_burst_chop)
begin
if (max_local_burst_size_divide_2 <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
end
else
begin
if (max_local_burst_size <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_minus_2;
end
end
else if (max_burst_left != 0)
max_burst_left <= max_burst_left - 1'b1;
end
end
// Delayed doing signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_doing <= 0;
end
else
begin
if (do_col_req)
begin
if (max_local_burst_size <= 1'b1) //do not generate delayed_doing if max burst count is 1
delayed_doing <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
delayed_doing <= 1'b0;
else
delayed_doing <= 1'b1;
end
else if (max_burst_left > 0)
delayed_doing <= 1'b1;
else
delayed_doing <= 1'b0;
end
end
// Keep track of last commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b0;
end
else
begin
if (do_wr_req)
begin
last_is_write <= 1'b1;
last_is_read <= 1'b0;
end
else if (do_rd_req)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b1;
end
end
end
// Doing write signal
always @ (*)
begin
if (do_rd_req)
doing_write = 1'b0;
else if (do_wr_req)
doing_write = ~terminate_doing;
else if (last_is_write)
doing_write = delayed_doing & ~terminate_doing;
else
doing_write = 1'b0;
end
// Doing read signal
always @ (*)
begin
if (do_wr_req)
doing_read = 1'b0;
else if (do_rd_req)
doing_read = ~terminate_doing;
else if (last_is_read)
doing_read = delayed_doing & ~terminate_doing;
else
doing_read = 1'b0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Generation Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
// Registered arb_do_rmw_* signal when there is a coumn request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_do_rmw_correct <= 0;
delayed_do_rmw_partial <= 0;
end
else
begin
if (do_col_req)
begin
delayed_do_rmw_correct <= do_rmw_correct;
delayed_do_rmw_partial <= do_rmw_partial;
end
end
end
// Prolong RMW information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
begin
combined_do_rmw_correct = do_rmw_correct;
combined_do_rmw_partial = do_rmw_partial;
end
else if (delayed_doing)
begin
combined_do_rmw_correct = delayed_do_rmw_correct;
combined_do_rmw_partial = delayed_do_rmw_partial;
end
else
begin
combined_do_rmw_correct = 0;
combined_do_rmw_partial = 0;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Data ID
//
//--------------------------------------------------------------------------------------------------------
// Register data ID when there is a column request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_dataid <= 0;
end
else
begin
if (do_col_req)
delayed_dataid <= dataid;
end
end
// Prolong data ID information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
combined_dataid = dataid;
else if (delayed_doing)
combined_dataid = delayed_dataid;
else
combined_dataid = 0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Data ID
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Column Address
//
//--------------------------------------------------------------------------------------------------------
// Change column address bit [2 : 0]
// see waveform examples in burst generation logic portion
always @ (*)
begin
modified_to_col = to_col;
// During burst chop in DDR3 only, retain original column address
// maximum local burst in DDR3 is 4 which is BL8 in full rate
if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
begin
if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
else
begin
if (max_local_burst_size [0]) // max local burst of 1
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 2 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [3]) // max local burst of 8
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 3 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Column Address
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Interrupt
//
// DDR, DDR2, LPDDR and LPDDR2 specific
//
// This logic re-use most of the existing logic in burst generation section (valid signal)
// This signal will be used in rank timer block to gate can_read and can_write signals
//
// Example: (DDR2 full rate, burst length of 8, this will result in maximum local burst of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Do Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Valid Signal ____/ 1 \_______________________/ 1 \_______________________/ 1 \_______________________/ 1 \_____
//
// Interrupt Ready (tCCD = 1) / HIGH \_____/ HIGH \___________/ HIGH \_________________/
// Interrupt Ready (tCCD = 2) / HIGH \_____/ HIGH \_____/ HIGH \_________________/ \_________________/
//
//--------------------------------------------------------------------------------------------------------
// n-prefetch architecture, related tCCD value (only support 1, 2 and 4)
// if tCCD is set to 1, command can be interrupted / terminated at every 2 memory burst boundary (1 memory clock cycle)
// if tCCD is set to 2, command can be interrupted / terminated at every 4 memory burst boundary (2 memory clock cycle)
// if tCCD is set to 4, command can be interrupted / terminated at every 8 memory burst boundary (4 memory clock cycle)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
n_prefetch <= 0;
end
else
begin
n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
end
end
// For n_prefetch of 0 and 1, we will allow interrupt at any controller clock cycles
// for n_prefetch of n, we will allow interrupt at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_interrupt <= 1'b1;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR3) // DDR3 specific, interrupt masking is handled by setting read-to-read and write-to-write to BL/2
int_allow_interrupt <= 1'b1;
else
begin
if (n_prefetch <= 1) // allow interrupt at any clock cycle
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address != 0))
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 2)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [0] == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 4)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [1 : 0] == 0)
int_allow_interrupt <= 1'b1;
end
end
end
end
// Interrupt info when interrupt feature is enabled
always @ (*)
begin
int_interrupt_enable_ready = int_allow_interrupt;
end
// Interrupt info when interrupt feature is disabled
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_interrupt_disable_ready <= 0;
end
else
begin
if (do_col_req)
begin
if (CFG_REG_GRANT)
begin
if (max_local_burst_size <= 2'd2) //do not generate int_interrupt_ready
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 3'd4)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
else
begin
if (max_local_burst_size <= 1'b1) //do not generate int_interrupt_ready if max burst count is 1
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
end
else if (!CFG_REG_GRANT && max_burst_left > 0)
int_interrupt_disable_ready <= 1'b1;
else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
int_interrupt_disable_ready <= 1'b1;
else
int_interrupt_disable_ready <= 1'b0;
end
end
// Assign to output ports
always @ (*)
begin
if (cfg_enable_burst_interrupt)
begin
interrupt_ready = ~int_interrupt_enable_ready;
end
else
begin
interrupt_ready = ~int_interrupt_disable_ready;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Interrupt
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Terminate
//
// LPDDR1 and LPDDR2 specific only
//
//--------------------------------------------------------------------------------------------------------
// For n_prefetch of 0 and 1, we will allow terminate at any controller clock cycles
// for n_prefetch of n, we will allow terminate at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else
begin
if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) // LPDDR1 and LPDDR2 only
begin
if (n_prefetch <= 1) // allow terminate at any clock cycle
begin
if (do_col_req && col_address != 0)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (do_col_req && col_address == 0 && size == 1'b1)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 2)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 4)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [1 : 0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
end
else
begin
int_allow_terminate <= 1'b0;
end
end
end
// Effective size, actual issued size migh be smaller that maximum local burst size
// we need to inform rank timer about this information for efficient DQ bus turnaround operation
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_effective_size <= 0;
end
else
begin
if (do_col_req)
int_effective_size <= 1'b1;
else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
int_effective_size <= int_effective_size + 1'b1;
end
end
// Terminate doing signal, this signal will be used to mask off doing_read or doing_write signal
// when we issue a burst terminate signal, we should also terminate doing_read and doing_write signal
// to prevent unwanted DQS toggle on the memory interface
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
doing_burst_terminate <= 1'b1;
else
doing_burst_terminate <= 1'b0;
end
end
always @ (*)
begin
if (cfg_enable_burst_terminate)
begin
terminate_doing = (|do_burst_terminate) | doing_burst_terminate;
end
else
begin
terminate_doing = zero;
end
end
// Burst terminate output ports
// set burst terminate signal to '0' when there is a do_col_req (in half and quarter rate)
// or both do_col_req and do_row_req (full rate) because this indicate there is a incoming command
// any command from arbiter is have higher priority compared to burst terminate command
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
int_do_req = do_col_req | do_row_req;
else
int_do_req = do_col_req;
end
generate
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate)
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
else
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
end
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate)
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
else
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
end
end
end
endgenerate
// Effective size output ports
always @ (*)
begin
if (cfg_enable_burst_terminate)
begin
effective_size = int_effective_size;
end
else
begin
effective_size = {CFG_INT_SIZE_WIDTH{zero}};
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Terminate
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Chop
//
// DDR3 specific only
//
//--------------------------------------------------------------------------------------------------------
// yyong generate
// yyong begin
// yyong if (CFG_DWIDTH_RATIO == 2)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size <= 2 && arb_to_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 4)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = 0;
// yyong
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 8)
// yyong begin
// yyong // Burst chop is not available in quarter rate
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{zero}};
// yyong end
// yyong end
// yyong end
// yyong endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Chop
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
module alt_mem_ddrx_burst_tracking
# (
// module parameter port list
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
// port list
ctl_clk,
ctl_reset_n,
// data burst interface
burst_ready,
burst_valid,
// burstcount counter sent to data_id_manager
burst_pending_burstcount,
burst_next_pending_burstcount,
// burstcount consumed by data_id_manager
burst_consumed_valid,
burst_counsumed_burstcount
);
// -----------------------------
// local parameter declarations
// -----------------------------
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// data burst interface
input burst_ready;
input burst_valid;
// burstcount counter sent to data_id_manager
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
// burstcount consumed by data_id_manager
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// data burst interface
wire burst_ready;
wire burst_valid;
// burstcount counter sent to data_id_manager
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
//wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_count_accepted;
// burstcount consumed by data_id_manager
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// signal declaration
// -----------------------------
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
// -----------------------------
// module definition
// -----------------------------
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_cmd_gen
# (parameter
// cmd_gen settings
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 4,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_DWIDTH_RATIO = 2, // 2-FR,4-HR,8-QR
CFG_CTL_QUEUE_DEPTH = 8,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary coded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_ENABLE_QUEUE = 1,
CFG_ENABLE_BURST_MERGE = 1,
CFG_CMD_GEN_OUTPUT_REG = 0,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
ctl_clk,
ctl_reset_n,
// tbp interface
tbp_full,
tbp_load,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_multicast,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// input interface
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_id,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
// datapath interface
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
proc_read,
proc_size,
proc_localid,
wdatap_free_id_valid, // from wdata path
wdatap_free_id_dataid, // from wdata path
rdatap_free_id_valid, // from rdata path
rdatap_free_id_dataid, // from rdata path
tbp_load_index,
data_complete,
data_rmw_complete,
// nodm and ecc signal
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
data_partial_be,
// configuration ports
cfg_enable_cmd_split,
cfg_burst_length,
cfg_addr_order,
cfg_enable_ecc,
cfg_enable_no_dm,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width
);
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + CFG_DATA_ID_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH;
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2(CFG_LOCAL_ADDR_WIDTH);
localparam INT_LOCAL_ADDR_WIDTH = 2**CFG_LOCAL_ADDR_BITSELECT_WIDTH;
input ctl_clk;
input ctl_reset_n;
input tbp_full;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] tbp_read;
input [CFG_CTL_TBP_NUM-1:0] tbp_write;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output cmd_gen_load;
output [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
output cmd_gen_write;
output cmd_gen_read;
output cmd_gen_multicast;
output [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
output [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
output cmd_gen_priority;
output cmd_gen_rmw_correct;
output cmd_gen_rmw_partial;
output cmd_gen_autopch;
output cmd_gen_complete;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output cmd_gen_full;
input cmd_valid;
input [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
input cmd_write;
input cmd_read;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
input cmd_multicast;
input [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
input cmd_priority;
input cmd_autoprecharge;
output proc_busy;
output proc_load;
output proc_load_dataid;
output proc_write;
output proc_read;
output [CFG_INT_SIZE_WIDTH-1:0] proc_size;
output [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
input wdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
input rdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output errcmd_ready; // high means cmd_gen accepts command
input errcmd_valid;
input [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
input [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
input data_partial_be;
input cfg_enable_cmd_split;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length; // this contains immediate BL value, max is 31
input [CFG_PORT_WIDTH_ADDR_ORDER-1:0] cfg_addr_order; // 0 is chiprowbankcol , 1 is chipbankrowcol , 2 is rowchipbankcol
input cfg_enable_ecc;
input cfg_enable_no_dm;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH-1:0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH-1:0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH-1:0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0] cfg_cs_addr_width;
// === address mapping
integer n;
integer j;
integer k;
integer m;
wire [INT_LOCAL_ADDR_WIDTH-1:0] int_cmd_address;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr;
// === command splitting block
reg [CFG_MEM_IF_CS_WIDTH-1:0] split_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] split_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] split_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] split_col_addr;
reg split_read;
reg split_write;
reg [CFG_INT_SIZE_WIDTH-1:0] split_size;
reg split_autopch;
reg split_multicast;
reg split_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] split_localid;
reg buf_read_req;
reg buf_write_req;
reg buf_autopch_req;
reg buf_multicast;
reg buf_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] buf_localid;
reg [CFG_LOCAL_SIZE_WIDTH:0] buf_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] buf_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] buf_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] buf_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] buf_col_addr;
reg [CFG_LOCAL_SIZE_WIDTH-1:0] decrmntd_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] incrmntd_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] incrmntd_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] incrmntd_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] incrmntd_col_addr;
reg [CFG_MEM_IF_CS_WIDTH-1:0] max_chip_from_csr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] max_bank_from_csr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] max_row_from_csr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] max_col_from_csr;
wire copy;
reg [2:0] unaligned_burst; // because planned max native size is 8, unaligned burst can be a max of 7
reg [3:0] native_size; // support native size up to 15, bl16 FR have native size of 8
wire require_gen;
reg deassert_ready;
reg registered;
reg generating;
// === ecc mux
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr_combi;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr_combi;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr_combi;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr_combi;
reg ecc_read_combi;
reg ecc_write_combi;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size_combi;
reg ecc_autopch_combi;
reg ecc_multicast_combi;
reg ecc_priority_combi;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid_combi;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr;
reg ecc_read;
reg ecc_write;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size;
reg ecc_autopch;
reg ecc_multicast;
reg ecc_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid;
reg ecc_int_combi;
reg errcmd_ready_combi;
reg partial_combi;
reg correct_combi;
reg partial_opr_combi;
reg ecc_int;
reg ecc_int_r;
reg errcmd_ready;
reg partial;
reg correct;
reg partial_opr;
wire mux_busy;
wire [CFG_MEM_IF_CS_WIDTH-1:0] muxed_cs_addr;
wire [CFG_MEM_IF_BA_WIDTH-1:0] muxed_bank_addr;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] muxed_row_addr;
wire [CFG_MEM_IF_COL_WIDTH-1:0] muxed_col_addr;
wire muxed_read;
wire muxed_write;
wire [CFG_INT_SIZE_WIDTH-1:0] muxed_size;
wire muxed_autopch;
wire muxed_multicast;
wire muxed_priority;
wire [CFG_LOCAL_ID_WIDTH-1:0] muxed_localid;
wire [CFG_DATA_ID_WIDTH-1:0] muxed_dataid;
wire muxed_complete;
wire muxed_correct;
wire muxed_partial;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_0;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_1;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_2;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_3;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
reg proc_busy_sig;
reg proc_ecc_busy_sig;
reg proc_load_sig;
reg proc_load_dataid_sig;
reg proc_write_sig;
reg proc_read_sig;
reg [CFG_INT_SIZE_WIDTH-1:0] proc_size_sig;
reg [CFG_LOCAL_ID_WIDTH-1:0] proc_localid_sig;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
// === merging signals
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_one;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_two;
wire can_merge;
reg [CFG_INT_SIZE_WIDTH-1:0] last_size;
reg last_read_req;
reg last_write_req;
reg last_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last_col_addr;
reg [CFG_INT_SIZE_WIDTH-1:0] last2_size;
reg last2_read_req;
reg last2_write_req;
reg last2_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last2_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last2_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last2_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last2_col_addr;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_row;
// === queue
reg [BUFFER_WIDTH-1:0] pipe[CFG_CTL_QUEUE_DEPTH-1:0];
reg pipefull[CFG_CTL_QUEUE_DEPTH-1:0];
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire write_to_queue;
wire queue_empty;
wire queue_full;
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_row_addr;
reg read [CFG_CTL_TBP_NUM-1:0];
reg write [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
wire [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire one = 1'b1;
wire zero = 1'b0;
//======================= TBP info ===========================
generate
genvar p;
for (p=0; p<CFG_CTL_TBP_NUM; p=p+1)
begin : info_per_tbp
always @ (*)
begin
if (tbp_load[p])
begin
read [p] = cmd_gen_read;
write [p] = cmd_gen_write;
chipsel[p] = cmd_gen_chipsel;
bank [p] = cmd_gen_bank;
row [p] = cmd_gen_row;
col [p] = cmd_gen_col;
end
else
begin
read [p] = tbp_read [p];
write [p] = tbp_write [p];
chipsel[p] = tbp_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
bank [p] = tbp_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
row [p] = tbp_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
col [p] = tbp_col [(p+1)*CFG_MEM_IF_COL_WIDTH-1:p*CFG_MEM_IF_COL_WIDTH];
end
end
end
for (p=0; p<CFG_CTL_SHADOW_TBP_NUM; p=p+1)
begin : info_per_shadow_tbp
assign shadow_chipsel[p] = tbp_shadow_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
assign shadow_bank [p] = tbp_shadow_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
assign shadow_row [p] = tbp_shadow_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
end
endgenerate
//======================= Address Remapping ===========================
// Pre-calculate int_*_addr chipsel, bank, row, col bit select offsets
always @ (*)
begin
// Row width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_row = cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_row = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_row = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Bank width info
if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_bank = cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_bank = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Chipsel width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
end
assign int_cmd_address = cmd_address;
// Supported addr order
// 0 - chip-row-bank-col
// 1 - chip-bank-row-col
// 2 - row-chip-bank-col
// Derive column address from address
always @(*)
begin : Col_addr_loop
int_col_addr[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0] = int_cmd_address[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0];
for (n = MIN_COL - log2(CFG_DWIDTH_RATIO);n < MAX_COL;n = n + 1'b1)
begin
if (n < (cfg_col_addr_width - log2(CFG_DWIDTH_RATIO))) // Bit of col_addr can be configured in CSR using cfg_col_addr_width
begin
int_col_addr[n] = int_cmd_address[n];
end
else
begin
int_col_addr[n] = 1'b0;
end
end
int_col_addr = int_col_addr << log2(CFG_DWIDTH_RATIO);
end
// Derive row address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_2;
always @(*)
begin : Row_addr_loop
for (j = 0;j < MIN_ROW;j = j + 1'b1) // The purpose of using this for-loop is to get rid of "if (j < cfg_row_addr_width) begin" which causes multiplexers
begin
row_addr_loop_1 = j + cfg_addr_bitsel_row;
int_row_addr[j] = int_cmd_address[row_addr_loop_1];
end
for (j = MIN_ROW;j < MAX_ROW;j = j + 1'b1)
begin
row_addr_loop_2 = j + cfg_addr_bitsel_row;
if(j < cfg_row_addr_width) // Bit of row_addr can be configured in CSR using cfg_row_addr_width
begin
int_row_addr[j] = int_cmd_address[row_addr_loop_2];
end
else
begin
int_row_addr[j] = 1'b0;
end
end
end
// Derive bank address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_2;
always @(*)
begin : Bank_addr_loop
for (k = 0;k < MIN_BANK;k = k + 1'b1) // The purpose of using this for-loop is to get rid of "if (k < cfg_bank_addr_width) begin" which causes multiplexers
begin
bank_addr_loop_1 = k + cfg_addr_bitsel_bank;
int_bank_addr[k] = int_cmd_address[bank_addr_loop_1];
end
for (k = MIN_BANK;k < MAX_BANK;k = k + 1'b1)
begin
bank_addr_loop_2 = k + cfg_addr_bitsel_bank;
if (k < cfg_bank_addr_width) // Bit of bank_addr can be configured in CSR using cfg_bank_addr_width
begin
int_bank_addr[k] = int_cmd_address[bank_addr_loop_2];
end
else
begin
int_bank_addr[k] = 1'b0;
end
end
end
// Derive chipsel address from address
always @(*)
begin
m = 0;
if (cfg_cs_addr_width > 1'b0) // If cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
begin
for (m=0; m<MIN_CS; m=m+1'b1) // The purpose of using this for-loop is to get rid of "if (m < cfg_cs_addr_width) begin" which causes multiplexers
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1)
begin
if (m < cfg_cs_addr_width) // Bit of cs_addr can be configured in CSR using cfg_cs_addr_width
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
else
begin
int_cs_addr[m] = 1'b0;
end
end
end
else // If CFG_MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
begin
int_cs_addr = {CFG_MEM_IF_CS_WIDTH{1'b0}};
end
end
//===================== end of address remapping =========================
//======================= burst splitting logic ===========================
assign cmd_gen_full = mux_busy | deassert_ready;
assign copy = ~cmd_gen_full & cmd_valid; // Copy current input command info into a register
assign require_gen = (cmd_size > native_size | unaligned_burst + cmd_size > native_size) & cfg_enable_cmd_split; // Indicate that current input command require splitting
// CSR address calculation
always @ (*)
begin
max_chip_from_csr = (2**cfg_cs_addr_width) - 1'b1;
max_bank_from_csr = (2**cfg_bank_addr_width) - 1'b1;
max_row_from_csr = (2**cfg_row_addr_width) - 1'b1;
max_col_from_csr = (2**cfg_col_addr_width) - 1'b1;
end
// Calculate native size for selected burstlength and controller rate
always @ (*)
begin
native_size = cfg_burst_length / CFG_DWIDTH_RATIO; // 1 for bl2 FR, 2 for bl8 HR, ...
end
always @(*)
begin
if (native_size == 1)
begin
unaligned_burst = 0;
end
else if (native_size == 2)
begin
unaligned_burst = {2'd0,int_col_addr[log2(CFG_DWIDTH_RATIO)]};
end
else if (native_size == 4)
begin
unaligned_burst = {1'd0,int_col_addr[(log2(CFG_DWIDTH_RATIO)+1):log2(CFG_DWIDTH_RATIO)]};
end
else // native_size == 8
begin
unaligned_burst = int_col_addr[(log2(CFG_DWIDTH_RATIO)+2):log2(CFG_DWIDTH_RATIO)];
end
end
// Deassert local_ready signal because need to split local command into multiple memory commands
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
deassert_ready <= 0;
end
else
begin
if (copy && require_gen)
begin
deassert_ready <= 1;
end
else if ((buf_size > native_size*2) && cfg_enable_cmd_split)
begin
deassert_ready <= 1;
end
else if (generating && ~mux_busy)
begin
deassert_ready <= 0;
end
end
end
// Assert register signal so that we will pass split command into TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
registered <= 0;
end
else
begin
if (copy && require_gen)
begin
registered <= 1;
end
else
begin
registered <= 0;
end
end
end
// Generating signal will notify that current command in under splitting process
// Signal stays high until the last memory burst aligned command is generated
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
generating <= 0;
end
else
begin
if (registered)
begin
generating <= 1;
end
else if ((generating && buf_size > native_size*2) && cfg_enable_cmd_split)
begin
generating <= 1;
end
else if (~mux_busy)
begin
generating <= 0;
end
end
end
// Determine the correct size
always @(*)
begin
if (!generating)
begin
if ((unaligned_burst + cmd_size < native_size) || !cfg_enable_cmd_split) //(local_size > 1 && !unaligned_burst)
begin
split_size = cmd_size;
end
else
begin
split_size = native_size - unaligned_burst;
end
end
else
begin
if (decrmntd_size > native_size - 1)
begin
split_size = native_size;
end
else
begin
split_size = decrmntd_size;
end
end
end
// MUX logic to determine where to take the command info from
always @(*)
begin
if (!generating) // not generating so take direct input from avalon if
begin
split_read = cmd_read & cmd_valid & ~registered;
split_write = cmd_write & cmd_valid & ~registered;
split_autopch = cmd_autoprecharge;
split_multicast = cmd_multicast;
split_priority = cmd_priority;
split_localid = cmd_id;
split_cs_addr = int_cs_addr;
split_bank_addr = int_bank_addr;
split_row_addr = int_row_addr;
split_col_addr = int_col_addr;
end
else // generating cmd so process buffer content
begin
split_read = buf_read_req;
split_write = buf_write_req;
split_autopch = buf_autopch_req;
split_multicast = buf_multicast;
split_priority = buf_priority;
split_localid = buf_localid;
split_cs_addr = incrmntd_cs_addr;
split_bank_addr = incrmntd_bank_addr;
split_row_addr = incrmntd_row_addr;
if (cfg_burst_length == 2)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1],1'b0};
end
else if (cfg_burst_length == 4)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2],2'b00};
end
else if (cfg_burst_length == 8)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3],3'b000};
end
else // if (cfg_burst_length == 16)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4],4'b0000};
end
end
end
// Buffered command info, to be used in split process
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_read_req <= 1'b0;
buf_write_req <= 1'b0;
buf_autopch_req <= 1'b0;
buf_multicast <= 1'b0;
buf_priority <= 1'b0;
buf_localid <= 0;
end
else
begin
if (copy)
begin
buf_read_req <= cmd_read;
buf_write_req <= cmd_write;
buf_autopch_req <= cmd_autoprecharge;
buf_multicast <= cmd_multicast;
buf_priority <= cmd_priority;
buf_localid <= cmd_id;
end
end
end
// Keep track of command size during a split process
// will keep decreasing when a split command was sent to TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_size <= 0;
end
else
begin
if (copy)
begin
buf_size <= cmd_size + unaligned_burst;
end
else if (!registered && buf_size > native_size && ~mux_busy)
begin
buf_size <= buf_size - native_size;
end
end
end
always @(*)
begin
decrmntd_size = buf_size - native_size;
end
// Keep track of command address during a split process
// will keep increasing when a split command was sent to TBP
// also takes into account address order
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_cs_addr <= 0;
buf_bank_addr <= 0;
buf_row_addr <= 0;
buf_col_addr <= 0;
end
else
if (copy)
begin
buf_cs_addr <= int_cs_addr;
buf_bank_addr <= int_bank_addr;
buf_row_addr <= int_row_addr;
buf_col_addr <= int_col_addr;
end
else if (registered || (generating && ~mux_busy))
if ((cfg_burst_length == 16 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
||
(cfg_burst_length == 8 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
||
(cfg_burst_length == 4 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
||
(cfg_burst_length == 2 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
)
begin
if (cfg_burst_length == 16)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] <= 0;
else if (cfg_burst_length == 8)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] <= 0;
else if (cfg_burst_length == 4)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] <= 0;
else // if (cfg_burst_length == 2)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] <= 0;
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL) // 2 is rowchipbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
begin
buf_cs_addr <= 0;
if (buf_row_addr == max_row_from_csr)
buf_row_addr <= 0;
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL) // 1 is chipbankrowcol
begin
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else // 0 is chiprowbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
end
else
buf_col_addr <= buf_col_addr + cfg_burst_length;
end
always @(*)
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr;
end
//======================= end of burst splitting logic ===========================
//====================== ecc mux start ========================
// ECC process info
always @ (*)
begin
ecc_int_combi = ecc_int;
correct_combi = correct;
partial_combi = partial;
errcmd_ready_combi = errcmd_ready;
ecc_dataid_combi = ecc_dataid;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert partial after ECC write was sent to TBP
begin
partial_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (correct)
begin
errcmd_ready_combi = 1'b0;
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert correct after ECC write was sent to TBP
begin
correct_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // if there is a auto correction request
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b1;
partial_combi = 1'b0;
errcmd_ready_combi = 1'b1;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // if there is a write request in no-DM or ECC case
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b0;
partial_combi = 1'b1;
ecc_dataid_combi = wdatap_free_id_dataid;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int <= 0;
correct <= 0;
partial <= 0;
errcmd_ready <= 0;
ecc_dataid <= 0;
end
else
begin
ecc_int <= ecc_int_combi;
correct <= correct_combi;
partial <= partial_combi;
errcmd_ready <= errcmd_ready_combi;
ecc_dataid <= ecc_dataid_combi;
end
end
// Buffer for ECC command information
always @ (*)
begin
if (partial || correct)
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
else if (cfg_enable_ecc && errcmd_valid) // take in error command info
begin
ecc_cs_addr_combi = errcmd_chipsel;
ecc_bank_addr_combi = errcmd_bank;
ecc_row_addr_combi = errcmd_row;
ecc_col_addr_combi = errcmd_column;
ecc_size_combi = errcmd_size;
ecc_autopch_combi = 1'b0;
ecc_multicast_combi = 1'b0;
ecc_localid_combi = errcmd_localid;
ecc_priority_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // take in command info from split logic
begin
ecc_cs_addr_combi = split_cs_addr;
ecc_bank_addr_combi = split_bank_addr;
ecc_row_addr_combi = split_row_addr;
ecc_col_addr_combi = split_col_addr;
ecc_size_combi = split_size;
ecc_autopch_combi = split_autopch;
ecc_multicast_combi = split_multicast;
ecc_localid_combi = split_localid;
ecc_priority_combi = split_priority;
end
else
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_cs_addr <= 0;
ecc_bank_addr <= 0;
ecc_row_addr <= 0;
ecc_col_addr <= 0;
ecc_size <= 0;
ecc_autopch <= 0;
ecc_multicast <= 0;
ecc_localid <= 0;
ecc_priority <= 0;
end
else
begin
ecc_cs_addr <= ecc_cs_addr_combi;
ecc_bank_addr <= ecc_bank_addr_combi;
ecc_row_addr <= ecc_row_addr_combi;
ecc_col_addr <= ecc_col_addr_combi;
ecc_size <= ecc_size_combi;
ecc_autopch <= ecc_autopch_combi;
ecc_multicast <= ecc_multicast_combi;
ecc_localid <= ecc_localid_combi;
ecc_priority <= ecc_priority_combi;
end
end
// Logic to determine when to issue ECC read/write request
// based on partial_be info from wdata path
// if partial_be is high, it issues a read-modify-write command
// else issues normal write command
always @ (*)
begin
ecc_read_combi = ecc_read;
ecc_write_combi = ecc_write;
partial_opr_combi = partial_opr;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
partial_opr_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (data_complete[0]) // wait for data_complete from wdata path
begin
if (!data_partial_be) // if not partial_be, issues normal write
begin
ecc_write_combi = 1'b1;
end
else // else issues a RMW's read
begin
ecc_read_combi = 1'b1;
partial_opr_combi = 1'b1;
end
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
begin
ecc_write_combi = 1'b1;
end
else
begin
ecc_write_combi = 1'b0;
end
end
end
else if (correct)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
ecc_write_combi = 1'b1;
else
ecc_write_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // issues a RMW's read when there is a error correction
begin
ecc_read_combi = 1'b1;
ecc_write_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy)
begin
ecc_read_combi = 1'b0;
ecc_write_combi = 1'b0;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_read <= 1'b0;
ecc_write <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_read <= ecc_read_combi;
ecc_write <= ecc_write_combi;
partial_opr <= partial_opr_combi;
end
end
// We only need to gate split_read/write in non cmd_gen registered output mode
assign mux_busy = (
queue_full |
errcmd_valid |
(
(cfg_enable_no_dm | cfg_enable_ecc) &
(
ecc_int |
(
!(CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE) &
(
(split_read & ~rdatap_free_id_valid) |
(split_write & ~wdatap_free_id_valid)
)
)
)
)
);
assign muxed_cs_addr = ecc_int ? ecc_cs_addr : split_cs_addr;
assign muxed_bank_addr = ecc_int ? ecc_bank_addr : split_bank_addr;
assign muxed_row_addr = ecc_int ? ecc_row_addr : split_row_addr;
assign muxed_col_addr = ecc_int ? ecc_col_addr : split_col_addr;
assign muxed_read = ecc_int ? (CFG_CMD_GEN_OUTPUT_REG ? (ecc_read & rdatap_free_id_valid) : ecc_read) : split_read & ~errcmd_valid; // We only need to check for free ID valid in CMD_GEN_OUTPUT_REG mode
assign muxed_write = (cfg_enable_no_dm || cfg_enable_ecc) ? ecc_write : split_write & ~errcmd_valid;
assign muxed_size = ecc_int ? ecc_size : split_size;
assign muxed_autopch = ecc_int ? ecc_autopch : split_autopch;
assign muxed_multicast = ecc_int ? ecc_multicast : split_multicast;
assign muxed_localid = ecc_int ? ecc_localid : split_localid;
assign muxed_priority = ecc_int ? ecc_priority : split_priority;
assign muxed_dataid = ecc_int ? ecc_dataid : rdatap_free_id_dataid;
assign muxed_complete = ecc_int ? 1'b1 : split_read;
assign muxed_correct = ecc_int ? correct : 1'b0;
assign muxed_partial = ecc_int ? partial_opr : 1'b0;
assign muxed_same_chipsel_addr = ecc_int_r ? ecc_same_chipsel_addr : split_same_chipsel_addr;
assign muxed_same_bank_addr = ecc_int_r ? ecc_same_bank_addr : split_same_bank_addr;
assign muxed_same_row_addr_0 = ecc_int_r ? ecc_same_row_addr_0 : split_same_row_addr_0;
assign muxed_same_row_addr_1 = ecc_int_r ? ecc_same_row_addr_1 : split_same_row_addr_1;
assign muxed_same_row_addr_2 = ecc_int_r ? ecc_same_row_addr_2 : split_same_row_addr_2;
assign muxed_same_row_addr_3 = ecc_int_r ? ecc_same_row_addr_3 : split_same_row_addr_3;
assign muxed_same_col_addr = ecc_int_r ? ecc_same_col_addr : split_same_col_addr;
assign muxed_same_read_cmd = ecc_int_r ? ecc_same_read_cmd : split_same_read_cmd;
assign muxed_same_write_cmd = ecc_int_r ? ecc_same_write_cmd : split_same_write_cmd;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int_r <= 1'b0;
end
else
begin
ecc_int_r <= ecc_int;
end
end
// Address comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (split_cs_addr == chipsel[j])
begin
split_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
split_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (split_bank_addr == bank[j])
begin
split_same_bank_addr_combi[j] = 1'b1;
end
else
begin
split_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (split_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_0_combi[j] = 1'b0;
end
if (split_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_1_combi[j] = 1'b0;
end
if (split_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_2_combi[j] = 1'b0;
end
if (split_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (split_col_addr == col[j])
begin
split_same_col_addr_combi[j] = 1'b1;
end
else
begin
split_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (split_read == read[j])
begin
split_same_read_cmd_combi[j] = 1'b1;
end
else
begin
split_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (split_write == write[j])
begin
split_same_write_cmd_combi[j] = 1'b1;
end
else
begin
split_same_write_cmd_combi[j] = 1'b0;
end
end
end
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (ecc_cs_addr == chipsel[j])
begin
ecc_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (ecc_bank_addr == bank[j])
begin
ecc_same_bank_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (ecc_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_0_combi[j] = 1'b0;
end
if (ecc_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_1_combi[j] = 1'b0;
end
if (ecc_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_2_combi[j] = 1'b0;
end
if (ecc_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (ecc_col_addr == col[j])
begin
ecc_same_col_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (ecc_read == read[j])
begin
ecc_same_read_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (ecc_write == write[j])
begin
ecc_same_write_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_write_cmd_combi[j] = 1'b0;
end
end
end
generate
if (CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE)
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
proc_write_sig <= 0;
proc_read_sig <= 0;
proc_size_sig <= 0;
proc_localid_sig <= 0;
proc_load_dataid_sig <= 0;
proc_ecc_busy_sig <= 0;
end
else
begin
if (proc_busy_sig)
begin
// Do nothing, keep old value
end
else
begin
proc_load_dataid_sig <= ~(ecc_int & (ecc_read | ecc_write));
if (ecc_int)
begin
proc_write_sig <= ecc_write & correct;
proc_read_sig <= ecc_read;
proc_size_sig <= ecc_size;
proc_localid_sig <= ecc_localid;
proc_ecc_busy_sig <= (ecc_read & ~rdatap_free_id_valid) | ((ecc_write & correct) & ~wdatap_free_id_valid);
end
else
begin
proc_write_sig <= split_write & ~errcmd_valid;
proc_read_sig <= split_read & ~errcmd_valid;
proc_size_sig <= split_size;
proc_localid_sig <= split_localid;
proc_ecc_busy_sig <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_same_chipsel_addr <= 0;
split_same_bank_addr <= 0;
split_same_row_addr_0 <= 0;
split_same_row_addr_1 <= 0;
split_same_row_addr_2 <= 0;
split_same_row_addr_3 <= 0;
split_same_col_addr <= 0;
split_same_read_cmd <= 0;
split_same_write_cmd <= 0;
ecc_same_chipsel_addr <= 0;
ecc_same_bank_addr <= 0;
ecc_same_row_addr_0 <= 0;
ecc_same_row_addr_1 <= 0;
ecc_same_row_addr_2 <= 0;
ecc_same_row_addr_3 <= 0;
ecc_same_col_addr <= 0;
ecc_same_read_cmd <= 0;
ecc_same_write_cmd <= 0;
end
else
begin
split_same_chipsel_addr <= split_same_chipsel_addr_combi;
split_same_bank_addr <= split_same_bank_addr_combi;
split_same_row_addr_0 <= split_same_row_addr_0_combi;
split_same_row_addr_1 <= split_same_row_addr_1_combi;
split_same_row_addr_2 <= split_same_row_addr_2_combi;
split_same_row_addr_3 <= split_same_row_addr_3_combi;
split_same_col_addr <= split_same_col_addr_combi;
split_same_read_cmd <= split_same_read_cmd_combi;
split_same_write_cmd <= split_same_write_cmd_combi;
ecc_same_chipsel_addr <= ecc_same_chipsel_addr_combi;
ecc_same_bank_addr <= ecc_same_bank_addr_combi;
ecc_same_row_addr_0 <= ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 <= ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 <= ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 <= ecc_same_row_addr_3_combi;
ecc_same_col_addr <= ecc_same_col_addr_combi;
ecc_same_read_cmd <= ecc_same_read_cmd_combi;
ecc_same_write_cmd <= ecc_same_write_cmd_combi;
end
end
end
else
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_ecc_busy_sig = zero;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
proc_load_dataid_sig = ~(ecc_int & (ecc_read | ecc_write));
proc_write_sig = ecc_int ? ecc_write & correct : split_write & ~errcmd_valid;
proc_read_sig = ecc_int ? ecc_read : split_read & ~errcmd_valid;
proc_size_sig = ecc_int ? ecc_size : split_size;
proc_localid_sig = ecc_int ? ecc_localid : split_localid;
end
always @ (*)
begin
split_same_chipsel_addr = split_same_chipsel_addr_combi;
split_same_bank_addr = split_same_bank_addr_combi;
split_same_row_addr_0 = split_same_row_addr_0_combi;
split_same_row_addr_1 = split_same_row_addr_1_combi;
split_same_row_addr_2 = split_same_row_addr_2_combi;
split_same_row_addr_3 = split_same_row_addr_3_combi;
split_same_col_addr = split_same_col_addr_combi;
split_same_read_cmd = split_same_read_cmd_combi;
split_same_write_cmd = split_same_write_cmd_combi;
ecc_same_chipsel_addr = ecc_same_chipsel_addr_combi;
ecc_same_bank_addr = ecc_same_bank_addr_combi;
ecc_same_row_addr_0 = ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 = ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 = ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 = ecc_same_row_addr_3_combi;
ecc_same_col_addr = ecc_same_col_addr_combi;
ecc_same_read_cmd = ecc_same_read_cmd_combi;
ecc_same_write_cmd = ecc_same_write_cmd_combi;
end
end
endgenerate
//====================== ecc mux end ========================
//====================== sequential address detector ========================
//Last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n)
begin
last_read_req <= 1'b0;
last_write_req <= 1'b0;
last_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last_read_req <= muxed_read;
last_write_req <= muxed_write;
last_multicast <= muxed_multicast;
last_chip_addr <= muxed_cs_addr;
last_bank_addr <= muxed_bank_addr;
last_row_addr <= muxed_row_addr;
last_col_addr <= muxed_col_addr;
last_size <= muxed_size;
end
else if (can_merge)
begin
last_size <= 2;
end
end
//Second last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last2_read_req <= 1'b0;
last2_write_req <= 1'b0;
last2_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last2_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last2_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last2_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last2_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last2_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last2_read_req <= last_read_req;
last2_write_req <= last_write_req;
last2_multicast <= last_multicast;
last2_chip_addr <= last_chip_addr;
last2_bank_addr <= last_bank_addr;
last2_row_addr <= last_row_addr;
last2_col_addr <= last_col_addr;
last2_size <= last_size;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last <= 0;
last_minus_one <= 0;
last_minus_two <= 0;
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
if (write_to_queue)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
else
begin
last <= last - 2;
last_minus_one <= last - 3;
last_minus_two <= last - 4;
end
end
else
begin
if (write_to_queue) begin
// do nothing
end
else if (last != 0)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
// do nothing
end
else if (!queue_empty)
begin
last <= last + 1;
last_minus_one <= last;
last_minus_two <= last - 1;
end
end
else if (can_merge)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
// Merging logic
assign can_merge = (CFG_ENABLE_BURST_MERGE == 1) ?
last != 0
& pipefull[last]
& last2_read_req == last_read_req
& last2_write_req == last_write_req
& last2_multicast == last_multicast
& last2_chip_addr == last_chip_addr
& last2_bank_addr == last_bank_addr
& last2_row_addr == last_row_addr
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2]) : (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3]) )
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[1] == 0 & last_col_addr[1] == 1) : (last2_col_addr[2] == 0 & last_col_addr[2] == 1) )
& last2_size == 1 & last_size == 1
:
1'b0;
//=================== end of sequential address detector ====================
//=============================== queue ===================================
// mapping of buffer_input
assign buffer_input = {muxed_read,muxed_write,muxed_multicast,muxed_autopch,muxed_priority,muxed_complete,muxed_correct,muxed_partial,muxed_dataid,muxed_localid,muxed_size,muxed_cs_addr,muxed_row_addr,muxed_bank_addr,muxed_col_addr};
generate
if (CFG_ENABLE_QUEUE == 1)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
// TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr = muxed_same_row_addr_0 & muxed_same_row_addr_1 & muxed_same_row_addr_2 & muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
// Chipselect address
if (cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
assign queue_empty = !pipefull[0];
assign queue_full = pipefull[CFG_CTL_QUEUE_DEPTH-1] | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
assign cmd_gen_load = pipefull[0] & ((cfg_enable_no_dm | cfg_enable_ecc) | ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid)));
assign cmd_gen_read = pipe[0][BUFFER_WIDTH-1];
assign cmd_gen_write = pipe[0][BUFFER_WIDTH-2];
assign cmd_gen_multicast = pipe[0][BUFFER_WIDTH-3];
assign cmd_gen_autopch = pipe[0][BUFFER_WIDTH-4];
assign cmd_gen_priority = pipe[0][BUFFER_WIDTH-5];
assign cmd_gen_complete = pipe[0][BUFFER_WIDTH-6];
assign cmd_gen_rmw_correct = pipe[0][BUFFER_WIDTH-7];
assign cmd_gen_rmw_partial = pipe[0][BUFFER_WIDTH-8];
assign cmd_gen_dataid = cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid;
assign cmd_gen_localid = pipe[0][CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_size = pipe[0][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_chipsel = pipe[0][CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_row = pipe[0][CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_bank = pipe[0][CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_col = pipe[0][CFG_MEM_IF_COL_WIDTH - 1 : 0];
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
else
begin
wire int_queue_full;
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
reg int_register_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cmd_gen_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_cmd_gen_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_cmd_gen_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_cmd_gen_col;
reg int_cmd_gen_write;
reg int_cmd_gen_read;
reg int_cmd_gen_multicast;
reg [CFG_INT_SIZE_WIDTH-1:0] int_cmd_gen_size;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_cmd_gen_localid;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid;
reg int_cmd_gen_priority;
reg int_cmd_gen_rmw_correct;
reg int_cmd_gen_rmw_partial;
reg int_cmd_gen_autopch;
reg int_cmd_gen_complete;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid_mux;
// TBP address and command comparison logic
always @ (*)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr_0 = muxed_same_row_addr_0;
int_same_row_addr_1 = muxed_same_row_addr_1;
int_same_row_addr_2 = muxed_same_row_addr_2;
int_same_row_addr_3 = muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (int_queue_full)
begin
// Chipselect address
if (int_cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (int_cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (int_cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
else
begin
// Chipselect address
if (muxed_cs_addr == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (muxed_bank_addr == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (muxed_row_addr == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
end
if (CFG_CMD_GEN_OUTPUT_REG)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr_r;
reg int_ecc_int;
reg int_queue_full_r;
assign int_queue_full = (tbp_full & int_register_valid) | ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid));
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_queue_full_r <= 1'b0;
end
else
begin
int_queue_full_r <= int_queue_full;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 0;
int_cmd_gen_write <= 0;
int_cmd_gen_multicast <= 0;
int_cmd_gen_autopch <= 0;
int_cmd_gen_priority <= 0;
int_cmd_gen_complete <= 0;
int_cmd_gen_rmw_correct <= 0;
int_cmd_gen_rmw_partial <= 0;
int_cmd_gen_dataid <= 0;
int_cmd_gen_localid <= 0;
int_cmd_gen_size <= 0;
int_cmd_gen_chipsel <= 0;
int_cmd_gen_row <= 0;
int_cmd_gen_bank <= 0;
int_cmd_gen_col <= 0;
int_ecc_int <= 0;
end
else
begin
if (fetch)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 1'b0;
int_cmd_gen_write <= 1'b0;
end
if (!int_queue_full)
begin
if (muxed_read || muxed_write)
begin
int_register_valid <= 1'b1;
end
int_cmd_gen_read <= muxed_read;
int_cmd_gen_write <= muxed_write;
int_cmd_gen_multicast <= muxed_multicast;
int_cmd_gen_autopch <= muxed_autopch;
int_cmd_gen_priority <= muxed_priority;
int_cmd_gen_complete <= muxed_complete;
int_cmd_gen_rmw_correct <= muxed_correct;
int_cmd_gen_rmw_partial <= muxed_partial;
int_cmd_gen_dataid <= muxed_dataid;
int_cmd_gen_localid <= muxed_localid;
int_cmd_gen_size <= muxed_size;
int_cmd_gen_chipsel <= muxed_cs_addr;
int_cmd_gen_row <= muxed_row_addr;
int_cmd_gen_bank <= muxed_bank_addr;
int_cmd_gen_col <= muxed_col_addr;
int_ecc_int <= ecc_int;
end
end
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_ecc_int ? int_cmd_gen_dataid : rdatap_free_id_dataid;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_same_chipsel_addr_r <= 0;
int_same_bank_addr_r <= 0;
int_same_row_addr_0_r <= 0;
int_same_row_addr_1_r <= 0;
int_same_row_addr_2_r <= 0;
int_same_row_addr_3_r <= 0;
int_same_col_addr_r <= 0;
int_same_read_cmd_r <= 0;
int_same_write_cmd_r <= 0;
int_same_shadow_chipsel_addr_r <= 0;
int_same_shadow_bank_addr_r <= 0;
int_same_shadow_row_addr_r <= 0;
end
else
begin
if (int_queue_full & !int_queue_full_r) // positive edge detector
begin
int_same_chipsel_addr_r <= int_same_chipsel_addr;
int_same_bank_addr_r <= int_same_bank_addr;
int_same_row_addr_0_r <= int_same_row_addr_0;
int_same_row_addr_1_r <= int_same_row_addr_1;
int_same_row_addr_2_r <= int_same_row_addr_2;
int_same_row_addr_3_r <= int_same_row_addr_3;
int_same_col_addr_r <= int_same_col_addr;
int_same_read_cmd_r <= int_same_read_cmd;
int_same_write_cmd_r <= int_same_write_cmd;
end
int_same_shadow_chipsel_addr_r <= int_same_shadow_chipsel_addr;
int_same_shadow_bank_addr_r <= int_same_shadow_bank_addr;
int_same_shadow_row_addr_r <= int_same_shadow_row_addr;
end
end
always @ (*)
begin
if (!int_queue_full_r)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1 & int_same_row_addr_2 & int_same_row_addr_3;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
end
else
begin
same_chipsel_addr = int_same_chipsel_addr_r;
same_bank_addr = int_same_bank_addr_r;
same_row_addr = int_same_row_addr_0_r & int_same_row_addr_1_r & int_same_row_addr_2_r & int_same_row_addr_3_r;
same_col_addr = int_same_col_addr_r;
same_read_cmd = int_same_read_cmd_r;
same_write_cmd = int_same_write_cmd_r;
end
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr_r;
same_shadow_bank_addr = int_same_shadow_bank_addr_r;
same_shadow_row_addr = int_same_shadow_row_addr_r;
end
end
else
begin
assign int_queue_full = tbp_full | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
always @ (*)
begin
int_register_valid = one;
int_cmd_gen_read = muxed_read;
int_cmd_gen_write = muxed_write;
int_cmd_gen_multicast = muxed_multicast;
int_cmd_gen_autopch = muxed_autopch;
int_cmd_gen_priority = muxed_priority;
int_cmd_gen_complete = muxed_complete;
int_cmd_gen_rmw_correct = muxed_correct;
int_cmd_gen_rmw_partial = muxed_partial;
int_cmd_gen_dataid = muxed_dataid;
int_cmd_gen_localid = muxed_localid;
int_cmd_gen_size = muxed_size;
int_cmd_gen_chipsel = muxed_cs_addr;
int_cmd_gen_row = muxed_row_addr;
int_cmd_gen_bank = muxed_bank_addr;
int_cmd_gen_col = muxed_col_addr;
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_cmd_gen_dataid;
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
end
assign queue_empty = 1;
assign queue_full = int_queue_full;
assign cmd_gen_load = (cmd_gen_read | cmd_gen_write) & ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid));
assign cmd_gen_read = int_cmd_gen_read;
assign cmd_gen_write = int_cmd_gen_write;
assign cmd_gen_multicast = int_cmd_gen_multicast;
assign cmd_gen_autopch = int_cmd_gen_autopch;
assign cmd_gen_priority = int_cmd_gen_priority;
assign cmd_gen_complete = int_cmd_gen_complete;
assign cmd_gen_rmw_correct = int_cmd_gen_rmw_correct;
assign cmd_gen_rmw_partial = int_cmd_gen_rmw_partial;
assign cmd_gen_dataid = (cfg_enable_no_dm || cfg_enable_ecc) ? int_cmd_gen_dataid_mux : (cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid);
assign cmd_gen_localid = int_cmd_gen_localid;
assign cmd_gen_size = int_cmd_gen_size;
assign cmd_gen_chipsel = int_cmd_gen_chipsel;
assign cmd_gen_row = int_cmd_gen_row;
assign cmd_gen_bank = int_cmd_gen_bank;
assign cmd_gen_col = int_cmd_gen_col;
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
endgenerate
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign write_to_queue = (muxed_read | muxed_write) & ~queue_full;
assign fetch = cmd_gen_load & ~tbp_full;
// proc signals to datapath
assign proc_busy = (cfg_enable_no_dm || cfg_enable_ecc) ? (proc_busy_sig | proc_ecc_busy_sig) : tbp_full;
assign proc_load = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_sig : cmd_gen_load;
assign proc_load_dataid= (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_dataid_sig : cmd_gen_load;
assign proc_write = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_write_sig : cmd_gen_write;
assign proc_read = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_read_sig : cmd_gen_read;
assign proc_size = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_size_sig : cmd_gen_size;
assign proc_localid = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_localid_sig : cmd_gen_localid;
assign tbp_load_index = (cfg_enable_no_dm || cfg_enable_ecc) ? 1 : tbp_load;
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
pipefull[j] <= 1'b0;
pipe [j] <= 0;
end
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else if (j == last_minus_one)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else if (j == last_minus_two)
begin
pipe[j] <= {pipe[j+1][BUFFER_WIDTH-1:BUFFER_WIDTH-4],2'd2,pipe[j+1][BUFFER_WIDTH-7:0]};
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe[CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
else
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= pipefull[CFG_CTL_QUEUE_DEPTH-1] & write_to_queue;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe [CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
pipe[last] <= buffer_input;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
else
begin
for(j=1; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0)
begin
pipefull[j] <= 1'b1;
pipe [j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0)
begin
pipefull[0] <= 1'b1;
pipe [0] <= buffer_input;
end
end
end
else if (can_merge)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else
begin
pipefull[j] <= pipefull[j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
end
end
//============================ end of queue ===============================
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_controller #
( parameter
// Local interface parameters
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_LOCAL_DATA_WIDTH = 80, // Maximum DQ width of 40
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_IF_TYPE = "AVALON",
// Memory interface parameters
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 15,
CFG_MEM_IF_COL_WIDTH = 12,
CFG_MEM_IF_ADDR_WIDTH = 15,
CFG_MEM_IF_CKE_WIDTH = 2,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_MEM_IF_DM_WIDTH = 5,
// Controller parameters
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1, // NOTICE: required?
CFG_OUTPUT_REGD = 0, // NOTICE: un-used and will be removed
CFG_CTL_TBP_NUM = 4,
CFG_LPDDR2_ENABLED = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_ECC_MULTIPLES_16_24_40_72 = 1,
// Data path buffer & fifo parameters
CFG_WRBUFFER_ADDR_WIDTH = 6,
CFG_RDBUFFER_ADDR_WIDTH = 10,
// MMR port width
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_DEVICE_WIDTH = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
// cfg: address mapping signals
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// cfg: control signals
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_USER_RFSH = 1,
CFG_PORT_WIDTH_SELF_RFSH = 1,
CFG_PORT_WIDTH_REGDIMM_ENABLE = 1,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_CMD_SPLIT = 1'b1, // disable this (set to 0) when using the controller with hard MPFE
// cfg: ecc signals
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
// cfg: odt
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
// cfg: ecc signals
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8,
// PHY parameters
CFG_WLAT_BUS_WIDTH = 4,
// controller read data return mode
CFG_RDATA_RETURN_MODE = "PASSTHROUGH"
)
(
// Clock and reset
ctl_clk,
ctl_reset_n,
// Command channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// Write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// Read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
itf_rd_data_id_early_valid, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
// Sideband signals
local_refresh_req,
local_refresh_chip,
local_deep_powerdn_chip,
local_deep_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
// Controller commands to the AFI interface
afi_rst_n,
afi_ba,
afi_addr,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_odt,
// Controller read and write data to the AFI interface
afi_wlat,
afi_dqs_burst,
afi_dm,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
// Status and control signal to the AFI interface
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_init_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
// cfg: general
cfg_type,
cfg_interface_width, // not sure where this signal is used
cfg_burst_length,
cfg_device_width, // not sure where this signal is used
cfg_output_regd,
// cfg: address mapping signals
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// cfg: timing parameters
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_auto_pd_cycles,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_power_saving_exit_cycles,
cfg_mem_clk_entry_cycles,
cfg_tmrd,
// cfg: extra timing parameters
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// cfg: control signals
cfg_reorder_data, // enable data reordering
cfg_starve_limit, // starvation counter limit
cfg_user_rfsh,
cfg_regdimm_enable,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// cfg: ecc signals
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_ecc_code_overwrites,
cfg_enable_no_dm,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// cfg: odt
cfg_write_odt_chip,
cfg_read_odt_chip,
// sts: ecc signals
ecc_interrupt,
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
//calibration
cfg_cal_req,
sts_cal_fail,
sts_cal_success,
// DQS enable tracking
cfg_enable_dqs_tracking, //enable DQS enable tracking support in controller
afi_ctl_refresh_done, // Controller asserts this after tRFC is done, also acts as stall ack to phy
afi_seq_busy, // Sequencer busy signal to controller, also acts as stall request to ctlr
afi_ctl_long_idle // Controller asserts this after long period of no refresh, protocol is the same as rfsh_done
);
// General parameters
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_INT_SIZE_WIDTH = (CFG_DWIDTH_RATIO == 2) ? 4 : ((CFG_DWIDTH_RATIO == 4) ? 3 : ((CFG_DWIDTH_RATIO == 8) ? 2 : 4));
localparam CFG_CTL_QUEUE_DEPTH = 8;
localparam CFG_ENABLE_QUEUE = 0;
localparam CFG_ENABLE_BURST_MERGE = 0;
localparam CFG_CMD_GEN_OUTPUT_REG = 1; // only in effect when CFG_ENABLE_QUEUE is set to '0'
localparam CFG_CTL_ARBITER_TYPE = "ROWCOL";
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_CODE_WIDTH = 8;
localparam CFG_ECC_MULTIPLES = CFG_DWIDTH_RATIO * CFG_ECC_MULTIPLES_16_24_40_72;
localparam CFG_PARTIAL_BE_PER_WORD_ENABLE = 1;
localparam CFG_ENABLE_BURST_GEN_OUTPUT_REG = 1;
localparam CFG_DISABLE_PRIORITY = 1;
localparam CFG_REG_GRANT = (CFG_DWIDTH_RATIO == 8) ? 0 : 1; // disable grant register for better efficiency in quarter rate
localparam CFG_REG_REQ = 0;
localparam CFG_RANK_TIMER_OUTPUT_REG = 1;
localparam CFG_ECC_DEC_REG = 1;
localparam CFG_ECC_RDATA_REG = 1;
localparam CFG_ECC_ENC_REG = 1; // only one of CFG_ECC_ENC_REG / CFG_WDATA_REG can be set to '1'
localparam CFG_WDATA_REG = 0; // only one of CFG_ECC_ENC_REG / CFG_WDATA_REG can be set to '1'
localparam CFG_DISABLE_READ_REODERING = 0;
localparam CFG_ENABLE_SHADOW_TBP = 0;
localparam CFG_CTL_SHADOW_TBP_NUM = CFG_CTL_TBP_NUM; // similar to TBP number
// Datapath buffer & fifo size calculation
localparam CFG_MAX_PENDING_RD_CMD = 16; // temporary
localparam CFG_MAX_PENDING_WR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_ERR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_RD_CMD_WIDTH = log2(CFG_MAX_PENDING_RD_CMD);
localparam CFG_WRDATA_ID_WIDTH = log2(CFG_MAX_PENDING_WR_CMD);
localparam CFG_ERRCMD_FIFO_ADDR_WIDTH = log2(CFG_MAX_PENDING_ERR_CMD);
localparam CFG_RDDATA_ID_WIDTH = CFG_RDBUFFER_ADDR_WIDTH - CFG_INT_SIZE_WIDTH;
localparam CFG_DATA_ID_WIDTH = (CFG_WRDATA_ID_WIDTH >= CFG_RDDATA_ID_WIDTH) ? CFG_WRDATA_ID_WIDTH : CFG_RDDATA_ID_WIDTH;
localparam integer CFG_DATA_ID_REMAINDER = 2**(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH);
localparam CFG_WRDATA_VEC_ID_WIDTH = CFG_MAX_PENDING_WR_CMD;
// AFI
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH;
localparam CFG_DRAM_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : CFG_MEM_IF_DQS_WIDTH; // Supports single / multiple DQS group of afi_wlat
localparam CFG_LOCAL_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : (((CFG_LOCAL_DATA_WIDTH / CFG_DWIDTH_RATIO) == CFG_MEM_IF_DQ_WIDTH) ? CFG_MEM_IF_DQS_WIDTH : CFG_MEM_IF_DQS_WIDTH - CFG_ECC_MULTIPLES_16_24_40_72); // Determine the wlat group for local data width (without ECC code)
// Derived timing parameters width
localparam T_PARAM_ACT_TO_RDWR_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_ACT_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_RD_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_BC_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_RD_AP_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_WR_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_BC_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_WR_AP_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_PCH_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_PCH_ALL_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 6; // temporary
localparam T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 6; // temporary
localparam T_PARAM_ARF_TO_VALID_WIDTH = 8; // temporary
localparam T_PARAM_PDN_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_SRF_TO_VALID_WIDTH = 10; // temporary
localparam T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10; // temporary
localparam T_PARAM_ARF_PERIOD_WIDTH = 13; // temporary
localparam T_PARAM_PDN_PERIOD_WIDTH = 16; // temporary
localparam T_PARAM_POWER_SAVING_EXIT_WIDTH = 6; // temporary
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam integer CFG_WRDATA_ID_WIDTH_SQRD = 2**CFG_WRDATA_ID_WIDTH;
// Clock and reset
input ctl_clk;
input ctl_reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// Sideband signals
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
// Controller commands to the AFI interface
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
output [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
// Controller read and write data to the AFI interface
input [CFG_WLAT_BUS_WIDTH - 1 : 0] afi_wlat;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
output [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
output [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
input [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Status and control signal to the AFI interface
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output ctl_init_req;
output [CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n ;
output [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// cfg: general
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd;
// cfg: address mapping signals
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// cfg: timing parameters
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
// cfg: extra timing parameters
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// cfg: control signals
input [CFG_PORT_WIDTH_REORDER_DATA - 1 : 0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
input [CFG_PORT_WIDTH_USER_RFSH - 1 : 0] cfg_user_rfsh;
input [CFG_PORT_WIDTH_REGDIMM_ENABLE - 1 : 0] cfg_regdimm_enable;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// cfg: ecc signals
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites;
// cfg: odt
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
// sts: ecc signals
output ecc_interrupt;
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// calibration signals
input cfg_cal_req;
output sts_cal_fail;
output sts_cal_success;
// DQS enable tracking
input cfg_enable_dqs_tracking;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
//==============================================================================
//
// Wires
//
//==============================================================================
// General
wire init_done = ctl_cal_success;
wire sts_cal_success = ctl_cal_success;
wire sts_cal_fail = ctl_cal_fail;
wire ctl_cal_req = cfg_cal_req;
wire ctl_init_req;
wire [CFG_MEM_IF_DQS_WIDTH*CFG_MEM_IF_CHIP-1: 0] ctl_cal_byte_lane_sel_n = 0;
// alt_mem_ddrx_input_if
wire itf_cmd_ready;
wire itf_wr_data_ready;
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
wire cmd_valid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] cmd_address;
wire cmd_write;
wire cmd_read;
wire cmd_multicast;
wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] cmd_size;
wire cmd_priority;
wire cmd_autoprecharge;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_id;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] write_data;
wire [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] byte_en;
wire write_data_valid;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] write_data_id;
wire local_refresh_ack;
wire local_deep_powerdn_ack;
wire local_power_down_ack;
wire local_self_rfsh_ack;
wire local_init_done;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] rfsh_chip;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] deep_powerdn_chip;
wire self_rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] self_rfsh_chip;
// alt_mem_ddrx_cmd_gen
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_row_addr;
wire cmd_gen_full;
// alt_mem_ddrx_tbp
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM - 1 : 0] row_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
wire [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
wire [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
wire [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_bank_active;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_timer_ready;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load_index;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
// alt_mem_ddrx_arbiter
wire [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
wire or_row_grant;
wire or_col_grant;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// alt_mem_ddrx_burst_gen
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
wire bg_interrupt_ready_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
wire bg_do_lmr_read = 0;
wire bg_do_refresh_1bank = 0;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
wire bg_doing_write;
wire bg_doing_read;
wire bg_rdwr_data_valid;
wire bg_interrupt_ready;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] bg_rddataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
wire [ 7 : 0] bg_to_lmr = 0;
// alt_mem_ddrx_addr_cmd_wrap
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
wire [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
wire [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
wire [CFG_AFI_IF_FR_ADDR_WIDTH - 1 : 0] lmr_opcode = 0;
// alt_mem_ddrx_rdwr_data_tmg
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
wire [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_read;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_first;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_first;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_last;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_last;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
// alt_mem_ddrx_wdata_path
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
wire wdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] wdatap_free_id_dataid;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] wdatap_free_id_wrdataid;
wire wr_data_mem_full;
wire [CFG_CTL_TBP_NUM - 1 : 0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [(CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS) - 1 : 0] wdatap_dm;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
wire [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// alt_mem_ddrx_rdata_path
wire rdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] rdatap_free_id_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] rdatap_free_id_rddataid;
wire read_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] read_data;
wire read_data_error;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] read_data_localid;
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
wire rdatap_rcvd_cmd;
wire rdatap_rcvd_corr_dropped;
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
wire ecc_rdata_valid;
wire [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
wire ecc_interrupt;
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// alt_mem_ddrx_sideband
wire rfsh_ack;
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire stall_row_arbiter;
wire stall_col_arbiter;
wire [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
wire [CFG_CTL_TBP_NUM - 1 : 0] sb_tbp_precharge_all;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// alt_mem_ddrx_rank_timer
wire [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_write;
// alt_mem_ddrx_timing_param
wire [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
wire [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
wire [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
wire [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
wire [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
wire [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
wire [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
wire [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
wire [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
wire [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
wire [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
wire [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
wire [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
wire [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
wire [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
wire [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
wire [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
wire [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
wire [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
wire [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
wire [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
wire [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
wire [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
wire [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
wire [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
wire [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
wire [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
wire [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
// Log 2 function
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
// register init_done signal
reg init_done_reg;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
init_done_reg <= 0;
end
else
begin
init_done_reg <= init_done;
end
end
//==============================================================================
// alt_mem_ddrx_input_if
//------------------------------------------------------------------------------
//
// Input interface block
//
// Info: Includes cmd channel, and both read and write channels
// * Optional half-rate bridge logic
//
//==============================================================================
alt_mem_ddrx_input_if #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE )
)
input_if_inst
(
.itf_cmd_ready (itf_cmd_ready ),
.itf_cmd_valid (itf_cmd_valid ),
.itf_cmd (itf_cmd ),
.itf_cmd_address (itf_cmd_address ),
.itf_cmd_burstlen (itf_cmd_burstlen ),
.itf_cmd_id (itf_cmd_id ),
.itf_cmd_priority (itf_cmd_priority ),
.itf_cmd_autopercharge (itf_cmd_autopercharge ),
.itf_cmd_multicast (itf_cmd_multicast ),
.itf_wr_data_ready (itf_wr_data_ready ),
.itf_wr_data_valid (itf_wr_data_valid ),
.itf_wr_data (itf_wr_data ),
.itf_wr_data_byte_en (itf_wr_data_byte_en ),
.itf_wr_data_begin (itf_wr_data_begin ),
.itf_wr_data_last (itf_wr_data_last ),
.itf_wr_data_id (itf_wr_data_id ),
.itf_rd_data_ready (itf_rd_data_ready ),
.itf_rd_data_valid (itf_rd_data_valid ),
.itf_rd_data (itf_rd_data ),
.itf_rd_data_error (itf_rd_data_error ),
.itf_rd_data_begin (itf_rd_data_begin ),
.itf_rd_data_last (itf_rd_data_last ),
.itf_rd_data_id (itf_rd_data_id ),
.itf_rd_data_id_early (itf_rd_data_id_early ),
.itf_rd_data_id_early_valid(itf_rd_data_id_early_valid ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.cmd_id (cmd_id ),
.write_data (write_data ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_id (write_data_id ),
.byte_en (byte_en ),
.write_data_valid (write_data_valid ),
.read_data (read_data ),
.read_data_valid (read_data_valid ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.read_data_begin ( ), // NOTICE: not connected?
.read_data_last ( ), // NOTICE: not connected?
.bg_do_read (bg_do_read ),
.bg_localid (bg_localid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.local_refresh_req (local_refresh_req ),
.local_refresh_chip (local_refresh_chip ),
.local_deep_powerdn_req (local_deep_powerdn_req ),
.local_deep_powerdn_chip (local_deep_powerdn_chip ),
.local_self_rfsh_req (local_self_rfsh_req ),
.local_self_rfsh_chip (local_self_rfsh_chip ),
.local_refresh_ack (local_refresh_ack ),
.local_deep_powerdn_ack (local_deep_powerdn_ack ),
.local_power_down_ack (local_power_down_ack ),
.local_self_rfsh_ack (local_self_rfsh_ack ),
.local_init_done (local_init_done ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.self_rfsh_ack (self_rfsh_ack ),
.init_done (init_done_reg )
);
//==============================================================================
// alt_mem_ddrx_cmd_gen
//------------------------------------------------------------------------------
//
// Command generator block
//
// Info: * generates cmd from local and internal ECC block
// * splitting and merging of all commands
// * optional queue for latency reduction purpose when no merging is required
//
//==============================================================================
alt_mem_ddrx_cmd_gen #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_QUEUE_DEPTH (CFG_CTL_QUEUE_DEPTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_ENABLE_QUEUE (CFG_ENABLE_QUEUE ),
.CFG_ENABLE_BURST_MERGE (CFG_ENABLE_BURST_MERGE ),
.CFG_CMD_GEN_OUTPUT_REG (CFG_CMD_GEN_OUTPUT_REG ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM )
)
cmd_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_load (tbp_load ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_multicast (cmd_gen_multicast ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_id (cmd_id ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_dataid ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_dataid ),
.tbp_load_index (tbp_load_index ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.data_partial_be (data_partial_be ),
.cfg_enable_cmd_split (CFG_ENABLE_CMD_SPLIT ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width )
);
//==============================================================================
// alt_mem_ddrx_tbp
//------------------------------------------------------------------------------
//
// Timing bank pool block
//
// Info: * parallel queue in which a cmd is present
// * tracks timer and bank status information of the command it hold
// * monitor other TBPs content to update status bit in itself such
// as the autoprecharge bit
// * pass timer value to another TBP if need arises
//
//==============================================================================
alt_mem_ddrx_tbp #
(
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM ),
.CFG_ENABLE_SHADOW_TBP (CFG_ENABLE_SHADOW_TBP ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_PORT_WIDTH_STARVE_LIMIT (CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_REORDER_DATA (CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_DATA_REORDERING_TYPE (CFG_DATA_REORDERING_TYPE ),
.CFG_DISABLE_READ_REODERING (CFG_DISABLE_READ_REODERING ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH )
)
tbp_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_empty (tbp_empty ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.row_req (row_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.col_req (col_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_precharge (tbp_precharge ),
.tbp_activate (tbp_activate ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.sb_do_precharge_all (sb_do_precharge_all ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.tbp_bank_active (tbp_bank_active ),
.tbp_timer_ready (tbp_timer_ready ),
.cfg_reorder_data (cfg_reorder_data ),
.tbp_load (tbp_load ),
.data_complete (data_complete ),
.cfg_starve_limit (cfg_starve_limit ),
.cfg_type (cfg_type )
);
//==============================================================================
// alt_mem_ddrx_arbiter
//------------------------------------------------------------------------------
//
// Arbiter block
//
// Info: Priority command-aging arbiter, it will grant command with priority
// first, during tie-break situation, oldest command will be granted.
// Read comment in arbiter code for more information
//
//==============================================================================
alt_mem_ddrx_arbiter #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY )
)
arbiter_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.row_req (row_req ),
.col_req (col_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_activate (tbp_activate ),
.tbp_precharge (tbp_precharge ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_write (can_write ),
.can_read (can_read ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size )
);
//==============================================================================
// alt_mem_ddrx_burst_gen
//------------------------------------------------------------------------------
//
// Burst generation block
//
// Info: Create DQ/DQS burst information for AFI block
//
//==============================================================================
alt_mem_ddrx_burst_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT (CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE (CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_ENABLE_BURST_GEN_OUTPUT_REG (CFG_ENABLE_BURST_GEN_OUTPUT_REG )
)
burst_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_burst_length (cfg_burst_length ),
.cfg_tccd (cfg_tccd ),
.cfg_enable_burst_interrupt (cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate (cfg_enable_burst_terminate ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size ),
.bg_do_write_combi (bg_do_write_combi ),
.bg_do_read_combi (bg_do_read_combi ),
.bg_do_burst_chop_combi (bg_do_burst_chop_combi ),
.bg_do_burst_terminate_combi (bg_do_burst_terminate_combi ),
.bg_do_activate_combi (bg_do_activate_combi ),
.bg_do_precharge_combi (bg_do_precharge_combi ),
.bg_to_chip_combi (bg_to_chip_combi ),
.bg_effective_size_combi (bg_effective_size_combi ),
.bg_interrupt_ready_combi (bg_interrupt_ready_combi ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr (bg_do_lmr ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_doing_write (bg_doing_write ),
.bg_doing_read (bg_doing_read ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.bg_interrupt_ready (bg_interrupt_ready ),
.bg_localid (bg_localid ),
.bg_dataid (bg_dataid ),
.bg_size (bg_size ),
.bg_effective_size (bg_effective_size )
);
//==============================================================================
// alt_mem_ddrx_addr_cmd_wrap
//------------------------------------------------------------------------------
//
// Address and command decoder block
//
// Info: Trasalate controller internal command into AFI command
//
//==============================================================================
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_to_chip = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0] | bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP ];
// wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] temp_to_bank = bg_to_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0] | bg_to_bank [2 * CFG_MEM_IF_BA_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH ];
// wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] temp_to_row = bg_to_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0] | bg_to_row [2 * CFG_MEM_IF_ROW_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH];
// wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] temp_to_col = bg_to_col [CFG_MEM_IF_COL_WIDTH - 1 : 0] | bg_to_col [2 * CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
//
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_refresh = bg_do_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_power_down = bg_do_power_down [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_power_down [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_self_refresh = bg_do_self_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_self_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_precharge_all = bg_do_precharge_all [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_precharge_all [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_deep_pdown = bg_do_deep_pdown [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_deep_pdown [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_zq_cal = bg_do_zq_cal [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_zq_cal [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
alt_mem_ddrx_addr_cmd_wrap #
(
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_AFI_IF_FR_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_LPDDR2_ENABLED (CFG_LPDDR2_ENABLED ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
addr_cmd_wrap_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_lmr (bg_do_lmr ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr_read (bg_do_lmr_read ),
.bg_do_refresh_1bank (bg_do_refresh_1bank ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_to_lmr (bg_to_lmr ),
.bg_dataid (bg_dataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.lmr_opcode (lmr_opcode ),
.afi_cke (afi_cke ),
.afi_cs_n (afi_cs_n ),
.afi_ras_n (afi_ras_n ),
.afi_cas_n (afi_cas_n ),
.afi_we_n (afi_we_n ),
.afi_ba (afi_ba ),
.afi_addr (afi_addr ),
.afi_rst_n (afi_rst_n ),
.afi_odt (afi_odt )
);
//==============================================================================
// alt_mem_ddrx_odt_gen
//------------------------------------------------------------------------------
//
// ODT generation block
//
// Info: Generate ODT information based on user configuration
//
//==============================================================================
// alt_mem_ddrx_odt_gen #
// (
// .CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
// .CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
// .CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
// .CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
// .CFG_OUTPUT_REGD (CFG_OUTPUT_REGD ),
// .CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
// .CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
// .CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
// .CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE )
// )
// odt_gen_inst
// (
// .ctl_clk (ctl_clk ),
// .ctl_reset_n (ctl_reset_n ),
// .cfg_type (cfg_type ),
// .cfg_tcl (cfg_tcl ),
// .cfg_cas_wr_lat (cfg_cas_wr_lat ),
// .cfg_add_lat (cfg_add_lat ),
// .cfg_write_odt_chip (cfg_write_odt_chip ),
// .cfg_read_odt_chip (cfg_read_odt_chip ),
// .cfg_burst_length (cfg_burst_length ),
// .bg_do_read (bg_do_read ),
// .bg_do_write (bg_do_write ),
// .bg_to_chip (bg_to_chip ),
// .afi_odt (afi_odt )
// );
//==============================================================================
// alt_mem_ddrx_rdwr_data_tmg
//------------------------------------------------------------------------------
//
// Read / write data timing block
//
// Info: Adjust read and write data timing based on AFI information
//
//==============================================================================
alt_mem_ddrx_rdwr_data_tmg #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DM_WIDTH (CFG_MEM_IF_DM_WIDTH ),
.CFG_WLAT_BUS_WIDTH (CFG_WLAT_BUS_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
rdwr_data_tmg_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_output_regd (cfg_output_regd ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_doing_read (bg_doing_read ),
.bg_doing_write (bg_doing_write ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.dataid (bg_dataid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_wdata (ecc_wdata ),
.ecc_dm (ecc_dm ),
.afi_wlat (afi_wlat ),
.afi_doing_read (afi_rdata_en ),
.afi_doing_read_full (afi_rdata_en_full ),
.ecc_wdata_fifo_read (ecc_wdata_fifo_read ),
.ecc_wdata_fifo_dataid (ecc_wdata_fifo_dataid ),
.ecc_wdata_fifo_dataid_vector (ecc_wdata_fifo_dataid_vector ),
.ecc_wdata_fifo_rmw_correct (ecc_wdata_fifo_rmw_correct ),
.ecc_wdata_fifo_rmw_partial (ecc_wdata_fifo_rmw_partial ),
.ecc_wdata_fifo_read_first (ecc_wdata_fifo_read_first ),
.ecc_wdata_fifo_dataid_first (ecc_wdata_fifo_dataid_first ),
.ecc_wdata_fifo_dataid_vector_first (ecc_wdata_fifo_dataid_vector_first ),
.ecc_wdata_fifo_rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.ecc_wdata_fifo_rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.ecc_wdata_fifo_first_vector (ecc_wdata_fifo_first_vector ),
.ecc_wdata_fifo_read_last (ecc_wdata_fifo_read_last ),
.ecc_wdata_fifo_dataid_last (ecc_wdata_fifo_dataid_last ),
.ecc_wdata_fifo_dataid_vector_last (ecc_wdata_fifo_dataid_vector_last ),
.ecc_wdata_fifo_rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.ecc_wdata_fifo_rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.afi_dqs_burst (afi_dqs_burst ),
.afi_wdata_valid (afi_wdata_valid ),
.afi_wdata (afi_wdata ),
.afi_dm (afi_dm )
);
//==============================================================================
// alt_mem_ddrx_wdata_path
//------------------------------------------------------------------------------
//
// Write data path block
//
// Info: Handles write data processing
//
//==============================================================================
// match datapath id width, with command path id width
generate
begin : gen_resolve_datap_id
genvar i;
for (i = 0;i < CFG_DRAM_WLAT_GROUP;i = i + 1)
begin : write_dataid_per_dqs_group
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ];
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH];
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ]};
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = {{CFG_DATA_ID_REMAINDER {1'b0}},ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH]};
end
end
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_WRDATA_ID_WIDTH){1'b0}},wdatap_free_id_wrdataid};
assign ecc_wdata_wrdataid_first = ecc_wdata_fifo_dataid_first;
assign ecc_wdata_wrdataid_vector_first = ecc_wdata_fifo_dataid_vector_first;
assign ecc_wdata_wrdataid_last = ecc_wdata_fifo_dataid_last;
assign ecc_wdata_wrdataid_vector_last = ecc_wdata_fifo_dataid_vector_last;
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = wdatap_free_id_wrdataid[CFG_DATA_ID_WIDTH-1:0];
assign ecc_wdata_wrdataid_first = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_first};
assign ecc_wdata_wrdataid_vector_first = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_first};
assign ecc_wdata_wrdataid_last = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_last};
assign ecc_wdata_wrdataid_vector_last = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_last};
end
if (CFG_RDDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_RDDATA_ID_WIDTH){1'b0}},rdatap_free_id_rddataid};
assign bg_rddataid = bg_dataid[CFG_RDDATA_ID_WIDTH-1:0];
end
else // (CFG_RDDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
assign bg_rddataid = {{(CFG_RDDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},bg_dataid};
end
end
endgenerate
alt_mem_ddrx_wdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_WRDATA_ID_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP ),
.CFG_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_BUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_PARTIAL_BE_PER_WORD_ENABLE (CFG_PARTIAL_BE_PER_WORD_ENABLE ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES (CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH )
)
wdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites (cfg_enable_ecc_code_overwrites ),
.cfg_interface_width (cfg_interface_width ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_wrdataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.tbp_load_index (tbp_load_index ),
.proc_size (proc_size ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_en (write_data_valid ),
.write_data (write_data ),
.byte_en (byte_en ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.data_partial_be (data_partial_be ),
.doing_write (ecc_wdata_fifo_read ),
.dataid (ecc_wdata_wrdataid ),
.dataid_vector (ecc_wdata_wrdataid_vector ),
.rdwr_data_valid (ecc_wdata_fifo_read ),
.rmw_correct (ecc_wdata_fifo_rmw_correct ),
.rmw_partial (ecc_wdata_fifo_rmw_partial ),
.doing_write_first (ecc_wdata_fifo_read_first ),
.dataid_first (ecc_wdata_wrdataid_first ),
.dataid_vector_first (ecc_wdata_wrdataid_vector_first ),
.rdwr_data_valid_first (ecc_wdata_fifo_read_first ),
.rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.doing_write_first_vector (ecc_wdata_fifo_first_vector ),
.rdwr_data_valid_first_vector (ecc_wdata_fifo_first_vector ),
.doing_write_last (ecc_wdata_fifo_read_last ),
.dataid_last (ecc_wdata_wrdataid_last ),
.dataid_vector_last (ecc_wdata_wrdataid_vector_last ),
.rdwr_data_valid_last (ecc_wdata_fifo_read_last ),
.rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_dm (wdatap_dm ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_rdata_path
//------------------------------------------------------------------------------
//
// Read data path block
//
// Info: Handles read data processing
//
//==============================================================================
alt_mem_ddrx_rdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_RDDATA_ID_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_BUFFER_ADDR_WIDTH (CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MAX_READ_CMD_NUM_WIDTH (CFG_MAX_PENDING_RD_CMD_WIDTH ),
.CFG_RDATA_RETURN_MODE (CFG_RDATA_RETURN_MODE ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_ERRCMD_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH )
)
rdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_rddataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.read_data_valid (read_data_valid ),
.read_data (read_data ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.bg_do_read (bg_do_read ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_column (bg_to_col ),
.bg_dataid (bg_rddataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_rdata (ecc_rdata ),
.ecc_rdatav (ecc_rdata_valid ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
//------------------------------------------------------------------------------
//
// ECC encoder/decoder block
//
// Info: Encode write data and decode read data, correct single bit error
// and detect double bit errors
//
//==============================================================================
alt_mem_ddrx_ecc_encoder_decoder_wrapper #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR),
.CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR ),
.STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR ),
.STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR ),
.STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT ),
.STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT ),
.STS_PORT_WIDTH_CORR_DROP_ERROR (STS_PORT_WIDTH_CORR_DROP_ERROR ),
.STS_PORT_WIDTH_CORR_DROP_COUNT (STS_PORT_WIDTH_CORR_DROP_COUNT )
)
ecc_encoder_decoder_wrapper_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_interface_width (cfg_interface_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_gen_sbe (cfg_gen_sbe ),
.cfg_gen_dbe (cfg_gen_dbe ),
.cfg_enable_intr (cfg_enable_intr ),
.cfg_mask_sbe_intr (cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr (cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr (cfg_mask_corr_dropped_intr ),
.cfg_clr_intr (cfg_clr_intr ),
.wdatap_dm (wdatap_dm ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.afi_rdata (afi_rdata ),
.afi_rdata_valid (afi_rdata_valid ),
.ecc_rdata (ecc_rdata ),
.ecc_rdata_valid (ecc_rdata_valid ),
.ecc_dm (ecc_dm ),
.ecc_wdata (ecc_wdata ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.ecc_interrupt (ecc_interrupt ),
.sts_sbe_error (sts_sbe_error ),
.sts_dbe_error (sts_dbe_error ),
.sts_sbe_count (sts_sbe_count ),
.sts_dbe_count (sts_dbe_count ),
.sts_err_addr (sts_err_addr ),
.sts_corr_dropped (sts_corr_dropped ),
.sts_corr_dropped_count (sts_corr_dropped_count ),
.sts_corr_dropped_addr (sts_corr_dropped_addr )
);
//==============================================================================
// alt_mem_ddrx_sideband
//------------------------------------------------------------------------------
//
// Sideband block
//
// Info: Monitor and issue sideband specific commands such as user/auto
// refresh, self refresh, power down, deep power down,
// precharge all and zq calibration commands
//
//==============================================================================
alt_mem_ddrx_sideband #
(
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_MEM_IF_CLK_PAIR_COUNT (CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH )
)
sideband_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.self_rfsh_ack (self_rfsh_ack ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.stall_chip (stall_chip ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.ctl_mem_clk_disable (ctl_mem_clk_disable ),
.ctl_init_req (ctl_init_req ),
.ctl_cal_success (ctl_cal_success ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit ),
.tbp_empty (tbp_empty ),
.tbp_bank_active (tbp_bank_active ),
.tbp_timer_ready (tbp_timer_ready ),
.row_grant (or_row_grant ),
.col_grant (or_col_grant ),
.afi_ctl_refresh_done (afi_ctl_refresh_done ),
.afi_seq_busy (afi_seq_busy ),
.afi_ctl_long_idle (afi_ctl_long_idle ),
.cfg_enable_dqs_tracking (cfg_enable_dqs_tracking ),
.cfg_user_rfsh (cfg_user_rfsh ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_regdimm_enable (cfg_regdimm_enable )
);
//==============================================================================
// alt_mem_ddrx_rank_timer
//------------------------------------------------------------------------------
//
// Rank timer block
//
// Info: Monitor rank specific timing parameter for activate, precharge,
// read and write commands
//
//==============================================================================
alt_mem_ddrx_rank_timer #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH )
)
rank_timer_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.bg_do_write (bg_do_write_combi ),
.bg_do_read (bg_do_read_combi ),
.bg_do_burst_chop (bg_do_burst_chop_combi ),
.bg_do_burst_terminate (bg_do_burst_terminate_combi ),
.bg_do_activate (bg_do_activate_combi ),
.bg_do_precharge (bg_do_precharge_combi ),
.bg_to_chip (bg_to_chip_combi ),
.bg_effective_size (bg_effective_size_combi ),
.bg_interrupt_ready (bg_interrupt_ready_combi ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.stall_chip (stall_chip ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_read (can_read ),
.can_write (can_write )
);
//==============================================================================
// alt_mem_ddrx_timing_param
//------------------------------------------------------------------------------
//
// Timing parameter block
//
// Info: Pre-calculate required timing parameters for each memory commands
// based on memory type
//
//==============================================================================
alt_mem_ddrx_timing_param #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD (CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW (CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC (CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI (CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD (CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP (CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR (CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR (CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP (CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS (CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC (CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD (CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES (CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES (CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES (CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES (CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH )
)
timing_param_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_type (cfg_type ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_tcl (cfg_tcl ),
.cfg_trrd (cfg_trrd ),
.cfg_tfaw (cfg_tfaw ),
.cfg_trfc (cfg_trfc ),
.cfg_trefi (cfg_trefi ),
.cfg_trcd (cfg_trcd ),
.cfg_trp (cfg_trp ),
.cfg_twr (cfg_twr ),
.cfg_twtr (cfg_twtr ),
.cfg_trtp (cfg_trtp ),
.cfg_tras (cfg_tras ),
.cfg_trc (cfg_trc ),
.cfg_tccd (cfg_tccd ),
.cfg_tmrd (cfg_tmrd ),
.cfg_self_rfsh_exit_cycles (cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles (cfg_pdn_exit_cycles ),
.cfg_auto_pd_cycles (cfg_auto_pd_cycles ),
.cfg_power_saving_exit_cycles (cfg_power_saving_exit_cycles ),
.cfg_extra_ctl_clk_act_to_rdwr (cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch (cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act (cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd (cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip (cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr (cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc (cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip (cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch (cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid (cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr (cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip (cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd (cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc (cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip (cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch (cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid (cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid (cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid (cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank (cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act (cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid (cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid (cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid (cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal (cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period (cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period (cfg_extra_ctl_clk_pdn_period ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit )
);
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//////////////////////////////////////////////////////////////////////////////
// This module is a ST wrapper for the soft IP NextGen controller and the MMR
//////////////////////////////////////////////////////////////////////////////
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
module alt_mem_ddrx_controller_st_top(
clk,
half_clk,
reset_n,
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_init_req,
afi_mem_clk_disable,
afi_cal_byte_lane_sel_n,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_init_done,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_deep_powerdn_ack,
local_refresh_req,
local_refresh_chip,
local_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_multicast,
local_priority,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_burst_count,
csr_beginbursttransfer,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest
);
//////////////////////////////////////////////////////////////////////////////
parameter LOCAL_SIZE_WIDTH = "";
parameter LOCAL_ADDR_WIDTH = "";
parameter LOCAL_DATA_WIDTH = "";
parameter LOCAL_BE_WIDTH = "";
parameter LOCAL_ID_WIDTH = "";
parameter LOCAL_CS_WIDTH = "";
parameter MEM_IF_ADDR_WIDTH = "";
parameter MEM_IF_CLK_PAIR_COUNT = "";
parameter LOCAL_IF_TYPE = "";
parameter DWIDTH_RATIO = "";
parameter CTL_ODT_ENABLED = "";
parameter CTL_OUTPUT_REGD = "";
parameter CTL_TBP_NUM = "";
parameter WRBUFFER_ADDR_WIDTH = "";
parameter RDBUFFER_ADDR_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_IF_CHIP = "";
parameter MEM_IF_BANKADDR_WIDTH = "";
parameter MEM_IF_ROW_WIDTH = "";
parameter MEM_IF_COL_WIDTH = "";
parameter MEM_IF_ODT_WIDTH = "";
parameter MEM_IF_DQS_WIDTH = "";
parameter MEM_IF_DWIDTH = "";
parameter MEM_IF_DM_WIDTH = "";
parameter MAX_MEM_IF_CS_WIDTH = "";
parameter MAX_MEM_IF_CHIP = "";
parameter MAX_MEM_IF_BANKADDR_WIDTH = "";
parameter MAX_MEM_IF_ROWADDR_WIDTH = "";
parameter MAX_MEM_IF_COLADDR_WIDTH = "";
parameter MAX_MEM_IF_ODT_WIDTH = "";
parameter MAX_MEM_IF_DQS_WIDTH = "";
parameter MAX_MEM_IF_DQ_WIDTH = "";
parameter MAX_MEM_IF_MASK_WIDTH = "";
parameter MAX_LOCAL_DATA_WIDTH = "";
parameter CFG_TYPE = "";
parameter CFG_INTERFACE_WIDTH = "";
parameter CFG_BURST_LENGTH = "";
parameter CFG_DEVICE_WIDTH = "";
parameter CFG_REORDER_DATA = "";
parameter CFG_DATA_REORDERING_TYPE = "";
parameter CFG_STARVE_LIMIT = "";
parameter CFG_ADDR_ORDER = "";
parameter MEM_CAS_WR_LAT = "";
parameter MEM_ADD_LAT = "";
parameter MEM_TCL = "";
parameter MEM_TRRD = "";
parameter MEM_TFAW = "";
parameter MEM_TRFC = "";
parameter MEM_TREFI = "";
parameter MEM_TRCD = "";
parameter MEM_TRP = "";
parameter MEM_TWR = "";
parameter MEM_TWTR = "";
parameter MEM_TRTP = "";
parameter MEM_TRAS = "";
parameter MEM_TRC = "";
parameter CFG_TCCD = "";
parameter MEM_AUTO_PD_CYCLES = "";
parameter CFG_SELF_RFSH_EXIT_CYCLES = "";
parameter CFG_PDN_EXIT_CYCLES = "";
parameter CFG_POWER_SAVING_EXIT_CYCLES = "";
parameter CFG_MEM_CLK_ENTRY_CYCLES = "";
parameter MEM_TMRD_CK = "";
parameter CTL_ECC_ENABLED = "";
parameter CTL_ECC_RMW_ENABLED = "";
parameter CTL_ECC_MULTIPLES_16_24_40_72 = "";
parameter CFG_GEN_SBE = "";
parameter CFG_GEN_DBE = "";
parameter CFG_ENABLE_INTR = "";
parameter CFG_MASK_SBE_INTR = "";
parameter CFG_MASK_DBE_INTR = "";
parameter CFG_MASK_CORRDROP_INTR = 0;
parameter CFG_CLR_INTR = "";
parameter CTL_USR_REFRESH = "";
parameter CTL_REGDIMM_ENABLED = "";
parameter CTL_ENABLE_BURST_INTERRUPT = "";
parameter CTL_ENABLE_BURST_TERMINATE = "";
parameter CFG_WRITE_ODT_CHIP = "";
parameter CFG_READ_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_WRITE_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_READ_ODT_CHIP = "";
parameter MEM_IF_CKE_WIDTH = "";//check
parameter CTL_CSR_ENABLED = "";
parameter CFG_ENABLE_NO_DM = "";
parameter CSR_ADDR_WIDTH = "";
parameter CSR_DATA_WIDTH = "";
parameter CSR_BE_WIDTH = "";
parameter CFG_ENABLE_DQS_TRACKING = 0;
parameter CFG_WLAT_BUS_WIDTH = 6;
parameter CFG_RLAT_BUS_WIDTH = 6;
parameter MEM_IF_RD_TO_WR_TURNAROUND_OCT = "";
parameter MEM_IF_WR_TO_RD_TURNAROUND_OCT = "";
parameter CTL_RD_TO_PCH_EXTRA_CLK = 0;
//////////////////////////////////////////////////////////////////////////////
localparam CFG_LOCAL_SIZE_WIDTH = LOCAL_SIZE_WIDTH;
localparam CFG_LOCAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH;
localparam CFG_LOCAL_DATA_WIDTH = LOCAL_DATA_WIDTH;
localparam CFG_LOCAL_BE_WIDTH = LOCAL_BE_WIDTH;
localparam CFG_LOCAL_ID_WIDTH = LOCAL_ID_WIDTH;
localparam CFG_LOCAL_IF_TYPE = LOCAL_IF_TYPE;
localparam CFG_MEM_IF_ADDR_WIDTH = MEM_IF_ADDR_WIDTH;
localparam CFG_MEM_IF_CLK_PAIR_COUNT = MEM_IF_CLK_PAIR_COUNT;
localparam CFG_DWIDTH_RATIO = DWIDTH_RATIO;
localparam CFG_ODT_ENABLED = CTL_ODT_ENABLED;
localparam CFG_CTL_TBP_NUM = CTL_TBP_NUM;
localparam CFG_WRBUFFER_ADDR_WIDTH = WRBUFFER_ADDR_WIDTH;
localparam CFG_RDBUFFER_ADDR_WIDTH = RDBUFFER_ADDR_WIDTH;
localparam CFG_MEM_IF_CS_WIDTH = MEM_IF_CS_WIDTH;
localparam CFG_MEM_IF_CHIP = MEM_IF_CHIP;
localparam CFG_MEM_IF_BA_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_MEM_IF_ROW_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_MEM_IF_COL_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_MEM_IF_CKE_WIDTH = MEM_IF_CKE_WIDTH;
localparam CFG_MEM_IF_ODT_WIDTH = MEM_IF_ODT_WIDTH;
localparam CFG_MEM_IF_DQS_WIDTH = MEM_IF_DQS_WIDTH;
localparam CFG_MEM_IF_DQ_WIDTH = MEM_IF_DWIDTH;
localparam CFG_MEM_IF_DM_WIDTH = MEM_IF_DM_WIDTH;
localparam CFG_COL_ADDR_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_ROW_ADDR_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_BANK_ADDR_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_CS_ADDR_WIDTH = LOCAL_CS_WIDTH;
localparam CFG_CAS_WR_LAT = MEM_CAS_WR_LAT;
localparam CFG_ADD_LAT = MEM_ADD_LAT;
localparam CFG_TCL = MEM_TCL;
localparam CFG_TRRD = MEM_TRRD;
localparam CFG_TFAW = MEM_TFAW;
localparam CFG_TRFC = MEM_TRFC;
localparam CFG_TREFI = MEM_TREFI;
localparam CFG_TRCD = MEM_TRCD;
localparam CFG_TRP = MEM_TRP;
localparam CFG_TWR = MEM_TWR;
localparam CFG_TWTR = MEM_TWTR;
localparam CFG_TRTP = MEM_TRTP;
localparam CFG_TRAS = MEM_TRAS;
localparam CFG_TRC = MEM_TRC;
localparam CFG_AUTO_PD_CYCLES = MEM_AUTO_PD_CYCLES;
localparam CFG_TMRD = MEM_TMRD_CK;
localparam CFG_ENABLE_ECC = CTL_ECC_ENABLED;
localparam CFG_ENABLE_AUTO_CORR = CTL_ECC_RMW_ENABLED;
localparam CFG_ECC_MULTIPLES_16_24_40_72 = CTL_ECC_MULTIPLES_16_24_40_72;
localparam CFG_ENABLE_ECC_CODE_OVERWRITES = 1'b1;
localparam CFG_CAL_REQ = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH = 0 + CTL_RD_TO_PCH_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0;
localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD = 0;
localparam CFG_OUTPUT_REGD = CTL_OUTPUT_REGD;
localparam CFG_MASK_CORR_DROPPED_INTR = 0;
localparam CFG_USER_RFSH = CTL_USR_REFRESH;
localparam CFG_REGDIMM_ENABLE = CTL_REGDIMM_ENABLED;
localparam CFG_ENABLE_BURST_INTERRUPT = CTL_ENABLE_BURST_INTERRUPT;
localparam CFG_ENABLE_BURST_TERMINATE = CTL_ENABLE_BURST_TERMINATE;
localparam CFG_PORT_WIDTH_TYPE = 3;
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
localparam CFG_PORT_WIDTH_BURST_LENGTH = 5;
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 4;
localparam CFG_PORT_WIDTH_REORDER_DATA = 1;
localparam CFG_PORT_WIDTH_STARVE_LIMIT = 6;
localparam CFG_PORT_WIDTH_OUTPUT_REGD = 1;
localparam CFG_PORT_WIDTH_ADDR_ORDER = 2;
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 4;
localparam CFG_PORT_WIDTH_ADD_LAT = 3;
localparam CFG_PORT_WIDTH_TCL = 4;
localparam CFG_PORT_WIDTH_TRRD = 4;
localparam CFG_PORT_WIDTH_TFAW = 6;
localparam CFG_PORT_WIDTH_TRFC = 8;
localparam CFG_PORT_WIDTH_TREFI = 13;
localparam CFG_PORT_WIDTH_TRCD = 4;
localparam CFG_PORT_WIDTH_TRP = 4;
localparam CFG_PORT_WIDTH_TWR = 4;
localparam CFG_PORT_WIDTH_TWTR = 4;
localparam CFG_PORT_WIDTH_TRTP = 4;
localparam CFG_PORT_WIDTH_TRAS = 5;
localparam CFG_PORT_WIDTH_TRC = 6;
localparam CFG_PORT_WIDTH_TCCD = 4;
localparam CFG_PORT_WIDTH_TMRD = 3;
localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10;
localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4;
localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4;
localparam CFG_PORT_WIDTH_ENABLE_ECC = 1;
localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1;
localparam CFG_PORT_WIDTH_GEN_SBE = 1;
localparam CFG_PORT_WIDTH_GEN_DBE = 1;
localparam CFG_PORT_WIDTH_ENABLE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1;
localparam CFG_PORT_WIDTH_CLR_INTR = 1;
localparam CFG_PORT_WIDTH_USER_RFSH = 1;
localparam CFG_PORT_WIDTH_SELF_RFSH = 1;
localparam CFG_PORT_WIDTH_REGDIMM_ENABLE = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1;
localparam CFG_RDATA_RETURN_MODE = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
localparam CFG_LPDDR2_ENABLED = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
localparam STS_PORT_WIDTH_SBE_ERROR = 1;
localparam STS_PORT_WIDTH_DBE_ERROR = 1;
localparam STS_PORT_WIDTH_CORR_DROP_ERROR = 1;
localparam STS_PORT_WIDTH_SBE_COUNT = 8;
localparam STS_PORT_WIDTH_DBE_COUNT = 8;
localparam STS_PORT_WIDTH_CORR_DROP_COUNT = 8;
// We are supposed to use these parameters when the CSR is enabled
// but the MAX_ parameters are not defined
//localparam AFI_CS_WIDTH = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CKE_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ODT_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ADDR_WIDTH = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_BA_WIDTH = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
localparam AFI_CS_WIDTH = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CKE_WIDTH = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ODT_WIDTH = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ADDR_WIDTH = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_BA_WIDTH = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
localparam AFI_CMD_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_DQS_BURST_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_VALID_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_DM_WIDTH = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_WLAT_WIDTH = CFG_WLAT_BUS_WIDTH;
localparam AFI_RDATA_EN_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_RDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_RDATA_VALID_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_RLAT_WIDTH = CFG_RLAT_BUS_WIDTH;
localparam AFI_OTF_BITNUM = 12;
localparam AFI_AUTO_PRECHARGE_BITNUM = 10;
localparam AFI_MEM_CLK_DISABLE_WIDTH = CFG_MEM_IF_CLK_PAIR_COUNT;
//////////////////////////////////////////////////////////////////////////////
// BEGIN PORT SECTION
// Clk and reset signals
input clk;
input half_clk;
input reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
// AFI signals
output [AFI_CMD_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CKE_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BA_WIDTH - 1 : 0] afi_ba;
output [AFI_CMD_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_we_n;
output [AFI_DQS_BURST_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WDATA_VALID_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_WDATA_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en_full;
input [AFI_RDATA_WIDTH - 1 : 0] afi_rdata;
input [AFI_RDATA_VALID_WIDTH - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output afi_init_req;
output [AFI_MEM_CLK_DISABLE_WIDTH - 1 : 0] afi_mem_clk_disable;
output [AFI_CAL_BYTE_LANE_SEL_N_WIDTH - 1 : 0] afi_cal_byte_lane_sel_n;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// Sideband signals
output local_init_done;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
output local_deep_powerdn_ack;
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_powerdn_req;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_deep_powerdn_chip;
input local_multicast;
input local_priority;
// Csr & ecc signals
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [1 - 1 : 0] csr_burst_count;
input csr_beginbursttransfer;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
// END PORT SECTION
//////////////////////////////////////////////////////////////////////////////
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_reorder_data;
wire cfg_user_rfsh;
wire cfg_regdimm_enable;
wire cfg_enable_burst_interrupt;
wire cfg_enable_burst_terminate;
wire cfg_enable_dqs_tracking;
wire cfg_output_regd;
wire cfg_enable_no_dm;
wire cfg_enable_ecc_code_overwrites;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
wire [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
wire [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
wire [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
wire [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_clr_intr;
wire cfg_cal_req;
wire [4 - 1 : 0] cfg_clock_off;
wire cfg_self_rfsh;
wire cfg_ganged_arf;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
wire [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
wire [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
wire [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
wire cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] cfg_mem_bl;
wire cfg_user_ecc_en;
//ECC related outputs from controller to csr
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//
// Reconfiguration Support
//
// cfg_* signals may be reconfigured to different values using the Configuration Status Registers
// - some cfg_* signals are not reconfigurable, and are always assigned to parameters
// - When CSR is not enabled
// - cfg_* signals are assigned to parameters
// - when CSR is enabled
// - cfg_* signals are assigned to csr_* signals
// - csr_* signal generation based on Configuration Registers
// - default value for csr_* signals are based on parameters
// cfg_* signals that are not reconfigurable
assign cfg_type = CFG_TYPE;
assign cfg_interface_width = CFG_INTERFACE_WIDTH;
assign cfg_device_width = CFG_DEVICE_WIDTH;
assign cfg_enable_ecc_code_overwrites = CFG_ENABLE_ECC_CODE_OVERWRITES;
assign cfg_enable_no_dm = CFG_ENABLE_NO_DM;
assign cfg_output_regd = CFG_OUTPUT_REGD;
assign cfg_pdn_exit_cycles = CFG_PDN_EXIT_CYCLES;
assign cfg_power_saving_exit_cycles = CFG_POWER_SAVING_EXIT_CYCLES;
assign cfg_mem_clk_entry_cycles = CFG_MEM_CLK_ENTRY_CYCLES;
assign cfg_self_rfsh_exit_cycles = CFG_SELF_RFSH_EXIT_CYCLES;
assign cfg_tccd = CFG_TCCD;
assign cfg_tmrd = CFG_TMRD;
assign cfg_user_rfsh = CFG_USER_RFSH;
assign cfg_write_odt_chip = CFG_WRITE_ODT_CHIP;
assign cfg_read_odt_chip = CFG_READ_ODT_CHIP;
assign cfg_enable_dqs_tracking = CFG_ENABLE_DQS_TRACKING;
assign cfg_enable_burst_interrupt = CFG_ENABLE_BURST_INTERRUPT;
assign cfg_enable_burst_terminate = CFG_ENABLE_BURST_TERMINATE;
assign cfg_extra_ctl_clk_act_to_rdwr = CFG_EXTRA_CTL_CLK_ACT_TO_RDWR;
assign cfg_extra_ctl_clk_act_to_pch = CFG_EXTRA_CTL_CLK_ACT_TO_PCH;
assign cfg_extra_ctl_clk_act_to_act = CFG_EXTRA_CTL_CLK_ACT_TO_ACT;
assign cfg_extra_ctl_clk_rd_to_rd = CFG_EXTRA_CTL_CLK_RD_TO_RD;
assign cfg_extra_ctl_clk_rd_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_wr = CFG_EXTRA_CTL_CLK_RD_TO_WR;
assign cfg_extra_ctl_clk_rd_to_wr_bc = CFG_EXTRA_CTL_CLK_RD_TO_WR_BC;
assign cfg_extra_ctl_clk_rd_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_pch = CFG_EXTRA_CTL_CLK_RD_TO_PCH;
assign cfg_extra_ctl_clk_rd_ap_to_valid = CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID;
assign cfg_extra_ctl_clk_wr_to_wr = CFG_EXTRA_CTL_CLK_WR_TO_WR;
assign cfg_extra_ctl_clk_wr_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_rd = CFG_EXTRA_CTL_CLK_WR_TO_RD;
assign cfg_extra_ctl_clk_wr_to_rd_bc = CFG_EXTRA_CTL_CLK_WR_TO_RD_BC;
assign cfg_extra_ctl_clk_wr_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_pch = CFG_EXTRA_CTL_CLK_WR_TO_PCH;
assign cfg_extra_ctl_clk_wr_ap_to_valid = CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID;
assign cfg_extra_ctl_clk_pch_to_valid = CFG_EXTRA_CTL_CLK_PCH_TO_VALID;
assign cfg_extra_ctl_clk_pch_all_to_valid = CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID;
assign cfg_extra_ctl_clk_act_to_act_diff_bank = CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK;
assign cfg_extra_ctl_clk_four_act_to_act = CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT;
assign cfg_extra_ctl_clk_arf_to_valid = CFG_EXTRA_CTL_CLK_ARF_TO_VALID;
assign cfg_extra_ctl_clk_pdn_to_valid = CFG_EXTRA_CTL_CLK_PDN_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_valid = CFG_EXTRA_CTL_CLK_SRF_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_zq_cal = CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL;
assign cfg_extra_ctl_clk_arf_period = CFG_EXTRA_CTL_CLK_ARF_PERIOD;
assign cfg_extra_ctl_clk_pdn_period = CFG_EXTRA_CTL_CLK_PDN_PERIOD;
// cfg_* signals that are reconfigurable
generate
if (CTL_CSR_ENABLED == 1) begin
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] csr_cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] csr_cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] csr_cfg_addr_order;
wire csr_cfg_enable_ecc;
wire csr_cfg_enable_auto_corr;
wire csr_cfg_gen_sbe;
wire csr_cfg_gen_dbe;
wire csr_cfg_reorder_data;
wire csr_cfg_regdimm_enable;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] csr_cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] csr_cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] csr_cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] csr_cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] csr_cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] csr_cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] csr_cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] csr_cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] csr_cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] csr_cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] csr_cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] csr_cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] csr_cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] csr_cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] csr_cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] csr_cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] csr_cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] csr_cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] csr_cfg_cs_addr_width;
wire csr_cfg_enable_intr;
wire csr_cfg_mask_sbe_intr;
wire csr_cfg_mask_dbe_intr;
wire csr_cfg_clr_intr;
wire csr_cfg_cal_req;
wire [4 - 1 : 0] csr_cfg_clock_off;
wire csr_cfg_self_rfsh;
wire csr_cfg_ganged_arf;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] csr_cfg_starve_limit;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] csr_cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] csr_cfg_device_width;
wire csr_cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] csr_cfg_mem_bl;
wire csr_cfg_user_ecc_en;
assign cfg_burst_length = csr_cfg_burst_length;
assign cfg_reorder_data = csr_cfg_reorder_data;
assign cfg_starve_limit = csr_cfg_starve_limit;
assign cfg_addr_order = csr_cfg_addr_order;
assign cfg_col_addr_width = csr_cfg_col_addr_width;
assign cfg_row_addr_width = csr_cfg_row_addr_width;
assign cfg_bank_addr_width = csr_cfg_bank_addr_width;
assign cfg_cs_addr_width = csr_cfg_cs_addr_width;
assign cfg_cas_wr_lat = csr_cfg_cas_wr_lat;
assign cfg_add_lat = csr_cfg_add_lat;
assign cfg_tcl = csr_cfg_tcl;
assign cfg_trrd = csr_cfg_trrd;
assign cfg_tfaw = csr_cfg_tfaw;
assign cfg_trfc = csr_cfg_trfc;
assign cfg_trefi = csr_cfg_trefi;
assign cfg_trcd = csr_cfg_trcd;
assign cfg_trp = csr_cfg_trp;
assign cfg_twr = csr_cfg_twr;
assign cfg_twtr = csr_cfg_twtr;
assign cfg_trtp = csr_cfg_trtp;
assign cfg_tras = csr_cfg_tras;
assign cfg_trc = csr_cfg_trc;
assign cfg_enable_ecc = csr_cfg_enable_ecc;
assign cfg_enable_auto_corr = csr_cfg_enable_auto_corr;
assign cfg_gen_sbe = csr_cfg_gen_sbe;
assign cfg_gen_dbe = csr_cfg_gen_dbe;
assign cfg_enable_intr = csr_cfg_enable_intr;
assign cfg_mask_sbe_intr = csr_cfg_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_cfg_mask_dbe_intr;
assign cfg_mask_corr_dropped_intr = csr_cfg_mask_corr_dropped_intr;
assign cfg_clr_intr = csr_cfg_clr_intr;
assign cfg_regdimm_enable = csr_cfg_regdimm_enable;
assign cfg_cal_req = csr_cfg_cal_req;
assign cfg_auto_pd_cycles = csr_cfg_auto_pd_cycles;
alt_mem_ddrx_csr # (
.CFG_AVALON_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CFG_AVALON_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CFG_BURST_LENGTH ( CFG_BURST_LENGTH ),
.CFG_REORDER_DATA ( CFG_REORDER_DATA ),
.CFG_STARVE_LIMIT ( CFG_STARVE_LIMIT ),
.CFG_ADDR_ORDER ( CFG_ADDR_ORDER ),
.CFG_COL_ADDR_WIDTH ( CFG_COL_ADDR_WIDTH ),
.CFG_ROW_ADDR_WIDTH ( CFG_ROW_ADDR_WIDTH ),
.CFG_BANK_ADDR_WIDTH ( CFG_BANK_ADDR_WIDTH ),
.CFG_CS_ADDR_WIDTH ( CFG_CS_ADDR_WIDTH ),
.CFG_CAS_WR_LAT ( CFG_CAS_WR_LAT ),
.CFG_ADD_LAT ( CFG_ADD_LAT ),
.CFG_TCL ( CFG_TCL ),
.CFG_TRRD ( CFG_TRRD ),
.CFG_TFAW ( CFG_TFAW ),
.CFG_TRFC ( CFG_TRFC ),
.CFG_TREFI ( CFG_TREFI ),
.CFG_TRCD ( CFG_TRCD ),
.CFG_TRP ( CFG_TRP ),
.CFG_TWR ( CFG_TWR ),
.CFG_TWTR ( CFG_TWTR ),
.CFG_TRTP ( CFG_TRTP ),
.CFG_TRAS ( CFG_TRAS ),
.CFG_TRC ( CFG_TRC ),
.CFG_AUTO_PD_CYCLES ( CFG_AUTO_PD_CYCLES ),
.CFG_ENABLE_ECC ( CFG_ENABLE_ECC ),
.CFG_ENABLE_AUTO_CORR ( CFG_ENABLE_AUTO_CORR ),
.CFG_REGDIMM_ENABLE ( CFG_REGDIMM_ENABLE ),
.MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH )
) register_control_inst (
.avalon_mm_read ( csr_read_req ),
.avalon_mm_write ( csr_write_req ),
.avalon_mm_addr ( csr_addr ),
.avalon_mm_wdata ( csr_wdata ),
.avalon_mm_rdata ( csr_rdata ),
.avalon_mm_be ( csr_be ),
.avalon_mm_waitrequest ( csr_waitrequest ),
.avalon_mm_rdata_valid ( csr_rdata_valid ),
.cfg_burst_length ( csr_cfg_burst_length ),
.cfg_addr_order ( csr_cfg_addr_order ),
.cfg_enable_ecc ( csr_cfg_enable_ecc ),
.cfg_enable_auto_corr ( csr_cfg_enable_auto_corr ),
.cfg_gen_sbe ( csr_cfg_gen_sbe ),
.cfg_gen_dbe ( csr_cfg_gen_dbe ),
.cfg_reorder_data ( csr_cfg_reorder_data ),
.cfg_regdimm_enable ( csr_cfg_regdimm_enable ),
.cfg_cas_wr_lat ( csr_cfg_cas_wr_lat ),
.cfg_add_lat ( csr_cfg_add_lat ),
.cfg_tcl ( csr_cfg_tcl ),
.cfg_trrd ( csr_cfg_trrd ),
.cfg_tfaw ( csr_cfg_tfaw ),
.cfg_trfc ( csr_cfg_trfc ),
.cfg_trefi ( csr_cfg_trefi ),
.cfg_trcd ( csr_cfg_trcd ),
.cfg_trp ( csr_cfg_trp ),
.cfg_twr ( csr_cfg_twr ),
.cfg_twtr ( csr_cfg_twtr ),
.cfg_trtp ( csr_cfg_trtp ),
.cfg_tras ( csr_cfg_tras ),
.cfg_trc ( csr_cfg_trc ),
.cfg_auto_pd_cycles ( csr_cfg_auto_pd_cycles ),
.cfg_col_addr_width ( csr_cfg_col_addr_width ),
.cfg_row_addr_width ( csr_cfg_row_addr_width ),
.cfg_bank_addr_width ( csr_cfg_bank_addr_width ),
.cfg_cs_addr_width ( csr_cfg_cs_addr_width ),
.cfg_enable_intr ( csr_cfg_enable_intr ),
.cfg_mask_sbe_intr ( csr_cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( csr_cfg_mask_dbe_intr ),
.cfg_clr_intr ( csr_cfg_clr_intr ),
.cfg_clock_off ( csr_cfg_clock_off ),
.cfg_starve_limit ( csr_cfg_starve_limit ),
.cfg_mask_corr_dropped_intr ( csr_cfg_mask_corr_dropped_intr ),
.cfg_cal_req ( csr_cfg_cal_req ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.sts_cal_success ( afi_cal_success ),
.sts_cal_fail ( afi_cal_fail ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( sts_err_addr ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( sts_corr_dropped_addr ),
.ctl_clk ( clk ),
.ctl_rst_n ( reset_n )
);
end
else begin
assign csr_rdata = 0;
assign csr_rdata_valid = 0;
assign csr_waitrequest = 0;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_cs_addr_width = CFG_CS_ADDR_WIDTH;
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_enable_ecc = CFG_ENABLE_ECC;
assign cfg_enable_auto_corr = CFG_ENABLE_AUTO_CORR;
assign cfg_gen_sbe = CFG_GEN_SBE;
assign cfg_gen_dbe = CFG_GEN_DBE;
assign cfg_enable_intr = CFG_ENABLE_INTR;
assign cfg_mask_sbe_intr = CFG_MASK_SBE_INTR;
assign cfg_mask_dbe_intr = CFG_MASK_DBE_INTR;
assign cfg_mask_corr_dropped_intr = CFG_MASK_CORR_DROPPED_INTR;
assign cfg_clr_intr = CFG_CLR_INTR;
assign cfg_regdimm_enable = CFG_REGDIMM_ENABLE;
assign cfg_cal_req = CFG_CAL_REQ;
end
endgenerate
// Next Gen Controller
alt_mem_ddrx_controller # (
.CFG_LOCAL_SIZE_WIDTH ( CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH ( CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH ( CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH ( CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_IF_TYPE ( CFG_LOCAL_IF_TYPE ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_CLK_PAIR_COUNT ( CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_DWIDTH_RATIO ( CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED ( CFG_ODT_ENABLED ),
.CFG_LPDDR2_ENABLED ( CFG_LPDDR2_ENABLED ),
.CFG_CTL_TBP_NUM ( CFG_CTL_TBP_NUM ),
.CFG_DATA_REORDERING_TYPE ( CFG_DATA_REORDERING_TYPE ),
.CFG_WRBUFFER_ADDR_WIDTH ( CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_RDBUFFER_ADDR_WIDTH ( CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_ECC_MULTIPLES_16_24_40_72 ( CFG_ECC_MULTIPLES_16_24_40_72 ),
.CFG_MEM_IF_CS_WIDTH ( CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ODT_WIDTH ( CFG_MEM_IF_ODT_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH ( CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DM_WIDTH ( CFG_MEM_IF_DM_WIDTH ),
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH ( CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH ( CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_DEVICE_WIDTH ( CFG_PORT_WIDTH_DEVICE_WIDTH ),
.CFG_PORT_WIDTH_REORDER_DATA ( CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_PORT_WIDTH_STARVE_LIMIT ( CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_PORT_WIDTH_ADDR_ORDER ( CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH ( CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH ( CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH ( CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH ( CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT ( CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT ( CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL ( CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD ( CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW ( CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC ( CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI ( CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD ( CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP ( CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR ( CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR ( CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP ( CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS ( CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC ( CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD ( CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD ( CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ( CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES ( CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES ( CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ( CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ( CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.CFG_PORT_WIDTH_ENABLE_ECC ( CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR ( CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_GEN_SBE ( CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE ( CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR ( CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR ( CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR ( CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_CLR_INTR ( CFG_PORT_WIDTH_CLR_INTR ),
.CFG_PORT_WIDTH_USER_RFSH ( CFG_PORT_WIDTH_USER_RFSH ),
.CFG_PORT_WIDTH_SELF_RFSH ( CFG_PORT_WIDTH_SELF_RFSH ),
.CFG_PORT_WIDTH_REGDIMM_ENABLE ( CFG_PORT_WIDTH_REGDIMM_ENABLE ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ( CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ( CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP ( CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP ( CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_WLAT_BUS_WIDTH ( CFG_WLAT_BUS_WIDTH ),
.CFG_RDATA_RETURN_MODE ( CFG_RDATA_RETURN_MODE )
) controller_inst (
.ctl_clk ( clk ),
.ctl_reset_n ( reset_n ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_deep_powerdn_req ( local_deep_powerdn_req ),
.local_deep_powerdn_chip ( local_deep_powerdn_chip ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_deep_powerdn_ack ( local_deep_powerdn_ack ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_init_done ( local_init_done ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_rdata_en ( afi_rdata_en ),
.afi_rdata_en_full ( afi_rdata_en_full ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.ctl_cal_success ( afi_cal_success ),
.ctl_cal_fail ( afi_cal_fail ),
.ctl_cal_req ( afi_cal_req ),
.ctl_init_req ( afi_init_req ),
.ctl_mem_clk_disable ( afi_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( afi_cal_byte_lane_sel_n ),
.cfg_type ( cfg_type ),
.cfg_interface_width ( cfg_interface_width ),
.cfg_burst_length ( cfg_burst_length ),
.cfg_device_width ( cfg_device_width ),
.cfg_reorder_data ( cfg_reorder_data ),
.cfg_starve_limit ( cfg_starve_limit ),
.cfg_output_regd ( cfg_output_regd ),
.cfg_addr_order ( cfg_addr_order ),
.cfg_col_addr_width ( cfg_col_addr_width ),
.cfg_row_addr_width ( cfg_row_addr_width ),
.cfg_bank_addr_width ( cfg_bank_addr_width ),
.cfg_cs_addr_width ( cfg_cs_addr_width ),
.cfg_cas_wr_lat ( cfg_cas_wr_lat ),
.cfg_add_lat ( cfg_add_lat ),
.cfg_tcl ( cfg_tcl ),
.cfg_trrd ( cfg_trrd ),
.cfg_tfaw ( cfg_tfaw ),
.cfg_trfc ( cfg_trfc ),
.cfg_trefi ( cfg_trefi ),
.cfg_trcd ( cfg_trcd ),
.cfg_trp ( cfg_trp ),
.cfg_twr ( cfg_twr ),
.cfg_twtr ( cfg_twtr ),
.cfg_trtp ( cfg_trtp ),
.cfg_tras ( cfg_tras ),
.cfg_trc ( cfg_trc ),
.cfg_tccd ( cfg_tccd ),
.cfg_auto_pd_cycles ( cfg_auto_pd_cycles ),
.cfg_self_rfsh_exit_cycles ( cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles ( cfg_pdn_exit_cycles ),
.cfg_power_saving_exit_cycles ( cfg_power_saving_exit_cycles ),
.cfg_mem_clk_entry_cycles ( cfg_mem_clk_entry_cycles ),
.cfg_tmrd ( cfg_tmrd ),
.cfg_enable_ecc ( cfg_enable_ecc ),
.cfg_enable_auto_corr ( cfg_enable_auto_corr ),
.cfg_enable_no_dm ( cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites ( cfg_enable_ecc_code_overwrites ),
.cfg_cal_req ( cfg_cal_req ),
.cfg_gen_sbe ( cfg_gen_sbe ),
.cfg_gen_dbe ( cfg_gen_dbe ),
.cfg_enable_intr ( cfg_enable_intr ),
.cfg_mask_sbe_intr ( cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr ( cfg_mask_corr_dropped_intr ),
.cfg_clr_intr ( cfg_clr_intr ),
.cfg_user_rfsh ( cfg_user_rfsh ),
.cfg_regdimm_enable ( cfg_regdimm_enable ),
.cfg_enable_burst_interrupt ( cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate ( cfg_enable_burst_terminate ),
.cfg_write_odt_chip ( cfg_write_odt_chip ),
.cfg_read_odt_chip ( cfg_read_odt_chip ),
.cfg_extra_ctl_clk_act_to_rdwr ( cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch ( cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act ( cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd ( cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip ( cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr ( cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc ( cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip ( cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch ( cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid ( cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr ( cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip ( cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd ( cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc ( cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip ( cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch ( cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid ( cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid ( cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid ( cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank ( cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act ( cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid ( cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid ( cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid ( cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal ( cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period ( cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period ( cfg_extra_ctl_clk_pdn_period ),
.cfg_enable_dqs_tracking ( cfg_enable_dqs_tracking ),
.ecc_interrupt ( ecc_interrupt ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( sts_err_addr ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( sts_corr_dropped_addr ),
.afi_ctl_refresh_done ( afi_ctl_refresh_done ),
.afi_seq_busy ( afi_seq_busy ),
.afi_ctl_long_idle ( afi_ctl_long_idle )
);
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
//altera message_off 10230
module alt_mem_ddrx_csr #
( parameter
DWIDTH_RATIO = 2,
CTL_CSR_ENABLED = 1,
CTL_ECC_CSR_ENABLED = 1,
CTL_CSR_READ_ONLY = 0,
CTL_ECC_CSR_READ_ONLY = 0,
CFG_AVALON_ADDR_WIDTH = 8,
CFG_AVALON_DATA_WIDTH = 32,
MEM_IF_CLK_PAIR_COUNT = 1,
MEM_IF_DQS_WIDTH = 72,
CFG_CS_ADDR_WIDTH = 1, // same as MEM_IF_CHIP
CFG_ROW_ADDR_WIDTH = 13, // max supported row bits
CFG_COL_ADDR_WIDTH = 10, // max supported column bits
CFG_BANK_ADDR_WIDTH = 3, // max supported bank bits
CFG_ENABLE_ECC = 1,
CFG_ENABLE_AUTO_CORR = 1,
CFG_REGDIMM_ENABLE = 0,
// timing parameter width
CAS_WR_LAT_BUS_WIDTH = 4, // max will be 8 in DDR3
ADD_LAT_BUS_WIDTH = 3, // max will be 6 in DDR2
TCL_BUS_WIDTH = 4, // max will be 11 in DDR3
BL_BUS_WIDTH = 5, //
TRRD_BUS_WIDTH = 4, // 2 - 8
TFAW_BUS_WIDTH = 6, // 6 - 32
TRFC_BUS_WIDTH = 8, // 12 - 140?
TREFI_BUS_WIDTH = 13, // 780 - 6240
TRCD_BUS_WIDTH = 4, // 2 - 11
TRP_BUS_WIDTH = 4, // 2 - 11
TWR_BUS_WIDTH = 4, // 2 - 12
TWTR_BUS_WIDTH = 4, // 1 - 10
TRTP_BUS_WIDTH = 4, // 2 - 8
TRAS_BUS_WIDTH = 5, // 4 - 29
TRC_BUS_WIDTH = 6, // 8 - 40
AUTO_PD_BUS_WIDTH = 16, // same as CSR interface
STARVE_LIMIT_BUS_WIDTH = 8,
// timing parameter
CFG_CAS_WR_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_ADD_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_TCL = 0, // these timing parameter must be set properly for controller to work
CFG_BURST_LENGTH = 0, // these timing parameter must be set properly for controller to work
CFG_TRRD = 0, // these timing parameter must be set properly for controller to work
CFG_TFAW = 0, // these timing parameter must be set properly for controller to work
CFG_TRFC = 0, // these timing parameter must be set properly for controller to work
CFG_TREFI = 0, // these timing parameter must be set properly for controller to work
CFG_TRCD = 0, // these timing parameter must be set properly for controller to work
CFG_TRP = 0, // these timing parameter must be set properly for controller to work
CFG_TWR = 0, // these timing parameter must be set properly for controller to work
CFG_TWTR = 0, // these timing parameter must be set properly for controller to work
CFG_TRTP = 0, // these timing parameter must be set properly for controller to work
CFG_TRAS = 0, // these timing parameter must be set properly for controller to work
CFG_TRC = 0, // these timing parameter must be set properly for controller to work
CFG_AUTO_PD_CYCLES = 0, // these timing parameter must be set properly for controller to work
// parameters used by input interface
CFG_ADDR_ORDER = 1, // normally we will use '1' for chip, bank, row, column arrangement
CFG_REORDER_DATA = 0,
CFG_STARVE_LIMIT = 0,
MEM_IF_CSR_COL_WIDTH = 5,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 3,
MEM_IF_CSR_CS_WIDTH = 3
)
(
ctl_clk,
ctl_rst_n,
// csr interface (Avalon)
avalon_mm_addr,
avalon_mm_be,
avalon_mm_write,
avalon_mm_wdata,
avalon_mm_read,
avalon_mm_rdata,
avalon_mm_rdata_valid,
avalon_mm_waitrequest,
// input from PHY
sts_cal_success,
sts_cal_fail,
// input from state machine
local_power_down_ack,
local_self_rfsh_ack,
// input from ecc
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
// output to PHY
cfg_cal_req,
cfg_clock_off,
ctl_cal_byte_lane_sel_n,
// output to timer
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_burst_length,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_auto_pd_cycles,
// output to input interface
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// output to ecc
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// output to others
cfg_regdimm_enable,
cfg_reorder_data,
cfg_starve_limit
);
localparam integer CFG_MEM_IF_CS_WIDTH = (2**CFG_CS_ADDR_WIDTH);
input ctl_clk;
input ctl_rst_n;
input avalon_mm_write;
input avalon_mm_read;
input [CFG_AVALON_ADDR_WIDTH - 1 : 0] avalon_mm_addr;
input [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_wdata;
input [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] avalon_mm_be;
output avalon_mm_waitrequest;
output avalon_mm_rdata_valid;
output [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
// input from AFI
input sts_cal_success;
input sts_cal_fail;
// input from state machine
input local_power_down_ack;
input local_self_rfsh_ack;
// input from ecc
input sts_sbe_error;
input sts_dbe_error;
input sts_corr_dropped;
input [7 : 0] sts_sbe_count;
input [7 : 0] sts_dbe_count;
input [7 : 0] sts_corr_dropped_count;
input [31 : 0] sts_err_addr;
input [31 : 0] sts_corr_dropped_addr;
// output to PHY
output cfg_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
output [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
output [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
output [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
output [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
output [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
output [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
output [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
output [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
output [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
output [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
output [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
output [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
output [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
output [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
output [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
output [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
output [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
output [1 : 0] cfg_addr_order;
output cfg_reorder_data;
output [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
output [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
output [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
output [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
output [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
output cfg_enable_ecc;
output cfg_enable_auto_corr;
output cfg_gen_sbe;
output cfg_gen_dbe;
output cfg_enable_intr;
output cfg_mask_sbe_intr;
output cfg_mask_dbe_intr;
output cfg_mask_corr_dropped_intr;
output cfg_clr_intr;
output cfg_regdimm_enable;
wire avalon_mm_waitrequest;
wire avalon_mm_rdata_valid;
wire [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
reg int_write_req;
reg int_read_req;
reg int_rdata_valid;
reg [8 - 1 : 0] int_addr; // hard-coded to only 8 bits
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_wdata;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_rdata;
reg [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] int_be;
reg int_mask_avalon_mm_write;
reg int_mask_avalon_mm_read;
reg int_mask_ecc_avalon_mm_write;
reg int_mask_ecc_avalon_mm_read;
// output to PHY
wire cfg_cal_req;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
wire [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
wire [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
wire [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
wire [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
wire [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
wire [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
wire [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
wire [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
wire [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
wire [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
wire [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
wire [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
wire [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
wire [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
wire [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
wire [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
wire [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
wire [1 : 0] cfg_addr_order;
wire cfg_reorder_data;
wire [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
wire [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
wire [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
wire [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_mask_corr_dropped_intr;
wire cfg_clr_intr;
// output to others
wire cfg_regdimm_enable;
// CSR read registers
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_100;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_110;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_120;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_121;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_122;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_123;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_124;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_125;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_126;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_130;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_131;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_132;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_133;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_134;
/*------------------------------------------------------------------------------
CSR Interface
------------------------------------------------------------------------------*/
// Assign waitrequest signal to '0'
assign avalon_mm_waitrequest = 1'b0;
generate
if (!CTL_CSR_ENABLED && !CTL_ECC_CSR_ENABLED)
begin
// when both csr and ecc csr is disabled
assign avalon_mm_rdata = 0;
assign avalon_mm_rdata_valid = 0;
end
else
begin
// register all inputs
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_write_req <= 0;
int_read_req <= 0;
int_addr <= 0;
int_wdata <= 0;
int_be <= 0;
end
else
begin
int_addr <= avalon_mm_addr [7 : 0]; // we only need the bottom 8 bits
int_wdata <= avalon_mm_wdata;
int_be <= avalon_mm_be;
if (avalon_mm_write)
int_write_req <= 1'b1;
else
int_write_req <= 1'b0;
if (avalon_mm_read)
int_read_req <= 1'b1;
else
int_read_req <= 1'b0;
end
end
// Write and read request mask
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
if (CTL_CSR_READ_ONLY)
begin
int_mask_avalon_mm_write <= 1'b1;
int_mask_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
end
if (CTL_ECC_CSR_READ_ONLY)
begin
int_mask_ecc_avalon_mm_write <= 1'b1;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
Read Interface
------------------------------------------------------------------------------*/
assign avalon_mm_rdata = int_rdata;
assign avalon_mm_rdata_valid = int_rdata_valid;
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_rdata <= 0;
int_rdata_valid <= 0;
end
else
begin
if (int_read_req)
begin
if (int_addr == 8'h00)
int_rdata <= read_csr_register_100;
else if (int_addr == 8'h10)
int_rdata <= read_csr_register_110;
else if (int_addr == 8'h20)
int_rdata <= read_csr_register_120;
else if (int_addr == 8'h21)
int_rdata <= read_csr_register_121;
else if (int_addr == 8'h22)
int_rdata <= read_csr_register_122;
else if (int_addr == 8'h23)
int_rdata <= read_csr_register_123;
else if (int_addr == 8'h24)
int_rdata <= read_csr_register_124;
else if (int_addr == 8'h25)
int_rdata <= read_csr_register_125;
else if (int_addr == 8'h26)
int_rdata <= read_csr_register_126;
else if (int_addr == 8'h30)
int_rdata <= read_csr_register_130;
else if (int_addr == 8'h31)
int_rdata <= read_csr_register_131;
else if (int_addr == 8'h32)
int_rdata <= read_csr_register_132;
else if (int_addr == 8'h33)
int_rdata <= read_csr_register_133;
else if (int_addr == 8'h34)
int_rdata <= read_csr_register_134;
end
if (int_read_req)
int_rdata_valid <= 1'b1;
else
int_rdata_valid <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
CSR Registers
------------------------------------------------------------------------------*/
generate
genvar i;
if (!CTL_CSR_ENABLED) // when csr is disabled
begin
// assigning values to the top
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_cs_addr_width = CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_cal_req = 0;
assign cfg_clock_off = 0;
assign ctl_cal_byte_lane_sel_n = 0;
assign cfg_regdimm_enable = 1'b1; // udimm or rdimm determined by parameter CFG_REGDIMM_ENABLE
end
else
begin
/*------------------------------------------------------------------------------
0x100 ALTMEPHY Status and Control Register
------------------------------------------------------------------------------*/
reg csr_cal_success;
reg csr_cal_fail;
reg csr_cal_req;
reg [5 : 0] csr_clock_off;
// assign value back to top
assign cfg_cal_req = csr_cal_req;
assign cfg_clock_off = csr_clock_off [MEM_IF_CLK_PAIR_COUNT - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_req <= 0;
csr_clock_off <= 0;
end
else
begin
// write request
if (int_write_req && int_addr == 8'h00)
begin
if (int_be [0])
begin
csr_cal_req <= int_wdata [2] ;
end
if (int_be [1])
begin
csr_clock_off <= int_wdata [13 : 8];
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_success <= 0;
csr_cal_fail <= 0;
end
else
begin
csr_cal_success <= sts_cal_success;
csr_cal_fail <= sts_cal_fail;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_100 = 0;
// then we set individual bits
read_csr_register_100 [0] = csr_cal_success;
read_csr_register_100 [1] = csr_cal_fail;
read_csr_register_100 [2] = csr_cal_req;
read_csr_register_100 [13 : 8] = csr_clock_off;
end
/*------------------------------------------------------------------------------
0x110 Controller Status and Control Register
------------------------------------------------------------------------------*/
reg [15 : 0] csr_auto_pd_cycles;
reg csr_auto_pd_ack;
reg csr_self_rfsh; // yyong: remember to handle this
reg csr_self_rfsh_ack;
reg csr_ganged_arf; // yyong: remember to handle this
reg [1 : 0] csr_addr_order;
reg csr_reg_dimm; // yyong: remember to handle this
reg [1 : 0] csr_drate;
// assign value back to top
assign cfg_auto_pd_cycles = csr_auto_pd_cycles;
assign cfg_addr_order = csr_addr_order;
assign cfg_regdimm_enable = csr_reg_dimm;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_cycles <= CFG_AUTO_PD_CYCLES; // reset to default value
csr_self_rfsh <= 0;
csr_ganged_arf <= 0;
csr_addr_order <= CFG_ADDR_ORDER; // reset to default value
csr_reg_dimm <= CFG_REGDIMM_ENABLE; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h10)
begin
if (int_be [0])
begin
csr_auto_pd_cycles [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_auto_pd_cycles [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_self_rfsh <= int_wdata [17] ;
csr_ganged_arf <= int_wdata [19] ;
csr_addr_order <= int_wdata [21 : 20];
csr_reg_dimm <= int_wdata [22] ;
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_ack <= 0;
csr_self_rfsh_ack <= 0;
csr_drate <= 0;
end
else
begin
csr_auto_pd_ack <= local_power_down_ack;
csr_self_rfsh_ack <= local_self_rfsh_ack;
csr_drate <= (DWIDTH_RATIO == 2) ? 2'b00 : 2'b01; // Fullrate - 00, Halfrate - 01
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_110 = 0;
// then we set individual bits
read_csr_register_110 [15 : 0 ] = csr_auto_pd_cycles;
read_csr_register_110 [16] = csr_auto_pd_ack;
read_csr_register_110 [17] = csr_self_rfsh;
read_csr_register_110 [18] = csr_self_rfsh_ack;
read_csr_register_110 [19] = csr_ganged_arf;
read_csr_register_110 [21 : 20] = csr_addr_order;
read_csr_register_110 [22] = csr_reg_dimm;
read_csr_register_110 [24 : 23] = csr_drate;
end
/*------------------------------------------------------------------------------
0x120 Memory Address Sizes 0
------------------------------------------------------------------------------*/
reg [7 : 0] csr_col_width;
reg [7 : 0] csr_row_width;
reg [3 : 0] csr_bank_width;
reg [3 : 0] csr_chip_width;
// assign value back to top
assign cfg_cs_addr_width = csr_chip_width [MEM_IF_CSR_CS_WIDTH - 1 : 0];
assign cfg_bank_addr_width = csr_bank_width [MEM_IF_CSR_BANK_WIDTH - 1 : 0];
assign cfg_row_addr_width = csr_row_width [MEM_IF_CSR_ROW_WIDTH - 1 : 0];
assign cfg_col_addr_width = csr_col_width [MEM_IF_CSR_COL_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_col_width <= CFG_COL_ADDR_WIDTH; // reset to default value
csr_row_width <= CFG_ROW_ADDR_WIDTH; // reset to default value
csr_bank_width <= CFG_BANK_ADDR_WIDTH; // reset to default value
csr_chip_width <= CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h20)
begin
if (int_be [0])
begin
if (int_wdata [7 : 0] <= CFG_COL_ADDR_WIDTH)
begin
csr_col_width <= int_wdata [7 : 0 ];
end
end
if (int_be [1])
begin
if (int_wdata [15 : 8] <= CFG_ROW_ADDR_WIDTH)
begin
csr_row_width <= int_wdata [15 : 8 ];
end
end
if (int_be [2])
begin
if (int_wdata [19 : 16] <= CFG_BANK_ADDR_WIDTH)
begin
csr_bank_width <= int_wdata [19 : 16];
end
if (int_wdata [23 : 20] <= (CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0))
begin
csr_chip_width <= int_wdata [23 : 20];
end
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_120 = 0;
// then we set individual bits
read_csr_register_120 [7 : 0 ] = csr_col_width;
read_csr_register_120 [15 : 8 ] = csr_row_width;
read_csr_register_120 [19 : 16] = csr_bank_width;
read_csr_register_120 [23 : 20] = csr_chip_width;
end
/*------------------------------------------------------------------------------
0x121 Memory Address Sizes 1
------------------------------------------------------------------------------*/
reg [31 : 0] csr_data_binary_representation;
reg [7 : 0] csr_chip_binary_representation;
reg [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] cal_byte_lane;
// assign value back to top
assign ctl_cal_byte_lane_sel_n = ~cal_byte_lane;
// determine cal_byte_lane base on csr data
for (i = 0;i < CFG_MEM_IF_CS_WIDTH;i = i + 1)
begin : ctl_cal_byte_lane_per_chip
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= {MEM_IF_DQS_WIDTH{1'b1}}; // setting to all ones
else
begin
if (csr_chip_binary_representation[i])
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= csr_data_binary_representation [MEM_IF_DQS_WIDTH - 1 : 0];
else
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= 0;
end
end
end
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_data_binary_representation <= {MEM_IF_DQS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h21)
begin
if (int_be [0])
begin
csr_data_binary_representation [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_data_binary_representation [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_data_binary_representation [23 : 16] <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_data_binary_representation [31 : 24] <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_121 = 0;
// then we set individual bits
read_csr_register_121 [31 : 0 ] = csr_data_binary_representation;
end
/*------------------------------------------------------------------------------
0x122 Memory Address Sizes 2
------------------------------------------------------------------------------*/
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_chip_binary_representation <= {CFG_MEM_IF_CS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h22)
begin
if (int_be [0])
begin
csr_chip_binary_representation [ 7 : 0] <= int_wdata [7 : 0 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_122 = 0;
// then we set individual bits
read_csr_register_122 [7 : 0 ] = csr_chip_binary_representation;
end
/*------------------------------------------------------------------------------
0x123 Memory Timing Parameters Registers 0
------------------------------------------------------------------------------*/
reg [3 : 0] csr_trcd;
reg [3 : 0] csr_trrd;
reg [3 : 0] csr_trp;
reg [3 : 0] csr_tmrd; // yyong: might remove this
reg [7 : 0] csr_tras;
reg [7 : 0] csr_trc;
// assign value back to top
assign cfg_trcd = csr_trcd [TRCD_BUS_WIDTH - 1 : 0];
assign cfg_trrd = csr_trrd [TRRD_BUS_WIDTH - 1 : 0];
assign cfg_trp = csr_trp [TRP_BUS_WIDTH - 1 : 0];
assign cfg_tras = csr_tras [TRAS_BUS_WIDTH - 1 : 0];
assign cfg_trc = csr_trc [TRC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trcd <= CFG_TRCD; // reset to default value
csr_trrd <= CFG_TRRD; // reset to default value
csr_trp <= CFG_TRP; // reset to default value
csr_tmrd <= 0; // yyong: might remove this
csr_tras <= CFG_TRAS; // reset to default value
csr_trc <= CFG_TRC; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h23)
begin
if (int_be [0])
begin
csr_trcd <= int_wdata [3 : 0 ];
csr_trrd <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_trp <= int_wdata [11 : 8 ];
csr_tmrd <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_tras <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_trc <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_123 = 0;
// then we set individual bits
read_csr_register_123 [3 : 0 ] = csr_trcd;
read_csr_register_123 [7 : 4 ] = csr_trrd;
read_csr_register_123 [11 : 8 ] = csr_trp;
read_csr_register_123 [15 : 12] = csr_tmrd;
read_csr_register_123 [23 : 16] = csr_tras;
read_csr_register_123 [31 : 24] = csr_trc;
end
/*------------------------------------------------------------------------------
0x124 Memory Timing Parameters Registers 1
------------------------------------------------------------------------------*/
reg [3 : 0] csr_twtr;
reg [3 : 0] csr_trtp;
reg [5 : 0] csr_tfaw;
// assign value back to top
assign cfg_twtr = csr_twtr [TWTR_BUS_WIDTH - 1 : 0];
assign cfg_trtp = csr_trtp [TRTP_BUS_WIDTH - 1 : 0];
assign cfg_tfaw = csr_tfaw [TFAW_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_twtr <= CFG_TWTR;
csr_trtp <= CFG_TRTP;
csr_tfaw <= CFG_TFAW;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h24)
begin
if (int_be [0])
begin
csr_twtr <= int_wdata [3 : 0 ];
csr_trtp <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_tfaw <= int_wdata [13 : 8 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_124 = 0;
// then we set individual bits
read_csr_register_124 [3 : 0 ] = csr_twtr;
read_csr_register_124 [7 : 4 ] = csr_trtp;
read_csr_register_124 [15 : 8 ] = csr_tfaw;
end
/*------------------------------------------------------------------------------
0x125 Memory Timing Parameters Registers 2
------------------------------------------------------------------------------*/
reg [15 : 0] csr_trefi;
reg [7 : 0] csr_trfc;
// assign value back to top
assign cfg_trefi = csr_trefi [TREFI_BUS_WIDTH - 1 : 0];
assign cfg_trfc = csr_trfc [TRFC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trefi <= CFG_TREFI;
csr_trfc <= CFG_TRFC;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h25)
begin
if (int_be [0])
begin
csr_trefi [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_trefi [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_trfc <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_125 = 0;
// then we set individual bits
read_csr_register_125 [15 : 0 ] = csr_trefi;
read_csr_register_125 [23 : 16] = csr_trfc;
end
/*------------------------------------------------------------------------------
0x126 Memory Timing Parameters Registers 3
------------------------------------------------------------------------------*/
reg [3 : 0] csr_tcl;
reg [3 : 0] csr_al;
reg [3 : 0] csr_cwl;
reg [3 : 0] csr_twr;
reg [7 : 0] csr_bl;
// assign value back to top
assign cfg_tcl = csr_tcl [TCL_BUS_WIDTH - 1 : 0];
assign cfg_add_lat = csr_al [ADD_LAT_BUS_WIDTH - 1 : 0];
assign cfg_cas_wr_lat = csr_cwl [CAS_WR_LAT_BUS_WIDTH - 1 : 0];
assign cfg_twr = csr_twr [TWR_BUS_WIDTH - 1 : 0];
assign cfg_burst_length = csr_bl [BL_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_tcl <= CFG_TCL;
csr_al <= CFG_ADD_LAT;
csr_cwl <= CFG_CAS_WR_LAT;
csr_twr <= CFG_TWR;
csr_bl <= CFG_BURST_LENGTH;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h26)
begin
if (int_be [0])
begin
csr_tcl <= int_wdata [3 : 0 ];
csr_al <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_cwl <= int_wdata [11 : 8 ];
csr_twr <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_bl <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_126 = 0;
// then we set individual bits
read_csr_register_126 [3 : 0 ] = csr_tcl;
read_csr_register_126 [7 : 4 ] = csr_al;
read_csr_register_126 [11 : 8 ] = csr_cwl;
read_csr_register_126 [15 : 12] = csr_twr;
read_csr_register_126 [23 : 16] = csr_bl;
end
end
if (!CTL_ECC_CSR_ENABLED)
begin
assign cfg_enable_ecc = 1'b1; // default value
assign cfg_enable_auto_corr = 1'b1; // default value
assign cfg_gen_sbe = 0;
assign cfg_gen_dbe = 0;
assign cfg_enable_intr = 1'b1; // default value
assign cfg_mask_sbe_intr = 0;
assign cfg_mask_dbe_intr = 0;
assign cfg_clr_intr = 0;
assign cfg_mask_corr_dropped_intr=0;
end
else
begin
/*------------------------------------------------------------------------------
0x130 ECC Control Register
------------------------------------------------------------------------------*/
reg csr_enable_ecc;
reg csr_enable_auto_corr;
reg csr_gen_sbe;
reg csr_gen_dbe;
reg csr_enable_intr;
reg csr_mask_sbe_intr;
reg csr_mask_dbe_intr;
reg csr_ecc_clear;
reg csr_mask_corr_dropped_intr;
// assign value back to top
assign cfg_enable_ecc = csr_enable_ecc;
assign cfg_enable_auto_corr = csr_enable_auto_corr;
assign cfg_gen_sbe = csr_gen_sbe;
assign cfg_gen_dbe = csr_gen_dbe;
assign cfg_enable_intr = csr_enable_intr;
assign cfg_mask_sbe_intr = csr_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_mask_dbe_intr;
assign cfg_clr_intr = csr_ecc_clear;
assign cfg_mask_corr_dropped_intr = csr_mask_corr_dropped_intr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_enable_ecc <= CFG_ENABLE_ECC;
csr_enable_auto_corr <= CFG_ENABLE_AUTO_CORR;
csr_gen_sbe <= 0;
csr_gen_dbe <= 0;
csr_enable_intr <= 1'b1;
csr_mask_sbe_intr <= 0;
csr_mask_dbe_intr <= 0;
csr_ecc_clear <= 0;
csr_mask_corr_dropped_intr <= 0;
end
else
begin
// write request
if (!int_mask_ecc_avalon_mm_write && int_write_req && int_addr == 8'h30)
begin
if (int_be [0])
begin
csr_enable_ecc <= int_wdata [0];
csr_enable_auto_corr <= int_wdata [1];
csr_gen_sbe <= int_wdata [2];
csr_gen_dbe <= int_wdata [3];
csr_enable_intr <= int_wdata [4];
csr_mask_sbe_intr <= int_wdata [5];
csr_mask_dbe_intr <= int_wdata [6];
csr_ecc_clear <= int_wdata [7];
end
if (int_be [1])
begin
csr_mask_corr_dropped_intr <= int_wdata [8];
end
end
// set csr_clear to zero after one clock cycle
if (csr_ecc_clear)
csr_ecc_clear <= 1'b0;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_130 = 0;
// then we set individual bits
read_csr_register_130 [0] = csr_enable_ecc;
read_csr_register_130 [1] = csr_enable_auto_corr;
read_csr_register_130 [2] = csr_gen_sbe;
read_csr_register_130 [3] = csr_gen_dbe;
read_csr_register_130 [4] = csr_enable_intr;
read_csr_register_130 [5] = csr_mask_sbe_intr;
read_csr_register_130 [6] = csr_mask_dbe_intr;
read_csr_register_130 [7] = csr_ecc_clear;
read_csr_register_130 [8] = csr_mask_corr_dropped_intr;
end
/*------------------------------------------------------------------------------
0x131 ECC Status Register (Read Only)
------------------------------------------------------------------------------*/
reg csr_sbe_error;
reg csr_dbe_error;
reg csr_corr_dropped;
reg [7 : 0] csr_sbe_count;
reg [7 : 0] csr_dbe_count;
reg [7 : 0] csr_corr_dropped_count;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
csr_sbe_error <= sts_sbe_error;
csr_dbe_error <= sts_dbe_error;
csr_sbe_count <= sts_sbe_count;
csr_dbe_count <= sts_dbe_count;
csr_corr_dropped <= sts_corr_dropped;
csr_corr_dropped_count <= sts_corr_dropped_count;
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_131 = 0;
// then we set individual bits
read_csr_register_131 [0 ] = csr_sbe_error;
read_csr_register_131 [1 ] = csr_dbe_error;
read_csr_register_131 [2 ] = csr_corr_dropped;
read_csr_register_131 [15 : 8 ] = csr_sbe_count;
read_csr_register_131 [23 : 16] = csr_dbe_count;
read_csr_register_131 [31 : 24] = csr_corr_dropped_count;
end
/*------------------------------------------------------------------------------
0x132 ECC Error Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_error_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_error_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_error_addr <= 0;
else
csr_error_addr <= sts_err_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_132 = csr_error_addr;
end
/*------------------------------------------------------------------------------
0x133 ECC Correction Dropped Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_corr_dropped_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_corr_dropped_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_corr_dropped_addr <= 0;
else
csr_corr_dropped_addr <= sts_corr_dropped_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_133 = csr_corr_dropped_addr;
end
/*------------------------------------------------------------------------------
0x134 Controller Status and Control Register - Advanced Features
------------------------------------------------------------------------------*/
reg csr_reorder_data;
reg [7 : 0] csr_starve_limit;
// assign value back to top
assign cfg_reorder_data = csr_reorder_data;
assign cfg_starve_limit = csr_starve_limit;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_reorder_data <= CFG_REORDER_DATA;
csr_starve_limit <= CFG_STARVE_LIMIT; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h34)
begin
if (int_be [0])
begin
csr_reorder_data <= int_wdata [ 0];
end
if (int_be [2])
begin
csr_starve_limit <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_134 = 0;
// then we set individual bits
read_csr_register_134 [ 0 ] = csr_reorder_data;
read_csr_register_134 [ 23 : 16 ] = csr_starve_limit;
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
module alt_mem_ddrx_dataid_manager
# (
parameter
CFG_DATA_ID_WIDTH = 8,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 1,
CFG_TBP_NUM = 4,
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_DWIDTH_RATIO = 2
)
(
// clock & reset
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
// update cmd interface
update_cmd_if_ready,
update_cmd_if_valid,
update_cmd_if_data_id,
update_cmd_if_burstcount,
update_cmd_if_tbp_id,
// update data interface
update_data_if_valid,
update_data_if_data_id,
update_data_if_data_id_vector,
update_data_if_burstcount,
update_data_if_next_burstcount,
// notify burstcount consumed interface
notify_data_if_valid,
notify_data_if_burstcount,
// notify data ready interface (TBP)
notify_tbp_data_ready,
notify_tbp_data_partial_be,
// buffer write address generate interface
write_data_if_ready,
write_data_if_valid,
write_data_if_accepted,
write_data_if_address,
write_data_if_partial_dm,
// buffer read addresss generate interface
read_data_if_valid,
read_data_if_data_id,
read_data_if_data_id_vector,
read_data_if_valid_first,
read_data_if_data_id_first,
read_data_if_data_id_vector_first,
read_data_if_valid_first_vector,
read_data_if_valid_last,
read_data_if_data_id_last,
read_data_if_data_id_vector_last,
read_data_if_address,
read_data_if_datavalid,
read_data_if_done
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
// clock & reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input cfg_enable_ecc;
input cfg_enable_auto_corr;
input cfg_enable_no_dm;
// update cmd interface
output update_cmd_if_ready;
input update_cmd_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
input [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
input [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
// update data interface
input update_data_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
input [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
output notify_data_if_valid;
output [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
// notify tbp interface
output [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
output notify_tbp_data_partial_be;
// buffer write address generate interface
output write_data_if_ready;
input write_data_if_valid;
output write_data_if_accepted;
output [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
input write_data_if_partial_dm;
// read data interface
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
input read_data_if_valid_first;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_first;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid_first_vector;
input read_data_if_valid_last;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_last;
output [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
output [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
output read_data_if_done;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_enable_no_dm;
// update cmd interface
reg update_cmd_if_ready;
wire update_cmd_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
wire [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
wire [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address;
// update data interface
wire update_data_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
wire notify_data_if_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_notify_data_if_valid;
reg [CFG_INT_SIZE_WIDTH-1:0] mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
// dataid array
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0]; // mano - this should be CFG_INT_SIZE_WIDTH?
reg [CFG_TBP_NUM-1:0] dataid_array_tbp_id [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_dataid_array_done;
// notify tbp interface
wire [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
reg notify_tbp_data_partial_be;
reg [CFG_TBP_NUM-1:0] mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] tbp_data_ready_r;
// buffer write address generate interface
reg write_data_if_ready;
wire write_data_if_valid;
wire write_data_if_accepted;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_nextaddress;
wire write_data_if_partial_dm;
// read data interface
wire [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
reg [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
wire [CFG_INT_SIZE_WIDTH-1:0] read_data_if_burstcount; // used in assertion check
reg [CFG_BUFFER_ADDR_WIDTH-1:0] mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
wire read_data_if_done;
reg write_data_if_address_blocked;
// -----------------------------
// signal declaration
// -----------------------------
reg cfg_enable_partial_be_notification;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount_2x;
wire update_cmd_if_accepted;
wire update_cmd_if_address_blocked;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextmaxaddress;
reg update_cmd_if_nextmaxaddress_wrapped; // nextmaxaddress has wrapped around buffer max address
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_unnotified_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_next_unnotified_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_write_data_if_address_blocked;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_update_cmd_if_address_blocked;
// error debug signals - used in assertions
reg err_dataid_array_overwritten;
reg err_dataid_array_invalidread;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter; // increments on data write, decrements on data read
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_cmd_unallocated_counter; // increments by cmd burstcount on update cmd, decrements on data read
reg buffer_valid_counter_full;
reg err_buffer_valid_counter_overflow;
reg err_buffer_cmd_unallocated_counter_overflow;
reg partial_be_detected;
reg partial_be_when_no_cmd_tracked;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_greatereq;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_same;
wire update_data_bc_gt_update_cmd_unnotified_bc;
wire burstcount_list_read;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_read_data;
wire burstcount_list_read_data_valid;
wire burstcount_list_write;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_write_data;
reg update_data_if_burstcount_greatereq_burstcount_list;
reg update_data_if_burstcount_same_burstcount_list;
integer k;
// -----------------------------
// module definition
// -----------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_enable_partial_be_notification <= 1'b0;
end
else
begin
cfg_enable_partial_be_notification <= cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_max_cmd_burstcount <= 0;
cfg_max_cmd_burstcount_2x <= 0;
end
else
begin
cfg_max_cmd_burstcount <= cfg_burst_length / CFG_DWIDTH_RATIO;
cfg_max_cmd_burstcount_2x <= 2 * cfg_max_cmd_burstcount;
end
end
assign burstcount_list_write = update_cmd_if_accepted;
assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
assign burstcount_list_read = notify_data_if_valid;
// Burst count list to keep track of burst count value,
// to be used for comparison with burst count value from burst tracking logic
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_INT_SIZE_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
burstcount_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (burstcount_list_read_data_valid),
.list_get_entry_ready (burstcount_list_read),
.list_get_entry_id (burstcount_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (burstcount_list_write),
.list_put_entry_ready (),
.list_put_entry_id (burstcount_list_write_data)
);
always @ (*)
begin
if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
end
if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
begin
update_data_if_burstcount_same_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_same_burstcount_list = 1'b0;
end
end
// dataid_array management
genvar i;
generate
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array_management
assign update_data_if_burstcount_greatereq [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
assign update_data_if_burstcount_same [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_address [i] <= 0;
dataid_array_burstcount [i] <= 0;
dataid_array_tbp_id [i] <= 0;
dataid_array_data_ready [i] <= 1'b0;
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b0;
err_dataid_array_overwritten <= 0;
err_dataid_array_invalidread <= 0;
end
else
begin
// update cmd, update data & read data will not happen on same cycle
// update cmd interface
if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
begin
dataid_array_address [i] <= update_cmd_if_address;
dataid_array_burstcount [i] <= update_cmd_if_burstcount;
dataid_array_tbp_id [i] <= update_cmd_if_tbp_id;
dataid_array_valid [i] <= 1'b1;
mux_dataid_array_done [i] <= 1'b0;
if (dataid_array_valid[i])
begin
err_dataid_array_overwritten <= 1;
end
end
// update data interface
if (update_data_if_burstcount_greatereq[i])
begin
dataid_array_data_ready [i] <= 1'b1;
end
// read data interface
if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
begin
dataid_array_address [i] <= dataid_array_address [i] + 1;
dataid_array_burstcount [i] <= dataid_array_burstcount [i] - 1;
dataid_array_data_ready [i] <= 0;
if (dataid_array_burstcount [i] == 1'b1)
begin
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b1;
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
if (~dataid_array_valid[i])
begin
err_dataid_array_invalidread <= 1;
end
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
end
end
always @ (*)
begin
if (update_data_if_burstcount_greatereq[i])
begin
mux_notify_data_if_valid [i] = 1'b1;
end
else
begin
mux_notify_data_if_valid [i] = 1'b0;
end
end
end
endgenerate
// mux to generate signals from output of dataid_array
// 1. notify TBP that data is ready to be read
// 2. notify other blocks burstcount consumed by dataid_array entry
// 3. generate read data address
assign notify_data_if_valid = update_data_if_burstcount_greatereq_burstcount_list;
assign notify_data_if_burstcount= burstcount_list_read_data;
assign read_data_if_burstcount = mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
assign read_data_if_done = |mux_dataid_array_done;
assign update_cmd_if_address_blocked= |mux_update_cmd_if_address_blocked;
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one afi_wlat group
begin
always @ (*)
begin
read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
end
end
else
begin
wire rdata_address_list_read;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
wire rdata_address_list_read_data_valid;
wire rdata_address_list_write;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
assign rdata_address_list_read = read_data_if_valid_last;
assign rdata_address_list_write = read_data_if_valid_first;
assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
// Read data address list, to keep track of read address to different write data buffer group
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CTL_LIST_DEPTH (CFG_DRAM_WLAT_GROUP),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
rdata_address_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (rdata_address_list_read_data_valid),
.list_get_entry_ready (rdata_address_list_read),
.list_get_entry_id (rdata_address_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (rdata_address_list_write),
.list_put_entry_ready (),
.list_put_entry_id (rdata_address_list_write_data)
);
for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
begin : rdata_if_address_per_dqs_group
always @ (*)
begin
if (read_data_if_valid_first_vector [i])
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
end
else
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address_blocked <= 0;
end
else
begin
write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
end
end
always @ (*)
begin
mux_tbp_data_ready [0] = (mux_notify_data_if_valid [0]) ? dataid_array_tbp_id [0] : {CFG_TBP_NUM{1'b0}};
mux_notify_data_if_burstcount [0] = (mux_notify_data_if_valid [0]) ? dataid_array_burstcount [0] : 0;
mux_read_data_if_address [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address [0] : 0;
mux_read_data_if_burstcount [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
mux_write_data_if_address_blocked [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ~( (dataid_array_address[0] < update_cmd_if_address) & (dataid_array_address[0] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
end
end
genvar j;
generate
for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
begin : gen_mux_dataid_array_output
always @ (*)
begin
mux_tbp_data_ready [j] = mux_tbp_data_ready [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_tbp_id [j] : {CFG_TBP_NUM{1'b0}} );
mux_notify_data_if_burstcount [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_burstcount [j] : 0 );
mux_read_data_if_address [j] = mux_read_data_if_address [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address [j] : 0 );
mux_read_data_if_burstcount [j] = mux_read_data_if_burstcount [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
mux_write_data_if_address_blocked [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ~( (dataid_array_address[j] < update_cmd_if_address) & (dataid_array_address[j] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
end
end
end
endgenerate
assign notify_tbp_data_ready = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
// address generation for data location in buffer
assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_address <= 0;
update_cmd_if_nextmaxaddress <= 0;
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
write_data_if_address <= 0;
write_data_if_nextaddress <= 0;
end
else
begin
if (update_cmd_if_accepted)
begin
// dataid allocation/deallocation makes sure doesn't overflow
update_cmd_if_address <= update_cmd_if_nextaddress;
update_cmd_if_nextmaxaddress <= update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x;
if (update_cmd_if_nextaddress > (update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x))
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b1;
end
else
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
end
end
if (write_data_if_accepted)
begin
write_data_if_address <= write_data_if_address + 1;
write_data_if_nextaddress <= write_data_if_address + 2;
end
else
begin
write_data_if_nextaddress <= write_data_if_address + 1;
end
end
end
// un-notified burstcount counter
always @ (*)
begin
// notify_data_if_valid isn't evaluated, as notify_data_if_burstcount is 0 when ~notify_data_if_burstcount
if (update_cmd_if_accepted)
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount + update_cmd_if_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
else
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_unnotified_burstcount <= 0;
end
else
begin
update_cmd_if_unnotified_burstcount <= update_cmd_if_next_unnotified_burstcount;
end
end
// currently buffer_cmd_unallocated_counter only used for debug purposes
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
err_buffer_cmd_unallocated_counter_overflow <= 0;
end
else
begin
if (update_cmd_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
end
else if (update_cmd_if_accepted)
begin
// write only
{err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
end
else if (read_data_if_valid_last)
begin
// read only
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
end
else
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_ready <= 0;
end
else
begin
update_cmd_if_ready <= ~update_cmd_if_address_blocked;
end
end
assign write_data_if_accepted = write_data_if_ready & write_data_if_valid;
always @ (*)
begin
if (write_data_if_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
write_data_if_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
// if cfg_enable_partial_be_notification, de-assert write read if partial be detected, and we have no commands being tracked currently
write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
read_data_if_datavalid <= 0;
end
else
begin
read_data_if_datavalid <= read_data_if_valid;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
buffer_valid_counter_full <= 1'b0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (write_data_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
else if (write_data_if_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0}) // when valid counter is counting up to all_ones
begin
buffer_valid_counter_full <= 1'b1;
end
else
begin
buffer_valid_counter_full <= 1'b0;
end
end
else if (read_data_if_valid_last)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
buffer_valid_counter_full <= 1'b0;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
end
end
// partial be generation logic
always @ (*)
begin
if (partial_be_when_no_cmd_tracked)
begin
notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
end
else
begin
notify_tbp_data_partial_be = partial_be_detected;
end
end
assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else if (partial_be_detected & ~notify_data_if_valid)
begin
partial_be_detected <= partial_be_detected;
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_dm & update_data_bc_gt_update_cmd_unnotified_bc;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
//For tCL = 3 and tCWL = 2 rdwr_data_tmg block output must be registered in order to support ODT
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr2_odt_gen
# ( parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_add_lat,
cfg_burst_length,
cfg_output_regd,
bg_do_write,
bg_do_read,
int_odt_l,
int_odt_h
);
//=================================================================================================//
// Local parameter definition //
//=================================================================================================//
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL; // okay to size this to 4 since max latency in DDR2 is 7+6=13
localparam CFG_TAOND = 2;
localparam CFG_TAOFD = 2.5;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_ADD_LAT-1:0] cfg_add_lat;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
output int_odt_l;
output int_odt_h;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
wire bg_do_read;
reg [1:0] regd_output;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl_unreg;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl;
reg int_tcwl_even;
reg int_tcwl_odd;
reg [CFG_PORT_WIDTH_TCL-1:0] write_latency;
reg [CFG_PORT_WIDTH_TCL-1:0] read_latency;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_read_pipe;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
regd_output <= 0;
end
else
begin
if (cfg_output_regd)
regd_output <= (CFG_DWIDTH_RATIO / 2);
else
regd_output <= 2'd0;
end
end
always @ (*)
begin
int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b0;
end
else
begin
if (int_tcwl % 2 == 0)
begin
int_tcwl_even <= 1'b1;
int_tcwl_odd <= 1'b0;
end
else
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_latency <= 0;
read_latency <= 0;
end
else
begin
write_latency <= (int_tcwl - 4) / (CFG_DWIDTH_RATIO / 2);
read_latency <= (int_tcwl - 3) / (CFG_DWIDTH_RATIO / 2);
end
end
//=================================================================================================//
// Delay ODT signal to match READ DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (bg_do_read)
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
else
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 3)
start_odt_read = bg_do_read;
else
start_odt_read = do_read_pipe[read_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_read_count <= 1;
else
doing_read_count <= 0;
end
else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
//=================================================================================================//
// Delay ODT signal to match WRITE DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (bg_do_write)
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_write};
else
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 4)
start_odt_write = bg_do_write;
else
start_odt_write = do_write_pipe[write_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_write_count <= 1;
else
doing_write_count <= 0;
end
else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else // half and quarter rate
begin
if (int_tcwl_even)
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
else
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
else // half and quarter rate
begin
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_write_count > 0)
begin
if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_read_count > 0)
begin
if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_h | reg_odt_h;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_l | reg_odt_l;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr3_odt_gen
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CAS_WR_LAT = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_cas_wr_lat,
cfg_output_regd,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
int_odt_l,
int_odt_h,
int_odt_i_1,
int_odt_i_2
);
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
//=================================================================================================//
// DDR3 ODT timing parameters //
//=================================================================================================//
localparam integer CFG_ODTH8 = 6; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTH4 = 4; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO / 2;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT-1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
output int_odt_l;
output int_odt_h;
output int_odt_i_1;
output int_odt_i_2;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
reg int_do_read;
reg int_do_write_burst_chop;
reg int_do_read_burst_chop;
reg int_do_read_burst_chop_c;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
wire [3:0] diff_modulo_unreg;
reg [3:0] diff_modulo;
wire [3:0] sel_do_read_pipe_unreg;
reg [3:0] sel_do_read_pipe;
reg diff_modulo_not_zero;
reg diff_modulo_one;
reg diff_modulo_two;
reg diff_modulo_three;
reg int_odt_l_int;
reg int_odt_l_int_r;
reg premux_odt_h;
reg premux_odt_h_r;
reg int_odt_h_int;
reg int_odt_h_int_r;
reg int_odt_i_1_int;
reg int_odt_i_2_int;
reg int_odt_i_1_int_r;
reg int_odt_i_2_int_r;
wire int_odt_l;
wire int_odt_h;
wire int_odt_i_1;
wire int_odt_i_2;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
wire doing_read_count_not_zero;
reg doing_read_count_not_zero_r;
wire [3:0] doing_write_count_limit;
wire [3:0] doing_read_count_limit;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_read_pipe;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_burst_chop_pipe;
//=================================================================================================//
// Define ODT pulse width during READ operation //
//=================================================================================================//
//ODTLon/ODTLoff are calculated based on CWL, Below logic is to compensate for that timing during read, Needs to delay ODT signal by cfg_tcl - cfg_cas_wr_lat
assign diff_unreg = cfg_tcl - cfg_cas_wr_lat;
assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD);
assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo_not_zero;
//assign diff_modulo_not_zero = (|diff_modulo);
//assign sel_do_read_pipe = diff - CFG_ODTPIPE_THRESHOLD;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff <= 0;
diff_modulo <= 0;
sel_do_read_pipe <= 0;
end
else
begin
diff <= diff_unreg;
diff_modulo <= diff_modulo_unreg;
sel_do_read_pipe <= (sel_do_read_pipe_unreg > 0) ? (sel_do_read_pipe_unreg - 1'b1) : 0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff_modulo_not_zero <= 1'b0;
diff_modulo_one <= 1'b0;
diff_modulo_two <= 1'b0;
diff_modulo_three <= 1'b0;
end
else
begin
diff_modulo_not_zero <= |diff_modulo;
diff_modulo_one <= (diff_modulo == 1) ? 1'b1 : 1'b0;
diff_modulo_two <= (diff_modulo == 2) ? 1'b1 : 1'b0;
diff_modulo_three <= (diff_modulo == 3) ? 1'b1 : 1'b0;
end
end
always @ (*)
begin
int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;
int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_read_burst_chop <= 1'b0;
end
else
begin
if (int_do_read)
begin
int_do_read_burst_chop <= int_do_read_burst_chop_c;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_read_pipe <= 0;
end
else
begin
do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_read};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_burst_chop_pipe <= 0;
end
else
begin
do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_burst_chop};
end
end
assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
assign doing_read_count_not_zero = (|doing_read_count);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_count <= 0;
end
else
begin
if (int_do_read)
begin
doing_read_count <= 1;
end
else if (doing_read_count >= doing_read_count_limit)
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
doing_read_count_not_zero_r <= 1'b0;
end
else
begin
doing_read_count_not_zero_r <= doing_read_count_not_zero;
end
end
//=================================================================================================//
// Define ODT pulse width during WRITE operation //
//=================================================================================================//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_write_burst_chop <= 1'b0;
end
else
begin
if (bg_do_write)
begin
int_do_write_burst_chop <= bg_do_burst_chop;
end
end
end
assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_count <= 0;
end
else
begin
if (bg_do_write)
begin
doing_write_count <= 1;
end
else if (doing_write_count >= doing_write_count_limit)
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (bg_do_write || int_do_read)
begin
premux_odt_h = 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
premux_odt_h = 1'b1;
end
else
begin
premux_odt_h = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
premux_odt_h_r <= 1'b0;
end
else
begin
if (int_do_read)
begin
premux_odt_h_r <= 1'b1;
end
else if ((doing_read_count > 1 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 4) || diff_modulo_two)) || (doing_read_count > 0 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 2) || diff_modulo_three)))
begin
premux_odt_h_r <= 1'b1;
end
else
begin
premux_odt_h_r <= 1'b0;
end
end
end
always @ (*)
begin
if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r))
begin
int_odt_h_int = premux_odt_h_r;
end
else // write, read with normal odt
begin
int_odt_h_int = premux_odt_h;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_l_int <= 1'b0;
end
else
begin
if (bg_do_write || (int_do_read && !diff_modulo_two && !diff_modulo_three))
begin
int_odt_l_int <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
int_odt_l_int <= 1'b1;
end
else
begin
int_odt_l_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_1_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_1_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && !diff_modulo_not_zero) || (doing_read_count > 0 && diff_modulo_not_zero))
begin
int_odt_i_1_int <= 1'b1;
end
else
begin
int_odt_i_1_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_2_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_2_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && (!diff_modulo_not_zero || diff_modulo_one)) || (doing_read_count > 0 && (diff_modulo_two || diff_modulo_three)))
begin
int_odt_i_2_int <= 1'b1;
end
else
begin
int_odt_i_2_int <= 1'b0;
end
end
end
//Generate registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_h_int_r <= 1'b0;
int_odt_l_int_r <= 1'b0;
int_odt_i_1_int_r <= 1'b0;
int_odt_i_2_int_r <= 1'b0;
end
else
begin
int_odt_h_int_r <= int_odt_h_int;
int_odt_l_int_r <= int_odt_l_int;
int_odt_i_1_int_r <= int_odt_i_1_int;
int_odt_i_2_int_r <= int_odt_i_2_int;
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i_1 = (cfg_output_regd) ? int_odt_i_1_int_r : int_odt_i_1_int;
assign int_odt_i_2 = (cfg_output_regd) ? int_odt_i_2_int_r : int_odt_i_2_int;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal,
err_sbe
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
reg err_sbe;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
wire int_err_sbe;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg int_err_sbe_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_err_sbe_r <= 1'b0;
int_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_err_sbe_r <= int_err_sbe;
int_output_ecc_code_r <= int_output_ecc_code;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
err_sbe = int_err_sbe_r;
output_ecc_code = int_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
err_sbe = int_err_sbe;
output_ecc_code = int_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64 decoder_inst
(
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
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